1	/*
2	* Copyright © 2012 Intel Corporation
3	*
4	* Permission is hereby granted, free of charge, to any person obtaining a
5	* copy of this software and associated documentation files (the "Software"),
6	* to deal in the Software without restriction, including without limitation
7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8	* and/or sell copies of the Software, and to permit persons to whom the
9	* Software is furnished to do so, subject to the following conditions:
10	*
11	* The above copyright notice and this permission notice (including the next
12	* paragraph) shall be included in all copies or substantial portions of the
13	* Software.
14	*
15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21	* IN THE SOFTWARE.
22	*
23	* Authors:
24	* Eugeni Dodonov <eugeni.dodonov@intel.com>
25	*
26	*/
27
28	#include <linux/iopoll.h>
29	#include <linux/seq_buf.h>
30	#include <linux/string_helpers.h>
31
32	#include <drm/display/drm_dp_helper.h>
33	#include <drm/display/drm_scdc_helper.h>
34	#include <drm/drm_print.h>
35	#include <drm/drm_privacy_screen_consumer.h>
36
37	#include "i915_reg.h"
38	#include "icl_dsi.h"
39	#include "intel_alpm.h"
40	#include "intel_audio.h"
41	#include "intel_audio_regs.h"
42	#include "intel_backlight.h"
43	#include "intel_combo_phy.h"
44	#include "intel_combo_phy_regs.h"
45	#include "intel_connector.h"
46	#include "intel_crtc.h"
47	#include "intel_cx0_phy.h"
48	#include "intel_cx0_phy_regs.h"
49	#include "intel_ddi.h"
50	#include "intel_ddi_buf_trans.h"
51	#include "intel_de.h"
52	#include "intel_display_power.h"
53	#include "intel_display_regs.h"
54	#include "intel_display_types.h"
55	#include "intel_display_utils.h"
56	#include "intel_dkl_phy.h"
57	#include "intel_dkl_phy_regs.h"
58	#include "intel_dp.h"
59	#include "intel_dp_aux.h"
60	#include "intel_dp_link_training.h"
61	#include "intel_dp_mst.h"
62	#include "intel_dp_test.h"
63	#include "intel_dp_tunnel.h"
64	#include "intel_dpio_phy.h"
65	#include "intel_dsi.h"
66	#include "intel_encoder.h"
67	#include "intel_fdi.h"
68	#include "intel_fifo_underrun.h"
69	#include "intel_gmbus.h"
70	#include "intel_hdcp.h"
71	#include "intel_hdmi.h"
72	#include "intel_hotplug.h"
73	#include "intel_hti.h"
74	#include "intel_lspcon.h"
75	#include "intel_lt_phy.h"
76	#include "intel_mg_phy_regs.h"
77	#include "intel_modeset_lock.h"
78	#include "intel_panel.h"
79	#include "intel_pfit.h"
80	#include "intel_pps.h"
81	#include "intel_psr.h"
82	#include "intel_quirks.h"
83	#include "intel_snps_phy.h"
84	#include "intel_step.h"
85	#include "intel_tc.h"
86	#include "intel_vdsc.h"
87	#include "intel_vdsc_regs.h"
88	#include "intel_vrr.h"
89	#include "skl_scaler.h"
90	#include "skl_universal_plane.h"
91
92	static const u8 index_to_dp_signal_levels[] = {
93	[0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
94	[1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
95	[2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
96	[3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
97	[4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
98	[5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
99	[6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
100	[7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
101	[8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
102	[9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
103	};
104
105	static int intel_ddi_hdmi_level(struct intel_encoder *encoder,
106	const struct intel_ddi_buf_trans *trans)
107	{
108	int level;
109
110	level = intel_bios_hdmi_level_shift(devdata: encoder->devdata);
111	if (level < 0)
112	level = trans->hdmi_default_entry;
113
114	return level;
115	}
116
117	static bool has_buf_trans_select(struct intel_display *display)
118	{
119	return DISPLAY_VER(display) < 10 && !display->platform.broxton;
120	}
121
122	static bool has_iboost(struct intel_display *display)
123	{
124	return DISPLAY_VER(display) == 9 && !display->platform.broxton;
125	}
126
127	/*
128	* Starting with Haswell, DDI port buffers must be programmed with correct
129	* values in advance. This function programs the correct values for
130	* DP/eDP/FDI use cases.
131	*/
132	void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
133	const struct intel_crtc_state *crtc_state)
134	{
135	struct intel_display *display = to_intel_display(encoder);
136	u32 iboost_bit = 0;
137	int i, n_entries;
138	enum port port = encoder->port;
139	const struct intel_ddi_buf_trans *trans;
140
141	trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
142	if (drm_WARN_ON_ONCE(display->drm, !trans))
143	return;
144
145	/* If we're boosting the current, set bit 31 of trans1 */
146	if (has_iboost(display) &&
147	intel_bios_dp_boost_level(devdata: encoder->devdata))
148	iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
149
150	for (i = 0; i < n_entries; i++) {
151	intel_de_write(display, DDI_BUF_TRANS_LO(port, i),
152	val: trans->entries[i].hsw.trans1 | iboost_bit);
153	intel_de_write(display, DDI_BUF_TRANS_HI(port, i),
154	val: trans->entries[i].hsw.trans2);
155	}
156	}
157
158	/*
159	* Starting with Haswell, DDI port buffers must be programmed with correct
160	* values in advance. This function programs the correct values for
161	* HDMI/DVI use cases.
162	*/
163	static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
164	const struct intel_crtc_state *crtc_state)
165	{
166	struct intel_display *display = to_intel_display(encoder);
167	int level = intel_ddi_level(encoder, crtc_state, lane: 0);
168	u32 iboost_bit = 0;
169	int n_entries;
170	enum port port = encoder->port;
171	const struct intel_ddi_buf_trans *trans;
172
173	trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
174	if (drm_WARN_ON_ONCE(display->drm, !trans))
175	return;
176
177	/* If we're boosting the current, set bit 31 of trans1 */
178	if (has_iboost(display) &&
179	intel_bios_hdmi_boost_level(devdata: encoder->devdata))
180	iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
181
182	/* Entry 9 is for HDMI: */
183	intel_de_write(display, DDI_BUF_TRANS_LO(port, 9),
184	val: trans->entries[level].hsw.trans1 | iboost_bit);
185	intel_de_write(display, DDI_BUF_TRANS_HI(port, 9),
186	val: trans->entries[level].hsw.trans2);
187	}
188
189	static i915_reg_t intel_ddi_buf_status_reg(struct intel_display *display, enum port port)
190	{
191	if (DISPLAY_VER(display) >= 14)
192	return XELPDP_PORT_BUF_CTL1(display, port);
193	else
194	return DDI_BUF_CTL(port);
195	}
196
197	void intel_wait_ddi_buf_idle(struct intel_display *display, enum port port)
198	{
199	/*
200	* Bspec's platform specific timeouts:
201	* MTL+ : 100 us
202	* BXT : fixed 16 us
203	* HSW-ADL: 8 us
204	*
205	* FIXME: MTL requires 10 ms based on tests, find out why 100 us is too short
206	*/
207	if (display->platform.broxton) {
208	udelay(usec: 16);
209	return;
210	}
211
212	static_assert(DDI_BUF_IS_IDLE == XELPDP_PORT_BUF_PHY_IDLE);
213	if (intel_de_wait_for_set_ms(display, reg: intel_ddi_buf_status_reg(display, port),
214	DDI_BUF_IS_IDLE, timeout_ms: 10))
215	drm_err(display->drm, "Timeout waiting for DDI BUF %c to get idle\n",
216	port_name(port));
217	}
218
219	static void intel_wait_ddi_buf_active(struct intel_encoder *encoder)
220	{
221	struct intel_display *display = to_intel_display(encoder);
222	enum port port = encoder->port;
223
224	/*
225	* Bspec's platform specific timeouts:
226	* MTL+ : 10000 us
227	* DG2 : 1200 us
228	* TGL-ADL combo PHY: 1000 us
229	* TGL-ADL TypeC PHY: 3000 us
230	* HSW-ICL : fixed 518 us
231	*/
232	if (DISPLAY_VER(display) < 10) {
233	usleep_range(min: 518, max: 1000);
234	return;
235	}
236
237	static_assert(DDI_BUF_IS_IDLE == XELPDP_PORT_BUF_PHY_IDLE);
238	if (intel_de_wait_for_clear_ms(display, reg: intel_ddi_buf_status_reg(display, port),
239	DDI_BUF_IS_IDLE, timeout_ms: 10))
240	drm_err(display->drm, "Timeout waiting for DDI BUF %c to get active\n",
241	port_name(port));
242	}
243
244	static u32 hsw_pll_to_ddi_pll_sel(const struct intel_dpll *pll)
245	{
246	switch (pll->info->id) {
247	case DPLL_ID_WRPLL1:
248	return PORT_CLK_SEL_WRPLL1;
249	case DPLL_ID_WRPLL2:
250	return PORT_CLK_SEL_WRPLL2;
251	case DPLL_ID_SPLL:
252	return PORT_CLK_SEL_SPLL;
253	case DPLL_ID_LCPLL_810:
254	return PORT_CLK_SEL_LCPLL_810;
255	case DPLL_ID_LCPLL_1350:
256	return PORT_CLK_SEL_LCPLL_1350;
257	case DPLL_ID_LCPLL_2700:
258	return PORT_CLK_SEL_LCPLL_2700;
259	default:
260	MISSING_CASE(pll->info->id);
261	return PORT_CLK_SEL_NONE;
262	}
263	}
264
265	static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder,
266	const struct intel_crtc_state *crtc_state)
267	{
268	const struct intel_dpll *pll = crtc_state->intel_dpll;
269	int clock = crtc_state->port_clock;
270	const enum intel_dpll_id id = pll->info->id;
271
272	switch (id) {
273	default:
274	/*
275	* DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used
276	* here, so do warn if this get passed in
277	*/
278	MISSING_CASE(id);
279	return DDI_CLK_SEL_NONE;
280	case DPLL_ID_ICL_TBTPLL:
281	switch (clock) {
282	case 162000:
283	return DDI_CLK_SEL_TBT_162;
284	case 270000:
285	return DDI_CLK_SEL_TBT_270;
286	case 540000:
287	return DDI_CLK_SEL_TBT_540;
288	case 810000:
289	return DDI_CLK_SEL_TBT_810;
290	default:
291	MISSING_CASE(clock);
292	return DDI_CLK_SEL_NONE;
293	}
294	case DPLL_ID_ICL_MGPLL1:
295	case DPLL_ID_ICL_MGPLL2:
296	case DPLL_ID_ICL_MGPLL3:
297	case DPLL_ID_ICL_MGPLL4:
298	case DPLL_ID_TGL_MGPLL5:
299	case DPLL_ID_TGL_MGPLL6:
300	return DDI_CLK_SEL_MG;
301	}
302	}
303
304	static u32 ddi_buf_phy_link_rate(int port_clock)
305	{
306	switch (port_clock) {
307	case 162000:
308	return DDI_BUF_PHY_LINK_RATE(0);
309	case 216000:
310	return DDI_BUF_PHY_LINK_RATE(4);
311	case 243000:
312	return DDI_BUF_PHY_LINK_RATE(5);
313	case 270000:
314	return DDI_BUF_PHY_LINK_RATE(1);
315	case 324000:
316	return DDI_BUF_PHY_LINK_RATE(6);
317	case 432000:
318	return DDI_BUF_PHY_LINK_RATE(7);
319	case 540000:
320	return DDI_BUF_PHY_LINK_RATE(2);
321	case 810000:
322	return DDI_BUF_PHY_LINK_RATE(3);
323	default:
324	MISSING_CASE(port_clock);
325	return DDI_BUF_PHY_LINK_RATE(0);
326	}
327	}
328
329	static int dp_phy_lane_stagger_delay(int port_clock)
330	{
331	/*
332	* Return the number of symbol clocks delay used to stagger the
333	* assertion/desassertion of the port lane enables. The target delay
334	* time is 100 ns or greater, return the number of symbols specific to
335	* the provided port_clock (aka link clock) corresponding to this delay
336	* time, i.e. so that
337	*
338	* number_of_symbols * duration_of_one_symbol >= 100 ns
339	*
340	* The delay must be applied only on TypeC DP outputs, for everything else
341	* the delay must be set to 0.
342	*
343	* Return the number of link symbols per 100 ns:
344	* port_clock (10 kHz) -> bits / 100 us
345	* / symbol_size -> symbols / 100 us
346	* / 1000 -> symbols / 100 ns
347	*/
348	return DIV_ROUND_UP(port_clock, intel_dp_link_symbol_size(port_clock) * 1000);
349	}
350
351	static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder,
352	const struct intel_crtc_state *crtc_state)
353	{
354	struct intel_display *display = to_intel_display(encoder);
355	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
356	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
357
358	/* DDI_BUF_CTL_ENABLE will be set by intel_ddi_prepare_link_retrain() later */
359	intel_dp->DP = DDI_PORT_WIDTH(crtc_state->lane_count) |
360	DDI_BUF_TRANS_SELECT(0);
361
362	if (dig_port->lane_reversal)
363	intel_dp->DP |= DDI_BUF_PORT_REVERSAL;
364	if (dig_port->ddi_a_4_lanes)
365	intel_dp->DP |= DDI_A_4_LANES;
366
367	if (DISPLAY_VER(display) >= 14) {
368	if (intel_dp_is_uhbr(crtc_state))
369	intel_dp->DP |= DDI_BUF_PORT_DATA_40BIT;
370	else
371	intel_dp->DP |= DDI_BUF_PORT_DATA_10BIT;
372	}
373
374	if (display->platform.alderlake_p && intel_encoder_is_tc(encoder)) {
375	intel_dp->DP |= ddi_buf_phy_link_rate(port_clock: crtc_state->port_clock);
376	if (!intel_tc_port_in_tbt_alt_mode(dig_port))
377	intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
378	}
379
380	if (IS_DISPLAY_VER(display, 11, 13) && intel_encoder_is_tc(encoder)) {
381	int delay = dp_phy_lane_stagger_delay(port_clock: crtc_state->port_clock);
382
383	intel_dp->DP |= DDI_BUF_LANE_STAGGER_DELAY(delay);
384	}
385	}
386
387	static int icl_calc_tbt_pll_link(struct intel_display *display, enum port port)
388	{
389	u32 val = intel_de_read(display, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
390
391	switch (val) {
392	case DDI_CLK_SEL_NONE:
393	return 0;
394	case DDI_CLK_SEL_TBT_162:
395	return 162000;
396	case DDI_CLK_SEL_TBT_270:
397	return 270000;
398	case DDI_CLK_SEL_TBT_540:
399	return 540000;
400	case DDI_CLK_SEL_TBT_810:
401	return 810000;
402	default:
403	MISSING_CASE(val);
404	return 0;
405	}
406	}
407
408	static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
409	{
410	/* CRT dotclock is determined via other means */
411	if (pipe_config->has_pch_encoder)
412	return;
413
414	pipe_config->hw.adjusted_mode.crtc_clock =
415	intel_crtc_dotclock(pipe_config);
416	}
417
418	void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state,
419	const struct drm_connector_state *conn_state)
420	{
421	struct intel_display *display = to_intel_display(crtc_state);
422	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
423	u32 temp;
424
425	if (!intel_crtc_has_dp_encoder(crtc_state))
426	return;
427
428	drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder));
429
430	temp = DP_MSA_MISC_SYNC_CLOCK;
431
432	switch (crtc_state->pipe_bpp) {
433	case 18:
434	temp |= DP_MSA_MISC_6_BPC;
435	break;
436	case 24:
437	temp |= DP_MSA_MISC_8_BPC;
438	break;
439	case 30:
440	temp |= DP_MSA_MISC_10_BPC;
441	break;
442	case 36:
443	temp |= DP_MSA_MISC_12_BPC;
444	break;
445	default:
446	MISSING_CASE(crtc_state->pipe_bpp);
447	break;
448	}
449
450	/* nonsense combination */
451	drm_WARN_ON(display->drm, crtc_state->limited_color_range &&
452	crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
453
454	if (crtc_state->limited_color_range)
455	temp |= DP_MSA_MISC_COLOR_CEA_RGB;
456
457	/*
458	* As per DP 1.2 spec section 2.3.4.3 while sending
459	* YCBCR 444 signals we should program MSA MISC1/0 fields with
460	* colorspace information.
461	*/
462	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
463	temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709;
464
465	/*
466	* As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
467	* of Color Encoding Format and Content Color Gamut] while sending
468	* YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields
469	* which indicate VSC SDP for the Pixel Encoding/Colorimetry Format.
470	*/
471	if (intel_dp_needs_vsc_sdp(crtc_state, conn_state))
472	temp |= DP_MSA_MISC_COLOR_VSC_SDP;
473
474	intel_de_write(display, TRANS_MSA_MISC(display, cpu_transcoder),
475	val: temp);
476	}
477
478	static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder)
479	{
480	if (master_transcoder == TRANSCODER_EDP)
481	return 0;
482	else
483	return master_transcoder + 1;
484	}
485
486	static void
487	intel_ddi_config_transcoder_dp2(const struct intel_crtc_state *crtc_state,
488	bool enable)
489	{
490	struct intel_display *display = to_intel_display(crtc_state);
491	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
492	u32 val = 0;
493
494	if (!HAS_DP20(display))
495	return;
496
497	if (enable && intel_dp_is_uhbr(crtc_state))
498	val = TRANS_DP2_128B132B_CHANNEL_CODING;
499
500	intel_de_write(display, TRANS_DP2_CTL(cpu_transcoder), val);
501	}
502
503	/*
504	* Returns the TRANS_DDI_FUNC_CTL value based on CRTC state.
505	*
506	* Only intended to be used by intel_ddi_enable_transcoder_func() and
507	* intel_ddi_config_transcoder_func().
508	*/
509	static u32
510	intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder,
511	const struct intel_crtc_state *crtc_state)
512	{
513	struct intel_display *display = to_intel_display(crtc_state);
514	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
515	enum pipe pipe = crtc->pipe;
516	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
517	enum port port = encoder->port;
518	u32 temp;
519
520	/* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
521	temp = TRANS_DDI_FUNC_ENABLE;
522	if (DISPLAY_VER(display) >= 12)
523	temp |= TGL_TRANS_DDI_SELECT_PORT(port);
524	else
525	temp |= TRANS_DDI_SELECT_PORT(port);
526
527	switch (crtc_state->pipe_bpp) {
528	default:
529	MISSING_CASE(crtc_state->pipe_bpp);
530	fallthrough;
531	case 18:
532	temp |= TRANS_DDI_BPC_6;
533	break;
534	case 24:
535	temp |= TRANS_DDI_BPC_8;
536	break;
537	case 30:
538	temp |= TRANS_DDI_BPC_10;
539	break;
540	case 36:
541	temp |= TRANS_DDI_BPC_12;
542	break;
543	}
544
545	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
546	temp |= TRANS_DDI_PVSYNC;
547	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
548	temp |= TRANS_DDI_PHSYNC;
549
550	if (cpu_transcoder == TRANSCODER_EDP) {
551	switch (pipe) {
552	default:
553	MISSING_CASE(pipe);
554	fallthrough;
555	case PIPE_A:
556	/* On Haswell, can only use the always-on power well for
557	* eDP when not using the panel fitter, and when not
558	* using motion blur mitigation (which we don't
559	* support). */
560	if (crtc_state->pch_pfit.force_thru)
561	temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
562	else
563	temp |= TRANS_DDI_EDP_INPUT_A_ON;
564	break;
565	case PIPE_B:
566	temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
567	break;
568	case PIPE_C:
569	temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
570	break;
571	}
572	}
573
574	if (intel_crtc_has_type(crtc_state, type: INTEL_OUTPUT_HDMI)) {
575	if (crtc_state->has_hdmi_sink)
576	temp |= TRANS_DDI_MODE_SELECT_HDMI;
577	else
578	temp |= TRANS_DDI_MODE_SELECT_DVI;
579
580	if (crtc_state->hdmi_scrambling)
581	temp |= TRANS_DDI_HDMI_SCRAMBLING;
582	if (crtc_state->hdmi_high_tmds_clock_ratio)
583	temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
584	if (DISPLAY_VER(display) >= 14)
585	temp |= TRANS_DDI_PORT_WIDTH(crtc_state->lane_count);
586	} else if (intel_crtc_has_type(crtc_state, type: INTEL_OUTPUT_ANALOG)) {
587	temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B;
588	temp |= (crtc_state->fdi_lanes - 1) << 1;
589	} else if (intel_crtc_has_type(crtc_state, type: INTEL_OUTPUT_DP_MST) ||
590	intel_dp_is_uhbr(crtc_state)) {
591	if (intel_dp_is_uhbr(crtc_state))
592	temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B;
593	else
594	temp |= TRANS_DDI_MODE_SELECT_DP_MST;
595	temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
596
597	if (DISPLAY_VER(display) >= 12) {
598	enum transcoder master;
599
600	master = crtc_state->mst_master_transcoder;
601	if (drm_WARN_ON(display->drm,
602	master == INVALID_TRANSCODER))
603	master = TRANSCODER_A;
604	temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master);
605	}
606	} else {
607	temp |= TRANS_DDI_MODE_SELECT_DP_SST;
608	temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
609	}
610
611	if (IS_DISPLAY_VER(display, 8, 10) &&
612	crtc_state->master_transcoder != INVALID_TRANSCODER) {
613	u8 master_select =
614	bdw_trans_port_sync_master_select(master_transcoder: crtc_state->master_transcoder);
615
616	temp |= TRANS_DDI_PORT_SYNC_ENABLE |
617	TRANS_DDI_PORT_SYNC_MASTER_SELECT(master_select);
618	}
619
620	return temp;
621	}
622
623	void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder,
624	const struct intel_crtc_state *crtc_state)
625	{
626	struct intel_display *display = to_intel_display(crtc_state);
627	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
628
629	if (DISPLAY_VER(display) >= 11) {
630	enum transcoder master_transcoder = crtc_state->master_transcoder;
631	u32 ctl2 = 0;
632
633	if (master_transcoder != INVALID_TRANSCODER) {
634	u8 master_select =
635	bdw_trans_port_sync_master_select(master_transcoder);
636
637	ctl2 |= PORT_SYNC_MODE_ENABLE |
638	PORT_SYNC_MODE_MASTER_SELECT(master_select);
639	}
640
641	intel_de_write(display,
642	TRANS_DDI_FUNC_CTL2(display, cpu_transcoder),
643	val: ctl2);
644	}
645
646	intel_de_write(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder),
647	val: intel_ddi_transcoder_func_reg_val_get(encoder,
648	crtc_state));
649	}
650
651	/*
652	* Same as intel_ddi_enable_transcoder_func(), but it does not set the enable
653	* bit for the DDI function and enables the DP2 configuration. Called for all
654	* transcoder types.
655	*/
656	void
657	intel_ddi_config_transcoder_func(struct intel_encoder *encoder,
658	const struct intel_crtc_state *crtc_state)
659	{
660	struct intel_display *display = to_intel_display(crtc_state);
661	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
662	u32 ctl;
663
664	intel_ddi_config_transcoder_dp2(crtc_state, enable: true);
665
666	ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state);
667	ctl &= ~TRANS_DDI_FUNC_ENABLE;
668	intel_de_write(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder),
669	val: ctl);
670	}
671
672	/*
673	* Disable the DDI function and port syncing.
674	* For SST, pre-TGL MST, TGL+ MST-slave transcoders: deselect the DDI port,
675	* SST/MST mode and disable the DP2 configuration. For TGL+ MST-master
676	* transcoders these are done later in intel_ddi_post_disable_dp().
677	*/
678	void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state)
679	{
680	struct intel_display *display = to_intel_display(crtc_state);
681	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
682	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
683	u32 ctl;
684
685	if (DISPLAY_VER(display) >= 11)
686	intel_de_write(display,
687	TRANS_DDI_FUNC_CTL2(display, cpu_transcoder),
688	val: 0);
689
690	ctl = intel_de_read(display,
691	TRANS_DDI_FUNC_CTL(display, cpu_transcoder));
692
693	drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING);
694
695	ctl &= ~TRANS_DDI_FUNC_ENABLE;
696
697	if (IS_DISPLAY_VER(display, 8, 10))
698	ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE |
699	TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK);
700
701	if (DISPLAY_VER(display) >= 12) {
702	if (!intel_dp_mst_is_master_trans(crtc_state)) {
703	ctl &= ~(TGL_TRANS_DDI_PORT_MASK |
704	TRANS_DDI_MODE_SELECT_MASK);
705	}
706	} else {
707	ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK);
708	}
709
710	intel_de_write(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder),
711	val: ctl);
712
713	if (intel_dp_mst_is_slave_trans(crtc_state))
714	intel_ddi_config_transcoder_dp2(crtc_state, enable: false);
715
716	if (intel_has_quirk(display, quirk: QUIRK_INCREASE_DDI_DISABLED_TIME) &&
717	intel_crtc_has_type(crtc_state, type: INTEL_OUTPUT_HDMI)) {
718	drm_dbg_kms(display->drm, "Quirk Increase DDI disabled time\n");
719	/* Quirk time at 100ms for reliable operation */
720	msleep(msecs: 100);
721	}
722	}
723
724	int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder,
725	enum transcoder cpu_transcoder,
726	bool enable, u32 hdcp_mask)
727	{
728	struct intel_display *display = to_intel_display(intel_encoder);
729	intel_wakeref_t wakeref;
730	int ret = 0;
731
732	wakeref = intel_display_power_get_if_enabled(display,
733	domain: intel_encoder->power_domain);
734	if (drm_WARN_ON(display->drm, !wakeref))
735	return -ENXIO;
736
737	intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder),
738	clear: hdcp_mask, set: enable ? hdcp_mask : 0);
739	intel_display_power_put(display, domain: intel_encoder->power_domain, wakeref);
740	return ret;
741	}
742
743	bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
744	{
745	struct intel_display *display = to_intel_display(intel_connector);
746	struct intel_encoder *encoder = intel_attached_encoder(connector: intel_connector);
747	int type = intel_connector->base.connector_type;
748	enum port port = encoder->port;
749	enum transcoder cpu_transcoder;
750	intel_wakeref_t wakeref;
751	enum pipe pipe = 0;
752	u32 ddi_mode;
753	bool ret;
754
755	wakeref = intel_display_power_get_if_enabled(display,
756	domain: encoder->power_domain);
757	if (!wakeref)
758	return false;
759
760	/* Note: This returns false for DP MST primary encoders. */
761	if (!encoder->get_hw_state(encoder, &pipe)) {
762	ret = false;
763	goto out;
764	}
765
766	if (HAS_TRANSCODER(display, TRANSCODER_EDP) && port == PORT_A)
767	cpu_transcoder = TRANSCODER_EDP;
768	else
769	cpu_transcoder = (enum transcoder) pipe;
770
771	ddi_mode = intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder)) &
772	TRANS_DDI_MODE_SELECT_MASK;
773
774	if (ddi_mode == TRANS_DDI_MODE_SELECT_HDMI ||
775	ddi_mode == TRANS_DDI_MODE_SELECT_DVI) {
776	ret = type == DRM_MODE_CONNECTOR_HDMIA;
777	} else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && !HAS_DP20(display)) {
778	ret = type == DRM_MODE_CONNECTOR_VGA;
779	} else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_SST) {
780	ret = type == DRM_MODE_CONNECTOR_eDP ||
781	type == DRM_MODE_CONNECTOR_DisplayPort;
782	} else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)) {
783	/*
784	* encoder->get_hw_state() should have bailed out on MST. This
785	* must be SST and non-eDP.
786	*/
787	ret = type == DRM_MODE_CONNECTOR_DisplayPort;
788	} else if (drm_WARN_ON(display->drm, ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST)) {
789	/* encoder->get_hw_state() should have bailed out on MST. */
790	ret = false;
791	} else {
792	ret = false;
793	}
794
795	out:
796	intel_display_power_put(display, domain: encoder->power_domain, wakeref);
797
798	return ret;
799	}
800
801	static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
802	u8 *pipe_mask, bool *is_dp_mst)
803	{
804	struct intel_display *display = to_intel_display(encoder);
805	enum port port = encoder->port;
806	intel_wakeref_t wakeref;
807	enum pipe p;
808	u32 tmp;
809	u8 mst_pipe_mask = 0, dp128b132b_pipe_mask = 0;
810
811	*pipe_mask = 0;
812	*is_dp_mst = false;
813
814	wakeref = intel_display_power_get_if_enabled(display,
815	domain: encoder->power_domain);
816	if (!wakeref)
817	return;
818
819	tmp = intel_de_read(display, DDI_BUF_CTL(port));
820	if (!(tmp & DDI_BUF_CTL_ENABLE))
821	goto out;
822
823	if (HAS_TRANSCODER(display, TRANSCODER_EDP) && port == PORT_A) {
824	tmp = intel_de_read(display,
825	TRANS_DDI_FUNC_CTL(display, TRANSCODER_EDP));
826
827	switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
828	default:
829	MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK);
830	fallthrough;
831	case TRANS_DDI_EDP_INPUT_A_ON:
832	case TRANS_DDI_EDP_INPUT_A_ONOFF:
833	*pipe_mask = BIT(PIPE_A);
834	break;
835	case TRANS_DDI_EDP_INPUT_B_ONOFF:
836	*pipe_mask = BIT(PIPE_B);
837	break;
838	case TRANS_DDI_EDP_INPUT_C_ONOFF:
839	*pipe_mask = BIT(PIPE_C);
840	break;
841	}
842
843	goto out;
844	}
845
846	for_each_pipe(display, p) {
847	enum transcoder cpu_transcoder = (enum transcoder)p;
848	u32 port_mask, ddi_select, ddi_mode;
849	intel_wakeref_t trans_wakeref;
850
851	trans_wakeref = intel_display_power_get_if_enabled(display,
852	POWER_DOMAIN_TRANSCODER(cpu_transcoder));
853	if (!trans_wakeref)
854	continue;
855
856	if (DISPLAY_VER(display) >= 12) {
857	port_mask = TGL_TRANS_DDI_PORT_MASK;
858	ddi_select = TGL_TRANS_DDI_SELECT_PORT(port);
859	} else {
860	port_mask = TRANS_DDI_PORT_MASK;
861	ddi_select = TRANS_DDI_SELECT_PORT(port);
862	}
863
864	tmp = intel_de_read(display,
865	TRANS_DDI_FUNC_CTL(display, cpu_transcoder));
866	intel_display_power_put(display, POWER_DOMAIN_TRANSCODER(cpu_transcoder),
867	wakeref: trans_wakeref);
868
869	if ((tmp & port_mask) != ddi_select)
870	continue;
871
872	ddi_mode = tmp & TRANS_DDI_MODE_SELECT_MASK;
873
874	if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST)
875	mst_pipe_mask |= BIT(p);
876	else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display))
877	dp128b132b_pipe_mask |= BIT(p);
878
879	*pipe_mask |= BIT(p);
880	}
881
882	if (!*pipe_mask)
883	drm_dbg_kms(display->drm,
884	"No pipe for [ENCODER:%d:%s] found\n",
885	encoder->base.base.id, encoder->base.name);
886
887	if (!mst_pipe_mask && dp128b132b_pipe_mask) {
888	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
889
890	/*
891	* If we don't have 8b/10b MST, but have more than one
892	* transcoder in 128b/132b mode, we know it must be 128b/132b
893	* MST.
894	*
895	* Otherwise, we fall back to checking the current MST
896	* state. It's not accurate for hardware takeover at probe, but
897	* we don't expect MST to have been enabled at that point, and
898	* can assume it's SST.
899	*/
900	if (hweight8(dp128b132b_pipe_mask) > 1 ||
901	intel_dp_mst_active_streams(intel_dp))
902	mst_pipe_mask = dp128b132b_pipe_mask;
903	}
904
905	if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) {
906	drm_dbg_kms(display->drm,
907	"Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n",
908	encoder->base.base.id, encoder->base.name,
909	*pipe_mask);
910	*pipe_mask = BIT(ffs(*pipe_mask) - 1);
911	}
912
913	if (mst_pipe_mask && mst_pipe_mask != *pipe_mask)
914	drm_dbg_kms(display->drm,
915	"Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe masks: all %02x, MST %02x, 128b/132b %02x)\n",
916	encoder->base.base.id, encoder->base.name,
917	*pipe_mask, mst_pipe_mask, dp128b132b_pipe_mask);
918	else
919	*is_dp_mst = mst_pipe_mask;
920
921	out:
922	if (*pipe_mask && (display->platform.geminilake || display->platform.broxton)) {
923	tmp = intel_de_read(display, BXT_PHY_CTL(port));
924	if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
925	BXT_PHY_LANE_POWERDOWN_ACK |
926	BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
927	drm_err(display->drm,
928	"[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n",
929	encoder->base.base.id, encoder->base.name, tmp);
930	}
931
932	intel_display_power_put(display, domain: encoder->power_domain, wakeref);
933	}
934
935	bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
936	enum pipe *pipe)
937	{
938	u8 pipe_mask;
939	bool is_mst;
940
941	intel_ddi_get_encoder_pipes(encoder, pipe_mask: &pipe_mask, is_dp_mst: &is_mst);
942
943	if (is_mst || !pipe_mask)
944	return false;
945
946	*pipe = ffs(pipe_mask) - 1;
947
948	return true;
949	}
950
951	static enum intel_display_power_domain
952	intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port,
953	const struct intel_crtc_state *crtc_state)
954	{
955	struct intel_display *display = to_intel_display(dig_port);
956
957	/*
958	* ICL+ HW requires corresponding AUX IOs to be powered up for PSR with
959	* DC states enabled at the same time, while for driver initiated AUX
960	* transfers we need the same AUX IOs to be powered but with DC states
961	* disabled. Accordingly use the AUX_IO_<port> power domain here which
962	* leaves DC states enabled.
963	*
964	* Before MTL TypeC PHYs (in all TypeC modes and both DP/HDMI) also require
965	* AUX IO to be enabled, but all these require DC_OFF to be enabled as
966	* well, so we can acquire a wider AUX_<port> power domain reference
967	* instead of a specific AUX_IO_<port> reference without powering up any
968	* extra wells.
969	*/
970	if (intel_psr_needs_aux_io_power(encoder: &dig_port->base, crtc_state))
971	return intel_display_power_aux_io_domain(display, aux_ch: dig_port->aux_ch);
972	else if (DISPLAY_VER(display) < 14 &&
973	(intel_crtc_has_dp_encoder(crtc_state) ||
974	intel_encoder_is_tc(encoder: &dig_port->base)))
975	return intel_aux_power_domain(dig_port);
976	else
977	return POWER_DOMAIN_INVALID;
978	}
979
980	static void
981	main_link_aux_power_domain_get(struct intel_digital_port *dig_port,
982	const struct intel_crtc_state *crtc_state)
983	{
984	struct intel_display *display = to_intel_display(dig_port);
985	enum intel_display_power_domain domain =
986	intel_ddi_main_link_aux_domain(dig_port, crtc_state);
987
988	drm_WARN_ON(display->drm, dig_port->aux_wakeref);
989
990	if (domain == POWER_DOMAIN_INVALID)
991	return;
992
993	dig_port->aux_wakeref = intel_display_power_get(display, domain);
994	}
995
996	static void
997	main_link_aux_power_domain_put(struct intel_digital_port *dig_port,
998	const struct intel_crtc_state *crtc_state)
999	{
1000	struct intel_display *display = to_intel_display(dig_port);
1001	enum intel_display_power_domain domain =
1002	intel_ddi_main_link_aux_domain(dig_port, crtc_state);
1003	intel_wakeref_t wf;
1004
1005	wf = fetch_and_zero(&dig_port->aux_wakeref);
1006	if (!wf)
1007	return;
1008
1009	intel_display_power_put(display, domain, wakeref: wf);
1010	}
1011
1012	static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
1013	struct intel_crtc_state *crtc_state)
1014	{
1015	struct intel_display *display = to_intel_display(encoder);
1016	struct intel_digital_port *dig_port;
1017
1018	/*
1019	* TODO: Add support for MST encoders. Atm, the following should never
1020	* happen since fake-MST encoders don't set their get_power_domains()
1021	* hook.
1022	*/
1023	if (drm_WARN_ON(display->drm,
1024	intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)))
1025	return;
1026
1027	dig_port = enc_to_dig_port(encoder);
1028
1029	if (!intel_tc_port_in_tbt_alt_mode(dig_port)) {
1030	drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref);
1031	dig_port->ddi_io_wakeref = intel_display_power_get(display,
1032	domain: dig_port->ddi_io_power_domain);
1033	}
1034
1035	main_link_aux_power_domain_get(dig_port, crtc_state);
1036	}
1037
1038	void intel_ddi_enable_transcoder_clock(struct intel_encoder *encoder,
1039	const struct intel_crtc_state *crtc_state)
1040	{
1041	struct intel_display *display = to_intel_display(crtc_state);
1042	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1043	enum phy phy = intel_encoder_to_phy(encoder);
1044	u32 val;
1045
1046	if (cpu_transcoder == TRANSCODER_EDP)
1047	return;
1048
1049	if (DISPLAY_VER(display) >= 13)
1050	val = TGL_TRANS_CLK_SEL_PORT(phy);
1051	else if (DISPLAY_VER(display) >= 12)
1052	val = TGL_TRANS_CLK_SEL_PORT(encoder->port);
1053	else
1054	val = TRANS_CLK_SEL_PORT(encoder->port);
1055
1056	intel_de_write(display, TRANS_CLK_SEL(cpu_transcoder), val);
1057	}
1058
1059	void intel_ddi_disable_transcoder_clock(const struct intel_crtc_state *crtc_state)
1060	{
1061	struct intel_display *display = to_intel_display(crtc_state);
1062	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1063	u32 val;
1064
1065	if (cpu_transcoder == TRANSCODER_EDP)
1066	return;
1067
1068	if (DISPLAY_VER(display) >= 12)
1069	val = TGL_TRANS_CLK_SEL_DISABLED;
1070	else
1071	val = TRANS_CLK_SEL_DISABLED;
1072
1073	intel_de_write(display, TRANS_CLK_SEL(cpu_transcoder), val);
1074	}
1075
1076	static void _skl_ddi_set_iboost(struct intel_display *display,
1077	enum port port, u8 iboost)
1078	{
1079	u32 tmp;
1080
1081	tmp = intel_de_read(display, DISPIO_CR_TX_BMU_CR0);
1082	tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
1083	if (iboost)
1084	tmp |= iboost << BALANCE_LEG_SHIFT(port);
1085	else
1086	tmp |= BALANCE_LEG_DISABLE(port);
1087	intel_de_write(display, DISPIO_CR_TX_BMU_CR0, val: tmp);
1088	}
1089
1090	static void skl_ddi_set_iboost(struct intel_encoder *encoder,
1091	const struct intel_crtc_state *crtc_state,
1092	int level)
1093	{
1094	struct intel_display *display = to_intel_display(encoder);
1095	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
1096	u8 iboost;
1097
1098	if (intel_crtc_has_type(crtc_state, type: INTEL_OUTPUT_HDMI))
1099	iboost = intel_bios_hdmi_boost_level(devdata: encoder->devdata);
1100	else
1101	iboost = intel_bios_dp_boost_level(devdata: encoder->devdata);
1102
1103	if (iboost == 0) {
1104	const struct intel_ddi_buf_trans *trans;
1105	int n_entries;
1106
1107	trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
1108	if (drm_WARN_ON_ONCE(display->drm, !trans))
1109	return;
1110
1111	iboost = trans->entries[level].hsw.i_boost;
1112	}
1113
1114	/* Make sure that the requested I_boost is valid */
1115	if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
1116	drm_err(display->drm, "Invalid I_boost value %u\n", iboost);
1117	return;
1118	}
1119
1120	_skl_ddi_set_iboost(display, port: encoder->port, iboost);
1121
1122	if (encoder->port == PORT_A && dig_port->max_lanes == 4)
1123	_skl_ddi_set_iboost(display, port: PORT_E, iboost);
1124	}
1125
1126	static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp,
1127	const struct intel_crtc_state *crtc_state)
1128	{
1129	struct intel_display *display = to_intel_display(intel_dp);
1130	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1131	int n_entries;
1132
1133	encoder->get_buf_trans(encoder, crtc_state, &n_entries);
1134
1135	if (drm_WARN_ON(display->drm, n_entries < 1))
1136	n_entries = 1;
1137	if (drm_WARN_ON(display->drm,
1138	n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
1139	n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
1140
1141	return index_to_dp_signal_levels[n_entries - 1] &
1142	DP_TRAIN_VOLTAGE_SWING_MASK;
1143	}
1144
1145	/*
1146	* We assume that the full set of pre-emphasis values can be
1147	* used on all DDI platforms. Should that change we need to
1148	* rethink this code.
1149	*/
1150	static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp)
1151	{
1152	return DP_TRAIN_PRE_EMPH_LEVEL_3;
1153	}
1154
1155	static u32 icl_combo_phy_loadgen_select(const struct intel_crtc_state *crtc_state,
1156	int lane)
1157	{
1158	if (crtc_state->port_clock > 600000)
1159	return 0;
1160
1161	if (crtc_state->lane_count == 4)
1162	return lane >= 1 ? LOADGEN_SELECT : 0;
1163	else
1164	return lane == 1 || lane == 2 ? LOADGEN_SELECT : 0;
1165	}
1166
1167	static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
1168	const struct intel_crtc_state *crtc_state)
1169	{
1170	struct intel_display *display = to_intel_display(encoder);
1171	const struct intel_ddi_buf_trans *trans;
1172	enum phy phy = intel_encoder_to_phy(encoder);
1173	int n_entries, ln;
1174	u32 val;
1175
1176	trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
1177	if (drm_WARN_ON_ONCE(display->drm, !trans))
1178	return;
1179
1180	if (intel_crtc_has_type(crtc_state, type: INTEL_OUTPUT_EDP)) {
1181	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1182
1183	val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED;
1184	intel_dp->hobl_active = is_hobl_buf_trans(table: trans);
1185	intel_de_rmw(display, ICL_PORT_CL_DW10(phy), clear: val,
1186	set: intel_dp->hobl_active ? val : 0);
1187	}
1188
1189	/* Set PORT_TX_DW5 */
1190	val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));
1191	val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
1192	COEFF_POLARITY | CURSOR_PROGRAM |
1193	TAP2_DISABLE | TAP3_DISABLE);
1194	val |= SCALING_MODE_SEL(0x2);
1195	val |= RTERM_SELECT(0x6);
1196	val |= TAP3_DISABLE;
1197	intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), val);
1198
1199	/* Program PORT_TX_DW2 */
1200	for (ln = 0; ln < 4; ln++) {
1201	int level = intel_ddi_level(encoder, crtc_state, lane: ln);
1202
1203	intel_de_rmw(display, ICL_PORT_TX_DW2_LN(ln, phy),
1204	SWING_SEL_UPPER_MASK | SWING_SEL_LOWER_MASK | RCOMP_SCALAR_MASK,
1205	SWING_SEL_UPPER(trans->entries[level].icl.dw2_swing_sel) |
1206	SWING_SEL_LOWER(trans->entries[level].icl.dw2_swing_sel) |
1207	RCOMP_SCALAR(0x98));
1208	}
1209
1210	/* Program PORT_TX_DW4 */
1211	/* We cannot write to GRP. It would overwrite individual loadgen. */
1212	for (ln = 0; ln < 4; ln++) {
1213	int level = intel_ddi_level(encoder, crtc_state, lane: ln);
1214
1215	intel_de_rmw(display, ICL_PORT_TX_DW4_LN(ln, phy),
1216	POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | CURSOR_COEFF_MASK,
1217	POST_CURSOR_1(trans->entries[level].icl.dw4_post_cursor_1) |
1218	POST_CURSOR_2(trans->entries[level].icl.dw4_post_cursor_2) |
1219	CURSOR_COEFF(trans->entries[level].icl.dw4_cursor_coeff));
1220	}
1221
1222	/* Program PORT_TX_DW7 */
1223	for (ln = 0; ln < 4; ln++) {
1224	int level = intel_ddi_level(encoder, crtc_state, lane: ln);
1225
1226	intel_de_rmw(display, ICL_PORT_TX_DW7_LN(ln, phy),
1227	N_SCALAR_MASK,
1228	N_SCALAR(trans->entries[level].icl.dw7_n_scalar));
1229	}
1230	}
1231
1232	static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder,
1233	const struct intel_crtc_state *crtc_state)
1234	{
1235	struct intel_display *display = to_intel_display(encoder);
1236	enum phy phy = intel_encoder_to_phy(encoder);
1237	u32 val;
1238	int ln;
1239
1240	/*
1241	* 1. If port type is eDP or DP,
1242	* set PORT_PCS_DW1 cmnkeeper_enable to 1b,
1243	* else clear to 0b.
1244	*/
1245	val = intel_de_read(display, ICL_PORT_PCS_DW1_LN(0, phy));
1246	if (intel_crtc_has_type(crtc_state, type: INTEL_OUTPUT_HDMI))
1247	val &= ~COMMON_KEEPER_EN;
1248	else
1249	val |= COMMON_KEEPER_EN;
1250	intel_de_write(display, ICL_PORT_PCS_DW1_GRP(phy), val);
1251
1252	/* 2. Program loadgen select */
1253	/*
1254	* Program PORT_TX_DW4 depending on Bit rate and used lanes
1255	* <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
1256	* <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
1257	* > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
1258	*/
1259	for (ln = 0; ln < 4; ln++) {
1260	intel_de_rmw(display, ICL_PORT_TX_DW4_LN(ln, phy),
1261	LOADGEN_SELECT,
1262	set: icl_combo_phy_loadgen_select(crtc_state, lane: ln));
1263	}
1264
1265	/* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
1266	intel_de_rmw(display, ICL_PORT_CL_DW5(phy),
1267	clear: 0, SUS_CLOCK_CONFIG);
1268
1269	/* 4. Clear training enable to change swing values */
1270	val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));
1271	val &= ~TX_TRAINING_EN;
1272	intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), val);
1273
1274	/* 5. Program swing and de-emphasis */
1275	icl_ddi_combo_vswing_program(encoder, crtc_state);
1276
1277	/* 6. Set training enable to trigger update */
1278	val = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));
1279	val |= TX_TRAINING_EN;
1280	intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), val);
1281	}
1282
1283	static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder,
1284	const struct intel_crtc_state *crtc_state)
1285	{
1286	struct intel_display *display = to_intel_display(encoder);
1287	enum tc_port tc_port = intel_encoder_to_tc(encoder);
1288	const struct intel_ddi_buf_trans *trans;
1289	int n_entries, ln;
1290
1291	if (intel_tc_port_in_tbt_alt_mode(dig_port: enc_to_dig_port(encoder)))
1292	return;
1293
1294	trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
1295	if (drm_WARN_ON_ONCE(display->drm, !trans))
1296	return;
1297
1298	for (ln = 0; ln < 2; ln++) {
1299	intel_de_rmw(display, MG_TX1_LINK_PARAMS(ln, tc_port),
1300	CRI_USE_FS32, set: 0);
1301	intel_de_rmw(display, MG_TX2_LINK_PARAMS(ln, tc_port),
1302	CRI_USE_FS32, set: 0);
1303	}
1304
1305	/* Program MG_TX_SWINGCTRL with values from vswing table */
1306	for (ln = 0; ln < 2; ln++) {
1307	int level;
1308
1309	level = intel_ddi_level(encoder, crtc_state, lane: 2*ln+0);
1310
1311	intel_de_rmw(display, MG_TX1_SWINGCTRL(ln, tc_port),
1312	CRI_TXDEEMPH_OVERRIDE_17_12_MASK,
1313	CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12));
1314
1315	level = intel_ddi_level(encoder, crtc_state, lane: 2*ln+1);
1316
1317	intel_de_rmw(display, MG_TX2_SWINGCTRL(ln, tc_port),
1318	CRI_TXDEEMPH_OVERRIDE_17_12_MASK,
1319	CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12));
1320	}
1321
1322	/* Program MG_TX_DRVCTRL with values from vswing table */
1323	for (ln = 0; ln < 2; ln++) {
1324	int level;
1325
1326	level = intel_ddi_level(encoder, crtc_state, lane: 2*ln+0);
1327
1328	intel_de_rmw(display, MG_TX1_DRVCTRL(ln, tc_port),
1329	CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
1330	CRI_TXDEEMPH_OVERRIDE_5_0_MASK,
1331	CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) |
1332	CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) |
1333	CRI_TXDEEMPH_OVERRIDE_EN);
1334
1335	level = intel_ddi_level(encoder, crtc_state, lane: 2*ln+1);
1336
1337	intel_de_rmw(display, MG_TX2_DRVCTRL(ln, tc_port),
1338	CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
1339	CRI_TXDEEMPH_OVERRIDE_5_0_MASK,
1340	CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) |
1341	CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) |
1342	CRI_TXDEEMPH_OVERRIDE_EN);
1343
1344	/* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */
1345	}
1346
1347	/*
1348	* Program MG_CLKHUB<LN, port being used> with value from frequency table
1349	* In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the
1350	* values from table for which TX1 and TX2 enabled.
1351	*/
1352	for (ln = 0; ln < 2; ln++) {
1353	intel_de_rmw(display, MG_CLKHUB(ln, tc_port),
1354	CFG_LOW_RATE_LKREN_EN,
1355	set: crtc_state->port_clock < 300000 ? CFG_LOW_RATE_LKREN_EN : 0);
1356	}
1357
1358	/* Program the MG_TX_DCC<LN, port being used> based on the link frequency */
1359	for (ln = 0; ln < 2; ln++) {
1360	intel_de_rmw(display, MG_TX1_DCC(ln, tc_port),
1361	CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK |
1362	CFG_AMI_CK_DIV_OVERRIDE_EN,
1363	set: crtc_state->port_clock > 500000 ?
1364	CFG_AMI_CK_DIV_OVERRIDE_VAL(1) |
1365	CFG_AMI_CK_DIV_OVERRIDE_EN : 0);
1366
1367	intel_de_rmw(display, MG_TX2_DCC(ln, tc_port),
1368	CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK |
1369	CFG_AMI_CK_DIV_OVERRIDE_EN,
1370	set: crtc_state->port_clock > 500000 ?
1371	CFG_AMI_CK_DIV_OVERRIDE_VAL(1) |
1372	CFG_AMI_CK_DIV_OVERRIDE_EN : 0);
1373	}
1374
1375	/* Program MG_TX_PISO_READLOAD with values from vswing table */
1376	for (ln = 0; ln < 2; ln++) {
1377	intel_de_rmw(display, MG_TX1_PISO_READLOAD(ln, tc_port),
1378	clear: 0, CRI_CALCINIT);
1379	intel_de_rmw(display, MG_TX2_PISO_READLOAD(ln, tc_port),
1380	clear: 0, CRI_CALCINIT);
1381	}
1382	}
1383
1384	static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder,
1385	const struct intel_crtc_state *crtc_state)
1386	{
1387	struct intel_display *display = to_intel_display(encoder);
1388	enum tc_port tc_port = intel_encoder_to_tc(encoder);
1389	const struct intel_ddi_buf_trans *trans;
1390	int n_entries, ln;
1391
1392	if (intel_tc_port_in_tbt_alt_mode(dig_port: enc_to_dig_port(encoder)))
1393	return;
1394
1395	trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
1396	if (drm_WARN_ON_ONCE(display->drm, !trans))
1397	return;
1398
1399	for (ln = 0; ln < 2; ln++) {
1400	int level;
1401
1402	/* Wa_16011342517:adl-p */
1403	if (display->platform.alderlake_p &&
1404	IS_DISPLAY_STEP(display, STEP_A0, STEP_D0)) {
1405	if ((intel_encoder_is_hdmi(encoder) &&
1406	crtc_state->port_clock == 594000) ||
1407	(intel_encoder_is_dp(encoder) &&
1408	crtc_state->port_clock == 162000)) {
1409	intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln),
1410	LOADGEN_SHARING_PMD_DISABLE, set: 1);
1411	} else {
1412	intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln),
1413	LOADGEN_SHARING_PMD_DISABLE, set: 0);
1414	}
1415	}
1416
1417	intel_dkl_phy_write(display, DKL_TX_PMD_LANE_SUS(tc_port, ln), val: 0);
1418
1419	level = intel_ddi_level(encoder, crtc_state, lane: 2*ln+0);
1420
1421	intel_dkl_phy_rmw(display, DKL_TX_DPCNTL0(tc_port, ln),
1422	DKL_TX_PRESHOOT_COEFF_MASK |
1423	DKL_TX_DE_EMPAHSIS_COEFF_MASK |
1424	DKL_TX_VSWING_CONTROL_MASK,
1425	DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) |
1426	DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) |
1427	DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing));
1428
1429	level = intel_ddi_level(encoder, crtc_state, lane: 2*ln+1);
1430
1431	intel_dkl_phy_rmw(display, DKL_TX_DPCNTL1(tc_port, ln),
1432	DKL_TX_PRESHOOT_COEFF_MASK |
1433	DKL_TX_DE_EMPAHSIS_COEFF_MASK |
1434	DKL_TX_VSWING_CONTROL_MASK,
1435	DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) |
1436	DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) |
1437	DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing));
1438
1439	intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln),
1440	DKL_TX_DP20BITMODE, set: 0);
1441
1442	if (display->platform.alderlake_p) {
1443	u32 val;
1444
1445	if (intel_crtc_has_type(crtc_state, type: INTEL_OUTPUT_HDMI)) {
1446	if (ln == 0) {
1447	val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0);
1448	val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(2);
1449	} else {
1450	val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(3);
1451	val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(3);
1452	}
1453	} else {
1454	val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0);
1455	val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(0);
1456	}
1457
1458	intel_dkl_phy_rmw(display, DKL_TX_DPCNTL2(tc_port, ln),
1459	DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK |
1460	DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK,
1461	set: val);
1462	}
1463	}
1464	}
1465
1466	static int translate_signal_level(struct intel_dp *intel_dp,
1467	u8 signal_levels)
1468	{
1469	struct intel_display *display = to_intel_display(intel_dp);
1470	const u8 *signal_array;
1471	size_t array_size;
1472	int i;
1473
1474	signal_array = index_to_dp_signal_levels;
1475	array_size = ARRAY_SIZE(index_to_dp_signal_levels);
1476
1477	for (i = 0; i < array_size; i++) {
1478	if (signal_array[i] == signal_levels)
1479	return i;
1480	}
1481
1482	drm_WARN(display->drm, 1,
1483	"Unsupported voltage swing/pre-emphasis level: 0x%x\n",
1484	signal_levels);
1485
1486	return 0;
1487	}
1488
1489	static int intel_ddi_dp_level(struct intel_dp *intel_dp,
1490	const struct intel_crtc_state *crtc_state,
1491	int lane)
1492	{
1493	u8 train_set = intel_dp->train_set[lane];
1494
1495	if (intel_dp_is_uhbr(crtc_state)) {
1496	return train_set & DP_TX_FFE_PRESET_VALUE_MASK;
1497	} else {
1498	u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1499	DP_TRAIN_PRE_EMPHASIS_MASK);
1500
1501	return translate_signal_level(intel_dp, signal_levels);
1502	}
1503	}
1504
1505	int intel_ddi_level(struct intel_encoder *encoder,
1506	const struct intel_crtc_state *crtc_state,
1507	int lane)
1508	{
1509	struct intel_display *display = to_intel_display(encoder);
1510	const struct intel_ddi_buf_trans *trans;
1511	int level, n_entries;
1512
1513	trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
1514	if (drm_WARN_ON_ONCE(display->drm, !trans))
1515	return 0;
1516
1517	if (intel_crtc_has_type(crtc_state, type: INTEL_OUTPUT_HDMI))
1518	level = intel_ddi_hdmi_level(encoder, trans);
1519	else
1520	level = intel_ddi_dp_level(intel_dp: enc_to_intel_dp(encoder), crtc_state,
1521	lane);
1522
1523	if (drm_WARN_ON_ONCE(display->drm, level >= n_entries))
1524	level = n_entries - 1;
1525
1526	return level;
1527	}
1528
1529	static void
1530	hsw_set_signal_levels(struct intel_encoder *encoder,
1531	const struct intel_crtc_state *crtc_state)
1532	{
1533	struct intel_display *display = to_intel_display(encoder);
1534	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1535	int level = intel_ddi_level(encoder, crtc_state, lane: 0);
1536	enum port port = encoder->port;
1537	u32 signal_levels;
1538
1539	if (has_iboost(display))
1540	skl_ddi_set_iboost(encoder, crtc_state, level);
1541
1542	/* HDMI ignores the rest */
1543	if (intel_crtc_has_type(crtc_state, type: INTEL_OUTPUT_HDMI))
1544	return;
1545
1546	signal_levels = DDI_BUF_TRANS_SELECT(level);
1547
1548	drm_dbg_kms(display->drm, "Using signal levels %08x\n",
1549	signal_levels);
1550
1551	intel_dp->DP &= ~DDI_BUF_EMP_MASK;
1552	intel_dp->DP |= signal_levels;
1553
1554	intel_de_write(display, DDI_BUF_CTL(port), val: intel_dp->DP);
1555	intel_de_posting_read(display, DDI_BUF_CTL(port));
1556	}
1557
1558	static void _icl_ddi_enable_clock(struct intel_display *display, i915_reg_t reg,
1559	u32 clk_sel_mask, u32 clk_sel, u32 clk_off)
1560	{
1561	mutex_lock(&display->dpll.lock);
1562
1563	intel_de_rmw(display, reg, clear: clk_sel_mask, set: clk_sel);
1564
1565	/*
1566	* "This step and the step before must be
1567	* done with separate register writes."
1568	*/
1569	intel_de_rmw(display, reg, clear: clk_off, set: 0);
1570
1571	mutex_unlock(lock: &display->dpll.lock);
1572	}
1573
1574	static void _icl_ddi_disable_clock(struct intel_display *display, i915_reg_t reg,
1575	u32 clk_off)
1576	{
1577	mutex_lock(&display->dpll.lock);
1578
1579	intel_de_rmw(display, reg, clear: 0, set: clk_off);
1580
1581	mutex_unlock(lock: &display->dpll.lock);
1582	}
1583
1584	static bool _icl_ddi_is_clock_enabled(struct intel_display *display, i915_reg_t reg,
1585	u32 clk_off)
1586	{
1587	return !(intel_de_read(display, reg) & clk_off);
1588	}
1589
1590	static struct intel_dpll *
1591	_icl_ddi_get_pll(struct intel_display *display, i915_reg_t reg,
1592	u32 clk_sel_mask, u32 clk_sel_shift)
1593	{
1594	enum intel_dpll_id id;
1595
1596	id = (intel_de_read(display, reg) & clk_sel_mask) >> clk_sel_shift;
1597
1598	return intel_get_dpll_by_id(display, id);
1599	}
1600
1601	static void adls_ddi_enable_clock(struct intel_encoder *encoder,
1602	const struct intel_crtc_state *crtc_state)
1603	{
1604	struct intel_display *display = to_intel_display(encoder);
1605	const struct intel_dpll *pll = crtc_state->intel_dpll;
1606	enum phy phy = intel_encoder_to_phy(encoder);
1607
1608	if (drm_WARN_ON(display->drm, !pll))
1609	return;
1610
1611	_icl_ddi_enable_clock(display, ADLS_DPCLKA_CFGCR(phy),
1612	ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy),
1613	clk_sel: pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy),
1614	ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1615	}
1616
1617	static void adls_ddi_disable_clock(struct intel_encoder *encoder)
1618	{
1619	struct intel_display *display = to_intel_display(encoder);
1620	enum phy phy = intel_encoder_to_phy(encoder);
1621
1622	_icl_ddi_disable_clock(display, ADLS_DPCLKA_CFGCR(phy),
1623	ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1624	}
1625
1626	static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder)
1627	{
1628	struct intel_display *display = to_intel_display(encoder);
1629	enum phy phy = intel_encoder_to_phy(encoder);
1630
1631	return _icl_ddi_is_clock_enabled(display, ADLS_DPCLKA_CFGCR(phy),
1632	ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1633	}
1634
1635	static struct intel_dpll *adls_ddi_get_pll(struct intel_encoder *encoder)
1636	{
1637	struct intel_display *display = to_intel_display(encoder);
1638	enum phy phy = intel_encoder_to_phy(encoder);
1639
1640	return _icl_ddi_get_pll(display, ADLS_DPCLKA_CFGCR(phy),
1641	ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy),
1642	ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy));
1643	}
1644
1645	static void rkl_ddi_enable_clock(struct intel_encoder *encoder,
1646	const struct intel_crtc_state *crtc_state)
1647	{
1648	struct intel_display *display = to_intel_display(encoder);
1649	const struct intel_dpll *pll = crtc_state->intel_dpll;
1650	enum phy phy = intel_encoder_to_phy(encoder);
1651
1652	if (drm_WARN_ON(display->drm, !pll))
1653	return;
1654
1655	_icl_ddi_enable_clock(display, ICL_DPCLKA_CFGCR0,
1656	RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
1657	RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
1658	RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1659	}
1660
1661	static void rkl_ddi_disable_clock(struct intel_encoder *encoder)
1662	{
1663	struct intel_display *display = to_intel_display(encoder);
1664	enum phy phy = intel_encoder_to_phy(encoder);
1665
1666	_icl_ddi_disable_clock(display, ICL_DPCLKA_CFGCR0,
1667	RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1668	}
1669
1670	static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder)
1671	{
1672	struct intel_display *display = to_intel_display(encoder);
1673	enum phy phy = intel_encoder_to_phy(encoder);
1674
1675	return _icl_ddi_is_clock_enabled(display, ICL_DPCLKA_CFGCR0,
1676	RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1677	}
1678
1679	static struct intel_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder)
1680	{
1681	struct intel_display *display = to_intel_display(encoder);
1682	enum phy phy = intel_encoder_to_phy(encoder);
1683
1684	return _icl_ddi_get_pll(display, ICL_DPCLKA_CFGCR0,
1685	RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
1686	RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy));
1687	}
1688
1689	static void dg1_ddi_enable_clock(struct intel_encoder *encoder,
1690	const struct intel_crtc_state *crtc_state)
1691	{
1692	struct intel_display *display = to_intel_display(encoder);
1693	const struct intel_dpll *pll = crtc_state->intel_dpll;
1694	enum phy phy = intel_encoder_to_phy(encoder);
1695
1696	if (drm_WARN_ON(display->drm, !pll))
1697	return;
1698
1699	/*
1700	* If we fail this, something went very wrong: first 2 PLLs should be
1701	* used by first 2 phys and last 2 PLLs by last phys
1702	*/
1703	if (drm_WARN_ON(display->drm,
1704	(pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) ||
1705	(pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C)))
1706	return;
1707
1708	_icl_ddi_enable_clock(display, DG1_DPCLKA_CFGCR0(phy),
1709	DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
1710	DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
1711	DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1712	}
1713
1714	static void dg1_ddi_disable_clock(struct intel_encoder *encoder)
1715	{
1716	struct intel_display *display = to_intel_display(encoder);
1717	enum phy phy = intel_encoder_to_phy(encoder);
1718
1719	_icl_ddi_disable_clock(display, DG1_DPCLKA_CFGCR0(phy),
1720	DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1721	}
1722
1723	static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder)
1724	{
1725	struct intel_display *display = to_intel_display(encoder);
1726	enum phy phy = intel_encoder_to_phy(encoder);
1727
1728	return _icl_ddi_is_clock_enabled(display, DG1_DPCLKA_CFGCR0(phy),
1729	DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1730	}
1731
1732	static struct intel_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder)
1733	{
1734	struct intel_display *display = to_intel_display(encoder);
1735	enum phy phy = intel_encoder_to_phy(encoder);
1736	enum intel_dpll_id id;
1737	u32 val;
1738
1739	val = intel_de_read(display, DG1_DPCLKA_CFGCR0(phy));
1740	val &= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
1741	val >>= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
1742	id = val;
1743
1744	/*
1745	* _DG1_DPCLKA0_CFGCR0 maps between DPLL 0 and 1 with one bit for phy A
1746	* and B while _DG1_DPCLKA1_CFGCR0 maps between DPLL 2 and 3 with one
1747	* bit for phy C and D.
1748	*/
1749	if (phy >= PHY_C)
1750	id += DPLL_ID_DG1_DPLL2;
1751
1752	return intel_get_dpll_by_id(display, id);
1753	}
1754
1755	static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder,
1756	const struct intel_crtc_state *crtc_state)
1757	{
1758	struct intel_display *display = to_intel_display(encoder);
1759	const struct intel_dpll *pll = crtc_state->intel_dpll;
1760	enum phy phy = intel_encoder_to_phy(encoder);
1761
1762	if (drm_WARN_ON(display->drm, !pll))
1763	return;
1764
1765	_icl_ddi_enable_clock(display, ICL_DPCLKA_CFGCR0,
1766	ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
1767	ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
1768	ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1769	}
1770
1771	static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder)
1772	{
1773	struct intel_display *display = to_intel_display(encoder);
1774	enum phy phy = intel_encoder_to_phy(encoder);
1775
1776	_icl_ddi_disable_clock(display, ICL_DPCLKA_CFGCR0,
1777	ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1778	}
1779
1780	static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder)
1781	{
1782	struct intel_display *display = to_intel_display(encoder);
1783	enum phy phy = intel_encoder_to_phy(encoder);
1784
1785	return _icl_ddi_is_clock_enabled(display, ICL_DPCLKA_CFGCR0,
1786	ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1787	}
1788
1789	struct intel_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder)
1790	{
1791	struct intel_display *display = to_intel_display(encoder);
1792	enum phy phy = intel_encoder_to_phy(encoder);
1793
1794	return _icl_ddi_get_pll(display, ICL_DPCLKA_CFGCR0,
1795	ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
1796	ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy));
1797	}
1798
1799	static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder,
1800	const struct intel_crtc_state *crtc_state)
1801	{
1802	struct intel_display *display = to_intel_display(encoder);
1803	const struct intel_dpll *pll = crtc_state->intel_dpll;
1804	enum port port = encoder->port;
1805
1806	if (drm_WARN_ON(display->drm, !pll))
1807	return;
1808
1809	/*
1810	* "For DDIC and DDID, program DDI_CLK_SEL to map the MG clock to the port.
1811	* MG does not exist, but the programming is required to ungate DDIC and DDID."
1812	*/
1813	intel_de_write(display, DDI_CLK_SEL(port), DDI_CLK_SEL_MG);
1814
1815	icl_ddi_combo_enable_clock(encoder, crtc_state);
1816	}
1817
1818	static void jsl_ddi_tc_disable_clock(struct intel_encoder *encoder)
1819	{
1820	struct intel_display *display = to_intel_display(encoder);
1821	enum port port = encoder->port;
1822
1823	icl_ddi_combo_disable_clock(encoder);
1824
1825	intel_de_write(display, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
1826	}
1827
1828	static bool jsl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder)
1829	{
1830	struct intel_display *display = to_intel_display(encoder);
1831	enum port port = encoder->port;
1832	u32 tmp;
1833
1834	tmp = intel_de_read(display, DDI_CLK_SEL(port));
1835
1836	if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE)
1837	return false;
1838
1839	return icl_ddi_combo_is_clock_enabled(encoder);
1840	}
1841
1842	static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder,
1843	const struct intel_crtc_state *crtc_state)
1844	{
1845	struct intel_display *display = to_intel_display(encoder);
1846	const struct intel_dpll *pll = crtc_state->intel_dpll;
1847	enum tc_port tc_port = intel_encoder_to_tc(encoder);
1848	enum port port = encoder->port;
1849
1850	if (drm_WARN_ON(display->drm, !pll))
1851	return;
1852
1853	intel_de_write(display, DDI_CLK_SEL(port),
1854	val: icl_pll_to_ddi_clk_sel(encoder, crtc_state));
1855
1856	mutex_lock(&display->dpll.lock);
1857
1858	intel_de_rmw(display, ICL_DPCLKA_CFGCR0,
1859	ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port), set: 0);
1860
1861	mutex_unlock(lock: &display->dpll.lock);
1862	}
1863
1864	static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder)
1865	{
1866	struct intel_display *display = to_intel_display(encoder);
1867	enum tc_port tc_port = intel_encoder_to_tc(encoder);
1868	enum port port = encoder->port;
1869
1870	mutex_lock(&display->dpll.lock);
1871
1872	intel_de_rmw(display, ICL_DPCLKA_CFGCR0,
1873	clear: 0, ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port));
1874
1875	mutex_unlock(lock: &display->dpll.lock);
1876
1877	intel_de_write(display, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
1878	}
1879
1880	static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder)
1881	{
1882	struct intel_display *display = to_intel_display(encoder);
1883	enum tc_port tc_port = intel_encoder_to_tc(encoder);
1884	enum port port = encoder->port;
1885	u32 tmp;
1886
1887	tmp = intel_de_read(display, DDI_CLK_SEL(port));
1888
1889	if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE)
1890	return false;
1891
1892	tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0);
1893
1894	return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port));
1895	}
1896
1897	static struct intel_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder)
1898	{
1899	struct intel_display *display = to_intel_display(encoder);
1900	enum tc_port tc_port = intel_encoder_to_tc(encoder);
1901	enum port port = encoder->port;
1902	enum intel_dpll_id id;
1903	u32 tmp;
1904
1905	tmp = intel_de_read(display, DDI_CLK_SEL(port));
1906
1907	switch (tmp & DDI_CLK_SEL_MASK) {
1908	case DDI_CLK_SEL_TBT_162:
1909	case DDI_CLK_SEL_TBT_270:
1910	case DDI_CLK_SEL_TBT_540:
1911	case DDI_CLK_SEL_TBT_810:
1912	id = DPLL_ID_ICL_TBTPLL;
1913	break;
1914	case DDI_CLK_SEL_MG:
1915	id = icl_tc_port_to_pll_id(tc_port);
1916	break;
1917	default:
1918	MISSING_CASE(tmp);
1919	fallthrough;
1920	case DDI_CLK_SEL_NONE:
1921	return NULL;
1922	}
1923
1924	return intel_get_dpll_by_id(display, id);
1925	}
1926
1927	static struct intel_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder)
1928	{
1929	struct intel_display *display = to_intel_display(encoder->base.dev);
1930	enum intel_dpll_id id;
1931
1932	switch (encoder->port) {
1933	case PORT_A:
1934	id = DPLL_ID_SKL_DPLL0;
1935	break;
1936	case PORT_B:
1937	id = DPLL_ID_SKL_DPLL1;
1938	break;
1939	case PORT_C:
1940	id = DPLL_ID_SKL_DPLL2;
1941	break;
1942	default:
1943	MISSING_CASE(encoder->port);
1944	return NULL;
1945	}
1946
1947	return intel_get_dpll_by_id(display, id);
1948	}
1949
1950	static void skl_ddi_enable_clock(struct intel_encoder *encoder,
1951	const struct intel_crtc_state *crtc_state)
1952	{
1953	struct intel_display *display = to_intel_display(encoder);
1954	const struct intel_dpll *pll = crtc_state->intel_dpll;
1955	enum port port = encoder->port;
1956
1957	if (drm_WARN_ON(display->drm, !pll))
1958	return;
1959
1960	mutex_lock(&display->dpll.lock);
1961
1962	intel_de_rmw(display, DPLL_CTRL2,
1963	DPLL_CTRL2_DDI_CLK_OFF(port) |
1964	DPLL_CTRL2_DDI_CLK_SEL_MASK(port),
1965	DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
1966	DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
1967
1968	mutex_unlock(lock: &display->dpll.lock);
1969	}
1970
1971	static void skl_ddi_disable_clock(struct intel_encoder *encoder)
1972	{
1973	struct intel_display *display = to_intel_display(encoder);
1974	enum port port = encoder->port;
1975
1976	mutex_lock(&display->dpll.lock);
1977
1978	intel_de_rmw(display, DPLL_CTRL2,
1979	clear: 0, DPLL_CTRL2_DDI_CLK_OFF(port));
1980
1981	mutex_unlock(lock: &display->dpll.lock);
1982	}
1983
1984	static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder)
1985	{
1986	struct intel_display *display = to_intel_display(encoder);
1987	enum port port = encoder->port;
1988
1989	/*
1990	* FIXME Not sure if the override affects both
1991	* the PLL selection and the CLK_OFF bit.
1992	*/
1993	return !(intel_de_read(display, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port));
1994	}
1995
1996	static struct intel_dpll *skl_ddi_get_pll(struct intel_encoder *encoder)
1997	{
1998	struct intel_display *display = to_intel_display(encoder);
1999	enum port port = encoder->port;
2000	enum intel_dpll_id id;
2001	u32 tmp;
2002
2003	tmp = intel_de_read(display, DPLL_CTRL2);
2004
2005	/*
2006	* FIXME Not sure if the override affects both
2007	* the PLL selection and the CLK_OFF bit.
2008	*/
2009	if ((tmp & DPLL_CTRL2_DDI_SEL_OVERRIDE(port)) == 0)
2010	return NULL;
2011
2012	id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >>
2013	DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port);
2014
2015	return intel_get_dpll_by_id(display, id);
2016	}
2017
2018	void hsw_ddi_enable_clock(struct intel_encoder *encoder,
2019	const struct intel_crtc_state *crtc_state)
2020	{
2021	struct intel_display *display = to_intel_display(encoder);
2022	const struct intel_dpll *pll = crtc_state->intel_dpll;
2023	enum port port = encoder->port;
2024
2025	if (drm_WARN_ON(display->drm, !pll))
2026	return;
2027
2028	intel_de_write(display, PORT_CLK_SEL(port), val: hsw_pll_to_ddi_pll_sel(pll));
2029	}
2030
2031	void hsw_ddi_disable_clock(struct intel_encoder *encoder)
2032	{
2033	struct intel_display *display = to_intel_display(encoder);
2034	enum port port = encoder->port;
2035
2036	intel_de_write(display, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
2037	}
2038
2039	bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder)
2040	{
2041	struct intel_display *display = to_intel_display(encoder);
2042	enum port port = encoder->port;
2043
2044	return intel_de_read(display, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE;
2045	}
2046
2047	static struct intel_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder)
2048	{
2049	struct intel_display *display = to_intel_display(encoder);
2050	enum port port = encoder->port;
2051	enum intel_dpll_id id;
2052	u32 tmp;
2053
2054	tmp = intel_de_read(display, PORT_CLK_SEL(port));
2055
2056	switch (tmp & PORT_CLK_SEL_MASK) {
2057	case PORT_CLK_SEL_WRPLL1:
2058	id = DPLL_ID_WRPLL1;
2059	break;
2060	case PORT_CLK_SEL_WRPLL2:
2061	id = DPLL_ID_WRPLL2;
2062	break;
2063	case PORT_CLK_SEL_SPLL:
2064	id = DPLL_ID_SPLL;
2065	break;
2066	case PORT_CLK_SEL_LCPLL_810:
2067	id = DPLL_ID_LCPLL_810;
2068	break;
2069	case PORT_CLK_SEL_LCPLL_1350:
2070	id = DPLL_ID_LCPLL_1350;
2071	break;
2072	case PORT_CLK_SEL_LCPLL_2700:
2073	id = DPLL_ID_LCPLL_2700;
2074	break;
2075	default:
2076	MISSING_CASE(tmp);
2077	fallthrough;
2078	case PORT_CLK_SEL_NONE:
2079	return NULL;
2080	}
2081
2082	return intel_get_dpll_by_id(display, id);
2083	}
2084
2085	void intel_ddi_enable_clock(struct intel_encoder *encoder,
2086	const struct intel_crtc_state *crtc_state)
2087	{
2088	if (encoder->enable_clock)
2089	encoder->enable_clock(encoder, crtc_state);
2090	}
2091
2092	void intel_ddi_disable_clock(struct intel_encoder *encoder)
2093	{
2094	if (encoder->disable_clock)
2095	encoder->disable_clock(encoder);
2096	}
2097
2098	void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
2099	{
2100	struct intel_display *display = to_intel_display(encoder);
2101	u32 port_mask;
2102	bool ddi_clk_needed;
2103
2104	/*
2105	* In case of DP MST, we sanitize the primary encoder only, not the
2106	* virtual ones.
2107	*/
2108	if (encoder->type == INTEL_OUTPUT_DP_MST)
2109	return;
2110
2111	if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) {
2112	u8 pipe_mask;
2113	bool is_mst;
2114
2115	intel_ddi_get_encoder_pipes(encoder, pipe_mask: &pipe_mask, is_dp_mst: &is_mst);
2116	/*
2117	* In the unlikely case that BIOS enables DP in MST mode, just
2118	* warn since our MST HW readout is incomplete.
2119	*/
2120	if (drm_WARN_ON(display->drm, is_mst))
2121	return;
2122	}
2123
2124	port_mask = BIT(encoder->port);
2125	ddi_clk_needed = encoder->base.crtc;
2126
2127	if (encoder->type == INTEL_OUTPUT_DSI) {
2128	struct intel_encoder *other_encoder;
2129
2130	port_mask = intel_dsi_encoder_ports(encoder);
2131	/*
2132	* Sanity check that we haven't incorrectly registered another
2133	* encoder using any of the ports of this DSI encoder.
2134	*/
2135	for_each_intel_encoder(display->drm, other_encoder) {
2136	if (other_encoder == encoder)
2137	continue;
2138
2139	if (drm_WARN_ON(display->drm,
2140	port_mask & BIT(other_encoder->port)))
2141	return;
2142	}
2143	/*
2144	* For DSI we keep the ddi clocks gated
2145	* except during enable/disable sequence.
2146	*/
2147	ddi_clk_needed = false;
2148	}
2149
2150	if (ddi_clk_needed || !encoder->is_clock_enabled ||
2151	!encoder->is_clock_enabled(encoder))
2152	return;
2153
2154	drm_dbg_kms(display->drm,
2155	"[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it\n",
2156	encoder->base.base.id, encoder->base.name);
2157
2158	encoder->disable_clock(encoder);
2159	}
2160
2161	static void
2162	tgl_dkl_phy_check_and_rewrite(struct intel_display *display,
2163	enum tc_port tc_port, u32 ln0, u32 ln1)
2164	{
2165	if (ln0 != intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 0)))
2166	intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 0), val: ln0);
2167	if (ln1 != intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 1)))
2168	intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 1), val: ln1);
2169	}
2170
2171	static void
2172	icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
2173	const struct intel_crtc_state *crtc_state)
2174	{
2175	struct intel_display *display = to_intel_display(crtc_state);
2176	enum tc_port tc_port = intel_encoder_to_tc(encoder: &dig_port->base);
2177	enum intel_tc_pin_assignment pin_assignment;
2178	u32 ln0, ln1;
2179	u8 width;
2180
2181	if (DISPLAY_VER(display) >= 14)
2182	return;
2183
2184	if (!intel_encoder_is_tc(encoder: &dig_port->base) ||
2185	intel_tc_port_in_tbt_alt_mode(dig_port))
2186	return;
2187
2188	if (DISPLAY_VER(display) >= 12) {
2189	ln0 = intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 0));
2190	ln1 = intel_dkl_phy_read(display, DKL_DP_MODE(tc_port, 1));
2191	} else {
2192	ln0 = intel_de_read(display, MG_DP_MODE(0, tc_port));
2193	ln1 = intel_de_read(display, MG_DP_MODE(1, tc_port));
2194	}
2195
2196	ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
2197	ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
2198
2199	/* DPPATC */
2200	pin_assignment = intel_tc_port_get_pin_assignment(dig_port);
2201	width = crtc_state->lane_count;
2202
2203	switch (pin_assignment) {
2204	case INTEL_TC_PIN_ASSIGNMENT_NONE:
2205	drm_WARN_ON(display->drm,
2206	!intel_tc_port_in_legacy_mode(dig_port));
2207	if (width == 1) {
2208	ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
2209	} else {
2210	ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2211	ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2212	}
2213	break;
2214	case INTEL_TC_PIN_ASSIGNMENT_A:
2215	if (width == 4) {
2216	ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2217	ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2218	}
2219	break;
2220	case INTEL_TC_PIN_ASSIGNMENT_B:
2221	if (width == 2) {
2222	ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2223	ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2224	}
2225	break;
2226	case INTEL_TC_PIN_ASSIGNMENT_C:
2227	case INTEL_TC_PIN_ASSIGNMENT_E:
2228	if (width == 1) {
2229	ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
2230	ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
2231	} else {
2232	ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2233	ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2234	}
2235	break;
2236	case INTEL_TC_PIN_ASSIGNMENT_D:
2237	case INTEL_TC_PIN_ASSIGNMENT_F:
2238	if (width == 1) {
2239	ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
2240	ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
2241	} else {
2242	ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2243	ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2244	}
2245	break;
2246	default:
2247	MISSING_CASE(pin_assignment);
2248	}
2249
2250	if (DISPLAY_VER(display) >= 12) {
2251	intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 0), val: ln0);
2252	intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 1), val: ln1);
2253	/* WA_14018221282 */
2254	if (IS_DISPLAY_VER(display, 12, 13))
2255	tgl_dkl_phy_check_and_rewrite(display, tc_port, ln0, ln1);
2256
2257	} else {
2258	intel_de_write(display, MG_DP_MODE(0, tc_port), val: ln0);
2259	intel_de_write(display, MG_DP_MODE(1, tc_port), val: ln1);
2260	}
2261	}
2262
2263	static enum transcoder
2264	tgl_dp_tp_transcoder(const struct intel_crtc_state *crtc_state)
2265	{
2266	if (intel_crtc_has_type(crtc_state, type: INTEL_OUTPUT_DP_MST))
2267	return crtc_state->mst_master_transcoder;
2268	else
2269	return crtc_state->cpu_transcoder;
2270	}
2271
2272	i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder,
2273	const struct intel_crtc_state *crtc_state)
2274	{
2275	struct intel_display *display = to_intel_display(encoder);
2276
2277	if (DISPLAY_VER(display) >= 12)
2278	return TGL_DP_TP_CTL(display,
2279	tgl_dp_tp_transcoder(crtc_state));
2280	else
2281	return DP_TP_CTL(encoder->port);
2282	}
2283
2284	static i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder,
2285	const struct intel_crtc_state *crtc_state)
2286	{
2287	struct intel_display *display = to_intel_display(encoder);
2288
2289	if (DISPLAY_VER(display) >= 12)
2290	return TGL_DP_TP_STATUS(display,
2291	tgl_dp_tp_transcoder(crtc_state));
2292	else
2293	return DP_TP_STATUS(encoder->port);
2294	}
2295
2296	void intel_ddi_clear_act_sent(struct intel_encoder *encoder,
2297	const struct intel_crtc_state *crtc_state)
2298	{
2299	struct intel_display *display = to_intel_display(encoder);
2300
2301	intel_de_write(display, reg: dp_tp_status_reg(encoder, crtc_state),
2302	DP_TP_STATUS_ACT_SENT);
2303	}
2304
2305	void intel_ddi_wait_for_act_sent(struct intel_encoder *encoder,
2306	const struct intel_crtc_state *crtc_state)
2307	{
2308	struct intel_display *display = to_intel_display(encoder);
2309
2310	if (intel_de_wait_for_set_ms(display, reg: dp_tp_status_reg(encoder, crtc_state),
2311	DP_TP_STATUS_ACT_SENT, timeout_ms: 1))
2312	drm_err(display->drm, "Timed out waiting for ACT sent\n");
2313	}
2314
2315	static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel_dp,
2316	const struct intel_crtc_state *crtc_state,
2317	bool enable)
2318	{
2319	struct intel_display *display = to_intel_display(intel_dp);
2320
2321	if (!crtc_state->vrr.enable)
2322	return;
2323
2324	if (drm_dp_dpcd_writeb(aux: &intel_dp->aux, DP_DOWNSPREAD_CTRL,
2325	value: enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0) <= 0)
2326	drm_dbg_kms(display->drm,
2327	"Failed to %s MSA_TIMING_PAR_IGNORE in the sink\n",
2328	str_enable_disable(enable));
2329	}
2330
2331	static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
2332	const struct intel_crtc_state *crtc_state,
2333	bool enable)
2334	{
2335	struct intel_display *display = to_intel_display(intel_dp);
2336
2337	if (!crtc_state->fec_enable)
2338	return;
2339
2340	if (drm_dp_dpcd_writeb(aux: &intel_dp->aux, DP_FEC_CONFIGURATION,
2341	value: enable ? DP_FEC_READY : 0) <= 0)
2342	drm_dbg_kms(display->drm, "Failed to set FEC_READY to %s in the sink\n",
2343	str_enabled_disabled(enable));
2344
2345	if (enable &&
2346	drm_dp_dpcd_writeb(aux: &intel_dp->aux, DP_FEC_STATUS,
2347	DP_FEC_DECODE_EN_DETECTED | DP_FEC_DECODE_DIS_DETECTED) <= 0)
2348	drm_dbg_kms(display->drm, "Failed to clear FEC detected flags\n");
2349	}
2350
2351	static int wait_for_fec_detected(struct drm_dp_aux *aux, bool enabled)
2352	{
2353	struct intel_display *display = to_intel_display(aux->drm_dev);
2354	int mask = enabled ? DP_FEC_DECODE_EN_DETECTED : DP_FEC_DECODE_DIS_DETECTED;
2355	u8 status = 0;
2356	int ret, err;
2357
2358	ret = poll_timeout_us(err = drm_dp_dpcd_read_byte(aux, DP_FEC_STATUS, &status),
2359	err || (status & mask),
2360	10 * 1000, 200 * 1000, false);
2361
2362	/* Either can be non-zero, but not both */
2363	ret = ret ?: err;
2364	if (ret) {
2365	drm_dbg_kms(display->drm,
2366	"Failed waiting for FEC %s to get detected: %d (status 0x%02x)\n",
2367	str_enabled_disabled(enabled), ret, status);
2368	return ret;
2369	}
2370
2371	return 0;
2372	}
2373
2374	int intel_ddi_wait_for_fec_status(struct intel_encoder *encoder,
2375	const struct intel_crtc_state *crtc_state,
2376	bool enabled)
2377	{
2378	struct intel_display *display = to_intel_display(encoder);
2379	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2380	int ret;
2381
2382	if (!crtc_state->fec_enable)
2383	return 0;
2384
2385	if (enabled)
2386	ret = intel_de_wait_for_set_ms(display, reg: dp_tp_status_reg(encoder, crtc_state),
2387	DP_TP_STATUS_FEC_ENABLE_LIVE, timeout_ms: 1);
2388	else
2389	ret = intel_de_wait_for_clear_ms(display, reg: dp_tp_status_reg(encoder, crtc_state),
2390	DP_TP_STATUS_FEC_ENABLE_LIVE, timeout_ms: 1);
2391
2392	if (ret) {
2393	drm_err(display->drm,
2394	"Timeout waiting for FEC live state to get %s\n",
2395	str_enabled_disabled(enabled));
2396	return ret;
2397	}
2398	/*
2399	* At least the Synoptics MST hub doesn't set the detected flag for
2400	* FEC decoding disabling so skip waiting for that.
2401	*/
2402	if (enabled) {
2403	ret = wait_for_fec_detected(aux: &intel_dp->aux, enabled);
2404	if (ret)
2405	return ret;
2406	}
2407
2408	return 0;
2409	}
2410
2411	static void intel_ddi_enable_fec(struct intel_encoder *encoder,
2412	const struct intel_crtc_state *crtc_state)
2413	{
2414	struct intel_display *display = to_intel_display(encoder);
2415	int i;
2416	int ret;
2417
2418	if (!crtc_state->fec_enable)
2419	return;
2420
2421	intel_de_rmw(display, reg: dp_tp_ctl_reg(encoder, crtc_state),
2422	clear: 0, DP_TP_CTL_FEC_ENABLE);
2423
2424	if (DISPLAY_VER(display) < 30)
2425	return;
2426
2427	ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, enabled: true);
2428	if (!ret)
2429	return;
2430
2431	for (i = 0; i < 3; i++) {
2432	drm_dbg_kms(display->drm, "Retry FEC enabling\n");
2433
2434	intel_de_rmw(display, reg: dp_tp_ctl_reg(encoder, crtc_state),
2435	DP_TP_CTL_FEC_ENABLE, set: 0);
2436
2437	ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, enabled: false);
2438	if (ret)
2439	continue;
2440
2441	intel_de_rmw(display, reg: dp_tp_ctl_reg(encoder, crtc_state),
2442	clear: 0, DP_TP_CTL_FEC_ENABLE);
2443
2444	ret = intel_ddi_wait_for_fec_status(encoder, crtc_state, enabled: true);
2445	if (!ret)
2446	return;
2447	}
2448
2449	drm_err(display->drm, "Failed to enable FEC after retries\n");
2450	}
2451
2452	static void intel_ddi_disable_fec(struct intel_encoder *encoder,
2453	const struct intel_crtc_state *crtc_state)
2454	{
2455	struct intel_display *display = to_intel_display(encoder);
2456
2457	if (!crtc_state->fec_enable)
2458	return;
2459
2460	intel_de_rmw(display, reg: dp_tp_ctl_reg(encoder, crtc_state),
2461	DP_TP_CTL_FEC_ENABLE, set: 0);
2462	intel_de_posting_read(display, reg: dp_tp_ctl_reg(encoder, crtc_state));
2463	}
2464
2465	static void intel_ddi_power_up_lanes(struct intel_encoder *encoder,
2466	const struct intel_crtc_state *crtc_state)
2467	{
2468	struct intel_display *display = to_intel_display(encoder);
2469	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2470
2471	if (intel_encoder_is_combo(encoder)) {
2472	enum phy phy = intel_encoder_to_phy(encoder);
2473
2474	intel_combo_phy_power_up_lanes(display, phy, is_dsi: false,
2475	lane_count: crtc_state->lane_count,
2476	lane_reversal: dig_port->lane_reversal);
2477	}
2478	}
2479
2480	/*
2481	* Splitter enable for eDP MSO is limited to certain pipes, on certain
2482	* platforms.
2483	*/
2484	static u8 intel_ddi_splitter_pipe_mask(struct intel_display *display)
2485	{
2486	if (DISPLAY_VER(display) > 20)
2487	return ~0;
2488	else if (display->platform.alderlake_p)
2489	return BIT(PIPE_A) | BIT(PIPE_B);
2490	else
2491	return BIT(PIPE_A);
2492	}
2493
2494	static void intel_ddi_mso_get_config(struct intel_encoder *encoder,
2495	struct intel_crtc_state *pipe_config)
2496	{
2497	struct intel_display *display = to_intel_display(pipe_config);
2498	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
2499	enum pipe pipe = crtc->pipe;
2500	u32 dss1;
2501
2502	if (!HAS_MSO(display))
2503	return;
2504
2505	dss1 = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe));
2506
2507	pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE;
2508	if (!pipe_config->splitter.enable)
2509	return;
2510
2511	if (drm_WARN_ON(display->drm, !(intel_ddi_splitter_pipe_mask(display) & BIT(pipe)))) {
2512	pipe_config->splitter.enable = false;
2513	return;
2514	}
2515
2516	switch (dss1 & SPLITTER_CONFIGURATION_MASK) {
2517	default:
2518	drm_WARN(display->drm, true,
2519	"Invalid splitter configuration, dss1=0x%08x\n", dss1);
2520	fallthrough;
2521	case SPLITTER_CONFIGURATION_2_SEGMENT:
2522	pipe_config->splitter.link_count = 2;
2523	break;
2524	case SPLITTER_CONFIGURATION_4_SEGMENT:
2525	pipe_config->splitter.link_count = 4;
2526	break;
2527	}
2528
2529	pipe_config->splitter.pixel_overlap = REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1);
2530	}
2531
2532	static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state)
2533	{
2534	struct intel_display *display = to_intel_display(crtc_state);
2535	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2536	enum pipe pipe = crtc->pipe;
2537	u32 dss1 = 0;
2538
2539	if (!HAS_MSO(display))
2540	return;
2541
2542	if (crtc_state->splitter.enable) {
2543	dss1 |= SPLITTER_ENABLE;
2544	dss1 |= OVERLAP_PIXELS(crtc_state->splitter.pixel_overlap);
2545	if (crtc_state->splitter.link_count == 2)
2546	dss1 |= SPLITTER_CONFIGURATION_2_SEGMENT;
2547	else
2548	dss1 |= SPLITTER_CONFIGURATION_4_SEGMENT;
2549	}
2550
2551	intel_de_rmw(display, ICL_PIPE_DSS_CTL1(pipe),
2552	SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK |
2553	OVERLAP_PIXELS_MASK, set: dss1);
2554	}
2555
2556	static void
2557	mtl_ddi_enable_d2d(struct intel_encoder *encoder)
2558	{
2559	struct intel_display *display = to_intel_display(encoder);
2560	enum port port = encoder->port;
2561	i915_reg_t reg;
2562	u32 set_bits, wait_bits;
2563	int ret;
2564
2565	if (DISPLAY_VER(display) < 14)
2566	return;
2567
2568	if (DISPLAY_VER(display) >= 20) {
2569	reg = DDI_BUF_CTL(port);
2570	set_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
2571	wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE;
2572	} else {
2573	reg = XELPDP_PORT_BUF_CTL1(display, port);
2574	set_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE;
2575	wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE;
2576	}
2577
2578	intel_de_rmw(display, reg, clear: 0, set: set_bits);
2579
2580	ret = intel_de_wait_for_set_us(display, reg, mask: wait_bits, timeout_us: 100);
2581	if (ret) {
2582	drm_err(display->drm, "Timeout waiting for D2D Link enable for DDI/PORT_BUF_CTL %c\n",
2583	port_name(port));
2584	}
2585	}
2586
2587	static void mtl_port_buf_ctl_program(struct intel_encoder *encoder,
2588	const struct intel_crtc_state *crtc_state)
2589	{
2590	struct intel_display *display = to_intel_display(encoder);
2591	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2592	enum port port = encoder->port;
2593	u32 val = 0;
2594
2595	val |= XELPDP_PORT_WIDTH(crtc_state->lane_count);
2596
2597	if (intel_dp_is_uhbr(crtc_state))
2598	val |= XELPDP_PORT_BUF_PORT_DATA_40BIT;
2599	else
2600	val |= XELPDP_PORT_BUF_PORT_DATA_10BIT;
2601
2602	if (dig_port->lane_reversal)
2603	val |= XELPDP_PORT_REVERSAL;
2604
2605	intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, port),
2606	XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK,
2607	set: val);
2608	}
2609
2610	static void mtl_port_buf_ctl_io_selection(struct intel_encoder *encoder)
2611	{
2612	struct intel_display *display = to_intel_display(encoder);
2613	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2614	u32 val;
2615
2616	val = intel_tc_port_in_tbt_alt_mode(dig_port) ?
2617	XELPDP_PORT_BUF_IO_SELECT_TBT : 0;
2618	intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder->port),
2619	XELPDP_PORT_BUF_IO_SELECT_TBT, set: val);
2620	}
2621
2622	static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state,
2623	struct intel_encoder *encoder,
2624	const struct intel_crtc_state *crtc_state,
2625	const struct drm_connector_state *conn_state)
2626	{
2627	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2628	bool is_mst = intel_crtc_has_type(crtc_state, type: INTEL_OUTPUT_DP_MST);
2629	bool transparent_mode;
2630	int ret;
2631
2632	intel_dp_set_link_params(intel_dp,
2633	link_rate: crtc_state->port_clock,
2634	lane_count: crtc_state->lane_count);
2635
2636	/*
2637	* We only configure what the register value will be here. Actual
2638	* enabling happens during link training farther down.
2639	*/
2640	intel_ddi_init_dp_buf_reg(encoder, crtc_state);
2641
2642	/*
2643	* 1. Enable Power Wells
2644	*
2645	* This was handled at the beginning of intel_atomic_commit_tail(),
2646	* before we called down into this function.
2647	*/
2648
2649	/* 2. PMdemand was already set */
2650
2651	/* 3. Select Thunderbolt */
2652	mtl_port_buf_ctl_io_selection(encoder);
2653
2654	/* 4. Enable Panel Power if PPS is required */
2655	intel_pps_on(intel_dp);
2656
2657	/* 5. Enable the port PLL */
2658	intel_ddi_enable_clock(encoder, crtc_state);
2659
2660	/*
2661	* 6.a Configure Transcoder Clock Select to direct the Port clock to the
2662	* Transcoder.
2663	*/
2664	intel_ddi_enable_transcoder_clock(encoder, crtc_state);
2665
2666	/*
2667	* 6.b If DP v2.0/128b mode - Configure TRANS_DP2_CTL register settings.
2668	* 6.c Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST
2669	* Transport Select
2670	*/
2671	intel_ddi_config_transcoder_func(encoder, crtc_state);
2672
2673	/*
2674	* 6.e Program CoG/MSO configuration bits in DSS_CTL1 if selected.
2675	*/
2676	intel_ddi_mso_configure(crtc_state);
2677
2678	if (!is_mst)
2679	intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
2680
2681	transparent_mode = intel_dp_lttpr_transparent_mode_enabled(intel_dp);
2682	drm_dp_lttpr_wake_timeout_setup(aux: &intel_dp->aux, transparent_mode);
2683
2684	intel_dp_configure_protocol_converter(intel_dp, crtc_state);
2685	if (!is_mst)
2686	intel_dp_sink_enable_decompression(state,
2687	to_intel_connector(conn_state->connector),
2688	new_crtc_state: crtc_state);
2689
2690	/*
2691	* DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit
2692	* in the FEC_CONFIGURATION register to 1 before initiating link
2693	* training
2694	*/
2695	intel_dp_sink_set_fec_ready(intel_dp, crtc_state, enable: true);
2696
2697	intel_dp_check_frl_training(intel_dp);
2698	intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
2699
2700	/*
2701	* 6. The rest of the below are substeps under the bspec's "Enable and
2702	* Train Display Port" step. Note that steps that are specific to
2703	* MST will be handled by intel_mst_pre_enable_dp() before/after it
2704	* calls into this function. Also intel_mst_pre_enable_dp() only calls
2705	* us when active_mst_links==0, so any steps designated for "single
2706	* stream or multi-stream master transcoder" can just be performed
2707	* unconditionally here.
2708	*
2709	* mtl_ddi_prepare_link_retrain() that is called by
2710	* intel_dp_start_link_train() will execute steps: 6.d, 6.f, 6.g, 6.h,
2711	* 6.i and 6.j
2712	*
2713	* 6.k Follow DisplayPort specification training sequence (see notes for
2714	* failure handling)
2715	* 6.m If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle
2716	* Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent)
2717	* (timeout after 800 us)
2718	*/
2719	intel_dp_start_link_train(state, intel_dp, crtc_state);
2720
2721	/* 6.n Set DP_TP_CTL link training to Normal */
2722	if (!is_trans_port_sync_mode(state: crtc_state))
2723	intel_dp_stop_link_train(intel_dp, crtc_state);
2724
2725	/* 6.o Configure and enable FEC if needed */
2726	intel_ddi_enable_fec(encoder, crtc_state);
2727
2728	/* 7.a 128b/132b SST. */
2729	if (!is_mst && intel_dp_is_uhbr(crtc_state)) {
2730	/* VCPID 1, start slot 0 for 128b/132b, tu slots */
2731	ret = drm_dp_dpcd_write_payload(aux: &intel_dp->aux, vcpid: 1, start_time_slot: 0, time_slot_count: crtc_state->dp_m_n.tu);
2732	if (ret < 0)
2733	intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state);
2734	}
2735
2736	if (!is_mst)
2737	intel_dsc_dp_pps_write(encoder, crtc_state);
2738	}
2739
2740	static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
2741	struct intel_encoder *encoder,
2742	const struct intel_crtc_state *crtc_state,
2743	const struct drm_connector_state *conn_state)
2744	{
2745	struct intel_display *display = to_intel_display(encoder);
2746	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2747	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2748	bool is_mst = intel_crtc_has_type(crtc_state, type: INTEL_OUTPUT_DP_MST);
2749	int ret;
2750
2751	intel_dp_set_link_params(intel_dp,
2752	link_rate: crtc_state->port_clock,
2753	lane_count: crtc_state->lane_count);
2754
2755	/*
2756	* We only configure what the register value will be here. Actual
2757	* enabling happens during link training farther down.
2758	*/
2759	intel_ddi_init_dp_buf_reg(encoder, crtc_state);
2760
2761	/*
2762	* 1. Enable Power Wells
2763	*
2764	* This was handled at the beginning of intel_atomic_commit_tail(),
2765	* before we called down into this function.
2766	*/
2767
2768	/* 2. Enable Panel Power if PPS is required */
2769	intel_pps_on(intel_dp);
2770
2771	/*
2772	* 3. For non-TBT Type-C ports, set FIA lane count
2773	* (DFLEXDPSP.DPX4TXLATC)
2774	*
2775	* This was done before tgl_ddi_pre_enable_dp by
2776	* hsw_crtc_enable()->intel_encoders_pre_pll_enable().
2777	*/
2778
2779	/*
2780	* 4. Enable the port PLL.
2781	*
2782	* The PLL enabling itself was already done before this function by
2783	* hsw_crtc_enable()->intel_enable_dpll(). We need only
2784	* configure the PLL to port mapping here.
2785	*/
2786	intel_ddi_enable_clock(encoder, crtc_state);
2787
2788	/* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */
2789	if (!intel_tc_port_in_tbt_alt_mode(dig_port)) {
2790	drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref);
2791	dig_port->ddi_io_wakeref = intel_display_power_get(display,
2792	domain: dig_port->ddi_io_power_domain);
2793	}
2794
2795	/* 6. Program DP_MODE */
2796	icl_program_mg_dp_mode(dig_port, crtc_state);
2797
2798	/*
2799	* 7. The rest of the below are substeps under the bspec's "Enable and
2800	* Train Display Port" step. Note that steps that are specific to
2801	* MST will be handled by intel_mst_pre_enable_dp() before/after it
2802	* calls into this function. Also intel_mst_pre_enable_dp() only calls
2803	* us when active_mst_links==0, so any steps designated for "single
2804	* stream or multi-stream master transcoder" can just be performed
2805	* unconditionally here.
2806	*/
2807
2808	/*
2809	* 7.a Configure Transcoder Clock Select to direct the Port clock to the
2810	* Transcoder.
2811	*/
2812	intel_ddi_enable_transcoder_clock(encoder, crtc_state);
2813
2814	/*
2815	* 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST
2816	* Transport Select
2817	*/
2818	intel_ddi_config_transcoder_func(encoder, crtc_state);
2819
2820	/*
2821	* 7.c Configure & enable DP_TP_CTL with link training pattern 1
2822	* selected
2823	*
2824	* This will be handled by the intel_dp_start_link_train() farther
2825	* down this function.
2826	*/
2827
2828	/* 7.e Configure voltage swing and related IO settings */
2829	encoder->set_signal_levels(encoder, crtc_state);
2830
2831	/*
2832	* 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up
2833	* the used lanes of the DDI.
2834	*/
2835	intel_ddi_power_up_lanes(encoder, crtc_state);
2836
2837	/*
2838	* 7.g Program CoG/MSO configuration bits in DSS_CTL1 if selected.
2839	*/
2840	intel_ddi_mso_configure(crtc_state);
2841
2842	if (!is_mst)
2843	intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
2844
2845	intel_dp_configure_protocol_converter(intel_dp, crtc_state);
2846	if (!is_mst)
2847	intel_dp_sink_enable_decompression(state,
2848	to_intel_connector(conn_state->connector),
2849	new_crtc_state: crtc_state);
2850	/*
2851	* DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit
2852	* in the FEC_CONFIGURATION register to 1 before initiating link
2853	* training
2854	*/
2855	intel_dp_sink_set_fec_ready(intel_dp, crtc_state, enable: true);
2856
2857	intel_dp_check_frl_training(intel_dp);
2858	intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
2859
2860	/*
2861	* 7.i Follow DisplayPort specification training sequence (see notes for
2862	* failure handling)
2863	* 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle
2864	* Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent)
2865	* (timeout after 800 us)
2866	*/
2867	intel_dp_start_link_train(state, intel_dp, crtc_state);
2868
2869	/* 7.k Set DP_TP_CTL link training to Normal */
2870	if (!is_trans_port_sync_mode(state: crtc_state))
2871	intel_dp_stop_link_train(intel_dp, crtc_state);
2872
2873	/* 7.l Configure and enable FEC if needed */
2874	intel_ddi_enable_fec(encoder, crtc_state);
2875
2876	if (!is_mst && intel_dp_is_uhbr(crtc_state)) {
2877	/* VCPID 1, start slot 0 for 128b/132b, tu slots */
2878	ret = drm_dp_dpcd_write_payload(aux: &intel_dp->aux, vcpid: 1, start_time_slot: 0, time_slot_count: crtc_state->dp_m_n.tu);
2879	if (ret < 0)
2880	intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state);
2881	}
2882
2883	if (!is_mst)
2884	intel_dsc_dp_pps_write(encoder, crtc_state);
2885	}
2886
2887	static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
2888	struct intel_encoder *encoder,
2889	const struct intel_crtc_state *crtc_state,
2890	const struct drm_connector_state *conn_state)
2891	{
2892	struct intel_display *display = to_intel_display(encoder);
2893	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2894	enum port port = encoder->port;
2895	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2896	bool is_mst = intel_crtc_has_type(crtc_state, type: INTEL_OUTPUT_DP_MST);
2897
2898	if (DISPLAY_VER(display) < 11)
2899	drm_WARN_ON(display->drm,
2900	is_mst && (port == PORT_A || port == PORT_E));
2901	else
2902	drm_WARN_ON(display->drm, is_mst && port == PORT_A);
2903
2904	intel_dp_set_link_params(intel_dp,
2905	link_rate: crtc_state->port_clock,
2906	lane_count: crtc_state->lane_count);
2907
2908	/*
2909	* We only configure what the register value will be here. Actual
2910	* enabling happens during link training farther down.
2911	*/
2912	intel_ddi_init_dp_buf_reg(encoder, crtc_state);
2913
2914	intel_pps_on(intel_dp);
2915
2916	intel_ddi_enable_clock(encoder, crtc_state);
2917
2918	if (!intel_tc_port_in_tbt_alt_mode(dig_port)) {
2919	drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref);
2920	dig_port->ddi_io_wakeref = intel_display_power_get(display,
2921	domain: dig_port->ddi_io_power_domain);
2922	}
2923
2924	icl_program_mg_dp_mode(dig_port, crtc_state);
2925
2926	if (has_buf_trans_select(display))
2927	hsw_prepare_dp_ddi_buffers(encoder, crtc_state);
2928
2929	encoder->set_signal_levels(encoder, crtc_state);
2930
2931	intel_ddi_power_up_lanes(encoder, crtc_state);
2932
2933	if (!is_mst)
2934	intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
2935	intel_dp_configure_protocol_converter(intel_dp, crtc_state);
2936	if (!is_mst)
2937	intel_dp_sink_enable_decompression(state,
2938	to_intel_connector(conn_state->connector),
2939	new_crtc_state: crtc_state);
2940	intel_dp_sink_set_fec_ready(intel_dp, crtc_state, enable: true);
2941	intel_dp_start_link_train(state, intel_dp, crtc_state);
2942	if ((port != PORT_A || DISPLAY_VER(display) >= 9) &&
2943	!is_trans_port_sync_mode(state: crtc_state))
2944	intel_dp_stop_link_train(intel_dp, crtc_state);
2945
2946	intel_ddi_enable_fec(encoder, crtc_state);
2947
2948	if (!is_mst) {
2949	intel_ddi_enable_transcoder_clock(encoder, crtc_state);
2950	intel_dsc_dp_pps_write(encoder, crtc_state);
2951	}
2952	}
2953
2954	static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,
2955	struct intel_encoder *encoder,
2956	const struct intel_crtc_state *crtc_state,
2957	const struct drm_connector_state *conn_state)
2958	{
2959	struct intel_display *display = to_intel_display(encoder);
2960
2961	if (HAS_DP20(display))
2962	intel_dp_128b132b_sdp_crc16(intel_dp: enc_to_intel_dp(encoder),
2963	crtc_state);
2964
2965	/* Panel replay has to be enabled in sink dpcd before link training. */
2966	intel_psr_panel_replay_enable_sink(intel_dp: enc_to_intel_dp(encoder));
2967
2968	if (DISPLAY_VER(display) >= 14)
2969	mtl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
2970	else if (DISPLAY_VER(display) >= 12)
2971	tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
2972	else
2973	hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
2974
2975	/* MST will call a setting of MSA after an allocating of Virtual Channel
2976	* from MST encoder pre_enable callback.
2977	*/
2978	if (!intel_crtc_has_type(crtc_state, type: INTEL_OUTPUT_DP_MST))
2979	intel_ddi_set_dp_msa(crtc_state, conn_state);
2980	}
2981
2982	static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state,
2983	struct intel_encoder *encoder,
2984	const struct intel_crtc_state *crtc_state,
2985	const struct drm_connector_state *conn_state)
2986	{
2987	struct intel_display *display = to_intel_display(encoder);
2988	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2989	struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
2990
2991	intel_dp_dual_mode_set_tmds_output(hdmi: intel_hdmi, enable: true);
2992	intel_ddi_enable_clock(encoder, crtc_state);
2993
2994	drm_WARN_ON(display->drm, dig_port->ddi_io_wakeref);
2995	dig_port->ddi_io_wakeref = intel_display_power_get(display,
2996	domain: dig_port->ddi_io_power_domain);
2997
2998	icl_program_mg_dp_mode(dig_port, crtc_state);
2999
3000	intel_ddi_enable_transcoder_clock(encoder, crtc_state);
3001
3002	dig_port->set_infoframes(encoder,
3003	crtc_state->has_infoframe,
3004	crtc_state, conn_state);
3005	}
3006
3007	/*
3008	* Note: Also called from the ->pre_enable of the first active MST stream
3009	* encoder on its primary encoder.
3010	*
3011	* When called from DP MST code:
3012	*
3013	* - conn_state will be NULL
3014	*
3015	* - encoder will be the primary encoder (i.e. mst->primary)
3016	*
3017	* - the main connector associated with this port won't be active or linked to a
3018	* crtc
3019	*
3020	* - crtc_state will be the state of the first stream to be activated on this
3021	* port, and it may not be the same stream that will be deactivated last, but
3022	* each stream should have a state that is identical when it comes to the DP
3023	* link parameters.
3024	*/
3025	static void intel_ddi_pre_enable(struct intel_atomic_state *state,
3026	struct intel_encoder *encoder,
3027	const struct intel_crtc_state *crtc_state,
3028	const struct drm_connector_state *conn_state)
3029	{
3030	struct intel_display *display = to_intel_display(state);
3031	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3032	enum pipe pipe = crtc->pipe;
3033
3034	drm_WARN_ON(display->drm, crtc_state->has_pch_encoder);
3035
3036	intel_set_cpu_fifo_underrun_reporting(display, pipe, enable: true);
3037
3038	if (intel_crtc_has_type(crtc_state, type: INTEL_OUTPUT_HDMI)) {
3039	intel_ddi_pre_enable_hdmi(state, encoder, crtc_state,
3040	conn_state);
3041	} else {
3042	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3043
3044	intel_ddi_pre_enable_dp(state, encoder, crtc_state,
3045	conn_state);
3046
3047	/* FIXME precompute everything properly */
3048	/* FIXME how do we turn infoframes off again? */
3049	if (intel_lspcon_active(dig_port) && intel_dp_has_hdmi_sink(intel_dp: &dig_port->dp))
3050	dig_port->set_infoframes(encoder,
3051	crtc_state->has_infoframe,
3052	crtc_state, conn_state);
3053	}
3054	}
3055
3056	static void
3057	mtl_ddi_disable_d2d(struct intel_encoder *encoder)
3058	{
3059	struct intel_display *display = to_intel_display(encoder);
3060	enum port port = encoder->port;
3061	i915_reg_t reg;
3062	u32 clr_bits, wait_bits;
3063	int ret;
3064
3065	if (DISPLAY_VER(display) < 14)
3066	return;
3067
3068	if (DISPLAY_VER(display) >= 20) {
3069	reg = DDI_BUF_CTL(port);
3070	clr_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
3071	wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE;
3072	} else {
3073	reg = XELPDP_PORT_BUF_CTL1(display, port);
3074	clr_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE;
3075	wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE;
3076	}
3077
3078	intel_de_rmw(display, reg, clear: clr_bits, set: 0);
3079
3080	ret = intel_de_wait_for_clear_us(display, reg, mask: wait_bits, timeout_us: 100);
3081	if (ret)
3082	drm_err(display->drm, "Timeout waiting for D2D Link disable for DDI/PORT_BUF_CTL %c\n",
3083	port_name(port));
3084	}
3085
3086	static void intel_ddi_buf_enable(struct intel_encoder *encoder, u32 buf_ctl)
3087	{
3088	struct intel_display *display = to_intel_display(encoder);
3089	enum port port = encoder->port;
3090
3091	intel_de_write(display, DDI_BUF_CTL(port), val: buf_ctl | DDI_BUF_CTL_ENABLE);
3092	intel_de_posting_read(display, DDI_BUF_CTL(port));
3093
3094	intel_wait_ddi_buf_active(encoder);
3095	}
3096
3097	static void intel_ddi_buf_disable(struct intel_encoder *encoder,
3098	const struct intel_crtc_state *crtc_state)
3099	{
3100	struct intel_display *display = to_intel_display(encoder);
3101	enum port port = encoder->port;
3102
3103	intel_de_rmw(display, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, set: 0);
3104
3105	if (DISPLAY_VER(display) >= 14)
3106	intel_wait_ddi_buf_idle(display, port);
3107
3108	mtl_ddi_disable_d2d(encoder);
3109
3110	if (intel_crtc_has_dp_encoder(crtc_state)) {
3111	intel_de_rmw(display, reg: dp_tp_ctl_reg(encoder, crtc_state),
3112	DP_TP_CTL_ENABLE, set: 0);
3113	}
3114
3115	intel_ddi_disable_fec(encoder, crtc_state);
3116
3117	if (DISPLAY_VER(display) < 14)
3118	intel_wait_ddi_buf_idle(display, port);
3119
3120	intel_ddi_wait_for_fec_status(encoder, crtc_state, enabled: false);
3121	}
3122
3123	static void intel_ddi_post_disable_dp(struct intel_atomic_state *state,
3124	struct intel_encoder *encoder,
3125	const struct intel_crtc_state *old_crtc_state,
3126	const struct drm_connector_state *old_conn_state)
3127	{
3128	struct intel_display *display = to_intel_display(encoder);
3129	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3130	struct intel_dp *intel_dp = &dig_port->dp;
3131	intel_wakeref_t wakeref;
3132	bool is_mst = intel_crtc_has_type(crtc_state: old_crtc_state,
3133	type: INTEL_OUTPUT_DP_MST);
3134
3135	if (!is_mst)
3136	intel_dp_set_infoframes(encoder, enable: false,
3137	crtc_state: old_crtc_state, conn_state: old_conn_state);
3138
3139	/*
3140	* Power down sink before disabling the port, otherwise we end
3141	* up getting interrupts from the sink on detecting link loss.
3142	*/
3143	intel_dp_set_power(intel_dp, DP_SET_POWER_D3);
3144
3145	if (DISPLAY_VER(display) >= 12) {
3146	if (is_mst || intel_dp_is_uhbr(crtc_state: old_crtc_state)) {
3147	enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
3148
3149	intel_de_rmw(display,
3150	TRANS_DDI_FUNC_CTL(display, cpu_transcoder),
3151	TGL_TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK,
3152	set: 0);
3153	}
3154	} else {
3155	if (!is_mst)
3156	intel_ddi_disable_transcoder_clock(crtc_state: old_crtc_state);
3157	}
3158
3159	intel_ddi_buf_disable(encoder, crtc_state: old_crtc_state);
3160
3161	intel_dp_sink_set_fec_ready(intel_dp, crtc_state: old_crtc_state, enable: false);
3162
3163	intel_ddi_config_transcoder_dp2(crtc_state: old_crtc_state, enable: false);
3164
3165	/*
3166	* From TGL spec: "If single stream or multi-stream master transcoder:
3167	* Configure Transcoder Clock select to direct no clock to the
3168	* transcoder"
3169	*/
3170	if (DISPLAY_VER(display) >= 12)
3171	intel_ddi_disable_transcoder_clock(crtc_state: old_crtc_state);
3172
3173	intel_pps_vdd_on(intel_dp);
3174	intel_pps_off(intel_dp);
3175
3176	wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref);
3177
3178	if (wakeref)
3179	intel_display_power_put(display,
3180	domain: dig_port->ddi_io_power_domain,
3181	wakeref);
3182
3183	intel_ddi_disable_clock(encoder);
3184
3185	/* De-select Thunderbolt */
3186	if (DISPLAY_VER(display) >= 14)
3187	intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder->port),
3188	XELPDP_PORT_BUF_IO_SELECT_TBT, set: 0);
3189	}
3190
3191	static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state,
3192	struct intel_encoder *encoder,
3193	const struct intel_crtc_state *old_crtc_state,
3194	const struct drm_connector_state *old_conn_state)
3195	{
3196	struct intel_display *display = to_intel_display(encoder);
3197	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3198	struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
3199	intel_wakeref_t wakeref;
3200
3201	dig_port->set_infoframes(encoder, false,
3202	old_crtc_state, old_conn_state);
3203
3204	if (DISPLAY_VER(display) < 12)
3205	intel_ddi_disable_transcoder_clock(crtc_state: old_crtc_state);
3206
3207	intel_ddi_buf_disable(encoder, crtc_state: old_crtc_state);
3208
3209	if (DISPLAY_VER(display) >= 12)
3210	intel_ddi_disable_transcoder_clock(crtc_state: old_crtc_state);
3211
3212	wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref);
3213	if (wakeref)
3214	intel_display_power_put(display,
3215	domain: dig_port->ddi_io_power_domain,
3216	wakeref);
3217
3218	intel_ddi_disable_clock(encoder);
3219
3220	intel_dp_dual_mode_set_tmds_output(hdmi: intel_hdmi, enable: false);
3221	}
3222
3223	static void intel_ddi_post_disable_hdmi_or_sst(struct intel_atomic_state *state,
3224	struct intel_encoder *encoder,
3225	const struct intel_crtc_state *old_crtc_state,
3226	const struct drm_connector_state *old_conn_state)
3227	{
3228	struct intel_display *display = to_intel_display(encoder);
3229	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3230	struct intel_crtc *pipe_crtc;
3231	bool is_hdmi = intel_crtc_has_type(crtc_state: old_crtc_state, type: INTEL_OUTPUT_HDMI);
3232	int i;
3233
3234	for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) {
3235	const struct intel_crtc_state *old_pipe_crtc_state =
3236	intel_atomic_get_old_crtc_state(state, crtc: pipe_crtc);
3237
3238	intel_crtc_vblank_off(crtc_state: old_pipe_crtc_state);
3239	}
3240
3241	intel_disable_transcoder(old_crtc_state);
3242
3243	/* 128b/132b SST */
3244	if (!is_hdmi && intel_dp_is_uhbr(crtc_state: old_crtc_state)) {
3245	/* VCPID 1, start slot 0 for 128b/132b, clear */
3246	drm_dp_dpcd_write_payload(aux: &intel_dp->aux, vcpid: 1, start_time_slot: 0, time_slot_count: 0);
3247
3248	intel_ddi_clear_act_sent(encoder, crtc_state: old_crtc_state);
3249
3250	intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, old_crtc_state->cpu_transcoder),
3251	TRANS_DDI_DP_VC_PAYLOAD_ALLOC, set: 0);
3252
3253	intel_ddi_wait_for_act_sent(encoder, crtc_state: old_crtc_state);
3254	drm_dp_dpcd_poll_act_handled(aux: &intel_dp->aux, timeout_ms: 0);
3255	}
3256
3257	intel_vrr_transcoder_disable(crtc_state: old_crtc_state);
3258
3259	intel_ddi_disable_transcoder_func(crtc_state: old_crtc_state);
3260
3261	for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) {
3262	const struct intel_crtc_state *old_pipe_crtc_state =
3263	intel_atomic_get_old_crtc_state(state, crtc: pipe_crtc);
3264
3265	intel_dsc_disable(crtc_state: old_pipe_crtc_state);
3266
3267	if (DISPLAY_VER(display) >= 9)
3268	skl_scaler_disable(old_crtc_state: old_pipe_crtc_state);
3269	else
3270	ilk_pfit_disable(old_crtc_state: old_pipe_crtc_state);
3271	}
3272	}
3273
3274	/*
3275	* Note: Also called from the ->post_disable of the last active MST stream
3276	* encoder on its primary encoder. See also the comment for
3277	* intel_ddi_pre_enable().
3278	*/
3279	static void intel_ddi_post_disable(struct intel_atomic_state *state,
3280	struct intel_encoder *encoder,
3281	const struct intel_crtc_state *old_crtc_state,
3282	const struct drm_connector_state *old_conn_state)
3283	{
3284	if (!intel_crtc_has_type(crtc_state: old_crtc_state, type: INTEL_OUTPUT_DP_MST))
3285	intel_ddi_post_disable_hdmi_or_sst(state, encoder, old_crtc_state,
3286	old_conn_state);
3287
3288	/*
3289	* When called from DP MST code:
3290	* - old_conn_state will be NULL
3291	* - encoder will be the main encoder (ie. mst->primary)
3292	* - the main connector associated with this port
3293	* won't be active or linked to a crtc
3294	* - old_crtc_state will be the state of the last stream to
3295	* be deactivated on this port, and it may not be the same
3296	* stream that was activated last, but each stream
3297	* should have a state that is identical when it comes to
3298	* the DP link parameters
3299	*/
3300
3301	if (intel_crtc_has_type(crtc_state: old_crtc_state, type: INTEL_OUTPUT_HDMI))
3302	intel_ddi_post_disable_hdmi(state, encoder, old_crtc_state,
3303	old_conn_state);
3304	else
3305	intel_ddi_post_disable_dp(state, encoder, old_crtc_state,
3306	old_conn_state);
3307	}
3308
3309	/*
3310	* Note: Also called from the ->post_pll_disable of the last active MST stream
3311	* encoder on its primary encoder. See also the comment for
3312	* intel_ddi_pre_enable().
3313	*/
3314	static void intel_ddi_post_pll_disable(struct intel_atomic_state *state,
3315	struct intel_encoder *encoder,
3316	const struct intel_crtc_state *old_crtc_state,
3317	const struct drm_connector_state *old_conn_state)
3318	{
3319	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3320
3321	main_link_aux_power_domain_put(dig_port, crtc_state: old_crtc_state);
3322
3323	if (intel_encoder_is_tc(encoder))
3324	intel_tc_port_put_link(dig_port);
3325	}
3326
3327	static void trans_port_sync_stop_link_train(struct intel_atomic_state *state,
3328	struct intel_encoder *encoder,
3329	const struct intel_crtc_state *crtc_state)
3330	{
3331	const struct drm_connector_state *conn_state;
3332	struct drm_connector *conn;
3333	int i;
3334
3335	if (!crtc_state->sync_mode_slaves_mask)
3336	return;
3337
3338	for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
3339	struct intel_encoder *slave_encoder =
3340	to_intel_encoder(conn_state->best_encoder);
3341	struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc);
3342	const struct intel_crtc_state *slave_crtc_state;
3343
3344	if (!slave_crtc)
3345	continue;
3346
3347	slave_crtc_state =
3348	intel_atomic_get_new_crtc_state(state, crtc: slave_crtc);
3349
3350	if (slave_crtc_state->master_transcoder !=
3351	crtc_state->cpu_transcoder)
3352	continue;
3353
3354	intel_dp_stop_link_train(intel_dp: enc_to_intel_dp(encoder: slave_encoder),
3355	crtc_state: slave_crtc_state);
3356	}
3357
3358	usleep_range(min: 200, max: 400);
3359
3360	intel_dp_stop_link_train(intel_dp: enc_to_intel_dp(encoder),
3361	crtc_state);
3362	}
3363
3364	static void intel_ddi_enable_dp(struct intel_atomic_state *state,
3365	struct intel_encoder *encoder,
3366	const struct intel_crtc_state *crtc_state,
3367	const struct drm_connector_state *conn_state)
3368	{
3369	struct intel_display *display = to_intel_display(encoder);
3370	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3371	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3372	enum port port = encoder->port;
3373
3374	if (port == PORT_A && DISPLAY_VER(display) < 9)
3375	intel_dp_stop_link_train(intel_dp, crtc_state);
3376
3377	drm_connector_update_privacy_screen(connector_state: conn_state);
3378	intel_edp_backlight_on(crtc_state, conn_state);
3379
3380	intel_panel_prepare(crtc_state, conn_state);
3381
3382	if (!intel_lspcon_active(dig_port) || intel_dp_has_hdmi_sink(intel_dp: &dig_port->dp))
3383	intel_dp_set_infoframes(encoder, enable: true, crtc_state, conn_state);
3384
3385	trans_port_sync_stop_link_train(state, encoder, crtc_state);
3386	}
3387
3388	static i915_reg_t
3389	gen9_chicken_trans_reg_by_port(struct intel_display *display, enum port port)
3390	{
3391	static const enum transcoder trans[] = {
3392	[PORT_A] = TRANSCODER_EDP,
3393	[PORT_B] = TRANSCODER_A,
3394	[PORT_C] = TRANSCODER_B,
3395	[PORT_D] = TRANSCODER_C,
3396	[PORT_E] = TRANSCODER_A,
3397	};
3398
3399	drm_WARN_ON(display->drm, DISPLAY_VER(display) < 9);
3400
3401	if (drm_WARN_ON(display->drm, port < PORT_A || port > PORT_E))
3402	port = PORT_A;
3403
3404	return CHICKEN_TRANS(display, trans[port]);
3405	}
3406
3407	static void intel_ddi_enable_hdmi(struct intel_atomic_state *state,
3408	struct intel_encoder *encoder,
3409	const struct intel_crtc_state *crtc_state,
3410	const struct drm_connector_state *conn_state)
3411	{
3412	struct intel_display *display = to_intel_display(encoder);
3413	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3414	struct drm_connector *connector = conn_state->connector;
3415	enum port port = encoder->port;
3416	u32 buf_ctl = 0;
3417
3418	if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3419	high_tmds_clock_ratio: crtc_state->hdmi_high_tmds_clock_ratio,
3420	scrambling: crtc_state->hdmi_scrambling))
3421	drm_dbg_kms(display->drm,
3422	"[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n",
3423	connector->base.id, connector->name);
3424
3425	if (has_buf_trans_select(display))
3426	hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state);
3427
3428	/* e. Enable D2D Link for C10/C20 Phy */
3429	mtl_ddi_enable_d2d(encoder);
3430
3431	encoder->set_signal_levels(encoder, crtc_state);
3432
3433	/* Display WA #1143: skl,kbl,cfl */
3434	if (DISPLAY_VER(display) == 9 && !display->platform.broxton) {
3435	/*
3436	* For some reason these chicken bits have been
3437	* stuffed into a transcoder register, event though
3438	* the bits affect a specific DDI port rather than
3439	* a specific transcoder.
3440	*/
3441	i915_reg_t reg = gen9_chicken_trans_reg_by_port(display, port);
3442	u32 val;
3443
3444	val = intel_de_read(display, reg);
3445
3446	if (port == PORT_E)
3447	val |= DDIE_TRAINING_OVERRIDE_ENABLE |
3448	DDIE_TRAINING_OVERRIDE_VALUE;
3449	else
3450	val |= DDI_TRAINING_OVERRIDE_ENABLE |
3451	DDI_TRAINING_OVERRIDE_VALUE;
3452
3453	intel_de_write(display, reg, val);
3454	intel_de_posting_read(display, reg);
3455
3456	udelay(usec: 1);
3457
3458	if (port == PORT_E)
3459	val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE |
3460	DDIE_TRAINING_OVERRIDE_VALUE);
3461	else
3462	val &= ~(DDI_TRAINING_OVERRIDE_ENABLE |
3463	DDI_TRAINING_OVERRIDE_VALUE);
3464
3465	intel_de_write(display, reg, val);
3466	}
3467
3468	intel_ddi_power_up_lanes(encoder, crtc_state);
3469
3470	/* In HDMI/DVI mode, the port width, and swing/emphasis values
3471	* are ignored so nothing special needs to be done besides
3472	* enabling the port.
3473	*
3474	* On ADL_P the PHY link rate and lane count must be programmed but
3475	* these are both 0 for HDMI.
3476	*
3477	* But MTL onwards HDMI2.1 is supported and in TMDS mode this
3478	* is filled with lane count, already set in the crtc_state.
3479	* The same is required to be filled in PORT_BUF_CTL for C10/20 Phy.
3480	*/
3481	if (dig_port->lane_reversal)
3482	buf_ctl |= DDI_BUF_PORT_REVERSAL;
3483	if (dig_port->ddi_a_4_lanes)
3484	buf_ctl |= DDI_A_4_LANES;
3485
3486	if (DISPLAY_VER(display) >= 14) {
3487	u32 port_buf = 0;
3488
3489	port_buf |= XELPDP_PORT_WIDTH(crtc_state->lane_count);
3490
3491	if (dig_port->lane_reversal)
3492	port_buf |= XELPDP_PORT_REVERSAL;
3493
3494	intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, port),
3495	XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_REVERSAL, set: port_buf);
3496
3497	buf_ctl |= DDI_PORT_WIDTH(crtc_state->lane_count);
3498
3499	if (DISPLAY_VER(display) >= 20)
3500	buf_ctl |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
3501	} else if (display->platform.alderlake_p && intel_encoder_is_tc(encoder)) {
3502	drm_WARN_ON(display->drm, !intel_tc_port_in_legacy_mode(dig_port));
3503	buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
3504	}
3505
3506	intel_ddi_buf_enable(encoder, buf_ctl);
3507	}
3508
3509	static void intel_ddi_enable(struct intel_atomic_state *state,
3510	struct intel_encoder *encoder,
3511	const struct intel_crtc_state *crtc_state,
3512	const struct drm_connector_state *conn_state)
3513	{
3514	struct intel_display *display = to_intel_display(encoder);
3515	struct intel_crtc *pipe_crtc;
3516	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
3517	bool is_hdmi = intel_crtc_has_type(crtc_state, type: INTEL_OUTPUT_HDMI);
3518	int i;
3519
3520	/* 128b/132b SST */
3521	if (!is_hdmi && intel_dp_is_uhbr(crtc_state)) {
3522	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
3523	u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock);
3524
3525	intel_de_write(display, TRANS_DP2_VFREQHIGH(cpu_transcoder),
3526	TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz >> 24));
3527	intel_de_write(display, TRANS_DP2_VFREQLOW(cpu_transcoder),
3528	TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff));
3529	}
3530
3531	intel_ddi_enable_transcoder_func(encoder, crtc_state);
3532
3533	intel_vrr_transcoder_enable(crtc_state);
3534
3535	/* 128b/132b SST */
3536	if (!is_hdmi && intel_dp_is_uhbr(crtc_state)) {
3537	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3538
3539	intel_ddi_clear_act_sent(encoder, crtc_state);
3540
3541	intel_de_rmw(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder), clear: 0,
3542	TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
3543
3544	intel_ddi_wait_for_act_sent(encoder, crtc_state);
3545	drm_dp_dpcd_poll_act_handled(aux: &intel_dp->aux, timeout_ms: 0);
3546	}
3547
3548	intel_enable_transcoder(new_crtc_state: crtc_state);
3549
3550	intel_ddi_wait_for_fec_status(encoder, crtc_state, enabled: true);
3551
3552	for_each_pipe_crtc_modeset_enable(display, pipe_crtc, crtc_state, i) {
3553	const struct intel_crtc_state *pipe_crtc_state =
3554	intel_atomic_get_new_crtc_state(state, crtc: pipe_crtc);
3555
3556	intel_crtc_vblank_on(crtc_state: pipe_crtc_state);
3557	}
3558
3559	if (is_hdmi)
3560	intel_ddi_enable_hdmi(state, encoder, crtc_state, conn_state);
3561	else
3562	intel_ddi_enable_dp(state, encoder, crtc_state, conn_state);
3563
3564	intel_hdcp_enable(state, encoder, pipe_config: crtc_state, conn_state);
3565
3566	}
3567
3568	static void intel_ddi_disable_dp(struct intel_atomic_state *state,
3569	struct intel_encoder *encoder,
3570	const struct intel_crtc_state *old_crtc_state,
3571	const struct drm_connector_state *old_conn_state)
3572	{
3573	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3574	struct intel_connector *connector =
3575	to_intel_connector(old_conn_state->connector);
3576
3577	intel_dp->link.active = false;
3578
3579	intel_panel_unprepare(old_conn_state);
3580	intel_psr_disable(intel_dp, old_crtc_state);
3581	intel_alpm_disable(intel_dp);
3582	intel_edp_backlight_off(conn_state: old_conn_state);
3583	/* Disable the decompression in DP Sink */
3584	intel_dp_sink_disable_decompression(state,
3585	connector, old_crtc_state);
3586	/* Disable Ignore_MSA bit in DP Sink */
3587	intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, crtc_state: old_crtc_state,
3588	enable: false);
3589	}
3590
3591	static void intel_ddi_disable_hdmi(struct intel_atomic_state *state,
3592	struct intel_encoder *encoder,
3593	const struct intel_crtc_state *old_crtc_state,
3594	const struct drm_connector_state *old_conn_state)
3595	{
3596	struct intel_display *display = to_intel_display(encoder);
3597	struct drm_connector *connector = old_conn_state->connector;
3598
3599	if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3600	high_tmds_clock_ratio: false, scrambling: false))
3601	drm_dbg_kms(display->drm,
3602	"[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n",
3603	connector->base.id, connector->name);
3604	}
3605
3606	static void intel_ddi_disable(struct intel_atomic_state *state,
3607	struct intel_encoder *encoder,
3608	const struct intel_crtc_state *old_crtc_state,
3609	const struct drm_connector_state *old_conn_state)
3610	{
3611	intel_tc_port_link_cancel_reset_work(dig_port: enc_to_dig_port(encoder));
3612
3613	intel_hdcp_disable(to_intel_connector(old_conn_state->connector));
3614
3615	if (intel_crtc_has_type(crtc_state: old_crtc_state, type: INTEL_OUTPUT_HDMI))
3616	intel_ddi_disable_hdmi(state, encoder, old_crtc_state,
3617	old_conn_state);
3618	else
3619	intel_ddi_disable_dp(state, encoder, old_crtc_state,
3620	old_conn_state);
3621	}
3622
3623	static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state,
3624	struct intel_encoder *encoder,
3625	const struct intel_crtc_state *crtc_state,
3626	const struct drm_connector_state *conn_state)
3627	{
3628	intel_ddi_set_dp_msa(crtc_state, conn_state);
3629
3630	intel_dp_set_infoframes(encoder, enable: true, crtc_state, conn_state);
3631
3632	intel_backlight_update(state, encoder, crtc_state, conn_state);
3633	drm_connector_update_privacy_screen(connector_state: conn_state);
3634	}
3635
3636	static void intel_ddi_update_pipe_hdmi(struct intel_encoder *encoder,
3637	const struct intel_crtc_state *crtc_state,
3638	const struct drm_connector_state *conn_state)
3639	{
3640	intel_hdmi_fastset_infoframes(encoder, crtc_state, conn_state);
3641	}
3642
3643	void intel_ddi_update_pipe(struct intel_atomic_state *state,
3644	struct intel_encoder *encoder,
3645	const struct intel_crtc_state *crtc_state,
3646	const struct drm_connector_state *conn_state)
3647	{
3648
3649	if (!intel_crtc_has_type(crtc_state, type: INTEL_OUTPUT_HDMI) &&
3650	!intel_encoder_is_mst(encoder))
3651	intel_ddi_update_pipe_dp(state, encoder, crtc_state,
3652	conn_state);
3653
3654	if (intel_crtc_has_type(crtc_state, type: INTEL_OUTPUT_HDMI))
3655	intel_ddi_update_pipe_hdmi(encoder, crtc_state,
3656	conn_state);
3657
3658	intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state);
3659	}
3660
3661	void intel_ddi_update_active_dpll(struct intel_atomic_state *state,
3662	struct intel_encoder *encoder,
3663	struct intel_crtc *crtc)
3664	{
3665	struct intel_display *display = to_intel_display(encoder);
3666	const struct intel_crtc_state *crtc_state =
3667	intel_atomic_get_new_crtc_state(state, crtc);
3668	struct intel_crtc *pipe_crtc;
3669
3670	/* FIXME: Add MTL pll_mgr */
3671	if (DISPLAY_VER(display) >= 14 || !intel_encoder_is_tc(encoder))
3672	return;
3673
3674	for_each_intel_crtc_in_pipe_mask(display->drm, pipe_crtc,
3675	intel_crtc_joined_pipe_mask(crtc_state))
3676	intel_dpll_update_active(state, crtc: pipe_crtc, encoder);
3677	}
3678
3679	/*
3680	* Note: Also called from the ->pre_pll_enable of the first active MST stream
3681	* encoder on its primary encoder. See also the comment for
3682	* intel_ddi_pre_enable().
3683	*/
3684	static void
3685	intel_ddi_pre_pll_enable(struct intel_atomic_state *state,
3686	struct intel_encoder *encoder,
3687	const struct intel_crtc_state *crtc_state,
3688	const struct drm_connector_state *conn_state)
3689	{
3690	struct intel_display *display = to_intel_display(encoder);
3691	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3692	bool is_tc_port = intel_encoder_is_tc(encoder);
3693
3694	if (is_tc_port) {
3695	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3696
3697	intel_tc_port_get_link(dig_port, required_lanes: crtc_state->lane_count);
3698	intel_ddi_update_active_dpll(state, encoder, crtc);
3699	}
3700
3701	main_link_aux_power_domain_get(dig_port, crtc_state);
3702
3703	if (is_tc_port && !intel_tc_port_in_tbt_alt_mode(dig_port))
3704	/*
3705	* Program the lane count for static/dynamic connections on
3706	* Type-C ports. Skip this step for TBT.
3707	*/
3708	intel_tc_port_set_fia_lane_count(dig_port, required_lanes: crtc_state->lane_count);
3709	else if (display->platform.geminilake || display->platform.broxton)
3710	bxt_dpio_phy_set_lane_optim_mask(encoder,
3711	lane_lat_optim_mask: crtc_state->lane_lat_optim_mask);
3712	}
3713
3714	static void adlp_tbt_to_dp_alt_switch_wa(struct intel_encoder *encoder)
3715	{
3716	struct intel_display *display = to_intel_display(encoder);
3717	enum tc_port tc_port = intel_encoder_to_tc(encoder);
3718	int ln;
3719
3720	for (ln = 0; ln < 2; ln++)
3721	intel_dkl_phy_rmw(display, DKL_PCS_DW5(tc_port, ln),
3722	DKL_PCS_DW5_CORE_SOFTRESET, set: 0);
3723	}
3724
3725	static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
3726	const struct intel_crtc_state *crtc_state)
3727	{
3728	struct intel_display *display = to_intel_display(crtc_state);
3729	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3730	struct intel_encoder *encoder = &dig_port->base;
3731	u32 dp_tp_ctl;
3732
3733	/*
3734	* TODO: To train with only a different voltage swing entry is not
3735	* necessary disable and enable port
3736	*/
3737	dp_tp_ctl = intel_de_read(display, reg: dp_tp_ctl_reg(encoder, crtc_state));
3738
3739	drm_WARN_ON(display->drm, dp_tp_ctl & DP_TP_CTL_ENABLE);
3740
3741	/* 6.d Configure and enable DP_TP_CTL with link training pattern 1 selected */
3742	dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1;
3743	if (intel_crtc_has_type(crtc_state, type: INTEL_OUTPUT_DP_MST) ||
3744	intel_dp_is_uhbr(crtc_state)) {
3745	dp_tp_ctl |= DP_TP_CTL_MODE_MST;
3746	} else {
3747	dp_tp_ctl |= DP_TP_CTL_MODE_SST;
3748	if (crtc_state->enhanced_framing)
3749	dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
3750	}
3751	intel_de_write(display, reg: dp_tp_ctl_reg(encoder, crtc_state), val: dp_tp_ctl);
3752	intel_de_posting_read(display, reg: dp_tp_ctl_reg(encoder, crtc_state));
3753
3754	/* 6.f Enable D2D Link */
3755	mtl_ddi_enable_d2d(encoder);
3756
3757	/* 6.g Configure voltage swing and related IO settings */
3758	encoder->set_signal_levels(encoder, crtc_state);
3759
3760	/* 6.h Configure PORT_BUF_CTL1 */
3761	mtl_port_buf_ctl_program(encoder, crtc_state);
3762
3763	/* 6.i Configure and enable DDI_CTL_DE to start sending valid data to port slice */
3764	if (DISPLAY_VER(display) >= 20)
3765	intel_dp->DP |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
3766
3767	intel_ddi_buf_enable(encoder, buf_ctl: intel_dp->DP);
3768	intel_dp->DP |= DDI_BUF_CTL_ENABLE;
3769
3770	/*
3771	* 6.k If AUX-Less ALPM is going to be enabled:
3772	* i. Configure PORT_ALPM_CTL and PORT_ALPM_LFPS_CTL here
3773	*/
3774	intel_alpm_port_configure(intel_dp, crtc_state);
3775
3776	/*
3777	* ii. Enable MAC Transmits LFPS in the "PHY Common Control 0" PIPE
3778	* register
3779	*/
3780	intel_lnl_mac_transmit_lfps(encoder, crtc_state);
3781	}
3782
3783	static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
3784	const struct intel_crtc_state *crtc_state)
3785	{
3786	struct intel_display *display = to_intel_display(intel_dp);
3787	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3788	struct intel_encoder *encoder = &dig_port->base;
3789	u32 dp_tp_ctl;
3790
3791	dp_tp_ctl = intel_de_read(display, reg: dp_tp_ctl_reg(encoder, crtc_state));
3792
3793	drm_WARN_ON(display->drm, dp_tp_ctl & DP_TP_CTL_ENABLE);
3794
3795	dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1;
3796	if (intel_crtc_has_type(crtc_state, type: INTEL_OUTPUT_DP_MST) ||
3797	intel_dp_is_uhbr(crtc_state)) {
3798	dp_tp_ctl |= DP_TP_CTL_MODE_MST;
3799	} else {
3800	dp_tp_ctl |= DP_TP_CTL_MODE_SST;
3801	if (crtc_state->enhanced_framing)
3802	dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
3803	}
3804	intel_de_write(display, reg: dp_tp_ctl_reg(encoder, crtc_state), val: dp_tp_ctl);
3805	intel_de_posting_read(display, reg: dp_tp_ctl_reg(encoder, crtc_state));
3806
3807	if (display->platform.alderlake_p &&
3808	(intel_tc_port_in_dp_alt_mode(dig_port) || intel_tc_port_in_legacy_mode(dig_port)))
3809	adlp_tbt_to_dp_alt_switch_wa(encoder);
3810
3811	intel_ddi_buf_enable(encoder, buf_ctl: intel_dp->DP);
3812	intel_dp->DP |= DDI_BUF_CTL_ENABLE;
3813	}
3814
3815	static void intel_ddi_set_link_train(struct intel_dp *intel_dp,
3816	const struct intel_crtc_state *crtc_state,
3817	u8 dp_train_pat)
3818	{
3819	struct intel_display *display = to_intel_display(intel_dp);
3820	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3821	u32 temp;
3822
3823	temp = intel_de_read(display, reg: dp_tp_ctl_reg(encoder, crtc_state));
3824
3825	temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3826	switch (intel_dp_training_pattern_symbol(pattern: dp_train_pat)) {
3827	case DP_TRAINING_PATTERN_DISABLE:
3828	temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
3829	break;
3830	case DP_TRAINING_PATTERN_1:
3831	temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
3832	break;
3833	case DP_TRAINING_PATTERN_2:
3834	temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
3835	break;
3836	case DP_TRAINING_PATTERN_3:
3837	temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
3838	break;
3839	case DP_TRAINING_PATTERN_4:
3840	temp |= DP_TP_CTL_LINK_TRAIN_PAT4;
3841	break;
3842	}
3843
3844	intel_de_write(display, reg: dp_tp_ctl_reg(encoder, crtc_state), val: temp);
3845	}
3846
3847	static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp,
3848	const struct intel_crtc_state *crtc_state)
3849	{
3850	struct intel_display *display = to_intel_display(intel_dp);
3851	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3852	enum port port = encoder->port;
3853
3854	intel_de_rmw(display, reg: dp_tp_ctl_reg(encoder, crtc_state),
3855	DP_TP_CTL_LINK_TRAIN_MASK, DP_TP_CTL_LINK_TRAIN_IDLE);
3856
3857	/*
3858	* Until TGL on PORT_A we can have only eDP in SST mode. There the only
3859	* reason we need to set idle transmission mode is to work around a HW
3860	* issue where we enable the pipe while not in idle link-training mode.
3861	* In this case there is requirement to wait for a minimum number of
3862	* idle patterns to be sent.
3863	*/
3864	if (port == PORT_A && DISPLAY_VER(display) < 12)
3865	return;
3866
3867	if (intel_de_wait_for_set_ms(display,
3868	reg: dp_tp_status_reg(encoder, crtc_state),
3869	DP_TP_STATUS_IDLE_DONE, timeout_ms: 2))
3870	drm_err(display->drm,
3871	"Timed out waiting for DP idle patterns\n");
3872	}
3873
3874	static bool intel_ddi_is_audio_enabled(struct intel_display *display,
3875	enum transcoder cpu_transcoder)
3876	{
3877	if (cpu_transcoder == TRANSCODER_EDP)
3878	return false;
3879
3880	if (!intel_display_power_is_enabled(display, domain: POWER_DOMAIN_AUDIO_MMIO))
3881	return false;
3882
3883	return intel_de_read(display, HSW_AUD_PIN_ELD_CP_VLD) &
3884	AUDIO_OUTPUT_ENABLE(cpu_transcoder);
3885	}
3886
3887	static int tgl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state)
3888	{
3889	if (crtc_state->port_clock > 594000)
3890	return 2;
3891	else
3892	return 0;
3893	}
3894
3895	static int jsl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state)
3896	{
3897	if (crtc_state->port_clock > 594000)
3898	return 3;
3899	else
3900	return 0;
3901	}
3902
3903	static int icl_ddi_min_voltage_level(const struct intel_crtc_state *crtc_state)
3904	{
3905	if (crtc_state->port_clock > 594000)
3906	return 1;
3907	else
3908	return 0;
3909	}
3910
3911	void intel_ddi_compute_min_voltage_level(struct intel_crtc_state *crtc_state)
3912	{
3913	struct intel_display *display = to_intel_display(crtc_state);
3914
3915	if (DISPLAY_VER(display) >= 14)
3916	crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state);
3917	else if (DISPLAY_VER(display) >= 12)
3918	crtc_state->min_voltage_level = tgl_ddi_min_voltage_level(crtc_state);
3919	else if (display->platform.jasperlake || display->platform.elkhartlake)
3920	crtc_state->min_voltage_level = jsl_ddi_min_voltage_level(crtc_state);
3921	else if (DISPLAY_VER(display) >= 11)
3922	crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state);
3923	}
3924
3925	static enum transcoder bdw_transcoder_master_readout(struct intel_display *display,
3926	enum transcoder cpu_transcoder)
3927	{
3928	u32 master_select;
3929
3930	if (DISPLAY_VER(display) >= 11) {
3931	u32 ctl2 = intel_de_read(display,
3932	TRANS_DDI_FUNC_CTL2(display, cpu_transcoder));
3933
3934	if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0)
3935	return INVALID_TRANSCODER;
3936
3937	master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2);
3938	} else {
3939	u32 ctl = intel_de_read(display,
3940	TRANS_DDI_FUNC_CTL(display, cpu_transcoder));
3941
3942	if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0)
3943	return INVALID_TRANSCODER;
3944
3945	master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl);
3946	}
3947
3948	if (master_select == 0)
3949	return TRANSCODER_EDP;
3950	else
3951	return master_select - 1;
3952	}
3953
3954	static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state)
3955	{
3956	struct intel_display *display = to_intel_display(crtc_state);
3957	u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
3958	BIT(TRANSCODER_C) | BIT(TRANSCODER_D);
3959	enum transcoder cpu_transcoder;
3960
3961	crtc_state->master_transcoder =
3962	bdw_transcoder_master_readout(display, cpu_transcoder: crtc_state->cpu_transcoder);
3963
3964	for_each_cpu_transcoder_masked(display, cpu_transcoder, transcoders) {
3965	enum intel_display_power_domain power_domain;
3966	intel_wakeref_t trans_wakeref;
3967
3968	power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
3969	trans_wakeref = intel_display_power_get_if_enabled(display,
3970	domain: power_domain);
3971
3972	if (!trans_wakeref)
3973	continue;
3974
3975	if (bdw_transcoder_master_readout(display, cpu_transcoder) ==
3976	crtc_state->cpu_transcoder)
3977	crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder);
3978
3979	intel_display_power_put(display, domain: power_domain, wakeref: trans_wakeref);
3980	}
3981
3982	drm_WARN_ON(display->drm,
3983	crtc_state->master_transcoder != INVALID_TRANSCODER &&
3984	crtc_state->sync_mode_slaves_mask);
3985	}
3986
3987	static void intel_ddi_read_func_ctl_dvi(struct intel_encoder *encoder,
3988	struct intel_crtc_state *crtc_state,
3989	u32 ddi_func_ctl)
3990	{
3991	struct intel_display *display = to_intel_display(encoder);
3992
3993	crtc_state->output_types |= BIT(INTEL_OUTPUT_HDMI);
3994	if (DISPLAY_VER(display) >= 14)
3995	crtc_state->lane_count =
3996	((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3997	else
3998	crtc_state->lane_count = 4;
3999	}
4000
4001	static void intel_ddi_read_func_ctl_hdmi(struct intel_encoder *encoder,
4002	struct intel_crtc_state *crtc_state,
4003	u32 ddi_func_ctl)
4004	{
4005	crtc_state->has_hdmi_sink = true;
4006
4007	crtc_state->infoframes.enable |=
4008	intel_hdmi_infoframes_enabled(encoder, crtc_state);
4009
4010	if (crtc_state->infoframes.enable)
4011	crtc_state->has_infoframe = true;
4012
4013	if (ddi_func_ctl & TRANS_DDI_HDMI_SCRAMBLING)
4014	crtc_state->hdmi_scrambling = true;
4015	if (ddi_func_ctl & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
4016	crtc_state->hdmi_high_tmds_clock_ratio = true;
4017
4018	intel_ddi_read_func_ctl_dvi(encoder, crtc_state, ddi_func_ctl);
4019	}
4020
4021	static void intel_ddi_read_func_ctl_fdi(struct intel_encoder *encoder,
4022	struct intel_crtc_state *crtc_state,
4023	u32 ddi_func_ctl)
4024	{
4025	struct intel_display *display = to_intel_display(encoder);
4026
4027	crtc_state->output_types |= BIT(INTEL_OUTPUT_ANALOG);
4028	crtc_state->enhanced_framing =
4029	intel_de_read(display, reg: dp_tp_ctl_reg(encoder, crtc_state)) &
4030	DP_TP_CTL_ENHANCED_FRAME_ENABLE;
4031	}
4032
4033	static void intel_ddi_read_func_ctl_dp_sst(struct intel_encoder *encoder,
4034	struct intel_crtc_state *crtc_state,
4035	u32 ddi_func_ctl)
4036	{
4037	struct intel_display *display = to_intel_display(encoder);
4038	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4039	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4040	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
4041
4042	if (encoder->type == INTEL_OUTPUT_EDP)
4043	crtc_state->output_types |= BIT(INTEL_OUTPUT_EDP);
4044	else
4045	crtc_state->output_types |= BIT(INTEL_OUTPUT_DP);
4046	crtc_state->lane_count =
4047	((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
4048
4049	if (DISPLAY_VER(display) >= 12 &&
4050	(ddi_func_ctl & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B)
4051	crtc_state->mst_master_transcoder =
4052	REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, ddi_func_ctl);
4053
4054	intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, m_n: &crtc_state->dp_m_n);
4055	intel_cpu_transcoder_get_m2_n2(crtc, cpu_transcoder, m_n: &crtc_state->dp_m2_n2);
4056
4057	crtc_state->enhanced_framing =
4058	intel_de_read(display, reg: dp_tp_ctl_reg(encoder, crtc_state)) &
4059	DP_TP_CTL_ENHANCED_FRAME_ENABLE;
4060
4061	if (DISPLAY_VER(display) >= 11)
4062	crtc_state->fec_enable =
4063	intel_de_read(display,
4064	reg: dp_tp_ctl_reg(encoder, crtc_state)) & DP_TP_CTL_FEC_ENABLE;
4065
4066	if (intel_lspcon_active(dig_port) && intel_dp_has_hdmi_sink(intel_dp: &dig_port->dp))
4067	crtc_state->infoframes.enable |=
4068	intel_lspcon_infoframes_enabled(encoder, pipe_config: crtc_state);
4069	else
4070	crtc_state->infoframes.enable |=
4071	intel_hdmi_infoframes_enabled(encoder, crtc_state);
4072	}
4073
4074	static void intel_ddi_read_func_ctl_dp_mst(struct intel_encoder *encoder,
4075	struct intel_crtc_state *crtc_state,
4076	u32 ddi_func_ctl)
4077	{
4078	struct intel_display *display = to_intel_display(encoder);
4079	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4080	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
4081
4082	crtc_state->output_types |= BIT(INTEL_OUTPUT_DP_MST);
4083	crtc_state->lane_count =
4084	((ddi_func_ctl & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
4085
4086	if (DISPLAY_VER(display) >= 12)
4087	crtc_state->mst_master_transcoder =
4088	REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, ddi_func_ctl);
4089
4090	intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder, m_n: &crtc_state->dp_m_n);
4091
4092	if (DISPLAY_VER(display) >= 11)
4093	crtc_state->fec_enable =
4094	intel_de_read(display,
4095	reg: dp_tp_ctl_reg(encoder, crtc_state)) & DP_TP_CTL_FEC_ENABLE;
4096
4097	crtc_state->infoframes.enable |=
4098	intel_hdmi_infoframes_enabled(encoder, crtc_state);
4099	}
4100
4101	static void intel_ddi_read_func_ctl(struct intel_encoder *encoder,
4102	struct intel_crtc_state *pipe_config)
4103	{
4104	struct intel_display *display = to_intel_display(encoder);
4105	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4106	u32 ddi_func_ctl, ddi_mode, flags = 0;
4107
4108	ddi_func_ctl = intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder));
4109	if (ddi_func_ctl & TRANS_DDI_PHSYNC)
4110	flags |= DRM_MODE_FLAG_PHSYNC;
4111	else
4112	flags |= DRM_MODE_FLAG_NHSYNC;
4113	if (ddi_func_ctl & TRANS_DDI_PVSYNC)
4114	flags |= DRM_MODE_FLAG_PVSYNC;
4115	else
4116	flags |= DRM_MODE_FLAG_NVSYNC;
4117
4118	pipe_config->hw.adjusted_mode.flags |= flags;
4119
4120	switch (ddi_func_ctl & TRANS_DDI_BPC_MASK) {
4121	case TRANS_DDI_BPC_6:
4122	pipe_config->pipe_bpp = 18;
4123	break;
4124	case TRANS_DDI_BPC_8:
4125	pipe_config->pipe_bpp = 24;
4126	break;
4127	case TRANS_DDI_BPC_10:
4128	pipe_config->pipe_bpp = 30;
4129	break;
4130	case TRANS_DDI_BPC_12:
4131	pipe_config->pipe_bpp = 36;
4132	break;
4133	default:
4134	break;
4135	}
4136
4137	ddi_mode = ddi_func_ctl & TRANS_DDI_MODE_SELECT_MASK;
4138
4139	if (ddi_mode == TRANS_DDI_MODE_SELECT_HDMI) {
4140	intel_ddi_read_func_ctl_hdmi(encoder, crtc_state: pipe_config, ddi_func_ctl);
4141	} else if (ddi_mode == TRANS_DDI_MODE_SELECT_DVI) {
4142	intel_ddi_read_func_ctl_dvi(encoder, crtc_state: pipe_config, ddi_func_ctl);
4143	} else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && !HAS_DP20(display)) {
4144	intel_ddi_read_func_ctl_fdi(encoder, crtc_state: pipe_config, ddi_func_ctl);
4145	} else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_SST) {
4146	intel_ddi_read_func_ctl_dp_sst(encoder, crtc_state: pipe_config, ddi_func_ctl);
4147	} else if (ddi_mode == TRANS_DDI_MODE_SELECT_DP_MST) {
4148	intel_ddi_read_func_ctl_dp_mst(encoder, crtc_state: pipe_config, ddi_func_ctl);
4149	} else if (ddi_mode == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B && HAS_DP20(display)) {
4150	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4151
4152	/*
4153	* If this is true, we know we're being called from mst stream
4154	* encoder's ->get_config().
4155	*/
4156	if (intel_dp_mst_active_streams(intel_dp))
4157	intel_ddi_read_func_ctl_dp_mst(encoder, crtc_state: pipe_config, ddi_func_ctl);
4158	else
4159	intel_ddi_read_func_ctl_dp_sst(encoder, crtc_state: pipe_config, ddi_func_ctl);
4160	}
4161	}
4162
4163	/*
4164	* Note: Also called from the ->get_config of the MST stream encoders on their
4165	* primary encoder, via the platform specific hooks here. See also the comment
4166	* for intel_ddi_pre_enable().
4167	*/
4168	static void intel_ddi_get_config(struct intel_encoder *encoder,
4169	struct intel_crtc_state *pipe_config)
4170	{
4171	struct intel_display *display = to_intel_display(encoder);
4172	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4173
4174	/* XXX: DSI transcoder paranoia */
4175	if (drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder)))
4176	return;
4177
4178	intel_ddi_read_func_ctl(encoder, pipe_config);
4179
4180	intel_ddi_mso_get_config(encoder, pipe_config);
4181
4182	pipe_config->has_audio =
4183	intel_ddi_is_audio_enabled(display, cpu_transcoder);
4184
4185	if (encoder->type == INTEL_OUTPUT_EDP)
4186	intel_edp_fixup_vbt_bpp(encoder, pipe_bpp: pipe_config->pipe_bpp);
4187
4188	ddi_dotclock_get(pipe_config);
4189
4190	if (display->platform.geminilake || display->platform.broxton)
4191	pipe_config->lane_lat_optim_mask =
4192	bxt_dpio_phy_get_lane_lat_optim_mask(encoder);
4193
4194	intel_ddi_compute_min_voltage_level(crtc_state: pipe_config);
4195
4196	intel_hdmi_read_gcp_infoframe(encoder, crtc_state: pipe_config);
4197
4198	intel_read_infoframe(encoder, crtc_state: pipe_config,
4199	type: HDMI_INFOFRAME_TYPE_AVI,
4200	frame: &pipe_config->infoframes.avi);
4201	intel_read_infoframe(encoder, crtc_state: pipe_config,
4202	type: HDMI_INFOFRAME_TYPE_SPD,
4203	frame: &pipe_config->infoframes.spd);
4204	intel_read_infoframe(encoder, crtc_state: pipe_config,
4205	type: HDMI_INFOFRAME_TYPE_VENDOR,
4206	frame: &pipe_config->infoframes.hdmi);
4207	intel_read_infoframe(encoder, crtc_state: pipe_config,
4208	type: HDMI_INFOFRAME_TYPE_DRM,
4209	frame: &pipe_config->infoframes.drm);
4210
4211	if (DISPLAY_VER(display) >= 8)
4212	bdw_get_trans_port_sync_config(crtc_state: pipe_config);
4213
4214	intel_psr_get_config(encoder, pipe_config);
4215
4216	intel_read_dp_sdp(encoder, crtc_state: pipe_config, type: HDMI_PACKET_TYPE_GAMUT_METADATA);
4217	intel_read_dp_sdp(encoder, crtc_state: pipe_config, DP_SDP_VSC);
4218	intel_read_dp_sdp(encoder, crtc_state: pipe_config, DP_SDP_ADAPTIVE_SYNC);
4219
4220	intel_audio_codec_get_config(encoder, crtc_state: pipe_config);
4221	}
4222
4223	void intel_ddi_get_clock(struct intel_encoder *encoder,
4224	struct intel_crtc_state *crtc_state,
4225	struct intel_dpll *pll)
4226	{
4227	struct intel_display *display = to_intel_display(encoder);
4228	enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT;
4229	struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id];
4230	bool pll_active;
4231
4232	if (drm_WARN_ON(display->drm, !pll))
4233	return;
4234
4235	port_dpll->pll = pll;
4236	pll_active = intel_dpll_get_hw_state(display, pll, dpll_hw_state: &port_dpll->hw_state);
4237	drm_WARN_ON(display->drm, !pll_active);
4238
4239	icl_set_active_port_dpll(crtc_state, port_dpll_id);
4240
4241	crtc_state->port_clock = intel_dpll_get_freq(display, pll: crtc_state->intel_dpll,
4242	dpll_hw_state: &crtc_state->dpll_hw_state);
4243	}
4244
4245	static void xe3plpd_ddi_get_config(struct intel_encoder *encoder,
4246	struct intel_crtc_state *crtc_state)
4247	{
4248	intel_lt_phy_pll_readout_hw_state(encoder, crtc_state, pll_state: &crtc_state->dpll_hw_state.ltpll);
4249
4250	if (crtc_state->dpll_hw_state.ltpll.tbt_mode)
4251	crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder);
4252	else
4253	crtc_state->port_clock =
4254	intel_lt_phy_calc_port_clock(encoder, crtc_state);
4255	intel_ddi_get_config(encoder, pipe_config: crtc_state);
4256	}
4257
4258	static void mtl_ddi_get_config(struct intel_encoder *encoder,
4259	struct intel_crtc_state *crtc_state)
4260	{
4261	intel_cx0pll_readout_hw_state(encoder, pll_state: &crtc_state->dpll_hw_state.cx0pll);
4262
4263	if (crtc_state->dpll_hw_state.cx0pll.tbt_mode)
4264	crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder);
4265	else
4266	crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, pll_state: &crtc_state->dpll_hw_state.cx0pll);
4267
4268	intel_ddi_get_config(encoder, pipe_config: crtc_state);
4269	}
4270
4271	static void dg2_ddi_get_config(struct intel_encoder *encoder,
4272	struct intel_crtc_state *crtc_state)
4273	{
4274	intel_mpllb_readout_hw_state(encoder, pll_state: &crtc_state->dpll_hw_state.mpllb);
4275	crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder, pll_state: &crtc_state->dpll_hw_state.mpllb);
4276
4277	intel_ddi_get_config(encoder, pipe_config: crtc_state);
4278	}
4279
4280	static void adls_ddi_get_config(struct intel_encoder *encoder,
4281	struct intel_crtc_state *crtc_state)
4282	{
4283	intel_ddi_get_clock(encoder, crtc_state, pll: adls_ddi_get_pll(encoder));
4284	intel_ddi_get_config(encoder, pipe_config: crtc_state);
4285	}
4286
4287	static void rkl_ddi_get_config(struct intel_encoder *encoder,
4288	struct intel_crtc_state *crtc_state)
4289	{
4290	intel_ddi_get_clock(encoder, crtc_state, pll: rkl_ddi_get_pll(encoder));
4291	intel_ddi_get_config(encoder, pipe_config: crtc_state);
4292	}
4293
4294	static void dg1_ddi_get_config(struct intel_encoder *encoder,
4295	struct intel_crtc_state *crtc_state)
4296	{
4297	intel_ddi_get_clock(encoder, crtc_state, pll: dg1_ddi_get_pll(encoder));
4298	intel_ddi_get_config(encoder, pipe_config: crtc_state);
4299	}
4300
4301	static void icl_ddi_combo_get_config(struct intel_encoder *encoder,
4302	struct intel_crtc_state *crtc_state)
4303	{
4304	intel_ddi_get_clock(encoder, crtc_state, pll: icl_ddi_combo_get_pll(encoder));
4305	intel_ddi_get_config(encoder, pipe_config: crtc_state);
4306	}
4307
4308	static bool icl_ddi_tc_pll_is_tbt(const struct intel_dpll *pll)
4309	{
4310	return pll->info->id == DPLL_ID_ICL_TBTPLL;
4311	}
4312
4313	static enum icl_port_dpll_id
4314	icl_ddi_tc_port_pll_type(struct intel_encoder *encoder,
4315	const struct intel_crtc_state *crtc_state)
4316	{
4317	struct intel_display *display = to_intel_display(encoder);
4318	const struct intel_dpll *pll = crtc_state->intel_dpll;
4319
4320	if (drm_WARN_ON(display->drm, !pll))
4321	return ICL_PORT_DPLL_DEFAULT;
4322
4323	if (icl_ddi_tc_pll_is_tbt(pll))
4324	return ICL_PORT_DPLL_DEFAULT;
4325	else
4326	return ICL_PORT_DPLL_MG_PHY;
4327	}
4328
4329	enum icl_port_dpll_id
4330	intel_ddi_port_pll_type(struct intel_encoder *encoder,
4331	const struct intel_crtc_state *crtc_state)
4332	{
4333	if (!encoder->port_pll_type)
4334	return ICL_PORT_DPLL_DEFAULT;
4335
4336	return encoder->port_pll_type(encoder, crtc_state);
4337	}
4338
4339	static void icl_ddi_tc_get_clock(struct intel_encoder *encoder,
4340	struct intel_crtc_state *crtc_state,
4341	struct intel_dpll *pll)
4342	{
4343	struct intel_display *display = to_intel_display(encoder);
4344	enum icl_port_dpll_id port_dpll_id;
4345	struct icl_port_dpll *port_dpll;
4346	bool pll_active;
4347
4348	if (drm_WARN_ON(display->drm, !pll))
4349	return;
4350
4351	if (icl_ddi_tc_pll_is_tbt(pll))
4352	port_dpll_id = ICL_PORT_DPLL_DEFAULT;
4353	else
4354	port_dpll_id = ICL_PORT_DPLL_MG_PHY;
4355
4356	port_dpll = &crtc_state->icl_port_dplls[port_dpll_id];
4357
4358	port_dpll->pll = pll;
4359	pll_active = intel_dpll_get_hw_state(display, pll, dpll_hw_state: &port_dpll->hw_state);
4360	drm_WARN_ON(display->drm, !pll_active);
4361
4362	icl_set_active_port_dpll(crtc_state, port_dpll_id);
4363
4364	if (icl_ddi_tc_pll_is_tbt(pll: crtc_state->intel_dpll))
4365	crtc_state->port_clock = icl_calc_tbt_pll_link(display, port: encoder->port);
4366	else
4367	crtc_state->port_clock = intel_dpll_get_freq(display, pll: crtc_state->intel_dpll,
4368	dpll_hw_state: &crtc_state->dpll_hw_state);
4369	}
4370
4371	static void icl_ddi_tc_get_config(struct intel_encoder *encoder,
4372	struct intel_crtc_state *crtc_state)
4373	{
4374	icl_ddi_tc_get_clock(encoder, crtc_state, pll: icl_ddi_tc_get_pll(encoder));
4375	intel_ddi_get_config(encoder, pipe_config: crtc_state);
4376	}
4377
4378	static void bxt_ddi_get_config(struct intel_encoder *encoder,
4379	struct intel_crtc_state *crtc_state)
4380	{
4381	intel_ddi_get_clock(encoder, crtc_state, pll: bxt_ddi_get_pll(encoder));
4382	intel_ddi_get_config(encoder, pipe_config: crtc_state);
4383	}
4384
4385	static void skl_ddi_get_config(struct intel_encoder *encoder,
4386	struct intel_crtc_state *crtc_state)
4387	{
4388	intel_ddi_get_clock(encoder, crtc_state, pll: skl_ddi_get_pll(encoder));
4389	intel_ddi_get_config(encoder, pipe_config: crtc_state);
4390	}
4391
4392	void hsw_ddi_get_config(struct intel_encoder *encoder,
4393	struct intel_crtc_state *crtc_state)
4394	{
4395	intel_ddi_get_clock(encoder, crtc_state, pll: hsw_ddi_get_pll(encoder));
4396	intel_ddi_get_config(encoder, pipe_config: crtc_state);
4397	}
4398
4399	static void intel_ddi_sync_state(struct intel_encoder *encoder,
4400	const struct intel_crtc_state *crtc_state)
4401	{
4402	if (intel_encoder_is_tc(encoder))
4403	intel_tc_port_sanitize_mode(dig_port: enc_to_dig_port(encoder),
4404	crtc_state);
4405
4406	if ((crtc_state && intel_crtc_has_dp_encoder(crtc_state)) ||
4407	(!crtc_state && intel_encoder_is_dp(encoder)))
4408	intel_dp_sync_state(encoder, crtc_state);
4409	}
4410
4411	static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder,
4412	struct intel_crtc_state *crtc_state)
4413	{
4414	struct intel_display *display = to_intel_display(encoder);
4415	bool fastset = true;
4416
4417	if (intel_encoder_is_tc(encoder)) {
4418	drm_dbg_kms(display->drm, "[ENCODER:%d:%s] Forcing full modeset to compute TC port DPLLs\n",
4419	encoder->base.base.id, encoder->base.name);
4420	crtc_state->uapi.mode_changed = true;
4421	fastset = false;
4422	}
4423
4424	if (intel_crtc_has_dp_encoder(crtc_state) &&
4425	!intel_dp_initial_fastset_check(encoder, crtc_state))
4426	fastset = false;
4427
4428	return fastset;
4429	}
4430
4431	static enum intel_output_type
4432	intel_ddi_compute_output_type(struct intel_encoder *encoder,
4433	struct intel_crtc_state *crtc_state,
4434	struct drm_connector_state *conn_state)
4435	{
4436	switch (conn_state->connector->connector_type) {
4437	case DRM_MODE_CONNECTOR_HDMIA:
4438	return INTEL_OUTPUT_HDMI;
4439	case DRM_MODE_CONNECTOR_eDP:
4440	return INTEL_OUTPUT_EDP;
4441	case DRM_MODE_CONNECTOR_DisplayPort:
4442	return INTEL_OUTPUT_DP;
4443	default:
4444	MISSING_CASE(conn_state->connector->connector_type);
4445	return INTEL_OUTPUT_UNUSED;
4446	}
4447	}
4448
4449	static int intel_ddi_compute_config(struct intel_encoder *encoder,
4450	struct intel_crtc_state *pipe_config,
4451	struct drm_connector_state *conn_state)
4452	{
4453	struct intel_display *display = to_intel_display(encoder);
4454	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
4455	enum port port = encoder->port;
4456	int ret;
4457
4458	if (HAS_TRANSCODER(display, TRANSCODER_EDP) && port == PORT_A)
4459	pipe_config->cpu_transcoder = TRANSCODER_EDP;
4460
4461	if (intel_crtc_has_type(crtc_state: pipe_config, type: INTEL_OUTPUT_HDMI)) {
4462	pipe_config->has_hdmi_sink =
4463	intel_hdmi_compute_has_hdmi_sink(encoder, crtc_state: pipe_config, conn_state);
4464
4465	ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
4466	} else {
4467	ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
4468	}
4469
4470	if (ret)
4471	return ret;
4472
4473	if (display->platform.haswell && crtc->pipe == PIPE_A &&
4474	pipe_config->cpu_transcoder == TRANSCODER_EDP)
4475	pipe_config->pch_pfit.force_thru =
4476	pipe_config->pch_pfit.enabled ||
4477	pipe_config->crc_enabled;
4478
4479	if (display->platform.geminilake || display->platform.broxton)
4480	pipe_config->lane_lat_optim_mask =
4481	bxt_dpio_phy_calc_lane_lat_optim_mask(lane_count: pipe_config->lane_count);
4482
4483	intel_ddi_compute_min_voltage_level(crtc_state: pipe_config);
4484
4485	return 0;
4486	}
4487
4488	static bool mode_equal(const struct drm_display_mode *mode1,
4489	const struct drm_display_mode *mode2)
4490	{
4491	return drm_mode_match(mode1, mode2,
4492	DRM_MODE_MATCH_TIMINGS |
4493	DRM_MODE_MATCH_FLAGS |
4494	DRM_MODE_MATCH_3D_FLAGS) &&
4495	mode1->clock == mode2->clock; /* we want an exact match */
4496	}
4497
4498	static bool m_n_equal(const struct intel_link_m_n *m_n_1,
4499	const struct intel_link_m_n *m_n_2)
4500	{
4501	return m_n_1->tu == m_n_2->tu &&
4502	m_n_1->data_m == m_n_2->data_m &&
4503	m_n_1->data_n == m_n_2->data_n &&
4504	m_n_1->link_m == m_n_2->link_m &&
4505	m_n_1->link_n == m_n_2->link_n;
4506	}
4507
4508	static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1,
4509	const struct intel_crtc_state *crtc_state2)
4510	{
4511	/*
4512	* FIXME the modeset sequence is currently wrong and
4513	* can't deal with joiner + port sync at the same time.
4514	*/
4515	return crtc_state1->hw.active && crtc_state2->hw.active &&
4516	!crtc_state1->joiner_pipes && !crtc_state2->joiner_pipes &&
4517	crtc_state1->output_types == crtc_state2->output_types &&
4518	crtc_state1->output_format == crtc_state2->output_format &&
4519	crtc_state1->lane_count == crtc_state2->lane_count &&
4520	crtc_state1->port_clock == crtc_state2->port_clock &&
4521	mode_equal(mode1: &crtc_state1->hw.adjusted_mode,
4522	mode2: &crtc_state2->hw.adjusted_mode) &&
4523	m_n_equal(m_n_1: &crtc_state1->dp_m_n, m_n_2: &crtc_state2->dp_m_n);
4524	}
4525
4526	static u8
4527	intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state,
4528	int tile_group_id)
4529	{
4530	struct intel_display *display = to_intel_display(ref_crtc_state);
4531	struct drm_connector *connector;
4532	const struct drm_connector_state *conn_state;
4533	struct intel_atomic_state *state =
4534	to_intel_atomic_state(ref_crtc_state->uapi.state);
4535	u8 transcoders = 0;
4536	int i;
4537
4538	/*
4539	* We don't enable port sync on BDW due to missing w/as and
4540	* due to not having adjusted the modeset sequence appropriately.
4541	*/
4542	if (DISPLAY_VER(display) < 9)
4543	return 0;
4544
4545	if (!intel_crtc_has_type(crtc_state: ref_crtc_state, type: INTEL_OUTPUT_DP))
4546	return 0;
4547
4548	for_each_new_connector_in_state(&state->base, connector, conn_state, i) {
4549	struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc);
4550	const struct intel_crtc_state *crtc_state;
4551
4552	if (!crtc)
4553	continue;
4554
4555	if (!connector->has_tile ||
4556	connector->tile_group->id !=
4557	tile_group_id)
4558	continue;
4559	crtc_state = intel_atomic_get_new_crtc_state(state,
4560	crtc);
4561	if (!crtcs_port_sync_compatible(crtc_state1: ref_crtc_state,
4562	crtc_state2: crtc_state))
4563	continue;
4564	transcoders |= BIT(crtc_state->cpu_transcoder);
4565	}
4566
4567	return transcoders;
4568	}
4569
4570	static int intel_ddi_compute_config_late(struct intel_encoder *encoder,
4571	struct intel_crtc_state *crtc_state,
4572	struct drm_connector_state *conn_state)
4573	{
4574	struct intel_display *display = to_intel_display(encoder);
4575	struct drm_connector *connector = conn_state->connector;
4576	u8 port_sync_transcoders = 0;
4577	int ret = 0;
4578
4579	if (intel_crtc_has_dp_encoder(crtc_state))
4580	ret = intel_dp_compute_config_late(encoder, crtc_state, conn_state);
4581
4582	if (ret)
4583	return ret;
4584
4585	drm_dbg_kms(display->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]\n",
4586	encoder->base.base.id, encoder->base.name,
4587	crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name);
4588
4589	if (connector->has_tile)
4590	port_sync_transcoders = intel_ddi_port_sync_transcoders(ref_crtc_state: crtc_state,
4591	tile_group_id: connector->tile_group->id);
4592
4593	/*
4594	* EDP Transcoders cannot be ensalved
4595	* make them a master always when present
4596	*/
4597	if (port_sync_transcoders & BIT(TRANSCODER_EDP))
4598	crtc_state->master_transcoder = TRANSCODER_EDP;
4599	else
4600	crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1;
4601
4602	if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) {
4603	crtc_state->master_transcoder = INVALID_TRANSCODER;
4604	crtc_state->sync_mode_slaves_mask =
4605	port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder);
4606	}
4607
4608	return 0;
4609	}
4610
4611	static void intel_ddi_encoder_destroy(struct drm_encoder *encoder)
4612	{
4613	struct intel_display *display = to_intel_display(encoder->dev);
4614	struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
4615
4616	intel_dp_encoder_flush_work(encoder);
4617	if (intel_encoder_is_tc(encoder: &dig_port->base))
4618	intel_tc_port_cleanup(dig_port);
4619	intel_display_power_flush_work(display);
4620
4621	drm_encoder_cleanup(encoder);
4622	kfree(objp: dig_port->hdcp.port_data.streams);
4623	kfree(objp: dig_port);
4624	}
4625
4626	static void intel_ddi_encoder_reset(struct drm_encoder *encoder)
4627	{
4628	struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder));
4629	struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
4630
4631	intel_dp->reset_link_params = true;
4632	intel_dp_invalidate_source_oui(intel_dp);
4633
4634	intel_pps_encoder_reset(intel_dp);
4635
4636	if (intel_encoder_is_tc(encoder: &dig_port->base))
4637	intel_tc_port_init_mode(dig_port);
4638	}
4639
4640	static int intel_ddi_encoder_late_register(struct drm_encoder *_encoder)
4641	{
4642	struct intel_encoder *encoder = to_intel_encoder(_encoder);
4643
4644	intel_tc_port_link_reset(dig_port: enc_to_dig_port(encoder));
4645
4646	return 0;
4647	}
4648
4649	static const struct drm_encoder_funcs intel_ddi_funcs = {
4650	.reset = intel_ddi_encoder_reset,
4651	.destroy = intel_ddi_encoder_destroy,
4652	.late_register = intel_ddi_encoder_late_register,
4653	};
4654
4655	static int intel_ddi_init_dp_connector(struct intel_digital_port *dig_port)
4656	{
4657	struct intel_display *display = to_intel_display(dig_port);
4658	struct intel_connector *connector;
4659	enum port port = dig_port->base.port;
4660
4661	connector = intel_connector_alloc();
4662	if (!connector)
4663	return -ENOMEM;
4664
4665	dig_port->dp.output_reg = DDI_BUF_CTL(port);
4666	if (DISPLAY_VER(display) >= 14)
4667	dig_port->dp.prepare_link_retrain = mtl_ddi_prepare_link_retrain;
4668	else
4669	dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain;
4670	dig_port->dp.set_link_train = intel_ddi_set_link_train;
4671	dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train;
4672
4673	dig_port->dp.voltage_max = intel_ddi_dp_voltage_max;
4674	dig_port->dp.preemph_max = intel_ddi_dp_preemph_max;
4675
4676	if (!intel_dp_init_connector(dig_port, intel_connector: connector)) {
4677	kfree(objp: connector);
4678	return -EINVAL;
4679	}
4680
4681	if (dig_port->base.type == INTEL_OUTPUT_EDP) {
4682	struct drm_privacy_screen *privacy_screen;
4683
4684	privacy_screen = drm_privacy_screen_get(dev: display->drm->dev, NULL);
4685	if (!IS_ERR(ptr: privacy_screen)) {
4686	drm_connector_attach_privacy_screen_provider(connector: &connector->base,
4687	priv: privacy_screen);
4688	} else if (PTR_ERR(ptr: privacy_screen) != -ENODEV) {
4689	drm_warn(display->drm, "Error getting privacy-screen\n");
4690	}
4691	}
4692
4693	return 0;
4694	}
4695
4696	static int intel_hdmi_reset_link(struct intel_encoder *encoder,
4697	struct drm_modeset_acquire_ctx *ctx)
4698	{
4699	struct intel_display *display = to_intel_display(encoder);
4700	struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder);
4701	struct intel_connector *connector = hdmi->attached_connector;
4702	struct i2c_adapter *ddc = connector->base.ddc;
4703	struct drm_connector_state *conn_state;
4704	struct intel_crtc_state *crtc_state;
4705	struct intel_crtc *crtc;
4706	u8 config;
4707	int ret;
4708
4709	if (connector->base.status != connector_status_connected)
4710	return 0;
4711
4712	ret = drm_modeset_lock(lock: &display->drm->mode_config.connection_mutex,
4713	ctx);
4714	if (ret)
4715	return ret;
4716
4717	conn_state = connector->base.state;
4718
4719	crtc = to_intel_crtc(conn_state->crtc);
4720	if (!crtc)
4721	return 0;
4722
4723	ret = drm_modeset_lock(lock: &crtc->base.mutex, ctx);
4724	if (ret)
4725	return ret;
4726
4727	crtc_state = to_intel_crtc_state(crtc->base.state);
4728
4729	drm_WARN_ON(display->drm,
4730	!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));
4731
4732	if (!crtc_state->hw.active)
4733	return 0;
4734
4735	if (!crtc_state->hdmi_high_tmds_clock_ratio &&
4736	!crtc_state->hdmi_scrambling)
4737	return 0;
4738
4739	if (conn_state->commit &&
4740	!try_wait_for_completion(x: &conn_state->commit->hw_done))
4741	return 0;
4742
4743	ret = drm_scdc_readb(adapter: ddc, SCDC_TMDS_CONFIG, value: &config);
4744	if (ret < 0) {
4745	drm_err(display->drm, "[CONNECTOR:%d:%s] Failed to read TMDS config: %d\n",
4746	connector->base.base.id, connector->base.name, ret);
4747	return 0;
4748	}
4749
4750	if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) ==
4751	crtc_state->hdmi_high_tmds_clock_ratio &&
4752	!!(config & SCDC_SCRAMBLING_ENABLE) ==
4753	crtc_state->hdmi_scrambling)
4754	return 0;
4755
4756	/*
4757	* HDMI 2.0 says that one should not send scrambled data
4758	* prior to configuring the sink scrambling, and that
4759	* TMDS clock/data transmission should be suspended when
4760	* changing the TMDS clock rate in the sink. So let's
4761	* just do a full modeset here, even though some sinks
4762	* would be perfectly happy if were to just reconfigure
4763	* the SCDC settings on the fly.
4764	*/
4765	return intel_modeset_commit_pipes(display, BIT(crtc->pipe), ctx);
4766	}
4767
4768	static void intel_ddi_link_check(struct intel_encoder *encoder)
4769	{
4770	struct intel_display *display = to_intel_display(encoder);
4771	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4772
4773	/* TODO: Move checking the HDMI link state here as well. */
4774	drm_WARN_ON(display->drm, !dig_port->dp.attached_connector);
4775
4776	intel_dp_link_check(encoder);
4777	}
4778
4779	static enum intel_hotplug_state
4780	intel_ddi_hotplug(struct intel_encoder *encoder,
4781	struct intel_connector *connector)
4782	{
4783	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4784	struct intel_dp *intel_dp = &dig_port->dp;
4785	bool is_tc = intel_encoder_is_tc(encoder);
4786	struct drm_modeset_acquire_ctx ctx;
4787	enum intel_hotplug_state state;
4788	int ret;
4789
4790	if (intel_dp_test_phy(intel_dp))
4791	return INTEL_HOTPLUG_UNCHANGED;
4792
4793	state = intel_encoder_hotplug(encoder, connector);
4794
4795	if (!intel_tc_port_link_reset(dig_port)) {
4796	if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) {
4797	intel_modeset_lock_ctx_retry(&ctx, NULL, 0, ret)
4798	ret = intel_hdmi_reset_link(encoder, ctx: &ctx);
4799	drm_WARN_ON(encoder->base.dev, ret);
4800	} else {
4801	intel_dp_check_link_state(intel_dp);
4802	}
4803	}
4804
4805	/*
4806	* Unpowered type-c dongles can take some time to boot and be
4807	* responsible, so here giving some time to those dongles to power up
4808	* and then retrying the probe.
4809	*
4810	* On many platforms the HDMI live state signal is known to be
4811	* unreliable, so we can't use it to detect if a sink is connected or
4812	* not. Instead we detect if it's connected based on whether we can
4813	* read the EDID or not. That in turn has a problem during disconnect,
4814	* since the HPD interrupt may be raised before the DDC lines get
4815	* disconnected (due to how the required length of DDC vs. HPD
4816	* connector pins are specified) and so we'll still be able to get a
4817	* valid EDID. To solve this schedule another detection cycle if this
4818	* time around we didn't detect any change in the sink's connection
4819	* status.
4820	*
4821	* Type-c connectors which get their HPD signal deasserted then
4822	* reasserted, without unplugging/replugging the sink from the
4823	* connector, introduce a delay until the AUX channel communication
4824	* becomes functional. Retry the detection for 5 seconds on type-c
4825	* connectors to account for this delay.
4826	*/
4827	if (state == INTEL_HOTPLUG_UNCHANGED &&
4828	connector->hotplug_retries < (is_tc ? 5 : 1) &&
4829	!dig_port->dp.is_mst)
4830	state = INTEL_HOTPLUG_RETRY;
4831
4832	return state;
4833	}
4834
4835	static bool lpt_digital_port_connected(struct intel_encoder *encoder)
4836	{
4837	struct intel_display *display = to_intel_display(encoder);
4838	u32 bit = display->hotplug.pch_hpd[encoder->hpd_pin];
4839
4840	return intel_de_read(display, SDEISR) & bit;
4841	}
4842
4843	static bool hsw_digital_port_connected(struct intel_encoder *encoder)
4844	{
4845	struct intel_display *display = to_intel_display(encoder);
4846	u32 bit = display->hotplug.hpd[encoder->hpd_pin];
4847
4848	return intel_de_read(display, DEISR) & bit;
4849	}
4850
4851	static bool bdw_digital_port_connected(struct intel_encoder *encoder)
4852	{
4853	struct intel_display *display = to_intel_display(encoder);
4854	u32 bit = display->hotplug.hpd[encoder->hpd_pin];
4855
4856	return intel_de_read(display, GEN8_DE_PORT_ISR) & bit;
4857	}
4858
4859	static int intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port)
4860	{
4861	struct intel_connector *connector;
4862	enum port port = dig_port->base.port;
4863
4864	connector = intel_connector_alloc();
4865	if (!connector)
4866	return -ENOMEM;
4867
4868	dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
4869
4870	if (!intel_hdmi_init_connector(dig_port, intel_connector: connector)) {
4871	/*
4872	* HDMI connector init failures may just mean conflicting DDC
4873	* pins or not having enough lanes. Handle them gracefully, but
4874	* don't fail the entire DDI init.
4875	*/
4876	dig_port->hdmi.hdmi_reg = INVALID_MMIO_REG;
4877	kfree(objp: connector);
4878	}
4879
4880	return 0;
4881	}
4882
4883	static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port)
4884	{
4885	struct intel_display *display = to_intel_display(dig_port);
4886
4887	if (dig_port->base.port != PORT_A)
4888	return false;
4889
4890	if (dig_port->ddi_a_4_lanes)
4891	return false;
4892
4893	/* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only
4894	* supported configuration
4895	*/
4896	if (display->platform.geminilake || display->platform.broxton)
4897	return true;
4898
4899	return false;
4900	}
4901
4902	static int
4903	intel_ddi_max_lanes(struct intel_digital_port *dig_port)
4904	{
4905	struct intel_display *display = to_intel_display(dig_port);
4906	enum port port = dig_port->base.port;
4907	int max_lanes = 4;
4908
4909	if (DISPLAY_VER(display) >= 11)
4910	return max_lanes;
4911
4912	if (port == PORT_A || port == PORT_E) {
4913	if (intel_de_read(display, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
4914	max_lanes = port == PORT_A ? 4 : 0;
4915	else
4916	/* Both A and E share 2 lanes */
4917	max_lanes = 2;
4918	}
4919
4920	/*
4921	* Some BIOS might fail to set this bit on port A if eDP
4922	* wasn't lit up at boot. Force this bit set when needed
4923	* so we use the proper lane count for our calculations.
4924	*/
4925	if (intel_ddi_a_force_4_lanes(dig_port)) {
4926	drm_dbg_kms(display->drm,
4927	"Forcing DDI_A_4_LANES for port A\n");
4928	dig_port->ddi_a_4_lanes = true;
4929	max_lanes = 4;
4930	}
4931
4932	return max_lanes;
4933	}
4934
4935	static enum hpd_pin xelpd_hpd_pin(struct intel_display *display, enum port port)
4936	{
4937	if (port >= PORT_D_XELPD)
4938	return HPD_PORT_D + port - PORT_D_XELPD;
4939	else if (port >= PORT_TC1)
4940	return HPD_PORT_TC1 + port - PORT_TC1;
4941	else
4942	return HPD_PORT_A + port - PORT_A;
4943	}
4944
4945	static enum hpd_pin dg1_hpd_pin(struct intel_display *display, enum port port)
4946	{
4947	if (port >= PORT_TC1)
4948	return HPD_PORT_C + port - PORT_TC1;
4949	else
4950	return HPD_PORT_A + port - PORT_A;
4951	}
4952
4953	static enum hpd_pin tgl_hpd_pin(struct intel_display *display, enum port port)
4954	{
4955	if (port >= PORT_TC1)
4956	return HPD_PORT_TC1 + port - PORT_TC1;
4957	else
4958	return HPD_PORT_A + port - PORT_A;
4959	}
4960
4961	static enum hpd_pin rkl_hpd_pin(struct intel_display *display, enum port port)
4962	{
4963	if (HAS_PCH_TGP(display))
4964	return tgl_hpd_pin(display, port);
4965
4966	if (port >= PORT_TC1)
4967	return HPD_PORT_C + port - PORT_TC1;
4968	else
4969	return HPD_PORT_A + port - PORT_A;
4970	}
4971
4972	static enum hpd_pin icl_hpd_pin(struct intel_display *display, enum port port)
4973	{
4974	if (port >= PORT_C)
4975	return HPD_PORT_TC1 + port - PORT_C;
4976	else
4977	return HPD_PORT_A + port - PORT_A;
4978	}
4979
4980	static enum hpd_pin ehl_hpd_pin(struct intel_display *display, enum port port)
4981	{
4982	if (port == PORT_D)
4983	return HPD_PORT_A;
4984
4985	if (HAS_PCH_TGP(display))
4986	return icl_hpd_pin(display, port);
4987
4988	return HPD_PORT_A + port - PORT_A;
4989	}
4990
4991	static enum hpd_pin skl_hpd_pin(struct intel_display *display, enum port port)
4992	{
4993	if (HAS_PCH_TGP(display))
4994	return icl_hpd_pin(display, port);
4995
4996	return HPD_PORT_A + port - PORT_A;
4997	}
4998
4999	static bool intel_ddi_is_tc(struct intel_display *display, enum port port)
5000	{
5001	if (DISPLAY_VER(display) >= 12)
5002	return port >= PORT_TC1;
5003	else if (DISPLAY_VER(display) >= 11)
5004	return port >= PORT_C;
5005	else
5006	return false;
5007	}
5008
5009	static void intel_ddi_encoder_suspend(struct intel_encoder *encoder)
5010	{
5011	intel_dp_encoder_suspend(intel_encoder: encoder);
5012	}
5013
5014	static void intel_ddi_tc_encoder_suspend_complete(struct intel_encoder *encoder)
5015	{
5016	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5017	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5018
5019	/*
5020	* TODO: Move this to intel_dp_encoder_suspend(),
5021	* once modeset locking around that is removed.
5022	*/
5023	intel_encoder_link_check_flush_work(encoder);
5024	intel_tc_port_suspend(dig_port);
5025	}
5026
5027	static void intel_ddi_encoder_shutdown(struct intel_encoder *encoder)
5028	{
5029	if (intel_encoder_is_dp(encoder))
5030	intel_dp_encoder_shutdown(intel_encoder: encoder);
5031	if (intel_encoder_is_hdmi(encoder))
5032	intel_hdmi_encoder_shutdown(encoder);
5033	}
5034
5035	static void intel_ddi_tc_encoder_shutdown_complete(struct intel_encoder *encoder)
5036	{
5037	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5038	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5039
5040	intel_tc_port_cleanup(dig_port);
5041	}
5042
5043	#define port_tc_name(port) ((port) - PORT_TC1 + '1')
5044	#define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1')
5045
5046	static bool port_strap_detected(struct intel_display *display, enum port port)
5047	{
5048	/* straps not used on skl+ */
5049	if (DISPLAY_VER(display) >= 9)
5050	return true;
5051
5052	switch (port) {
5053	case PORT_A:
5054	return intel_de_read(display, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
5055	case PORT_B:
5056	return intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_DDIB_DETECTED;
5057	case PORT_C:
5058	return intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_DDIC_DETECTED;
5059	case PORT_D:
5060	return intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_DDID_DETECTED;
5061	case PORT_E:
5062	return true; /* no strap for DDI-E */
5063	default:
5064	MISSING_CASE(port);
5065	return false;
5066	}
5067	}
5068
5069	static bool need_aux_ch(struct intel_encoder *encoder, bool init_dp)
5070	{
5071	return init_dp || intel_encoder_is_tc(encoder);
5072	}
5073
5074	static bool assert_has_icl_dsi(struct intel_display *display)
5075	{
5076	return !drm_WARN(display->drm, !display->platform.alderlake_p &&
5077	!display->platform.tigerlake && DISPLAY_VER(display) != 11,
5078	"Platform does not support DSI\n");
5079	}
5080
5081	static bool port_in_use(struct intel_display *display, enum port port)
5082	{
5083	struct intel_encoder *encoder;
5084
5085	for_each_intel_encoder(display->drm, encoder) {
5086	/* FIXME what about second port for dual link DSI? */
5087	if (encoder->port == port)
5088	return true;
5089	}
5090
5091	return false;
5092	}
5093
5094	static const char *intel_ddi_encoder_name(struct intel_display *display,
5095	enum port port, enum phy phy,
5096	struct seq_buf *s)
5097	{
5098	if (DISPLAY_VER(display) >= 13 && port >= PORT_D_XELPD) {
5099	seq_buf_printf(s, fmt: "DDI %c/PHY %c",
5100	port_name(port - PORT_D_XELPD + PORT_D),
5101	phy_name(phy));
5102	} else if (DISPLAY_VER(display) >= 12) {
5103	enum tc_port tc_port = intel_port_to_tc(display, port);
5104
5105	seq_buf_printf(s, fmt: "DDI %s%c/PHY %s%c",
5106	port >= PORT_TC1 ? "TC" : "",
5107	port >= PORT_TC1 ? port_tc_name(port) : port_name(port),
5108	tc_port != TC_PORT_NONE ? "TC" : "",
5109	tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy));
5110	} else if (DISPLAY_VER(display) >= 11) {
5111	enum tc_port tc_port = intel_port_to_tc(display, port);
5112
5113	seq_buf_printf(s, fmt: "DDI %c%s/PHY %s%c",
5114	port_name(port),
5115	port >= PORT_C ? " (TC)" : "",
5116	tc_port != TC_PORT_NONE ? "TC" : "",
5117	tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy));
5118	} else {
5119	seq_buf_printf(s, fmt: "DDI %c/PHY %c", port_name(port), phy_name(phy));
5120	}
5121
5122	drm_WARN_ON(display->drm, seq_buf_has_overflowed(s));
5123
5124	return seq_buf_str(s);
5125	}
5126
5127	void intel_ddi_init(struct intel_display *display,
5128	const struct intel_bios_encoder_data *devdata)
5129	{
5130	struct intel_digital_port *dig_port;
5131	struct intel_encoder *encoder;
5132	DECLARE_SEQ_BUF(encoder_name, 20);
5133	bool init_hdmi, init_dp;
5134	enum port port;
5135	enum phy phy;
5136	u32 ddi_buf_ctl;
5137
5138	port = intel_bios_encoder_port(devdata);
5139	if (port == PORT_NONE)
5140	return;
5141
5142	if (!port_strap_detected(display, port)) {
5143	drm_dbg_kms(display->drm,
5144	"Port %c strap not detected\n", port_name(port));
5145	return;
5146	}
5147
5148	if (!assert_port_valid(display, port))
5149	return;
5150
5151	if (port_in_use(display, port)) {
5152	drm_dbg_kms(display->drm,
5153	"Port %c already claimed\n", port_name(port));
5154	return;
5155	}
5156
5157	if (intel_bios_encoder_supports_dsi(devdata)) {
5158	/* BXT/GLK handled elsewhere, for now at least */
5159	if (!assert_has_icl_dsi(display))
5160	return;
5161
5162	icl_dsi_init(display, devdata);
5163	return;
5164	}
5165
5166	phy = intel_port_to_phy(display, port);
5167
5168	/*
5169	* On platforms with HTI (aka HDPORT), if it's enabled at boot it may
5170	* have taken over some of the PHYs and made them unavailable to the
5171	* driver. In that case we should skip initializing the corresponding
5172	* outputs.
5173	*/
5174	if (intel_hti_uses_phy(display, phy)) {
5175	drm_dbg_kms(display->drm, "PORT %c / PHY %c reserved by HTI\n",
5176	port_name(port), phy_name(phy));
5177	return;
5178	}
5179
5180	init_hdmi = intel_bios_encoder_supports_dvi(devdata) ||
5181	intel_bios_encoder_supports_hdmi(devdata);
5182	init_dp = intel_bios_encoder_supports_dp(devdata);
5183
5184	if (intel_bios_encoder_is_lspcon(devdata)) {
5185	/*
5186	* Lspcon device needs to be driven with DP connector
5187	* with special detection sequence. So make sure DP
5188	* is initialized before lspcon.
5189	*/
5190	init_dp = true;
5191	init_hdmi = false;
5192	drm_dbg_kms(display->drm, "VBT says port %c has lspcon\n",
5193	port_name(port));
5194	}
5195
5196	if (!init_dp && !init_hdmi) {
5197	drm_dbg_kms(display->drm,
5198	"VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
5199	port_name(port));
5200	return;
5201	}
5202
5203	if (intel_phy_is_snps(display, phy) &&
5204	display->snps.phy_failed_calibration & BIT(phy)) {
5205	drm_dbg_kms(display->drm,
5206	"SNPS PHY %c failed to calibrate, proceeding anyway\n",
5207	phy_name(phy));
5208	}
5209
5210	dig_port = intel_dig_port_alloc();
5211	if (!dig_port)
5212	return;
5213
5214	encoder = &dig_port->base;
5215	encoder->devdata = devdata;
5216
5217	drm_encoder_init(dev: display->drm, encoder: &encoder->base, funcs: &intel_ddi_funcs,
5218	DRM_MODE_ENCODER_TMDS, name: "%s",
5219	intel_ddi_encoder_name(display, port, phy, s: &encoder_name));
5220
5221	intel_encoder_link_check_init(encoder, callback: intel_ddi_link_check);
5222
5223	encoder->hotplug = intel_ddi_hotplug;
5224	encoder->compute_output_type = intel_ddi_compute_output_type;
5225	encoder->compute_config = intel_ddi_compute_config;
5226	encoder->compute_config_late = intel_ddi_compute_config_late;
5227	encoder->enable = intel_ddi_enable;
5228	encoder->pre_pll_enable = intel_ddi_pre_pll_enable;
5229	encoder->pre_enable = intel_ddi_pre_enable;
5230	encoder->disable = intel_ddi_disable;
5231	encoder->post_pll_disable = intel_ddi_post_pll_disable;
5232	encoder->post_disable = intel_ddi_post_disable;
5233	encoder->update_pipe = intel_ddi_update_pipe;
5234	encoder->audio_enable = intel_audio_codec_enable;
5235	encoder->audio_disable = intel_audio_codec_disable;
5236	encoder->get_hw_state = intel_ddi_get_hw_state;
5237	encoder->sync_state = intel_ddi_sync_state;
5238	encoder->initial_fastset_check = intel_ddi_initial_fastset_check;
5239	encoder->suspend = intel_ddi_encoder_suspend;
5240	encoder->shutdown = intel_ddi_encoder_shutdown;
5241	encoder->get_power_domains = intel_ddi_get_power_domains;
5242
5243	encoder->type = INTEL_OUTPUT_DDI;
5244	encoder->power_domain = intel_display_power_ddi_lanes_domain(display, port);
5245	encoder->port = port;
5246	encoder->cloneable = 0;
5247	encoder->pipe_mask = ~0;
5248
5249	if (HAS_LT_PHY(display)) {
5250	encoder->enable_clock = intel_xe3plpd_pll_enable;
5251	encoder->disable_clock = intel_xe3plpd_pll_disable;
5252	encoder->port_pll_type = intel_mtl_port_pll_type;
5253	encoder->get_config = xe3plpd_ddi_get_config;
5254	} else if (DISPLAY_VER(display) >= 14) {
5255	encoder->enable_clock = intel_mtl_pll_enable;
5256	encoder->disable_clock = intel_mtl_pll_disable;
5257	encoder->port_pll_type = intel_mtl_port_pll_type;
5258	encoder->get_config = mtl_ddi_get_config;
5259	} else if (display->platform.dg2) {
5260	encoder->enable_clock = intel_mpllb_enable;
5261	encoder->disable_clock = intel_mpllb_disable;
5262	encoder->get_config = dg2_ddi_get_config;
5263	} else if (display->platform.alderlake_s) {
5264	encoder->enable_clock = adls_ddi_enable_clock;
5265	encoder->disable_clock = adls_ddi_disable_clock;
5266	encoder->is_clock_enabled = adls_ddi_is_clock_enabled;
5267	encoder->get_config = adls_ddi_get_config;
5268	} else if (display->platform.rocketlake) {
5269	encoder->enable_clock = rkl_ddi_enable_clock;
5270	encoder->disable_clock = rkl_ddi_disable_clock;
5271	encoder->is_clock_enabled = rkl_ddi_is_clock_enabled;
5272	encoder->get_config = rkl_ddi_get_config;
5273	} else if (display->platform.dg1) {
5274	encoder->enable_clock = dg1_ddi_enable_clock;
5275	encoder->disable_clock = dg1_ddi_disable_clock;
5276	encoder->is_clock_enabled = dg1_ddi_is_clock_enabled;
5277	encoder->get_config = dg1_ddi_get_config;
5278	} else if (display->platform.jasperlake || display->platform.elkhartlake) {
5279	if (intel_ddi_is_tc(display, port)) {
5280	encoder->enable_clock = jsl_ddi_tc_enable_clock;
5281	encoder->disable_clock = jsl_ddi_tc_disable_clock;
5282	encoder->is_clock_enabled = jsl_ddi_tc_is_clock_enabled;
5283	encoder->port_pll_type = icl_ddi_tc_port_pll_type;
5284	encoder->get_config = icl_ddi_combo_get_config;
5285	} else {
5286	encoder->enable_clock = icl_ddi_combo_enable_clock;
5287	encoder->disable_clock = icl_ddi_combo_disable_clock;
5288	encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled;
5289	encoder->get_config = icl_ddi_combo_get_config;
5290	}
5291	} else if (DISPLAY_VER(display) >= 11) {
5292	if (intel_ddi_is_tc(display, port)) {
5293	encoder->enable_clock = icl_ddi_tc_enable_clock;
5294	encoder->disable_clock = icl_ddi_tc_disable_clock;
5295	encoder->is_clock_enabled = icl_ddi_tc_is_clock_enabled;
5296	encoder->port_pll_type = icl_ddi_tc_port_pll_type;
5297	encoder->get_config = icl_ddi_tc_get_config;
5298	} else {
5299	encoder->enable_clock = icl_ddi_combo_enable_clock;
5300	encoder->disable_clock = icl_ddi_combo_disable_clock;
5301	encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled;
5302	encoder->get_config = icl_ddi_combo_get_config;
5303	}
5304	} else if (display->platform.geminilake || display->platform.broxton) {
5305	/* BXT/GLK have fixed PLL->port mapping */
5306	encoder->get_config = bxt_ddi_get_config;
5307	} else if (DISPLAY_VER(display) == 9) {
5308	encoder->enable_clock = skl_ddi_enable_clock;
5309	encoder->disable_clock = skl_ddi_disable_clock;
5310	encoder->is_clock_enabled = skl_ddi_is_clock_enabled;
5311	encoder->get_config = skl_ddi_get_config;
5312	} else if (display->platform.broadwell || display->platform.haswell) {
5313	encoder->enable_clock = hsw_ddi_enable_clock;
5314	encoder->disable_clock = hsw_ddi_disable_clock;
5315	encoder->is_clock_enabled = hsw_ddi_is_clock_enabled;
5316	encoder->get_config = hsw_ddi_get_config;
5317	}
5318
5319	if (HAS_LT_PHY(display)) {
5320	encoder->set_signal_levels = intel_lt_phy_set_signal_levels;
5321	} else if (DISPLAY_VER(display) >= 14) {
5322	encoder->set_signal_levels = intel_cx0_phy_set_signal_levels;
5323	} else if (display->platform.dg2) {
5324	encoder->set_signal_levels = intel_snps_phy_set_signal_levels;
5325	} else if (DISPLAY_VER(display) >= 12) {
5326	if (intel_encoder_is_combo(encoder))
5327	encoder->set_signal_levels = icl_combo_phy_set_signal_levels;
5328	else
5329	encoder->set_signal_levels = tgl_dkl_phy_set_signal_levels;
5330	} else if (DISPLAY_VER(display) >= 11) {
5331	if (intel_encoder_is_combo(encoder))
5332	encoder->set_signal_levels = icl_combo_phy_set_signal_levels;
5333	else
5334	encoder->set_signal_levels = icl_mg_phy_set_signal_levels;
5335	} else if (display->platform.geminilake || display->platform.broxton) {
5336	encoder->set_signal_levels = bxt_dpio_phy_set_signal_levels;
5337	} else {
5338	encoder->set_signal_levels = hsw_set_signal_levels;
5339	}
5340
5341	intel_ddi_buf_trans_init(encoder);
5342
5343	if (DISPLAY_VER(display) >= 13)
5344	encoder->hpd_pin = xelpd_hpd_pin(display, port);
5345	else if (display->platform.dg1)
5346	encoder->hpd_pin = dg1_hpd_pin(display, port);
5347	else if (display->platform.rocketlake)
5348	encoder->hpd_pin = rkl_hpd_pin(display, port);
5349	else if (DISPLAY_VER(display) >= 12)
5350	encoder->hpd_pin = tgl_hpd_pin(display, port);
5351	else if (display->platform.jasperlake || display->platform.elkhartlake)
5352	encoder->hpd_pin = ehl_hpd_pin(display, port);
5353	else if (DISPLAY_VER(display) == 11)
5354	encoder->hpd_pin = icl_hpd_pin(display, port);
5355	else if (DISPLAY_VER(display) == 9 && !display->platform.broxton)
5356	encoder->hpd_pin = skl_hpd_pin(display, port);
5357	else
5358	encoder->hpd_pin = intel_hpd_pin_default(port);
5359
5360	ddi_buf_ctl = intel_de_read(display, DDI_BUF_CTL(port));
5361
5362	dig_port->lane_reversal = intel_bios_encoder_lane_reversal(devdata) ||
5363	ddi_buf_ctl & DDI_BUF_PORT_REVERSAL;
5364
5365	dig_port->ddi_a_4_lanes = DISPLAY_VER(display) < 11 && ddi_buf_ctl & DDI_A_4_LANES;
5366
5367	dig_port->max_lanes = intel_ddi_max_lanes(dig_port);
5368
5369	if (need_aux_ch(encoder, init_dp)) {
5370	dig_port->aux_ch = intel_dp_aux_ch(encoder);
5371	if (dig_port->aux_ch == AUX_CH_NONE)
5372	goto err;
5373	}
5374
5375	if (intel_encoder_is_tc(encoder)) {
5376	bool is_legacy =
5377	!intel_bios_encoder_supports_typec_usb(devdata) &&
5378	!intel_bios_encoder_supports_tbt(devdata);
5379
5380	if (!is_legacy && init_hdmi) {
5381	is_legacy = !init_dp;
5382
5383	drm_dbg_kms(display->drm,
5384	"VBT says port %c is non-legacy TC and has HDMI (with DP: %s), assume it's %s\n",
5385	port_name(port),
5386	str_yes_no(init_dp),
5387	is_legacy ? "legacy" : "non-legacy");
5388	}
5389
5390	encoder->suspend_complete = intel_ddi_tc_encoder_suspend_complete;
5391	encoder->shutdown_complete = intel_ddi_tc_encoder_shutdown_complete;
5392
5393	dig_port->lock = intel_tc_port_lock;
5394	dig_port->unlock = intel_tc_port_unlock;
5395
5396	if (intel_tc_port_init(dig_port, is_legacy) < 0)
5397	goto err;
5398	}
5399
5400	drm_WARN_ON(display->drm, port > PORT_I);
5401	dig_port->ddi_io_power_domain = intel_display_power_ddi_io_domain(display, port);
5402
5403	if (DISPLAY_VER(display) >= 11) {
5404	if (intel_encoder_is_tc(encoder))
5405	dig_port->connected = intel_tc_port_connected;
5406	else
5407	dig_port->connected = lpt_digital_port_connected;
5408	} else if (display->platform.geminilake || display->platform.broxton) {
5409	dig_port->connected = bdw_digital_port_connected;
5410	} else if (DISPLAY_VER(display) == 9) {
5411	dig_port->connected = lpt_digital_port_connected;
5412	} else if (display->platform.broadwell) {
5413	if (port == PORT_A)
5414	dig_port->connected = bdw_digital_port_connected;
5415	else
5416	dig_port->connected = lpt_digital_port_connected;
5417	} else if (display->platform.haswell) {
5418	if (port == PORT_A)
5419	dig_port->connected = hsw_digital_port_connected;
5420	else
5421	dig_port->connected = lpt_digital_port_connected;
5422	}
5423
5424	intel_infoframe_init(dig_port);
5425
5426	if (init_dp) {
5427	if (intel_ddi_init_dp_connector(dig_port))
5428	goto err;
5429
5430	dig_port->hpd_pulse = intel_dp_hpd_pulse;
5431
5432	if (dig_port->dp.mso_link_count)
5433	encoder->pipe_mask = intel_ddi_splitter_pipe_mask(display);
5434	}
5435
5436	/*
5437	* In theory we don't need the encoder->type check,
5438	* but leave it just in case we have some really bad VBTs...
5439	*/
5440	if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
5441	if (intel_ddi_init_hdmi_connector(dig_port))
5442	goto err;
5443	}
5444
5445	return;
5446
5447	err:
5448	drm_encoder_cleanup(encoder: &encoder->base);
5449	kfree(objp: dig_port);
5450	}
5451