| 1 | /* SPDX-License-Identifier: MIT */ |
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| 2 | /* |
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| 3 | * Copyright © 2022 Intel Corporation |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef __INTEL_MG_PHY_REGS__ |
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| 7 | #define __INTEL_MG_PHY_REGS__ |
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| 8 | |
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| 9 | #include "intel_display_reg_defs.h" |
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| 10 | |
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| 11 | #define MG_PHY_PORT_LN(ln, tc_port, ln0p1, ln0p2, ln1p1) \ |
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| 12 | _MMIO(_PORT(tc_port, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1))) |
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| 13 | |
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| 14 | #define MG_TX_LINK_PARAMS_TX1LN0_PORT1 0x16812C |
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| 15 | #define MG_TX_LINK_PARAMS_TX1LN1_PORT1 0x16852C |
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| 16 | #define MG_TX_LINK_PARAMS_TX1LN0_PORT2 0x16912C |
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| 17 | #define MG_TX_LINK_PARAMS_TX1LN1_PORT2 0x16952C |
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| 18 | #define MG_TX1_LINK_PARAMS(ln, tc_port) \ |
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| 19 | MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX1LN0_PORT1, \ |
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| 20 | MG_TX_LINK_PARAMS_TX1LN0_PORT2, \ |
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| 21 | MG_TX_LINK_PARAMS_TX1LN1_PORT1) |
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| 22 | |
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| 23 | #define MG_TX_LINK_PARAMS_TX2LN0_PORT1 0x1680AC |
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| 24 | #define MG_TX_LINK_PARAMS_TX2LN1_PORT1 0x1684AC |
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| 25 | #define MG_TX_LINK_PARAMS_TX2LN0_PORT2 0x1690AC |
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| 26 | #define MG_TX_LINK_PARAMS_TX2LN1_PORT2 0x1694AC |
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| 27 | #define MG_TX2_LINK_PARAMS(ln, tc_port) \ |
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| 28 | MG_PHY_PORT_LN(ln, tc_port, MG_TX_LINK_PARAMS_TX2LN0_PORT1, \ |
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| 29 | MG_TX_LINK_PARAMS_TX2LN0_PORT2, \ |
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| 30 | MG_TX_LINK_PARAMS_TX2LN1_PORT1) |
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| 31 | #define CRI_USE_FS32 (1 << 5) |
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| 32 | |
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| 33 | #define MG_TX_PISO_READLOAD_TX1LN0_PORT1 0x16814C |
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| 34 | #define MG_TX_PISO_READLOAD_TX1LN1_PORT1 0x16854C |
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| 35 | #define MG_TX_PISO_READLOAD_TX1LN0_PORT2 0x16914C |
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| 36 | #define MG_TX_PISO_READLOAD_TX1LN1_PORT2 0x16954C |
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| 37 | #define MG_TX1_PISO_READLOAD(ln, tc_port) \ |
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| 38 | MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX1LN0_PORT1, \ |
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| 39 | MG_TX_PISO_READLOAD_TX1LN0_PORT2, \ |
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| 40 | MG_TX_PISO_READLOAD_TX1LN1_PORT1) |
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| 41 | |
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| 42 | #define MG_TX_PISO_READLOAD_TX2LN0_PORT1 0x1680CC |
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| 43 | #define MG_TX_PISO_READLOAD_TX2LN1_PORT1 0x1684CC |
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| 44 | #define MG_TX_PISO_READLOAD_TX2LN0_PORT2 0x1690CC |
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| 45 | #define MG_TX_PISO_READLOAD_TX2LN1_PORT2 0x1694CC |
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| 46 | #define MG_TX2_PISO_READLOAD(ln, tc_port) \ |
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| 47 | MG_PHY_PORT_LN(ln, tc_port, MG_TX_PISO_READLOAD_TX2LN0_PORT1, \ |
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| 48 | MG_TX_PISO_READLOAD_TX2LN0_PORT2, \ |
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| 49 | MG_TX_PISO_READLOAD_TX2LN1_PORT1) |
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| 50 | #define CRI_CALCINIT (1 << 1) |
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| 51 | |
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| 52 | #define MG_TX_SWINGCTRL_TX1LN0_PORT1 0x168148 |
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| 53 | #define MG_TX_SWINGCTRL_TX1LN1_PORT1 0x168548 |
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| 54 | #define MG_TX_SWINGCTRL_TX1LN0_PORT2 0x169148 |
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| 55 | #define MG_TX_SWINGCTRL_TX1LN1_PORT2 0x169548 |
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| 56 | #define MG_TX1_SWINGCTRL(ln, tc_port) \ |
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| 57 | MG_PHY_PORT_LN(ln, tc_port, MG_TX_SWINGCTRL_TX1LN0_PORT1, \ |
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| 58 | MG_TX_SWINGCTRL_TX1LN0_PORT2, \ |
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| 59 | MG_TX_SWINGCTRL_TX1LN1_PORT1) |
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| 60 | |
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| 61 | #define MG_TX_SWINGCTRL_TX2LN0_PORT1 0x1680C8 |
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| 62 | #define MG_TX_SWINGCTRL_TX2LN1_PORT1 0x1684C8 |
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| 63 | #define MG_TX_SWINGCTRL_TX2LN0_PORT2 0x1690C8 |
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| 64 | #define MG_TX_SWINGCTRL_TX2LN1_PORT2 0x1694C8 |
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| 65 | #define MG_TX2_SWINGCTRL(ln, tc_port) \ |
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| 66 | MG_PHY_PORT_LN(ln, tc_port, MG_TX_SWINGCTRL_TX2LN0_PORT1, \ |
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| 67 | MG_TX_SWINGCTRL_TX2LN0_PORT2, \ |
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| 68 | MG_TX_SWINGCTRL_TX2LN1_PORT1) |
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| 69 | #define CRI_TXDEEMPH_OVERRIDE_17_12(x) ((x) << 0) |
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| 70 | #define CRI_TXDEEMPH_OVERRIDE_17_12_MASK (0x3F << 0) |
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| 71 | |
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| 72 | #define MG_TX_DRVCTRL_TX1LN0_TXPORT1 0x168144 |
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| 73 | #define MG_TX_DRVCTRL_TX1LN1_TXPORT1 0x168544 |
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| 74 | #define MG_TX_DRVCTRL_TX1LN0_TXPORT2 0x169144 |
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| 75 | #define MG_TX_DRVCTRL_TX1LN1_TXPORT2 0x169544 |
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| 76 | #define MG_TX_DRVCTRL_TX1LN0_TXPORT3 0x16A144 |
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| 77 | #define MG_TX_DRVCTRL_TX1LN1_TXPORT3 0x16A544 |
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| 78 | #define MG_TX_DRVCTRL_TX1LN0_TXPORT4 0x16B144 |
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| 79 | #define MG_TX_DRVCTRL_TX1LN1_TXPORT4 0x16B544 |
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| 80 | #define MG_TX1_DRVCTRL(ln, tc_port) \ |
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| 81 | MG_PHY_PORT_LN(ln, tc_port, MG_TX_DRVCTRL_TX1LN0_TXPORT1, \ |
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| 82 | MG_TX_DRVCTRL_TX1LN0_TXPORT2, \ |
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| 83 | MG_TX_DRVCTRL_TX1LN1_TXPORT1) |
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| 84 | |
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| 85 | #define MG_TX_DRVCTRL_TX2LN0_PORT1 0x1680C4 |
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| 86 | #define MG_TX_DRVCTRL_TX2LN1_PORT1 0x1684C4 |
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| 87 | #define MG_TX_DRVCTRL_TX2LN0_PORT2 0x1690C4 |
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| 88 | #define MG_TX_DRVCTRL_TX2LN1_PORT2 0x1694C4 |
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| 89 | #define MG_TX2_DRVCTRL(ln, tc_port) \ |
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| 90 | MG_PHY_PORT_LN(ln, tc_port, MG_TX_DRVCTRL_TX2LN0_PORT1, \ |
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| 91 | MG_TX_DRVCTRL_TX2LN0_PORT2, \ |
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| 92 | MG_TX_DRVCTRL_TX2LN1_PORT1) |
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| 93 | #define CRI_TXDEEMPH_OVERRIDE_11_6(x) ((x) << 24) |
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| 94 | #define CRI_TXDEEMPH_OVERRIDE_11_6_MASK (0x3F << 24) |
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| 95 | #define CRI_TXDEEMPH_OVERRIDE_EN (1 << 22) |
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| 96 | #define CRI_TXDEEMPH_OVERRIDE_5_0(x) ((x) << 16) |
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| 97 | #define CRI_TXDEEMPH_OVERRIDE_5_0_MASK (0x3F << 16) |
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| 98 | #define CRI_LOADGEN_SEL(x) ((x) << 12) |
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| 99 | #define CRI_LOADGEN_SEL_MASK (0x3 << 12) |
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| 100 | |
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| 101 | #define MG_CLKHUB_LN0_PORT1 0x16839C |
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| 102 | #define MG_CLKHUB_LN1_PORT1 0x16879C |
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| 103 | #define MG_CLKHUB_LN0_PORT2 0x16939C |
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| 104 | #define MG_CLKHUB_LN1_PORT2 0x16979C |
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| 105 | #define MG_CLKHUB(ln, tc_port) \ |
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| 106 | MG_PHY_PORT_LN(ln, tc_port, MG_CLKHUB_LN0_PORT1, \ |
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| 107 | MG_CLKHUB_LN0_PORT2, \ |
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| 108 | MG_CLKHUB_LN1_PORT1) |
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| 109 | #define CFG_LOW_RATE_LKREN_EN (1 << 11) |
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| 110 | |
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| 111 | #define MG_TX_DCC_TX1LN0_PORT1 0x168110 |
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| 112 | #define MG_TX_DCC_TX1LN1_PORT1 0x168510 |
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| 113 | #define MG_TX_DCC_TX1LN0_PORT2 0x169110 |
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| 114 | #define MG_TX_DCC_TX1LN1_PORT2 0x169510 |
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| 115 | #define MG_TX1_DCC(ln, tc_port) \ |
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| 116 | MG_PHY_PORT_LN(ln, tc_port, MG_TX_DCC_TX1LN0_PORT1, \ |
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| 117 | MG_TX_DCC_TX1LN0_PORT2, \ |
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| 118 | MG_TX_DCC_TX1LN1_PORT1) |
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| 119 | #define MG_TX_DCC_TX2LN0_PORT1 0x168090 |
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| 120 | #define MG_TX_DCC_TX2LN1_PORT1 0x168490 |
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| 121 | #define MG_TX_DCC_TX2LN0_PORT2 0x169090 |
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| 122 | #define MG_TX_DCC_TX2LN1_PORT2 0x169490 |
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| 123 | #define MG_TX2_DCC(ln, tc_port) \ |
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| 124 | MG_PHY_PORT_LN(ln, tc_port, MG_TX_DCC_TX2LN0_PORT1, \ |
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| 125 | MG_TX_DCC_TX2LN0_PORT2, \ |
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| 126 | MG_TX_DCC_TX2LN1_PORT1) |
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| 127 | #define CFG_AMI_CK_DIV_OVERRIDE_VAL(x) ((x) << 25) |
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| 128 | #define CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK (0x3 << 25) |
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| 129 | #define CFG_AMI_CK_DIV_OVERRIDE_EN (1 << 24) |
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| 130 | |
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| 131 | #define MG_DP_MODE_LN0_ACU_PORT1 0x1683A0 |
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| 132 | #define MG_DP_MODE_LN1_ACU_PORT1 0x1687A0 |
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| 133 | #define MG_DP_MODE_LN0_ACU_PORT2 0x1693A0 |
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| 134 | #define MG_DP_MODE_LN1_ACU_PORT2 0x1697A0 |
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| 135 | #define MG_DP_MODE(ln, tc_port) \ |
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| 136 | MG_PHY_PORT_LN(ln, tc_port, MG_DP_MODE_LN0_ACU_PORT1, \ |
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| 137 | MG_DP_MODE_LN0_ACU_PORT2, \ |
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| 138 | MG_DP_MODE_LN1_ACU_PORT1) |
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| 139 | #define MG_DP_MODE_CFG_DP_X2_MODE (1 << 7) |
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| 140 | #define MG_DP_MODE_CFG_DP_X1_MODE (1 << 6) |
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| 141 | |
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| 142 | #define FIA1_BASE 0x163000 |
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| 143 | #define FIA2_BASE 0x16E000 |
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| 144 | #define FIA3_BASE 0x16F000 |
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| 145 | #define _FIA(fia) _PICK_EVEN_2RANGES((fia), 1, \ |
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| 146 | FIA1_BASE, FIA1_BASE,\ |
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| 147 | FIA2_BASE, FIA3_BASE) |
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| 148 | #define _MMIO_FIA(fia, off) _MMIO(_FIA(fia) + (off)) |
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| 149 | |
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| 150 | /* ICL PHY DFLEX registers */ |
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| 151 | #define PORT_TX_DFLEXDPMLE1(fia) _MMIO_FIA((fia), 0x008C0) |
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| 152 | #define DFLEXDPMLE1_DPMLETC_MASK(idx) (0xf << (4 * (idx))) |
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| 153 | #define DFLEXDPMLE1_DPMLETC_ML0(idx) (1 << (4 * (idx))) |
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| 154 | #define DFLEXDPMLE1_DPMLETC_ML1_0(idx) (3 << (4 * (idx))) |
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| 155 | #define DFLEXDPMLE1_DPMLETC_ML3(idx) (8 << (4 * (idx))) |
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| 156 | #define DFLEXDPMLE1_DPMLETC_ML3_2(idx) (12 << (4 * (idx))) |
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| 157 | #define DFLEXDPMLE1_DPMLETC_ML3_0(idx) (15 << (4 * (idx))) |
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| 158 | |
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| 159 | #define _MG_REFCLKIN_CTL_PORT1 0x16892C |
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| 160 | #define _MG_REFCLKIN_CTL_PORT2 0x16992C |
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| 161 | #define MG_REFCLKIN_CTL_OD_2_MUX(x) ((x) << 8) |
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| 162 | #define MG_REFCLKIN_CTL_OD_2_MUX_MASK (0x7 << 8) |
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| 163 | #define MG_REFCLKIN_CTL(tc_port) _MMIO_PORT((tc_port), \ |
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| 164 | _MG_REFCLKIN_CTL_PORT1, \ |
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| 165 | _MG_REFCLKIN_CTL_PORT2) |
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| 166 | |
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| 167 | #define _MG_CLKTOP2_CORECLKCTL1_PORT1 0x1688D8 |
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| 168 | #define _MG_CLKTOP2_CORECLKCTL1_PORT2 0x1698D8 |
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| 169 | #define MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO(x) ((x) << 16) |
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| 170 | #define MG_CLKTOP2_CORECLKCTL1_B_DIVRATIO_MASK (0xff << 16) |
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| 171 | #define MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO(x) ((x) << 8) |
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| 172 | #define MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK (0xff << 8) |
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| 173 | #define MG_CLKTOP2_CORECLKCTL1(tc_port) _MMIO_PORT((tc_port), \ |
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| 174 | _MG_CLKTOP2_CORECLKCTL1_PORT1, \ |
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| 175 | _MG_CLKTOP2_CORECLKCTL1_PORT2) |
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| 176 | |
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| 177 | #define _MG_CLKTOP2_HSCLKCTL_PORT1 0x1688D4 |
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| 178 | #define _MG_CLKTOP2_HSCLKCTL_PORT2 0x1698D4 |
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| 179 | #define MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL(x) ((x) << 16) |
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| 180 | #define MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK (0x1 << 16) |
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| 181 | #define MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL(x) ((x) << 14) |
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| 182 | #define MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK (0x3 << 14) |
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| 183 | #define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK (0x3 << 12) |
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| 184 | #define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2 (0 << 12) |
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| 185 | #define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3 (1 << 12) |
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| 186 | #define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5 (2 << 12) |
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| 187 | #define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7 (3 << 12) |
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| 188 | #define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(x) ((x) << 8) |
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| 189 | #define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT 8 |
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| 190 | #define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK (0xf << 8) |
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| 191 | #define MG_CLKTOP2_HSCLKCTL(tc_port) _MMIO_PORT((tc_port), \ |
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| 192 | _MG_CLKTOP2_HSCLKCTL_PORT1, \ |
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| 193 | _MG_CLKTOP2_HSCLKCTL_PORT2) |
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| 194 | |
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| 195 | #define _MG_PLL_DIV0_PORT1 0x168A00 |
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| 196 | #define _MG_PLL_DIV0_PORT2 0x169A00 |
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| 197 | #define MG_PLL_DIV0_FRACNEN_H (1 << 30) |
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| 198 | #define MG_PLL_DIV0_FBDIV_FRAC_MASK (0x3fffff << 8) |
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| 199 | #define MG_PLL_DIV0_FBDIV_FRAC_SHIFT 8 |
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| 200 | #define MG_PLL_DIV0_FBDIV_FRAC(x) ((x) << 8) |
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| 201 | #define MG_PLL_DIV0_FBDIV_INT_MASK (0xff << 0) |
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| 202 | #define MG_PLL_DIV0_FBDIV_INT(x) ((x) << 0) |
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| 203 | #define MG_PLL_DIV0(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV0_PORT1, \ |
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| 204 | _MG_PLL_DIV0_PORT2) |
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| 205 | |
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| 206 | #define _MG_PLL_DIV1_PORT1 0x168A04 |
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| 207 | #define _MG_PLL_DIV1_PORT2 0x169A04 |
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| 208 | #define MG_PLL_DIV1_IREF_NDIVRATIO(x) ((x) << 16) |
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| 209 | #define MG_PLL_DIV1_DITHER_DIV_1 (0 << 12) |
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| 210 | #define MG_PLL_DIV1_DITHER_DIV_2 (1 << 12) |
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| 211 | #define MG_PLL_DIV1_DITHER_DIV_4 (2 << 12) |
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| 212 | #define MG_PLL_DIV1_DITHER_DIV_8 (3 << 12) |
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| 213 | #define MG_PLL_DIV1_NDIVRATIO(x) ((x) << 4) |
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| 214 | #define MG_PLL_DIV1_FBPREDIV_MASK (0xf << 0) |
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| 215 | #define MG_PLL_DIV1_FBPREDIV(x) ((x) << 0) |
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| 216 | #define MG_PLL_DIV1(tc_port) _MMIO_PORT((tc_port), _MG_PLL_DIV1_PORT1, \ |
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| 217 | _MG_PLL_DIV1_PORT2) |
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| 218 | |
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| 219 | #define _MG_PLL_LF_PORT1 0x168A08 |
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| 220 | #define _MG_PLL_LF_PORT2 0x169A08 |
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| 221 | #define MG_PLL_LF_TDCTARGETCNT(x) ((x) << 24) |
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| 222 | #define MG_PLL_LF_AFCCNTSEL_256 (0 << 20) |
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| 223 | #define MG_PLL_LF_AFCCNTSEL_512 (1 << 20) |
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| 224 | #define MG_PLL_LF_GAINCTRL(x) ((x) << 16) |
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| 225 | #define MG_PLL_LF_INT_COEFF(x) ((x) << 8) |
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| 226 | #define MG_PLL_LF_PROP_COEFF(x) ((x) << 0) |
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| 227 | #define MG_PLL_LF(tc_port) _MMIO_PORT((tc_port), _MG_PLL_LF_PORT1, \ |
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| 228 | _MG_PLL_LF_PORT2) |
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| 229 | |
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| 230 | #define _MG_PLL_FRAC_LOCK_PORT1 0x168A0C |
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| 231 | #define _MG_PLL_FRAC_LOCK_PORT2 0x169A0C |
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| 232 | #define MG_PLL_FRAC_LOCK_TRUELOCK_CRIT_32 (1 << 18) |
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| 233 | #define MG_PLL_FRAC_LOCK_EARLYLOCK_CRIT_32 (1 << 16) |
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| 234 | #define MG_PLL_FRAC_LOCK_LOCKTHRESH(x) ((x) << 11) |
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| 235 | #define MG_PLL_FRAC_LOCK_DCODITHEREN (1 << 10) |
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| 236 | #define MG_PLL_FRAC_LOCK_FEEDFWRDCAL_EN (1 << 8) |
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| 237 | #define MG_PLL_FRAC_LOCK_FEEDFWRDGAIN(x) ((x) << 0) |
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| 238 | #define MG_PLL_FRAC_LOCK(tc_port) _MMIO_PORT((tc_port), \ |
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| 239 | _MG_PLL_FRAC_LOCK_PORT1, \ |
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| 240 | _MG_PLL_FRAC_LOCK_PORT2) |
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| 241 | |
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| 242 | #define _MG_PLL_SSC_PORT1 0x168A10 |
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| 243 | #define _MG_PLL_SSC_PORT2 0x169A10 |
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| 244 | #define MG_PLL_SSC_EN (1 << 28) |
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| 245 | #define MG_PLL_SSC_TYPE(x) ((x) << 26) |
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| 246 | #define MG_PLL_SSC_STEPLENGTH(x) ((x) << 16) |
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| 247 | #define MG_PLL_SSC_STEPNUM(x) ((x) << 10) |
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| 248 | #define MG_PLL_SSC_FLLEN (1 << 9) |
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| 249 | #define MG_PLL_SSC_STEPSIZE(x) ((x) << 0) |
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| 250 | #define MG_PLL_SSC(tc_port) _MMIO_PORT((tc_port), _MG_PLL_SSC_PORT1, \ |
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| 251 | _MG_PLL_SSC_PORT2) |
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| 252 | |
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| 253 | #define _MG_PLL_BIAS_PORT1 0x168A14 |
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| 254 | #define _MG_PLL_BIAS_PORT2 0x169A14 |
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| 255 | #define MG_PLL_BIAS_BIAS_GB_SEL(x) ((x) << 30) |
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| 256 | #define MG_PLL_BIAS_BIAS_GB_SEL_MASK (0x3 << 30) |
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| 257 | #define MG_PLL_BIAS_INIT_DCOAMP(x) ((x) << 24) |
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| 258 | #define MG_PLL_BIAS_INIT_DCOAMP_MASK (0x3f << 24) |
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| 259 | #define MG_PLL_BIAS_BIAS_BONUS(x) ((x) << 16) |
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| 260 | #define MG_PLL_BIAS_BIAS_BONUS_MASK (0xff << 16) |
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| 261 | #define MG_PLL_BIAS_BIASCAL_EN (1 << 15) |
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| 262 | #define MG_PLL_BIAS_CTRIM(x) ((x) << 8) |
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| 263 | #define MG_PLL_BIAS_CTRIM_MASK (0x1f << 8) |
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| 264 | #define MG_PLL_BIAS_VREF_RDAC(x) ((x) << 5) |
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| 265 | #define MG_PLL_BIAS_VREF_RDAC_MASK (0x7 << 5) |
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| 266 | #define MG_PLL_BIAS_IREFTRIM(x) ((x) << 0) |
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| 267 | #define MG_PLL_BIAS_IREFTRIM_MASK (0x1f << 0) |
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| 268 | #define MG_PLL_BIAS(tc_port) _MMIO_PORT((tc_port), _MG_PLL_BIAS_PORT1, \ |
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| 269 | _MG_PLL_BIAS_PORT2) |
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| 270 | |
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| 271 | #define _MG_PLL_TDC_COLDST_BIAS_PORT1 0x168A18 |
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| 272 | #define _MG_PLL_TDC_COLDST_BIAS_PORT2 0x169A18 |
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| 273 | #define MG_PLL_TDC_COLDST_IREFINT_EN (1 << 27) |
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| 274 | #define MG_PLL_TDC_COLDST_REFBIAS_START_PULSE_W(x) ((x) << 17) |
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| 275 | #define MG_PLL_TDC_COLDST_COLDSTART (1 << 16) |
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| 276 | #define MG_PLL_TDC_TDCOVCCORR_EN (1 << 2) |
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| 277 | #define MG_PLL_TDC_TDCSEL(x) ((x) << 0) |
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| 278 | #define MG_PLL_TDC_COLDST_BIAS(tc_port) _MMIO_PORT((tc_port), \ |
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| 279 | _MG_PLL_TDC_COLDST_BIAS_PORT1, \ |
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| 280 | _MG_PLL_TDC_COLDST_BIAS_PORT2) |
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| 281 | |
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| 282 | #endif /* __INTEL_MG_PHY_REGS__ */ |
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| 283 | |
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