| 1 | /* SPDX-License-Identifier: MIT |
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| 2 | * |
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| 3 | * Copyright © 2023 Intel Corporation |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef __INTEL_CX0_PHY_REGS_H__ |
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| 7 | #define __INTEL_CX0_PHY_REGS_H__ |
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| 8 | |
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| 9 | #include "intel_display_limits.h" |
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| 10 | #include "intel_display_reg_defs.h" |
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| 11 | |
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| 12 | /* DDI Buffer Control */ |
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| 13 | #define _DDI_CLK_VALFREQ_A 0x64030 |
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| 14 | #define _DDI_CLK_VALFREQ_B 0x64130 |
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| 15 | #define DDI_CLK_VALFREQ(port) _MMIO_PORT(port, _DDI_CLK_VALFREQ_A, _DDI_CLK_VALFREQ_B) |
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| 16 | |
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| 17 | /* |
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| 18 | * Wrapper macro to convert from port number to the index used in some of the |
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| 19 | * registers. For Display version 20 and above it converts the port number to a |
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| 20 | * single range, starting with the TC offsets. When used together with |
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| 21 | * _PICK_EVEN_2RANGES(idx, PORT_TC1, ...), this single range will be the second |
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| 22 | * range. Example: |
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| 23 | * |
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| 24 | * PORT_TC1 -> PORT_TC1 |
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| 25 | * PORT_TC2 -> PORT_TC2 |
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| 26 | * PORT_TC3 -> PORT_TC3 |
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| 27 | * PORT_TC4 -> PORT_TC4 |
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| 28 | * PORT_A -> PORT_TC4 + 1 |
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| 29 | * PORT_B -> PORT_TC4 + 2 |
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| 30 | * ... |
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| 31 | */ |
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| 32 | #define __xe2lpd_port_idx(port) \ |
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| 33 | (port >= PORT_TC1 ? port : PORT_TC4 + 1 + port - PORT_A) |
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| 34 | |
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| 35 | #define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A 0x64040 |
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| 36 | #define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B 0x64140 |
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| 37 | #define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1 0x16F240 |
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| 38 | #define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2 0x16F440 |
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| 39 | #define _XELPDP_PORT_M2P_MSGBUS_CTL(idx, lane) _MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \ |
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| 40 | _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A, \ |
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| 41 | _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B, \ |
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| 42 | _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1, \ |
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| 43 | _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2) + (lane) * 4) |
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| 44 | #define XELPDP_PORT_M2P_MSGBUS_CTL(i915__, port, lane) \ |
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| 45 | (DISPLAY_VER(i915__) >= 20 ? \ |
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| 46 | _XELPDP_PORT_M2P_MSGBUS_CTL(__xe2lpd_port_idx(port), lane) : \ |
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| 47 | _XELPDP_PORT_M2P_MSGBUS_CTL(port, lane)) |
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| 48 | #define XELPDP_PORT_M2P_TRANSACTION_PENDING REG_BIT(31) |
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| 49 | #define XELPDP_PORT_M2P_COMMAND_TYPE_MASK REG_GENMASK(30, 27) |
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| 50 | #define XELPDP_PORT_M2P_COMMAND_WRITE_UNCOMMITTED REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x1) |
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| 51 | #define XELPDP_PORT_M2P_COMMAND_WRITE_COMMITTED REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x2) |
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| 52 | #define XELPDP_PORT_M2P_COMMAND_READ REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x3) |
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| 53 | #define XELPDP_PORT_P2P_TRANSACTION_PENDING REG_BIT(24) |
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| 54 | #define XELPDP_PORT_M2P_DATA_MASK REG_GENMASK(23, 16) |
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| 55 | #define XELPDP_PORT_M2P_DATA(val) REG_FIELD_PREP(XELPDP_PORT_M2P_DATA_MASK, val) |
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| 56 | #define XELPDP_PORT_M2P_TRANSACTION_RESET REG_BIT(15) |
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| 57 | #define XELPDP_PORT_M2P_ADDRESS_MASK REG_GENMASK(11, 0) |
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| 58 | #define XELPDP_PORT_M2P_ADDRESS(val) REG_FIELD_PREP(XELPDP_PORT_M2P_ADDRESS_MASK, val) |
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| 59 | |
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| 60 | #define _XELPDP_PORT_P2M_MSGBUS_STATUS(idx, lane) _MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \ |
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| 61 | _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A, \ |
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| 62 | _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B, \ |
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| 63 | _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1, \ |
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| 64 | _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2) + (lane) * 4 + 8) |
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| 65 | #define XELPDP_PORT_P2M_MSGBUS_STATUS(i915__, port, lane) \ |
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| 66 | (DISPLAY_VER(i915__) >= 20 ? \ |
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| 67 | _XELPDP_PORT_P2M_MSGBUS_STATUS(__xe2lpd_port_idx(port), lane) : \ |
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| 68 | _XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane)) |
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| 69 | #define XELPDP_PORT_P2M_RESPONSE_READY REG_BIT(31) |
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| 70 | #define XELPDP_PORT_P2M_COMMAND_TYPE_MASK REG_GENMASK(30, 27) |
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| 71 | #define XELPDP_PORT_P2M_COMMAND_READ_ACK 0x4 |
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| 72 | #define XELPDP_PORT_P2M_COMMAND_WRITE_ACK 0x5 |
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| 73 | #define XELPDP_PORT_P2M_DATA_MASK REG_GENMASK(23, 16) |
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| 74 | #define XELPDP_PORT_P2M_DATA(val) REG_FIELD_PREP(XELPDP_PORT_P2M_DATA_MASK, val) |
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| 75 | #define XELPDP_PORT_P2M_ERROR_SET REG_BIT(15) |
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| 76 | |
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| 77 | #define XELPDP_MSGBUS_TIMEOUT_MS 1 |
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| 78 | #define XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US 3200 |
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| 79 | #define XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US 20 |
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| 80 | #define XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US 100 |
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| 81 | #define XELPDP_PORT_RESET_START_TIMEOUT_US 5 |
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| 82 | #define XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_MS 2 |
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| 83 | #define XELPDP_PORT_RESET_END_TIMEOUT_MS 15 |
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| 84 | #define XELPDP_REFCLK_ENABLE_TIMEOUT_US 1 |
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| 85 | |
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| 86 | #define _XELPDP_PORT_BUF_CTL1_LN0_A 0x64004 |
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| 87 | #define _XELPDP_PORT_BUF_CTL1_LN0_B 0x64104 |
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| 88 | #define _XELPDP_PORT_BUF_CTL1_LN0_USBC1 0x16F200 |
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| 89 | #define _XELPDP_PORT_BUF_CTL1_LN0_USBC2 0x16F400 |
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| 90 | #define _XELPDP_PORT_BUF_CTL1(idx) _MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \ |
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| 91 | _XELPDP_PORT_BUF_CTL1_LN0_A, \ |
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| 92 | _XELPDP_PORT_BUF_CTL1_LN0_B, \ |
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| 93 | _XELPDP_PORT_BUF_CTL1_LN0_USBC1, \ |
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| 94 | _XELPDP_PORT_BUF_CTL1_LN0_USBC2)) |
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| 95 | #define XELPDP_PORT_BUF_CTL1(i915__, port) \ |
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| 96 | (DISPLAY_VER(i915__) >= 20 ? \ |
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| 97 | _XELPDP_PORT_BUF_CTL1(__xe2lpd_port_idx(port)) : \ |
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| 98 | _XELPDP_PORT_BUF_CTL1(port)) |
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| 99 | #define XELPDP_PORT_BUF_D2D_LINK_ENABLE REG_BIT(29) |
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| 100 | #define XELPDP_PORT_BUF_D2D_LINK_STATE REG_BIT(28) |
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| 101 | #define XELPDP_PORT_BUF_SOC_PHY_READY REG_BIT(24) |
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| 102 | #define XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK REG_GENMASK(19, 18) |
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| 103 | #define XELPDP_PORT_BUF_PORT_DATA_10BIT REG_FIELD_PREP(XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK, 0) |
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| 104 | #define XELPDP_PORT_BUF_PORT_DATA_20BIT REG_FIELD_PREP(XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK, 1) |
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| 105 | #define XELPDP_PORT_BUF_PORT_DATA_40BIT REG_FIELD_PREP(XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK, 2) |
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| 106 | #define XELPDP_PORT_REVERSAL REG_BIT(16) |
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| 107 | #define XE3PLPDP_PHY_MODE_MASK REG_GENMASK(15, 12) |
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| 108 | #define XE3PLPDP_PHY_MODE_DP REG_FIELD_PREP(XE3PLPDP_PHY_MODE_MASK, 0x3) |
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| 109 | #define XELPDP_PORT_BUF_IO_SELECT_TBT REG_BIT(11) |
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| 110 | #define XELPDP_PORT_BUF_PHY_IDLE REG_BIT(7) |
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| 111 | #define XELPDP_TC_PHY_OWNERSHIP REG_BIT(6) |
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| 112 | #define XELPDP_TCSS_POWER_REQUEST REG_BIT(5) |
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| 113 | #define XELPDP_TCSS_POWER_STATE REG_BIT(4) |
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| 114 | #define XELPDP_PORT_WIDTH_MASK REG_GENMASK(3, 1) |
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| 115 | #define XELPDP_PORT_WIDTH(width) REG_FIELD_PREP(XELPDP_PORT_WIDTH_MASK, \ |
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| 116 | ((width) == 3 ? 4 : (width) - 1)) |
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| 117 | |
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| 118 | #define _XELPDP_PORT_BUF_CTL2(idx) _MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \ |
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| 119 | _XELPDP_PORT_BUF_CTL1_LN0_A, \ |
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| 120 | _XELPDP_PORT_BUF_CTL1_LN0_B, \ |
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| 121 | _XELPDP_PORT_BUF_CTL1_LN0_USBC1, \ |
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| 122 | _XELPDP_PORT_BUF_CTL1_LN0_USBC2) + 4) |
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| 123 | #define XELPDP_PORT_BUF_CTL2(i915__, port) \ |
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| 124 | (DISPLAY_VER(i915__) >= 20 ? \ |
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| 125 | _XELPDP_PORT_BUF_CTL2(__xe2lpd_port_idx(port)) : \ |
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| 126 | _XELPDP_PORT_BUF_CTL2(port)) |
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| 127 | #define XELPDP_LANE_PIPE_RESET(lane) _PICK(lane, REG_BIT(31), REG_BIT(30)) |
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| 128 | #define XELPDP_LANE_PHY_CURRENT_STATUS(lane) _PICK(lane, REG_BIT(29), REG_BIT(28)) |
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| 129 | #define XE3PLPDP_LANE_PHY_PULSE_STATUS(lane) _PICK(lane, REG_BIT(27), REG_BIT(26)) |
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| 130 | #define XELPDP_LANE_POWERDOWN_UPDATE(lane) _PICK(lane, REG_BIT(25), REG_BIT(24)) |
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| 131 | #define _XELPDP_LANE0_POWERDOWN_NEW_STATE_MASK REG_GENMASK(23, 20) |
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| 132 | #define _XELPDP_LANE0_POWERDOWN_NEW_STATE(val) REG_FIELD_PREP(_XELPDP_LANE0_POWERDOWN_NEW_STATE_MASK, val) |
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| 133 | #define _XELPDP_LANE1_POWERDOWN_NEW_STATE_MASK REG_GENMASK(19, 16) |
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| 134 | #define _XELPDP_LANE1_POWERDOWN_NEW_STATE(val) REG_FIELD_PREP(_XELPDP_LANE1_POWERDOWN_NEW_STATE_MASK, val) |
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| 135 | #define XELPDP_LANE_POWERDOWN_NEW_STATE(lane, val) _PICK(lane, \ |
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| 136 | _XELPDP_LANE0_POWERDOWN_NEW_STATE(val), \ |
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| 137 | _XELPDP_LANE1_POWERDOWN_NEW_STATE(val)) |
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| 138 | #define XELPDP_LANE_POWERDOWN_NEW_STATE_MASK REG_GENMASK(3, 0) |
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| 139 | #define XELPDP_POWER_STATE_READY_MASK REG_GENMASK(7, 4) |
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| 140 | #define XELPDP_POWER_STATE_READY(val) REG_FIELD_PREP(XELPDP_POWER_STATE_READY_MASK, val) |
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| 141 | |
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| 142 | #define _XELPDP_PORT_BUF_CTL3(idx) _MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \ |
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| 143 | _XELPDP_PORT_BUF_CTL1_LN0_A, \ |
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| 144 | _XELPDP_PORT_BUF_CTL1_LN0_B, \ |
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| 145 | _XELPDP_PORT_BUF_CTL1_LN0_USBC1, \ |
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| 146 | _XELPDP_PORT_BUF_CTL1_LN0_USBC2) + 8) |
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| 147 | #define XELPDP_PORT_BUF_CTL3(i915__, port) \ |
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| 148 | (DISPLAY_VER(i915__) >= 20 ? \ |
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| 149 | _XELPDP_PORT_BUF_CTL3(__xe2lpd_port_idx(port)) : \ |
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| 150 | _XELPDP_PORT_BUF_CTL3(port)) |
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| 151 | #define XELPDP_PLL_LANE_STAGGERING_DELAY_MASK REG_GENMASK(15, 8) |
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| 152 | #define XELPDP_PLL_LANE_STAGGERING_DELAY(val) REG_FIELD_PREP(XELPDP_PLL_LANE_STAGGERING_DELAY_MASK, val) |
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| 153 | #define XELPDP_POWER_STATE_ACTIVE_MASK REG_GENMASK(3, 0) |
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| 154 | #define XELPDP_POWER_STATE_ACTIVE(val) REG_FIELD_PREP(XELPDP_POWER_STATE_ACTIVE_MASK, val) |
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| 155 | #define XELPDP_P0_STATE_ACTIVE 0x0 |
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| 156 | #define XELPDP_P2_STATE_READY 0x2 |
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| 157 | #define XE3PLPD_P4_STATE_DISABLE 0x4 |
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| 158 | #define XELPDP_P2PG_STATE_DISABLE 0x9 |
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| 159 | #define XELPDP_P4PG_STATE_DISABLE 0xC |
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| 160 | #define XELPDP_P2_STATE_RESET 0x2 |
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| 161 | |
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| 162 | #define _XELPDP_PORT_MSGBUS_TIMER_LN0_A 0x640d8 |
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| 163 | #define _XELPDP_PORT_MSGBUS_TIMER_LN0_B 0x641d8 |
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| 164 | #define _XELPDP_PORT_MSGBUS_TIMER_LN0_USBC1 0x16f258 |
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| 165 | #define _XELPDP_PORT_MSGBUS_TIMER_LN0_USBC2 0x16f458 |
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| 166 | #define _XELPDP_PORT_MSGBUS_TIMER(port, lane) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \ |
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| 167 | _XELPDP_PORT_MSGBUS_TIMER_LN0_A, \ |
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| 168 | _XELPDP_PORT_MSGBUS_TIMER_LN0_B, \ |
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| 169 | _XELPDP_PORT_MSGBUS_TIMER_LN0_USBC1, \ |
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| 170 | _XELPDP_PORT_MSGBUS_TIMER_LN0_USBC2) + (lane) * 4) |
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| 171 | #define XELPDP_PORT_MSGBUS_TIMER(i915__, port, lane) \ |
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| 172 | (DISPLAY_VER(i915__) >= 20 ? \ |
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| 173 | _XELPDP_PORT_MSGBUS_TIMER(__xe2lpd_port_idx(port), lane) : \ |
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| 174 | _XELPDP_PORT_MSGBUS_TIMER(port, lane)) |
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| 175 | #define XELPDP_PORT_MSGBUS_TIMER_TIMED_OUT REG_BIT(31) |
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| 176 | #define XELPDP_PORT_MSGBUS_TIMER_VAL_MASK REG_GENMASK(23, 0) |
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| 177 | #define XELPDP_PORT_MSGBUS_TIMER_VAL REG_FIELD_PREP(XELPDP_PORT_MSGBUS_TIMER_VAL_MASK, 0xa000) |
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| 178 | |
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| 179 | #define _XELPDP_PORT_CLOCK_CTL_A 0x640E0 |
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| 180 | #define _XELPDP_PORT_CLOCK_CTL_B 0x641E0 |
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| 181 | #define _XELPDP_PORT_CLOCK_CTL_USBC1 0x16F260 |
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| 182 | #define _XELPDP_PORT_CLOCK_CTL_USBC2 0x16F460 |
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| 183 | #define _XELPDP_PORT_CLOCK_CTL(idx) _MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \ |
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| 184 | _XELPDP_PORT_CLOCK_CTL_A, \ |
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| 185 | _XELPDP_PORT_CLOCK_CTL_B, \ |
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| 186 | _XELPDP_PORT_CLOCK_CTL_USBC1, \ |
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| 187 | _XELPDP_PORT_CLOCK_CTL_USBC2)) |
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| 188 | #define XELPDP_PORT_CLOCK_CTL(i915__, port) \ |
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| 189 | (DISPLAY_VER(i915__) >= 20 ? \ |
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| 190 | _XELPDP_PORT_CLOCK_CTL(__xe2lpd_port_idx(port)) : \ |
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| 191 | _XELPDP_PORT_CLOCK_CTL(port)) |
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| 192 | #define XELPDP_LANE_PCLK_PLL_REQUEST(lane) REG_BIT(31 - ((lane) * 4)) |
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| 193 | #define XELPDP_LANE_PCLK_PLL_ACK(lane) REG_BIT(30 - ((lane) * 4)) |
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| 194 | #define XELPDP_LANE_PCLK_REFCLK_REQUEST(lane) REG_BIT(29 - ((lane) * 4)) |
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| 195 | #define XELPDP_LANE_PCLK_REFCLK_ACK(lane) REG_BIT(28 - ((lane) * 4)) |
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| 196 | |
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| 197 | #define XELPDP_TBT_CLOCK_REQUEST REG_BIT(19) |
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| 198 | #define XELPDP_TBT_CLOCK_ACK REG_BIT(18) |
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| 199 | #define _XELPDP_DDI_CLOCK_SELECT_MASK REG_GENMASK(15, 12) |
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| 200 | #define _XE3_DDI_CLOCK_SELECT_MASK REG_GENMASK(16, 12) |
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| 201 | #define XELPDP_DDI_CLOCK_SELECT_MASK(display) (DISPLAY_VER(display) >= 30 ? \ |
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| 202 | _XE3_DDI_CLOCK_SELECT_MASK : _XELPDP_DDI_CLOCK_SELECT_MASK) |
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| 203 | #define XELPDP_DDI_CLOCK_SELECT_PREP(display, val) (DISPLAY_VER(display) >= 30 ? \ |
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| 204 | REG_FIELD_PREP(_XE3_DDI_CLOCK_SELECT_MASK, (val)) : \ |
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| 205 | REG_FIELD_PREP(_XELPDP_DDI_CLOCK_SELECT_MASK, (val))) |
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| 206 | #define XELPDP_DDI_CLOCK_SELECT_GET(display, val) (DISPLAY_VER(display) >= 30 ? \ |
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| 207 | REG_FIELD_GET(_XE3_DDI_CLOCK_SELECT_MASK, (val)) : \ |
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| 208 | REG_FIELD_GET(_XELPDP_DDI_CLOCK_SELECT_MASK, (val))) |
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| 209 | |
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| 210 | #define XELPDP_DDI_CLOCK_SELECT_NONE 0x0 |
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| 211 | #define XELPDP_DDI_CLOCK_SELECT_MAXPCLK 0x8 |
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| 212 | #define XELPDP_DDI_CLOCK_SELECT_DIV18CLK 0x9 |
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| 213 | #define XELPDP_DDI_CLOCK_SELECT_TBT_162 0xc |
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| 214 | #define XELPDP_DDI_CLOCK_SELECT_TBT_270 0xd |
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| 215 | #define XELPDP_DDI_CLOCK_SELECT_TBT_540 0xe |
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| 216 | #define XELPDP_DDI_CLOCK_SELECT_TBT_810 0xf |
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| 217 | #define XELPDP_DDI_CLOCK_SELECT_TBT_312_5 0x18 |
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| 218 | #define XELPDP_DDI_CLOCK_SELECT_TBT_625 0x19 |
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| 219 | #define XELPDP_FORWARD_CLOCK_UNGATE REG_BIT(10) |
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| 220 | #define XELPDP_LANE1_PHY_CLOCK_SELECT REG_BIT(8) |
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| 221 | #define XELPDP_SSC_ENABLE_PLLA REG_BIT(1) |
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| 222 | #define XELPDP_SSC_ENABLE_PLLB REG_BIT(0) |
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| 223 | |
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| 224 | #define TCSS_DISP_MAILBOX_IN_CMD _MMIO(0x161300) |
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| 225 | #define TCSS_DISP_MAILBOX_IN_CMD_RUN_BUSY REG_BIT(31) |
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| 226 | #define TCSS_DISP_MAILBOX_IN_CMD_CMD_MASK REG_GENMASK(7, 0) |
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| 227 | #define TCSS_DISP_MAILBOX_IN_CMD_DATA(val) REG_FIELD_PREP(TCSS_DISP_MAILBOX_IN_CMD_CMD_MASK, val) |
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| 228 | |
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| 229 | #define TCSS_DISP_MAILBOX_IN_DATA _MMIO(0x161304) |
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| 230 | |
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| 231 | /* C10 Vendor Registers */ |
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| 232 | #define PHY_C10_VDR_PLL(idx) (0xC00 + (idx)) |
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| 233 | #define C10_PLL0_SSC_EN REG_BIT8(0) |
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| 234 | #define C10_PLL0_DIVCLK_EN REG_BIT8(1) |
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| 235 | #define C10_PLL0_DIV5CLK_EN REG_BIT8(2) |
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| 236 | #define C10_PLL0_WORDDIV2_EN REG_BIT8(3) |
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| 237 | #define C10_PLL0_FRACEN REG_BIT8(4) |
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| 238 | #define C10_PLL0_PMIX_EN REG_BIT8(5) |
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| 239 | #define C10_PLL0_ANA_FREQ_VCO_MASK REG_GENMASK8(7, 6) |
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| 240 | #define C10_PLL1_DIV_MULTIPLIER_MASK REG_GENMASK8(7, 0) |
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| 241 | #define C10_PLL2_MULTIPLIERL_MASK REG_GENMASK8(7, 0) |
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| 242 | #define C10_PLL3_MULTIPLIERH_MASK REG_GENMASK8(3, 0) |
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| 243 | #define C10_PLL8_SSC_UP_SPREAD REG_BIT8(5) |
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| 244 | #define C10_PLL9_FRACN_DENL_MASK REG_GENMASK8(7, 0) |
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| 245 | #define C10_PLL10_FRACN_DENH_MASK REG_GENMASK8(7, 0) |
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| 246 | #define C10_PLL11_FRACN_QUOT_L_MASK REG_GENMASK8(7, 0) |
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| 247 | #define C10_PLL12_FRACN_QUOT_H_MASK REG_GENMASK8(7, 0) |
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| 248 | #define C10_PLL13_FRACN_REM_L_MASK REG_GENMASK8(7, 0) |
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| 249 | #define C10_PLL14_FRACN_REM_H_MASK REG_GENMASK8(7, 0) |
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| 250 | #define C10_PLL15_TXCLKDIV_MASK REG_GENMASK8(2, 0) |
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| 251 | #define C10_PLL15_HDMIDIV_MASK REG_GENMASK8(5, 3) |
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| 252 | #define C10_PLL15_PIXELCLKDIV_MASK REG_GENMASK8(7, 6) |
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| 253 | #define C10_PLL16_ANA_CPINT REG_GENMASK8(6, 0) |
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| 254 | #define C10_PLL16_ANA_CPINTGS_L REG_BIT8(7) |
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| 255 | #define C10_PLL17_ANA_CPINTGS_H_MASK REG_GENMASK8(5, 0) |
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| 256 | #define C10_PLL17_ANA_CPPROP_L_MASK REG_GENMASK8(7, 6) |
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| 257 | #define C10_PLL18_ANA_CPPROP_H_MASK REG_GENMASK8(4, 0) |
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| 258 | #define C10_PLL18_ANA_CPPROPGS_L_MASK REG_GENMASK8(7, 5) |
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| 259 | #define C10_PLL19_ANA_CPPROPGS_H_MASK REG_GENMASK8(3, 0) |
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| 260 | #define C10_PLL19_ANA_V2I_MASK REG_GENMASK8(5, 4) |
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| 261 | |
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| 262 | #define PHY_C10_VDR_CMN(idx) (0xC20 + (idx)) |
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| 263 | #define C10_CMN0_REF_RANGE REG_FIELD_PREP(REG_GENMASK(4, 0), 1) |
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| 264 | #define C10_CMN0_REF_CLK_MPLLB_DIV REG_FIELD_PREP(REG_GENMASK(7, 5), 1) |
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| 265 | #define C10_CMN3_TXVBOOST_MASK REG_GENMASK8(7, 5) |
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| 266 | #define C10_CMN3_TXVBOOST(val) REG_FIELD_PREP8(C10_CMN3_TXVBOOST_MASK, val) |
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| 267 | #define PHY_C10_VDR_TX(idx) (0xC30 + (idx)) |
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| 268 | #define C10_TX0_TX_MPLLB_SEL REG_BIT(4) |
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| 269 | #define C10_TX1_TERMCTL_MASK REG_GENMASK8(7, 5) |
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| 270 | #define C10_TX1_TERMCTL(val) REG_FIELD_PREP8(C10_TX1_TERMCTL_MASK, val) |
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| 271 | #define PHY_C10_VDR_CONTROL(idx) (0xC70 + (idx) - 1) |
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| 272 | #define C10_VDR_CTRL_MSGBUS_ACCESS REG_BIT8(2) |
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| 273 | #define C10_VDR_CTRL_MASTER_LANE REG_BIT8(1) |
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| 274 | #define C10_VDR_CTRL_UPDATE_CFG REG_BIT8(0) |
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| 275 | #define PHY_C10_VDR_CUSTOM_WIDTH 0xD02 |
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| 276 | #define C10_VDR_CUSTOM_WIDTH_MASK REG_GENMASK(1, 0) |
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| 277 | #define C10_VDR_CUSTOM_WIDTH_8_10 REG_FIELD_PREP(C10_VDR_CUSTOM_WIDTH_MASK, 0) |
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| 278 | #define PHY_C10_VDR_OVRD 0xD71 |
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| 279 | #define PHY_C10_VDR_OVRD_TX1 REG_BIT8(0) |
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| 280 | #define PHY_C10_VDR_OVRD_TX2 REG_BIT8(2) |
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| 281 | #define PHY_C10_VDR_PRE_OVRD_TX1 0xD80 |
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| 282 | #define C10_PHY_OVRD_LEVEL_MASK REG_GENMASK8(5, 0) |
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| 283 | #define C10_PHY_OVRD_LEVEL(val) REG_FIELD_PREP8(C10_PHY_OVRD_LEVEL_MASK, val) |
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| 284 | #define PHY_CX0_VDROVRD_CTL(lane, tx, control) \ |
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| 285 | (PHY_C10_VDR_PRE_OVRD_TX1 + \ |
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| 286 | ((lane) ^ (tx)) * 0x10 + (control)) |
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| 287 | |
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| 288 | /* PIPE SPEC Defined Registers */ |
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| 289 | #define PHY_CX0_TX_CONTROL(tx, control) (0x400 + ((tx) - 1) * 0x200 + (control)) |
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| 290 | #define CONTROL2_DISABLE_SINGLE_TX REG_BIT(6) |
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| 291 | |
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| 292 | #define PHY_CMN1_CONTROL(tx, control) (0x800 + ((tx) - 1) * 0x200 + (control)) |
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| 293 | #define CONTROL0_MAC_TRANSMIT_LFPS REG_BIT(1) |
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| 294 | |
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| 295 | /* C20 Registers */ |
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| 296 | #define PHY_C20_WR_ADDRESS_L 0xC02 |
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| 297 | #define PHY_C20_WR_ADDRESS_H 0xC03 |
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| 298 | #define PHY_C20_WR_DATA_L 0xC04 |
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| 299 | #define PHY_C20_WR_DATA_H 0xC05 |
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| 300 | #define PHY_C20_RD_ADDRESS_L 0xC06 |
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| 301 | #define PHY_C20_RD_ADDRESS_H 0xC07 |
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| 302 | #define PHY_C20_RD_DATA_L 0xC08 |
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| 303 | #define PHY_C20_RD_DATA_H 0xC09 |
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| 304 | #define PHY_C20_VDR_CUSTOM_SERDES_RATE 0xD00 |
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| 305 | #define PHY_C20_IS_HDMI_FRL REG_BIT8(7) |
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| 306 | #define PHY_C20_IS_DP REG_BIT8(6) |
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| 307 | #define PHY_C20_DP_RATE_MASK REG_GENMASK8(4, 1) |
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| 308 | #define PHY_C20_DP_RATE(val) REG_FIELD_PREP8(PHY_C20_DP_RATE_MASK, val) |
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| 309 | #define PHY_C20_CONTEXT_TOGGLE REG_BIT8(0) |
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| 310 | #define PHY_C20_VDR_HDMI_RATE 0xD01 |
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| 311 | #define PHY_C20_HDMI_RATE_MASK REG_GENMASK8(1, 0) |
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| 312 | #define PHY_C20_HDMI_RATE(val) REG_FIELD_PREP8(PHY_C20_HDMI_RATE_MASK, val) |
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| 313 | #define PHY_C20_VDR_CUSTOM_WIDTH 0xD02 |
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| 314 | #define PHY_C20_CUSTOM_WIDTH_MASK REG_GENMASK(1, 0) |
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| 315 | #define PHY_C20_CUSTOM_WIDTH(val) REG_FIELD_PREP8(PHY_C20_CUSTOM_WIDTH_MASK, val) |
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| 316 | |
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| 317 | #define _MTL_C20_A_TX_CNTX_CFG 0xCF2E |
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| 318 | #define _MTL_C20_B_TX_CNTX_CFG 0xCF2A |
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| 319 | #define _MTL_C20_A_CMN_CNTX_CFG 0xCDAA |
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| 320 | #define _MTL_C20_B_CMN_CNTX_CFG 0xCDA5 |
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| 321 | #define _MTL_C20_A_MPLLA_CFG 0xCCF0 |
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| 322 | #define _MTL_C20_B_MPLLA_CFG 0xCCE5 |
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| 323 | #define _MTL_C20_A_MPLLB_CFG 0xCB5A |
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| 324 | #define _MTL_C20_B_MPLLB_CFG 0xCB4E |
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| 325 | |
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| 326 | #define _XE2HPD_C20_A_TX_CNTX_CFG 0xCF5E |
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| 327 | #define _XE2HPD_C20_B_TX_CNTX_CFG 0xCF5A |
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| 328 | #define _XE2HPD_C20_A_CMN_CNTX_CFG 0xCE8E |
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| 329 | #define _XE2HPD_C20_B_CMN_CNTX_CFG 0xCE89 |
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| 330 | #define _XE2HPD_C20_A_MPLLA_CFG 0xCE58 |
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| 331 | #define _XE2HPD_C20_B_MPLLA_CFG 0xCE4D |
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| 332 | #define _XE2HPD_C20_A_MPLLB_CFG 0xCCC2 |
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| 333 | #define _XE2HPD_C20_B_MPLLB_CFG 0xCCB6 |
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| 334 | |
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| 335 | #define _IS_XE2HPD_C20(i915) (DISPLAY_VERx100(i915) == 1401) |
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| 336 | |
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| 337 | #define PHY_C20_A_TX_CNTX_CFG(i915, idx) \ |
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| 338 | ((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_A_TX_CNTX_CFG : _MTL_C20_A_TX_CNTX_CFG) - (idx)) |
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| 339 | #define PHY_C20_B_TX_CNTX_CFG(i915, idx) \ |
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| 340 | ((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_B_TX_CNTX_CFG : _MTL_C20_B_TX_CNTX_CFG) - (idx)) |
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| 341 | #define C20_PHY_TX_RATE REG_GENMASK(2, 0) |
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| 342 | #define C20_PHY_TX_MISC_MASK REG_GENMASK16(7, 0) |
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| 343 | #define C20_PHY_TX_MISC(val) REG_FIELD_PREP16(C20_PHY_TX_MISC_MASK, (val)) |
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| 344 | #define C20_PHY_TX_DCC_CAL_RANGE_MASK REG_GENMASK16(11, 8) |
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| 345 | #define C20_PHY_TX_DCC_CAL_RANGE(val) \ |
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| 346 | REG_FIELD_PREP16(C20_PHY_TX_DCC_CAL_RANGE_MASK, (val)) |
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| 347 | #define C20_PHY_TX_DCC_BYPASS REG_BIT(12) |
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| 348 | #define C20_PHY_TX_TERM_CTL_MASK REG_GENMASK16(15, 13) |
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| 349 | #define C20_PHY_TX_TERM_CTL(val) REG_FIELD_PREP16(C20_PHY_TX_TERM_CTL_MASK, (val)) |
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| 350 | |
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| 351 | #define PHY_C20_A_CMN_CNTX_CFG(i915, idx) \ |
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| 352 | ((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_A_CMN_CNTX_CFG : _MTL_C20_A_CMN_CNTX_CFG) - (idx)) |
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| 353 | #define PHY_C20_B_CMN_CNTX_CFG(i915, idx) \ |
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| 354 | ((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_B_CMN_CNTX_CFG : _MTL_C20_B_CMN_CNTX_CFG) - (idx)) |
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| 355 | #define PHY_C20_A_MPLLA_CNTX_CFG(i915, idx) \ |
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| 356 | ((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_A_MPLLA_CFG : _MTL_C20_A_MPLLA_CFG) - (idx)) |
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| 357 | #define PHY_C20_B_MPLLA_CNTX_CFG(i915, idx) \ |
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| 358 | ((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_B_MPLLA_CFG : _MTL_C20_B_MPLLA_CFG) - (idx)) |
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| 359 | #define C20_MPLLA_FRACEN REG_BIT(14) |
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| 360 | #define C20_FB_CLK_DIV4_EN REG_BIT(13) |
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| 361 | #define C20_MPLLA_TX_CLK_DIV_MASK REG_GENMASK(10, 8) |
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| 362 | |
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| 363 | #define PHY_C20_A_MPLLB_CNTX_CFG(i915, idx) \ |
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| 364 | ((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_A_MPLLB_CFG : _MTL_C20_A_MPLLB_CFG) - (idx)) |
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| 365 | #define PHY_C20_B_MPLLB_CNTX_CFG(i915, idx) \ |
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| 366 | ((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_B_MPLLB_CFG : _MTL_C20_B_MPLLB_CFG) - (idx)) |
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| 367 | |
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| 368 | #define C20_MPLLB_TX_CLK_DIV_MASK REG_GENMASK(15, 13) |
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| 369 | #define C20_MPLLB_FRACEN REG_BIT(13) |
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| 370 | #define C20_REF_CLK_MPLLB_DIV_MASK REG_GENMASK(12, 10) |
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| 371 | #define C20_MULTIPLIER_MASK REG_GENMASK(11, 0) |
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| 372 | #define C20_PHY_USE_MPLLB REG_BIT(7) |
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| 373 | |
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| 374 | /* C20 Phy VSwing Masks */ |
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| 375 | #define C20_PHY_VSWING_PREEMPH_MASK REG_GENMASK8(5, 0) |
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| 376 | #define C20_PHY_VSWING_PREEMPH(val) REG_FIELD_PREP8(C20_PHY_VSWING_PREEMPH_MASK, val) |
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| 377 | |
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| 378 | #define RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK(idx) (0x303D + (idx)) |
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| 379 | |
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| 380 | /* C20 HDMI computed pll definitions */ |
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| 381 | #define REFCLK_38_4_MHZ 38400000 |
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| 382 | #define CLOCK_4999MHZ 4999999999 |
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| 383 | #define CLOCK_9999MHZ 9999999999 |
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| 384 | #define DATARATE_3000000000 3000000000 |
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| 385 | #define DATARATE_3500000000 3500000000 |
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| 386 | #define DATARATE_4000000000 4000000000 |
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| 387 | #define MPLL_FRACN_DEN 0xFFFF |
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| 388 | |
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| 389 | #define SSC_UP_SPREAD REG_BIT16(9) |
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| 390 | #define WORD_CLK_DIV REG_BIT16(8) |
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| 391 | |
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| 392 | #define MPLL_TX_CLK_DIV(val) REG_FIELD_PREP16(C20_MPLLB_TX_CLK_DIV_MASK, val) |
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| 393 | #define MPLL_MULTIPLIER(val) REG_FIELD_PREP16(C20_MULTIPLIER_MASK, val) |
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| 394 | |
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| 395 | #define MPLLB_ANA_FREQ_VCO_0 0 |
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| 396 | #define MPLLB_ANA_FREQ_VCO_1 1 |
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| 397 | #define MPLLB_ANA_FREQ_VCO_2 2 |
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| 398 | #define MPLLB_ANA_FREQ_VCO_3 3 |
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| 399 | #define MPLLB_ANA_FREQ_VCO_MASK REG_GENMASK16(15, 14) |
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| 400 | #define MPLLB_ANA_FREQ_VCO(val) REG_FIELD_PREP16(MPLLB_ANA_FREQ_VCO_MASK, val) |
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| 401 | |
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| 402 | #define MPLL_DIV_MULTIPLIER_MASK REG_GENMASK16(7, 0) |
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| 403 | #define MPLL_DIV_MULTIPLIER(val) REG_FIELD_PREP16(MPLL_DIV_MULTIPLIER_MASK, val) |
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| 404 | |
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| 405 | #define CAL_DAC_CODE_31 31 |
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| 406 | #define CAL_DAC_CODE_MASK REG_GENMASK16(14, 10) |
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| 407 | #define CAL_DAC_CODE(val) REG_FIELD_PREP16(CAL_DAC_CODE_MASK, val) |
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| 408 | |
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| 409 | #define CP_INT_GS_28 28 |
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| 410 | #define CP_INT_GS_MASK REG_GENMASK16(6, 0) |
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| 411 | #define CP_INT_GS(val) REG_FIELD_PREP16(CP_INT_GS_MASK, val) |
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| 412 | |
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| 413 | #define CP_PROP_GS_30 30 |
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| 414 | #define CP_PROP_GS_MASK REG_GENMASK16(13, 7) |
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| 415 | #define CP_PROP_GS(val) REG_FIELD_PREP16(CP_PROP_GS_MASK, val) |
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| 416 | |
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| 417 | #define CP_INT_6 6 |
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| 418 | #define CP_INT_MASK REG_GENMASK16(6, 0) |
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| 419 | #define CP_INT(val) REG_FIELD_PREP16(CP_INT_MASK, val) |
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| 420 | |
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| 421 | #define CP_PROP_20 20 |
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| 422 | #define CP_PROP_MASK REG_GENMASK16(13, 7) |
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| 423 | #define CP_PROP(val) REG_FIELD_PREP16(CP_PROP_MASK, val) |
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| 424 | |
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| 425 | #define V2I_2 2 |
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| 426 | #define V2I_MASK REG_GENMASK16(15, 14) |
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| 427 | #define V2I(val) REG_FIELD_PREP16(V2I_MASK, val) |
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| 428 | |
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| 429 | #define HDMI_DIV_1 1 |
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| 430 | #define HDMI_DIV_MASK REG_GENMASK16(2, 0) |
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| 431 | #define HDMI_DIV(val) REG_FIELD_PREP16(HDMI_DIV_MASK, val) |
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| 432 | |
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| 433 | #define PICA_PHY_CONFIG_CONTROL _MMIO(0x16FE68) |
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| 434 | #define EDP_ON_TYPEC REG_BIT(31) |
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| 435 | |
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| 436 | #endif /* __INTEL_CX0_REG_DEFS_H__ */ |
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| 437 | |
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