1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27#include <linux/dmi.h>
28#include <linux/i2c.h>
29#include <linux/slab.h>
30
31#include <drm/drm_atomic_helper.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_edid.h>
34#include <drm/drm_print.h>
35#include <drm/drm_probe_helper.h>
36
37#include "intel_connector.h"
38#include "intel_crt.h"
39#include "intel_crt_regs.h"
40#include "intel_crtc.h"
41#include "intel_ddi.h"
42#include "intel_ddi_buf_trans.h"
43#include "intel_de.h"
44#include "intel_display_driver.h"
45#include "intel_display_regs.h"
46#include "intel_display_types.h"
47#include "intel_fdi.h"
48#include "intel_fdi_regs.h"
49#include "intel_fifo_underrun.h"
50#include "intel_gmbus.h"
51#include "intel_hotplug.h"
52#include "intel_hotplug_irq.h"
53#include "intel_link_bw.h"
54#include "intel_load_detect.h"
55#include "intel_pch_display.h"
56#include "intel_pch_refclk.h"
57#include "intel_pfit.h"
58
59/* Here's the desired hotplug mode */
60#define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_ENABLE | \
61 ADPA_CRT_HOTPLUG_PERIOD_128 | \
62 ADPA_CRT_HOTPLUG_WARMUP_10MS | \
63 ADPA_CRT_HOTPLUG_SAMPLE_4S | \
64 ADPA_CRT_HOTPLUG_VOLTAGE_50 | \
65 ADPA_CRT_HOTPLUG_VOLREF_325MV)
66#define ADPA_HOTPLUG_MASK (ADPA_CRT_HOTPLUG_MONITOR_MASK | \
67 ADPA_CRT_HOTPLUG_ENABLE | \
68 ADPA_CRT_HOTPLUG_PERIOD_MASK | \
69 ADPA_CRT_HOTPLUG_WARMUP_MASK | \
70 ADPA_CRT_HOTPLUG_SAMPLE_MASK | \
71 ADPA_CRT_HOTPLUG_VOLTAGE_MASK | \
72 ADPA_CRT_HOTPLUG_VOLREF_MASK | \
73 ADPA_CRT_HOTPLUG_FORCE_TRIGGER)
74
75struct intel_crt {
76 struct intel_encoder base;
77 bool force_hotplug_required;
78 i915_reg_t adpa_reg;
79};
80
81static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder)
82{
83 return container_of(encoder, struct intel_crt, base);
84}
85
86static struct intel_crt *intel_attached_crt(struct intel_connector *connector)
87{
88 return intel_encoder_to_crt(encoder: intel_attached_encoder(connector));
89}
90
91bool intel_crt_port_enabled(struct intel_display *display,
92 i915_reg_t adpa_reg, enum pipe *pipe)
93{
94 u32 val;
95
96 val = intel_de_read(display, reg: adpa_reg);
97
98 /* asserts want to know the pipe even if the port is disabled */
99 if (HAS_PCH_CPT(display))
100 *pipe = REG_FIELD_GET(ADPA_PIPE_SEL_MASK_CPT, val);
101 else
102 *pipe = REG_FIELD_GET(ADPA_PIPE_SEL_MASK, val);
103
104 return val & ADPA_DAC_ENABLE;
105}
106
107static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
108 enum pipe *pipe)
109{
110 struct intel_display *display = to_intel_display(encoder);
111 struct intel_crt *crt = intel_encoder_to_crt(encoder);
112 intel_wakeref_t wakeref;
113 bool ret;
114
115 wakeref = intel_display_power_get_if_enabled(display,
116 domain: encoder->power_domain);
117 if (!wakeref)
118 return false;
119
120 ret = intel_crt_port_enabled(display, adpa_reg: crt->adpa_reg, pipe);
121
122 intel_display_power_put(display, domain: encoder->power_domain, wakeref);
123
124 return ret;
125}
126
127static unsigned int intel_crt_get_flags(struct intel_encoder *encoder)
128{
129 struct intel_display *display = to_intel_display(encoder);
130 struct intel_crt *crt = intel_encoder_to_crt(encoder);
131 u32 tmp, flags = 0;
132
133 tmp = intel_de_read(display, reg: crt->adpa_reg);
134
135 if (tmp & ADPA_HSYNC_ACTIVE_HIGH)
136 flags |= DRM_MODE_FLAG_PHSYNC;
137 else
138 flags |= DRM_MODE_FLAG_NHSYNC;
139
140 if (tmp & ADPA_VSYNC_ACTIVE_HIGH)
141 flags |= DRM_MODE_FLAG_PVSYNC;
142 else
143 flags |= DRM_MODE_FLAG_NVSYNC;
144
145 return flags;
146}
147
148static void intel_crt_get_config(struct intel_encoder *encoder,
149 struct intel_crtc_state *crtc_state)
150{
151 crtc_state->output_types |= BIT(INTEL_OUTPUT_ANALOG);
152
153 crtc_state->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder);
154
155 crtc_state->hw.adjusted_mode.crtc_clock = crtc_state->port_clock;
156}
157
158static void hsw_crt_get_config(struct intel_encoder *encoder,
159 struct intel_crtc_state *crtc_state)
160{
161 lpt_pch_get_config(crtc_state);
162
163 hsw_ddi_get_config(encoder, crtc_state);
164
165 crtc_state->hw.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |
166 DRM_MODE_FLAG_NHSYNC |
167 DRM_MODE_FLAG_PVSYNC |
168 DRM_MODE_FLAG_NVSYNC);
169 crtc_state->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder);
170}
171
172/* Note: The caller is required to filter out dpms modes not supported by the
173 * platform. */
174static void intel_crt_set_dpms(struct intel_encoder *encoder,
175 const struct intel_crtc_state *crtc_state,
176 int mode)
177{
178 struct intel_display *display = to_intel_display(encoder);
179 struct intel_crt *crt = intel_encoder_to_crt(encoder);
180 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
181 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
182 u32 adpa;
183
184 if (DISPLAY_VER(display) >= 5)
185 adpa = ADPA_HOTPLUG_BITS;
186 else
187 adpa = 0;
188
189 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
190 adpa |= ADPA_HSYNC_ACTIVE_HIGH;
191 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
192 adpa |= ADPA_VSYNC_ACTIVE_HIGH;
193
194 /* For CPT allow 3 pipe config, for others just use A or B */
195 if (HAS_PCH_LPT(display))
196 ; /* Those bits don't exist here */
197 else if (HAS_PCH_CPT(display))
198 adpa |= ADPA_PIPE_SEL_CPT(crtc->pipe);
199 else
200 adpa |= ADPA_PIPE_SEL(crtc->pipe);
201
202 if (!HAS_PCH_SPLIT(display))
203 intel_de_write(display, BCLRPAT(display, crtc->pipe), val: 0);
204
205 switch (mode) {
206 case DRM_MODE_DPMS_ON:
207 adpa |= ADPA_DAC_ENABLE;
208 break;
209 case DRM_MODE_DPMS_STANDBY:
210 adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE;
211 break;
212 case DRM_MODE_DPMS_SUSPEND:
213 adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE;
214 break;
215 case DRM_MODE_DPMS_OFF:
216 adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
217 break;
218 }
219
220 intel_de_write(display, reg: crt->adpa_reg, val: adpa);
221}
222
223static void intel_disable_crt(struct intel_atomic_state *state,
224 struct intel_encoder *encoder,
225 const struct intel_crtc_state *old_crtc_state,
226 const struct drm_connector_state *old_conn_state)
227{
228 intel_crt_set_dpms(encoder, crtc_state: old_crtc_state, DRM_MODE_DPMS_OFF);
229}
230
231static void pch_disable_crt(struct intel_atomic_state *state,
232 struct intel_encoder *encoder,
233 const struct intel_crtc_state *old_crtc_state,
234 const struct drm_connector_state *old_conn_state)
235{
236}
237
238static void pch_post_disable_crt(struct intel_atomic_state *state,
239 struct intel_encoder *encoder,
240 const struct intel_crtc_state *old_crtc_state,
241 const struct drm_connector_state *old_conn_state)
242{
243 intel_disable_crt(state, encoder, old_crtc_state, old_conn_state);
244}
245
246static void hsw_disable_crt(struct intel_atomic_state *state,
247 struct intel_encoder *encoder,
248 const struct intel_crtc_state *old_crtc_state,
249 const struct drm_connector_state *old_conn_state)
250{
251 struct intel_display *display = to_intel_display(encoder);
252
253 drm_WARN_ON(display->drm, !old_crtc_state->has_pch_encoder);
254
255 intel_set_pch_fifo_underrun_reporting(display, pch_transcoder: PIPE_A, enable: false);
256}
257
258static void hsw_post_disable_crt(struct intel_atomic_state *state,
259 struct intel_encoder *encoder,
260 const struct intel_crtc_state *old_crtc_state,
261 const struct drm_connector_state *old_conn_state)
262{
263 struct intel_display *display = to_intel_display(encoder);
264 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
265
266 intel_crtc_vblank_off(crtc_state: old_crtc_state);
267
268 intel_disable_transcoder(old_crtc_state);
269
270 intel_ddi_disable_transcoder_func(crtc_state: old_crtc_state);
271
272 ilk_pfit_disable(old_crtc_state);
273
274 intel_ddi_disable_transcoder_clock(crtc_state: old_crtc_state);
275
276 pch_post_disable_crt(state, encoder, old_crtc_state, old_conn_state);
277
278 lpt_pch_disable(state, crtc);
279
280 hsw_fdi_disable(encoder);
281
282 drm_WARN_ON(display->drm, !old_crtc_state->has_pch_encoder);
283
284 intel_set_pch_fifo_underrun_reporting(display, pch_transcoder: PIPE_A, enable: true);
285}
286
287static void hsw_pre_pll_enable_crt(struct intel_atomic_state *state,
288 struct intel_encoder *encoder,
289 const struct intel_crtc_state *crtc_state,
290 const struct drm_connector_state *conn_state)
291{
292 struct intel_display *display = to_intel_display(encoder);
293
294 drm_WARN_ON(display->drm, !crtc_state->has_pch_encoder);
295
296 intel_set_pch_fifo_underrun_reporting(display, pch_transcoder: PIPE_A, enable: false);
297}
298
299static void hsw_pre_enable_crt(struct intel_atomic_state *state,
300 struct intel_encoder *encoder,
301 const struct intel_crtc_state *crtc_state,
302 const struct drm_connector_state *conn_state)
303{
304 struct intel_display *display = to_intel_display(encoder);
305 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
306 enum pipe pipe = crtc->pipe;
307
308 drm_WARN_ON(display->drm, !crtc_state->has_pch_encoder);
309
310 intel_set_cpu_fifo_underrun_reporting(display, pipe, enable: false);
311
312 hsw_fdi_link_train(encoder, crtc_state);
313
314 intel_ddi_enable_transcoder_clock(encoder, crtc_state);
315}
316
317static void hsw_enable_crt(struct intel_atomic_state *state,
318 struct intel_encoder *encoder,
319 const struct intel_crtc_state *crtc_state,
320 const struct drm_connector_state *conn_state)
321{
322 struct intel_display *display = to_intel_display(encoder);
323 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
324 enum pipe pipe = crtc->pipe;
325
326 drm_WARN_ON(display->drm, !crtc_state->has_pch_encoder);
327
328 intel_ddi_enable_transcoder_func(encoder, crtc_state);
329
330 intel_enable_transcoder(new_crtc_state: crtc_state);
331
332 lpt_pch_enable(state, crtc);
333
334 intel_crtc_vblank_on(crtc_state);
335
336 intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON);
337
338 intel_crtc_wait_for_next_vblank(crtc);
339 intel_crtc_wait_for_next_vblank(crtc);
340 intel_set_cpu_fifo_underrun_reporting(display, pipe, enable: true);
341 intel_set_pch_fifo_underrun_reporting(display, pch_transcoder: PIPE_A, enable: true);
342}
343
344static void intel_enable_crt(struct intel_atomic_state *state,
345 struct intel_encoder *encoder,
346 const struct intel_crtc_state *crtc_state,
347 const struct drm_connector_state *conn_state)
348{
349 intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON);
350}
351
352static enum drm_mode_status
353intel_crt_mode_valid(struct drm_connector *connector,
354 const struct drm_display_mode *mode)
355{
356 struct intel_display *display = to_intel_display(connector->dev);
357 int max_dotclk = display->cdclk.max_dotclk_freq;
358 enum drm_mode_status status;
359 int max_clock;
360
361 status = intel_cpu_transcoder_mode_valid(display, mode);
362 if (status != MODE_OK)
363 return status;
364
365 if (mode->clock < 25000)
366 return MODE_CLOCK_LOW;
367
368 if (HAS_PCH_LPT(display))
369 max_clock = 180000;
370 else if (display->platform.valleyview)
371 /*
372 * 270 MHz due to current DPLL limits,
373 * DAC limit supposedly 355 MHz.
374 */
375 max_clock = 270000;
376 else if (IS_DISPLAY_VER(display, 3, 4))
377 max_clock = 400000;
378 else
379 max_clock = 350000;
380 if (mode->clock > max_clock)
381 return MODE_CLOCK_HIGH;
382
383 if (mode->clock > max_dotclk)
384 return MODE_CLOCK_HIGH;
385
386 /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */
387 if (HAS_PCH_LPT(display) &&
388 ilk_get_lanes_required(target_clock: mode->clock, link_bw: 270000, bpp: 24) > 2)
389 return MODE_CLOCK_HIGH;
390
391 /* HSW/BDW FDI limited to 4k */
392 if (mode->hdisplay > 4096)
393 return MODE_H_ILLEGAL;
394
395 return MODE_OK;
396}
397
398static int intel_crt_compute_config(struct intel_encoder *encoder,
399 struct intel_crtc_state *crtc_state,
400 struct drm_connector_state *conn_state)
401{
402 struct drm_display_mode *adjusted_mode =
403 &crtc_state->hw.adjusted_mode;
404
405 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
406 return -EINVAL;
407
408 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB;
409 crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB;
410
411 return 0;
412}
413
414static int pch_crt_compute_config(struct intel_encoder *encoder,
415 struct intel_crtc_state *crtc_state,
416 struct drm_connector_state *conn_state)
417{
418 struct drm_display_mode *adjusted_mode =
419 &crtc_state->hw.adjusted_mode;
420
421 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
422 return -EINVAL;
423
424 crtc_state->has_pch_encoder = true;
425 if (!intel_link_bw_compute_pipe_bpp(crtc_state))
426 return -EINVAL;
427
428 crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB;
429
430 return 0;
431}
432
433static int hsw_crt_compute_config(struct intel_encoder *encoder,
434 struct intel_crtc_state *crtc_state,
435 struct drm_connector_state *conn_state)
436{
437 struct intel_display *display = to_intel_display(encoder);
438 struct drm_display_mode *adjusted_mode =
439 &crtc_state->hw.adjusted_mode;
440
441 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
442 return -EINVAL;
443
444 /* HSW/BDW FDI limited to 4k */
445 if (adjusted_mode->crtc_hdisplay > 4096 ||
446 adjusted_mode->crtc_hblank_start > 4096)
447 return -EINVAL;
448
449 crtc_state->has_pch_encoder = true;
450 if (!intel_link_bw_compute_pipe_bpp(crtc_state))
451 return -EINVAL;
452
453 crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB;
454
455 /* LPT FDI RX only supports 8bpc. */
456 if (HAS_PCH_LPT(display)) {
457 /* TODO: Check crtc_state->max_link_bpp_x16 instead of bw_constrained */
458 if (crtc_state->bw_constrained && crtc_state->pipe_bpp < 24) {
459 drm_dbg_kms(display->drm,
460 "LPT only supports 24bpp\n");
461 return -EINVAL;
462 }
463
464 crtc_state->pipe_bpp = 24;
465 }
466
467 /* FDI must always be 2.7 GHz */
468 crtc_state->port_clock = 135000 * 2;
469
470 crtc_state->enhanced_framing = true;
471
472 adjusted_mode->crtc_clock = lpt_iclkip(crtc_state);
473
474 return 0;
475}
476
477static bool ilk_crt_detect_hotplug(struct drm_connector *connector)
478{
479 struct intel_display *display = to_intel_display(connector->dev);
480 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
481 u32 adpa;
482 bool ret;
483
484 /* The first time through, trigger an explicit detection cycle */
485 if (crt->force_hotplug_required) {
486 bool turn_off_dac = HAS_PCH_SPLIT(display);
487 u32 save_adpa;
488
489 crt->force_hotplug_required = false;
490
491 save_adpa = adpa = intel_de_read(display, reg: crt->adpa_reg);
492 drm_dbg_kms(display->drm,
493 "trigger hotplug detect cycle: adpa=0x%x\n", adpa);
494
495 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
496 if (turn_off_dac)
497 adpa &= ~ADPA_DAC_ENABLE;
498
499 intel_de_write(display, reg: crt->adpa_reg, val: adpa);
500
501 if (intel_de_wait_for_clear_ms(display,
502 reg: crt->adpa_reg,
503 ADPA_CRT_HOTPLUG_FORCE_TRIGGER,
504 timeout_ms: 1000))
505 drm_dbg_kms(display->drm,
506 "timed out waiting for FORCE_TRIGGER");
507
508 if (turn_off_dac) {
509 intel_de_write(display, reg: crt->adpa_reg, val: save_adpa);
510 intel_de_posting_read(display, reg: crt->adpa_reg);
511 }
512 }
513
514 /* Check the status to see if both blue and green are on now */
515 adpa = intel_de_read(display, reg: crt->adpa_reg);
516 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
517 ret = true;
518 else
519 ret = false;
520 drm_dbg_kms(display->drm, "ironlake hotplug adpa=0x%x, result %d\n",
521 adpa, ret);
522
523 return ret;
524}
525
526static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
527{
528 struct intel_display *display = to_intel_display(connector->dev);
529 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
530 u32 adpa;
531 bool ret;
532 u32 save_adpa;
533
534 /*
535 * Doing a force trigger causes a hpd interrupt to get sent, which can
536 * get us stuck in a loop if we're polling:
537 * - We enable power wells and reset the ADPA
538 * - output_poll_exec does force probe on VGA, triggering a hpd
539 * - HPD handler waits for poll to unlock dev->mode_config.mutex
540 * - output_poll_exec shuts off the ADPA, unlocks
541 * dev->mode_config.mutex
542 * - HPD handler runs, resets ADPA and brings us back to the start
543 *
544 * Just disable HPD interrupts here to prevent this
545 */
546 intel_hpd_block(encoder: &crt->base);
547
548 save_adpa = adpa = intel_de_read(display, reg: crt->adpa_reg);
549 drm_dbg_kms(display->drm,
550 "trigger hotplug detect cycle: adpa=0x%x\n", adpa);
551
552 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
553
554 intel_de_write(display, reg: crt->adpa_reg, val: adpa);
555
556 if (intel_de_wait_for_clear_ms(display, reg: crt->adpa_reg,
557 ADPA_CRT_HOTPLUG_FORCE_TRIGGER, timeout_ms: 1000)) {
558 drm_dbg_kms(display->drm,
559 "timed out waiting for FORCE_TRIGGER");
560 intel_de_write(display, reg: crt->adpa_reg, val: save_adpa);
561 }
562
563 /* Check the status to see if both blue and green are on now */
564 adpa = intel_de_read(display, reg: crt->adpa_reg);
565 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
566 ret = true;
567 else
568 ret = false;
569
570 drm_dbg_kms(display->drm,
571 "valleyview hotplug adpa=0x%x, result %d\n", adpa, ret);
572
573 intel_hpd_clear_and_unblock(encoder: &crt->base);
574
575 return ret;
576}
577
578static bool intel_crt_detect_hotplug(struct drm_connector *connector)
579{
580 struct intel_display *display = to_intel_display(connector->dev);
581 u32 stat;
582 bool ret = false;
583 int i, tries = 0;
584
585 if (HAS_PCH_SPLIT(display))
586 return ilk_crt_detect_hotplug(connector);
587
588 if (display->platform.valleyview)
589 return valleyview_crt_detect_hotplug(connector);
590
591 /*
592 * On 4 series desktop, CRT detect sequence need to be done twice
593 * to get a reliable result.
594 */
595
596 if (display->platform.g45)
597 tries = 2;
598 else
599 tries = 1;
600
601 for (i = 0; i < tries ; i++) {
602 /* turn on the FORCE_DETECT */
603 i915_hotplug_interrupt_update(display,
604 CRT_HOTPLUG_FORCE_DETECT,
605 CRT_HOTPLUG_FORCE_DETECT);
606 /* wait for FORCE_DETECT to go off */
607 if (intel_de_wait_for_clear_ms(display, PORT_HOTPLUG_EN(display),
608 CRT_HOTPLUG_FORCE_DETECT, timeout_ms: 1000))
609 drm_dbg_kms(display->drm,
610 "timed out waiting for FORCE_DETECT to go off");
611 }
612
613 stat = intel_de_read(display, PORT_HOTPLUG_STAT(display));
614 if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
615 ret = true;
616
617 /* clear the interrupt we just generated, if any */
618 intel_de_write(display, PORT_HOTPLUG_STAT(display),
619 CRT_HOTPLUG_INT_STATUS);
620
621 i915_hotplug_interrupt_update(display, CRT_HOTPLUG_FORCE_DETECT, bits: 0);
622
623 return ret;
624}
625
626static const struct drm_edid *intel_crt_get_edid(struct drm_connector *connector,
627 struct i2c_adapter *ddc)
628{
629 const struct drm_edid *drm_edid;
630
631 drm_edid = drm_edid_read_ddc(connector, adapter: ddc);
632
633 if (!drm_edid && !intel_gmbus_is_forced_bit(adapter: ddc)) {
634 drm_dbg_kms(connector->dev,
635 "CRT GMBUS EDID read failed, retry using GPIO bit-banging\n");
636 intel_gmbus_force_bit(adapter: ddc, force_bit: true);
637 drm_edid = drm_edid_read_ddc(connector, adapter: ddc);
638 intel_gmbus_force_bit(adapter: ddc, force_bit: false);
639 }
640
641 return drm_edid;
642}
643
644/* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */
645static int intel_crt_ddc_get_modes(struct drm_connector *connector,
646 struct i2c_adapter *ddc)
647{
648 const struct drm_edid *drm_edid;
649 int ret;
650
651 drm_edid = intel_crt_get_edid(connector, ddc);
652 if (!drm_edid)
653 return 0;
654
655 ret = intel_connector_update_modes(connector, drm_edid);
656
657 drm_edid_free(drm_edid);
658
659 return ret;
660}
661
662static bool intel_crt_detect_ddc(struct drm_connector *connector)
663{
664 struct intel_display *display = to_intel_display(connector->dev);
665 const struct drm_edid *drm_edid;
666 bool ret = false;
667
668 drm_edid = intel_crt_get_edid(connector, ddc: connector->ddc);
669
670 if (drm_edid) {
671 /*
672 * This may be a DVI-I connector with a shared DDC
673 * link between analog and digital outputs, so we
674 * have to check the EDID input spec of the attached device.
675 */
676 if (drm_edid_is_digital(drm_edid)) {
677 drm_dbg_kms(display->drm,
678 "CRT not detected via DDC:0x50 [EDID reports a digital panel]\n");
679 } else {
680 drm_dbg_kms(display->drm,
681 "CRT detected via DDC:0x50 [EDID]\n");
682 ret = true;
683 }
684 } else {
685 drm_dbg_kms(display->drm,
686 "CRT not detected via DDC:0x50 [no valid EDID found]\n");
687 }
688
689 drm_edid_free(drm_edid);
690
691 return ret;
692}
693
694static enum drm_connector_status
695intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
696{
697 struct intel_display *display = to_intel_display(&crt->base);
698 enum transcoder cpu_transcoder = (enum transcoder)pipe;
699 u32 save_bclrpat;
700 u32 save_vtotal;
701 u32 vtotal, vactive;
702 u32 vsample;
703 u32 vblank, vblank_start, vblank_end;
704 u32 dsl;
705 u8 st00;
706 enum drm_connector_status status;
707
708 drm_dbg_kms(display->drm, "starting load-detect on CRT\n");
709
710 save_bclrpat = intel_de_read(display,
711 BCLRPAT(display, cpu_transcoder));
712 save_vtotal = intel_de_read(display,
713 TRANS_VTOTAL(display, cpu_transcoder));
714 vblank = intel_de_read(display,
715 TRANS_VBLANK(display, cpu_transcoder));
716
717 vtotal = REG_FIELD_GET(VTOTAL_MASK, save_vtotal) + 1;
718 vactive = REG_FIELD_GET(VACTIVE_MASK, save_vtotal) + 1;
719
720 vblank_start = REG_FIELD_GET(VBLANK_START_MASK, vblank) + 1;
721 vblank_end = REG_FIELD_GET(VBLANK_END_MASK, vblank) + 1;
722
723 /* Set the border color to purple. */
724 intel_de_write(display, BCLRPAT(display, cpu_transcoder), val: 0x500050);
725
726 if (DISPLAY_VER(display) != 2) {
727 u32 transconf = intel_de_read(display,
728 TRANSCONF(display, cpu_transcoder));
729
730 intel_de_write(display, TRANSCONF(display, cpu_transcoder),
731 val: transconf | TRANSCONF_FORCE_BORDER);
732 intel_de_posting_read(display,
733 TRANSCONF(display, cpu_transcoder));
734 /*
735 * Wait for next Vblank to substitute
736 * border color for Color info.
737 */
738 intel_crtc_wait_for_next_vblank(crtc: intel_crtc_for_pipe(display, pipe));
739 st00 = intel_de_read8(display, _VGA_MSR_WRITE);
740 status = ((st00 & (1 << 4)) != 0) ?
741 connector_status_connected :
742 connector_status_disconnected;
743
744 intel_de_write(display, TRANSCONF(display, cpu_transcoder),
745 val: transconf);
746 } else {
747 bool restore_vblank = false;
748 int count, detect;
749
750 /*
751 * If there isn't any border, add some.
752 * Yes, this will flicker
753 */
754 if (vblank_start <= vactive && vblank_end >= vtotal) {
755 u32 vsync = intel_de_read(display,
756 TRANS_VSYNC(display, cpu_transcoder));
757 u32 vsync_start = REG_FIELD_GET(VSYNC_START_MASK, vsync) + 1;
758
759 vblank_start = vsync_start;
760 intel_de_write(display,
761 TRANS_VBLANK(display, cpu_transcoder),
762 VBLANK_START(vblank_start - 1) |
763 VBLANK_END(vblank_end - 1));
764 restore_vblank = true;
765 }
766 /* sample in the vertical border, selecting the larger one */
767 if (vblank_start - vactive >= vtotal - vblank_end)
768 vsample = (vblank_start + vactive) >> 1;
769 else
770 vsample = (vtotal + vblank_end) >> 1;
771
772 /*
773 * Wait for the border to be displayed
774 */
775 while (intel_de_read(display, PIPEDSL(display, pipe)) >= vactive)
776 ;
777 while ((dsl = intel_de_read(display, PIPEDSL(display, pipe))) <= vsample)
778 ;
779 /*
780 * Watch ST00 for an entire scanline
781 */
782 detect = 0;
783 count = 0;
784 do {
785 count++;
786 /* Read the ST00 VGA status register */
787 st00 = intel_de_read8(display, _VGA_MSR_WRITE);
788 if (st00 & (1 << 4))
789 detect++;
790 } while ((intel_de_read(display, PIPEDSL(display, pipe)) == dsl));
791
792 /* restore vblank if necessary */
793 if (restore_vblank)
794 intel_de_write(display,
795 TRANS_VBLANK(display, cpu_transcoder),
796 val: vblank);
797 /*
798 * If more than 3/4 of the scanline detected a monitor,
799 * then it is assumed to be present. This works even on i830,
800 * where there isn't any way to force the border color across
801 * the screen
802 */
803 status = detect * 4 > count * 3 ?
804 connector_status_connected :
805 connector_status_disconnected;
806 }
807
808 /* Restore previous settings */
809 intel_de_write(display, BCLRPAT(display, cpu_transcoder),
810 val: save_bclrpat);
811
812 return status;
813}
814
815static int intel_spurious_crt_detect_dmi_callback(const struct dmi_system_id *id)
816{
817 DRM_DEBUG_DRIVER("Skipping CRT detection for %s\n", id->ident);
818 return 1;
819}
820
821static const struct dmi_system_id intel_spurious_crt_detect[] = {
822 {
823 .callback = intel_spurious_crt_detect_dmi_callback,
824 .ident = "ACER ZGB",
825 .matches = {
826 DMI_MATCH(DMI_SYS_VENDOR, "ACER"),
827 DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"),
828 },
829 },
830 {
831 .callback = intel_spurious_crt_detect_dmi_callback,
832 .ident = "Intel DZ77BH-55K",
833 .matches = {
834 DMI_MATCH(DMI_BOARD_VENDOR, "Intel Corporation"),
835 DMI_MATCH(DMI_BOARD_NAME, "DZ77BH-55K"),
836 },
837 },
838 { }
839};
840
841static int
842intel_crt_detect(struct drm_connector *connector,
843 struct drm_modeset_acquire_ctx *ctx,
844 bool force)
845{
846 struct intel_display *display = to_intel_display(connector->dev);
847 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
848 struct intel_encoder *encoder = &crt->base;
849 struct drm_atomic_state *state;
850 intel_wakeref_t wakeref;
851 int status;
852
853 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] force=%d\n",
854 connector->base.id, connector->name,
855 force);
856
857 if (!intel_display_device_enabled(display))
858 return connector_status_disconnected;
859
860 if (!intel_display_driver_check_access(display))
861 return connector->status;
862
863 if (display->params.load_detect_test) {
864 wakeref = intel_display_power_get(display, domain: encoder->power_domain);
865 goto load_detect;
866 }
867
868 /* Skip machines without VGA that falsely report hotplug events */
869 if (dmi_check_system(list: intel_spurious_crt_detect))
870 return connector_status_disconnected;
871
872 wakeref = intel_display_power_get(display, domain: encoder->power_domain);
873
874 if (HAS_HOTPLUG(display)) {
875 /* We can not rely on the HPD pin always being correctly wired
876 * up, for example many KVM do not pass it through, and so
877 * only trust an assertion that the monitor is connected.
878 */
879 if (intel_crt_detect_hotplug(connector)) {
880 drm_dbg_kms(display->drm,
881 "CRT detected via hotplug\n");
882 status = connector_status_connected;
883 goto out;
884 } else
885 drm_dbg_kms(display->drm,
886 "CRT not detected via hotplug\n");
887 }
888
889 if (intel_crt_detect_ddc(connector)) {
890 status = connector_status_connected;
891 goto out;
892 }
893
894 /* Load detection is broken on HPD capable machines. Whoever wants a
895 * broken monitor (without edid) to work behind a broken kvm (that fails
896 * to have the right resistors for HP detection) needs to fix this up.
897 * For now just bail out. */
898 if (HAS_HOTPLUG(display)) {
899 status = connector_status_disconnected;
900 goto out;
901 }
902
903load_detect:
904 if (!force) {
905 status = connector->status;
906 goto out;
907 }
908
909 /* for pre-945g platforms use load detect */
910 state = intel_load_detect_get_pipe(connector, ctx);
911 if (IS_ERR(ptr: state)) {
912 status = PTR_ERR(ptr: state);
913 } else if (!state) {
914 status = connector_status_unknown;
915 } else {
916 if (intel_crt_detect_ddc(connector))
917 status = connector_status_connected;
918 else if (DISPLAY_VER(display) < 4)
919 status = intel_crt_load_detect(crt,
920 to_intel_crtc(connector->state->crtc)->pipe);
921 else if (display->params.load_detect_test)
922 status = connector_status_disconnected;
923 else
924 status = connector_status_unknown;
925 intel_load_detect_release_pipe(connector, old: state, ctx);
926 }
927
928out:
929 intel_display_power_put(display, domain: encoder->power_domain, wakeref);
930
931 return status;
932}
933
934static int intel_crt_get_modes(struct drm_connector *connector)
935{
936 struct intel_display *display = to_intel_display(connector->dev);
937 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
938 struct intel_encoder *encoder = &crt->base;
939 intel_wakeref_t wakeref;
940 struct i2c_adapter *ddc;
941 int ret;
942
943 if (!intel_display_driver_check_access(display))
944 return drm_edid_connector_add_modes(connector);
945
946 wakeref = intel_display_power_get(display, domain: encoder->power_domain);
947
948 ret = intel_crt_ddc_get_modes(connector, ddc: connector->ddc);
949 if (ret || !display->platform.g4x)
950 goto out;
951
952 /* Try to probe digital port for output in DVI-I -> VGA mode. */
953 ddc = intel_gmbus_get_adapter(display, GMBUS_PIN_DPB);
954 ret = intel_crt_ddc_get_modes(connector, ddc);
955
956out:
957 intel_display_power_put(display, domain: encoder->power_domain, wakeref);
958
959 return ret;
960}
961
962void intel_crt_reset(struct drm_encoder *encoder)
963{
964 struct intel_display *display = to_intel_display(encoder->dev);
965 struct intel_crt *crt = intel_encoder_to_crt(to_intel_encoder(encoder));
966
967 if (DISPLAY_VER(display) >= 5) {
968 u32 adpa;
969
970 adpa = intel_de_read(display, reg: crt->adpa_reg);
971 adpa &= ~ADPA_HOTPLUG_MASK;
972 adpa |= ADPA_HOTPLUG_BITS;
973 intel_de_write(display, reg: crt->adpa_reg, val: adpa);
974 intel_de_posting_read(display, reg: crt->adpa_reg);
975
976 drm_dbg_kms(display->drm, "crt adpa set to 0x%x\n", adpa);
977 crt->force_hotplug_required = true;
978 }
979
980}
981
982/*
983 * Routines for controlling stuff on the analog port
984 */
985
986static const struct drm_connector_funcs intel_crt_connector_funcs = {
987 .fill_modes = drm_helper_probe_single_connector_modes,
988 .late_register = intel_connector_register,
989 .early_unregister = intel_connector_unregister,
990 .destroy = intel_connector_destroy,
991 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
992 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
993};
994
995static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = {
996 .detect_ctx = intel_crt_detect,
997 .mode_valid = intel_crt_mode_valid,
998 .get_modes = intel_crt_get_modes,
999};
1000
1001static const struct drm_encoder_funcs intel_crt_enc_funcs = {
1002 .reset = intel_crt_reset,
1003 .destroy = intel_encoder_destroy,
1004};
1005
1006void intel_crt_init(struct intel_display *display)
1007{
1008 struct intel_connector *connector;
1009 struct intel_crt *crt;
1010 i915_reg_t adpa_reg;
1011 u8 ddc_pin;
1012 u32 adpa;
1013
1014 if (HAS_PCH_SPLIT(display))
1015 adpa_reg = PCH_ADPA;
1016 else if (display->platform.valleyview)
1017 adpa_reg = VLV_ADPA;
1018 else
1019 adpa_reg = ADPA;
1020
1021 adpa = intel_de_read(display, reg: adpa_reg);
1022 if ((adpa & ADPA_DAC_ENABLE) == 0) {
1023 /*
1024 * On some machines (some IVB at least) CRT can be
1025 * fused off, but there's no known fuse bit to
1026 * indicate that. On these machine the ADPA register
1027 * works normally, except the DAC enable bit won't
1028 * take. So the only way to tell is attempt to enable
1029 * it and see what happens.
1030 */
1031 intel_de_write(display, reg: adpa_reg,
1032 val: adpa | ADPA_DAC_ENABLE |
1033 ADPA_HSYNC_CNTL_DISABLE |
1034 ADPA_VSYNC_CNTL_DISABLE);
1035 if ((intel_de_read(display, reg: adpa_reg) & ADPA_DAC_ENABLE) == 0)
1036 return;
1037 intel_de_write(display, reg: adpa_reg, val: adpa);
1038 }
1039
1040 crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
1041 if (!crt)
1042 return;
1043
1044 connector = intel_connector_alloc();
1045 if (!connector) {
1046 kfree(objp: crt);
1047 return;
1048 }
1049
1050 ddc_pin = display->vbt.crt_ddc_pin;
1051
1052 drm_connector_init_with_ddc(dev: display->drm, connector: &connector->base,
1053 funcs: &intel_crt_connector_funcs,
1054 DRM_MODE_CONNECTOR_VGA,
1055 ddc: intel_gmbus_get_adapter(display, pin: ddc_pin));
1056
1057 drm_encoder_init(dev: display->drm, encoder: &crt->base.base, funcs: &intel_crt_enc_funcs,
1058 DRM_MODE_ENCODER_DAC, name: "CRT");
1059
1060 intel_connector_attach_encoder(connector, encoder: &crt->base);
1061
1062 crt->base.type = INTEL_OUTPUT_ANALOG;
1063 crt->base.cloneable = BIT(INTEL_OUTPUT_DVO) | BIT(INTEL_OUTPUT_HDMI);
1064 if (display->platform.i830)
1065 crt->base.pipe_mask = BIT(PIPE_A);
1066 else
1067 crt->base.pipe_mask = ~0;
1068
1069 if (DISPLAY_VER(display) != 2)
1070 connector->base.interlace_allowed = true;
1071
1072 crt->adpa_reg = adpa_reg;
1073
1074 crt->base.power_domain = POWER_DOMAIN_PORT_CRT;
1075
1076 if (HAS_HOTPLUG(display) &&
1077 !dmi_check_system(list: intel_spurious_crt_detect)) {
1078 crt->base.hpd_pin = HPD_CRT;
1079 crt->base.hotplug = intel_encoder_hotplug;
1080 connector->polled = DRM_CONNECTOR_POLL_HPD;
1081 } else {
1082 connector->polled = DRM_CONNECTOR_POLL_CONNECT;
1083 }
1084 connector->base.polled = connector->polled;
1085
1086 if (HAS_DDI(display)) {
1087 assert_port_valid(display, port: PORT_E);
1088
1089 crt->base.port = PORT_E;
1090 crt->base.get_config = hsw_crt_get_config;
1091 crt->base.get_hw_state = intel_ddi_get_hw_state;
1092 crt->base.compute_config = hsw_crt_compute_config;
1093 crt->base.pre_pll_enable = hsw_pre_pll_enable_crt;
1094 crt->base.pre_enable = hsw_pre_enable_crt;
1095 crt->base.enable = hsw_enable_crt;
1096 crt->base.disable = hsw_disable_crt;
1097 crt->base.post_disable = hsw_post_disable_crt;
1098 crt->base.enable_clock = hsw_ddi_enable_clock;
1099 crt->base.disable_clock = hsw_ddi_disable_clock;
1100 crt->base.is_clock_enabled = hsw_ddi_is_clock_enabled;
1101
1102 intel_ddi_buf_trans_init(encoder: &crt->base);
1103 } else {
1104 if (HAS_PCH_SPLIT(display)) {
1105 crt->base.compute_config = pch_crt_compute_config;
1106 crt->base.disable = pch_disable_crt;
1107 crt->base.post_disable = pch_post_disable_crt;
1108 } else {
1109 crt->base.compute_config = intel_crt_compute_config;
1110 crt->base.disable = intel_disable_crt;
1111 }
1112 crt->base.port = PORT_NONE;
1113 crt->base.get_config = intel_crt_get_config;
1114 crt->base.get_hw_state = intel_crt_get_hw_state;
1115 crt->base.enable = intel_enable_crt;
1116 }
1117 connector->get_hw_state = intel_connector_get_hw_state;
1118
1119 drm_connector_helper_add(connector: &connector->base, funcs: &intel_crt_connector_helper_funcs);
1120
1121 /*
1122 * TODO: find a proper way to discover whether we need to set the the
1123 * polarity and link reversal bits or not, instead of relying on the
1124 * BIOS.
1125 */
1126 if (HAS_PCH_LPT(display)) {
1127 u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT |
1128 FDI_RX_LINK_REVERSAL_OVERRIDE;
1129
1130 display->fdi.rx_config = intel_de_read(display,
1131 FDI_RX_CTL(PIPE_A)) & fdi_config;
1132 }
1133
1134 intel_crt_reset(encoder: &crt->base.base);
1135}
1136

source code of linux/drivers/gpu/drm/i915/display/intel_crt.c