1/*
2 * Copyright © 2007-2008 Intel Corporation
3 * Jesse Barnes <jesse.barnes@intel.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 */
23#ifndef __DRM_EDID_H__
24#define __DRM_EDID_H__
25
26#include <linux/types.h>
27
28enum hdmi_quantization_range;
29struct drm_connector;
30struct drm_device;
31struct drm_display_mode;
32struct drm_edid;
33struct drm_printer;
34struct hdmi_avi_infoframe;
35struct hdmi_vendor_infoframe;
36struct i2c_adapter;
37
38#define EDID_LENGTH 128
39#define DDC_ADDR 0x50
40#define DDC_ADDR2 0x52 /* E-DDC 1.2 - where DisplayID can hide */
41
42#define CEA_EXT 0x02
43#define VTB_EXT 0x10
44#define DI_EXT 0x40
45#define LS_EXT 0x50
46#define MI_EXT 0x60
47#define DISPLAYID_EXT 0x70
48
49struct est_timings {
50 u8 t1;
51 u8 t2;
52 u8 mfg_rsvd;
53} __packed;
54
55/* 00=16:10, 01=4:3, 10=5:4, 11=16:9 */
56#define EDID_TIMING_ASPECT_SHIFT 6
57#define EDID_TIMING_ASPECT_MASK (0x3 << EDID_TIMING_ASPECT_SHIFT)
58
59/* need to add 60 */
60#define EDID_TIMING_VFREQ_SHIFT 0
61#define EDID_TIMING_VFREQ_MASK (0x3f << EDID_TIMING_VFREQ_SHIFT)
62
63struct std_timing {
64 u8 hsize; /* need to multiply by 8 then add 248 */
65 u8 vfreq_aspect;
66} __packed;
67
68#define DRM_EDID_PT_HSYNC_POSITIVE (1 << 1)
69#define DRM_EDID_PT_VSYNC_POSITIVE (1 << 2)
70#define DRM_EDID_PT_SEPARATE_SYNC (3 << 3)
71#define DRM_EDID_PT_STEREO (1 << 5)
72#define DRM_EDID_PT_INTERLACED (1 << 7)
73
74/* If detailed data is pixel timing */
75struct detailed_pixel_timing {
76 u8 hactive_lo;
77 u8 hblank_lo;
78 u8 hactive_hblank_hi;
79 u8 vactive_lo;
80 u8 vblank_lo;
81 u8 vactive_vblank_hi;
82 u8 hsync_offset_lo;
83 u8 hsync_pulse_width_lo;
84 u8 vsync_offset_pulse_width_lo;
85 u8 hsync_vsync_offset_pulse_width_hi;
86 u8 width_mm_lo;
87 u8 height_mm_lo;
88 u8 width_height_mm_hi;
89 u8 hborder;
90 u8 vborder;
91 u8 misc;
92} __packed;
93
94/* If it's not pixel timing, it'll be one of the below */
95struct detailed_data_string {
96 u8 str[13];
97} __packed;
98
99#define DRM_EDID_RANGE_OFFSET_MIN_VFREQ (1 << 0) /* 1.4 */
100#define DRM_EDID_RANGE_OFFSET_MAX_VFREQ (1 << 1) /* 1.4 */
101#define DRM_EDID_RANGE_OFFSET_MIN_HFREQ (1 << 2) /* 1.4 */
102#define DRM_EDID_RANGE_OFFSET_MAX_HFREQ (1 << 3) /* 1.4 */
103
104#define DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG 0x00 /* 1.3 */
105#define DRM_EDID_RANGE_LIMITS_ONLY_FLAG 0x01 /* 1.4 */
106#define DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG 0x02 /* 1.3 */
107#define DRM_EDID_CVT_SUPPORT_FLAG 0x04 /* 1.4 */
108
109#define DRM_EDID_CVT_FLAGS_STANDARD_BLANKING (1 << 3)
110#define DRM_EDID_CVT_FLAGS_REDUCED_BLANKING (1 << 4)
111
112enum drm_edid_quirk {
113 /* Do a dummy read before DPCD accesses, to prevent corruption. */
114 DRM_EDID_QUIRK_DP_DPCD_PROBE,
115
116 DRM_EDID_QUIRK_NUM,
117};
118
119struct detailed_data_monitor_range {
120 u8 min_vfreq;
121 u8 max_vfreq;
122 u8 min_hfreq_khz;
123 u8 max_hfreq_khz;
124 u8 pixel_clock_mhz; /* need to multiply by 10 */
125 u8 flags;
126 union {
127 struct {
128 u8 reserved;
129 u8 hfreq_start_khz; /* need to multiply by 2 */
130 u8 c; /* need to divide by 2 */
131 __le16 m;
132 u8 k;
133 u8 j; /* need to divide by 2 */
134 } __packed gtf2;
135 struct {
136 u8 version;
137 u8 data1; /* high 6 bits: extra clock resolution */
138 u8 data2; /* plus low 2 of above: max hactive */
139 u8 supported_aspects;
140 u8 flags; /* preferred aspect and blanking support */
141 u8 supported_scalings;
142 u8 preferred_refresh;
143 } __packed cvt;
144 } __packed formula;
145} __packed;
146
147struct detailed_data_wpindex {
148 u8 white_yx_lo; /* Lower 2 bits each */
149 u8 white_x_hi;
150 u8 white_y_hi;
151 u8 gamma; /* need to divide by 100 then add 1 */
152} __packed;
153
154struct detailed_data_color_point {
155 u8 windex1;
156 u8 wpindex1[3];
157 u8 windex2;
158 u8 wpindex2[3];
159} __packed;
160
161struct cvt_timing {
162 u8 code[3];
163} __packed;
164
165struct detailed_non_pixel {
166 u8 pad1;
167 u8 type; /* ff=serial, fe=string, fd=monitor range, fc=monitor name
168 fb=color point data, fa=standard timing data,
169 f9=undefined, f8=mfg. reserved */
170 u8 pad2;
171 union {
172 struct detailed_data_string str;
173 struct detailed_data_monitor_range range;
174 struct detailed_data_wpindex color;
175 struct std_timing timings[6];
176 struct cvt_timing cvt[4];
177 } __packed data;
178} __packed;
179
180#define EDID_DETAIL_EST_TIMINGS 0xf7
181#define EDID_DETAIL_CVT_3BYTE 0xf8
182#define EDID_DETAIL_COLOR_MGMT_DATA 0xf9
183#define EDID_DETAIL_STD_MODES 0xfa
184#define EDID_DETAIL_MONITOR_CPDATA 0xfb
185#define EDID_DETAIL_MONITOR_NAME 0xfc
186#define EDID_DETAIL_MONITOR_RANGE 0xfd
187#define EDID_DETAIL_MONITOR_STRING 0xfe
188#define EDID_DETAIL_MONITOR_SERIAL 0xff
189
190struct detailed_timing {
191 __le16 pixel_clock; /* need to multiply by 10 KHz */
192 union {
193 struct detailed_pixel_timing pixel_data;
194 struct detailed_non_pixel other_data;
195 } __packed data;
196} __packed;
197
198#define DRM_EDID_INPUT_SERRATION_VSYNC (1 << 0)
199#define DRM_EDID_INPUT_SYNC_ON_GREEN (1 << 1)
200#define DRM_EDID_INPUT_COMPOSITE_SYNC (1 << 2)
201#define DRM_EDID_INPUT_SEPARATE_SYNCS (1 << 3)
202#define DRM_EDID_INPUT_BLANK_TO_BLACK (1 << 4)
203#define DRM_EDID_INPUT_VIDEO_LEVEL (3 << 5)
204#define DRM_EDID_INPUT_DIGITAL (1 << 7)
205#define DRM_EDID_DIGITAL_DEPTH_MASK (7 << 4) /* 1.4 */
206#define DRM_EDID_DIGITAL_DEPTH_UNDEF (0 << 4) /* 1.4 */
207#define DRM_EDID_DIGITAL_DEPTH_6 (1 << 4) /* 1.4 */
208#define DRM_EDID_DIGITAL_DEPTH_8 (2 << 4) /* 1.4 */
209#define DRM_EDID_DIGITAL_DEPTH_10 (3 << 4) /* 1.4 */
210#define DRM_EDID_DIGITAL_DEPTH_12 (4 << 4) /* 1.4 */
211#define DRM_EDID_DIGITAL_DEPTH_14 (5 << 4) /* 1.4 */
212#define DRM_EDID_DIGITAL_DEPTH_16 (6 << 4) /* 1.4 */
213#define DRM_EDID_DIGITAL_DEPTH_RSVD (7 << 4) /* 1.4 */
214#define DRM_EDID_DIGITAL_TYPE_MASK (7 << 0) /* 1.4 */
215#define DRM_EDID_DIGITAL_TYPE_UNDEF (0 << 0) /* 1.4 */
216#define DRM_EDID_DIGITAL_TYPE_DVI (1 << 0) /* 1.4 */
217#define DRM_EDID_DIGITAL_TYPE_HDMI_A (2 << 0) /* 1.4 */
218#define DRM_EDID_DIGITAL_TYPE_HDMI_B (3 << 0) /* 1.4 */
219#define DRM_EDID_DIGITAL_TYPE_MDDI (4 << 0) /* 1.4 */
220#define DRM_EDID_DIGITAL_TYPE_DP (5 << 0) /* 1.4 */
221#define DRM_EDID_DIGITAL_DFP_1_X (1 << 0) /* 1.3 */
222
223#define DRM_EDID_FEATURE_DEFAULT_GTF (1 << 0) /* 1.2 */
224#define DRM_EDID_FEATURE_CONTINUOUS_FREQ (1 << 0) /* 1.4 */
225#define DRM_EDID_FEATURE_PREFERRED_TIMING (1 << 1)
226#define DRM_EDID_FEATURE_STANDARD_COLOR (1 << 2)
227/* If analog */
228#define DRM_EDID_FEATURE_DISPLAY_TYPE (3 << 3) /* 00=mono, 01=rgb, 10=non-rgb, 11=unknown */
229/* If digital */
230#define DRM_EDID_FEATURE_COLOR_MASK (3 << 3)
231#define DRM_EDID_FEATURE_RGB (0 << 3)
232#define DRM_EDID_FEATURE_RGB_YCRCB444 (1 << 3)
233#define DRM_EDID_FEATURE_RGB_YCRCB422 (2 << 3)
234#define DRM_EDID_FEATURE_RGB_YCRCB (3 << 3) /* both 4:4:4 and 4:2:2 */
235
236#define DRM_EDID_FEATURE_PM_ACTIVE_OFF (1 << 5)
237#define DRM_EDID_FEATURE_PM_SUSPEND (1 << 6)
238#define DRM_EDID_FEATURE_PM_STANDBY (1 << 7)
239
240#define DRM_EDID_HDMI_DC_48 (1 << 6)
241#define DRM_EDID_HDMI_DC_36 (1 << 5)
242#define DRM_EDID_HDMI_DC_30 (1 << 4)
243#define DRM_EDID_HDMI_DC_Y444 (1 << 3)
244
245/* YCBCR 420 deep color modes */
246#define DRM_EDID_YCBCR420_DC_48 (1 << 2)
247#define DRM_EDID_YCBCR420_DC_36 (1 << 1)
248#define DRM_EDID_YCBCR420_DC_30 (1 << 0)
249#define DRM_EDID_YCBCR420_DC_MASK (DRM_EDID_YCBCR420_DC_48 | \
250 DRM_EDID_YCBCR420_DC_36 | \
251 DRM_EDID_YCBCR420_DC_30)
252
253/* HDMI 2.1 additional fields */
254#define DRM_EDID_MAX_FRL_RATE_MASK 0xf0
255#define DRM_EDID_FAPA_START_LOCATION (1 << 0)
256#define DRM_EDID_ALLM (1 << 1)
257#define DRM_EDID_FVA (1 << 2)
258
259/* Deep Color specific */
260#define DRM_EDID_DC_30BIT_420 (1 << 0)
261#define DRM_EDID_DC_36BIT_420 (1 << 1)
262#define DRM_EDID_DC_48BIT_420 (1 << 2)
263
264/* VRR specific */
265#define DRM_EDID_CNMVRR (1 << 3)
266#define DRM_EDID_CINEMA_VRR (1 << 4)
267#define DRM_EDID_MDELTA (1 << 5)
268#define DRM_EDID_VRR_MAX_UPPER_MASK 0xc0
269#define DRM_EDID_VRR_MAX_LOWER_MASK 0xff
270#define DRM_EDID_VRR_MIN_MASK 0x3f
271
272/* DSC specific */
273#define DRM_EDID_DSC_10BPC (1 << 0)
274#define DRM_EDID_DSC_12BPC (1 << 1)
275#define DRM_EDID_DSC_16BPC (1 << 2)
276#define DRM_EDID_DSC_ALL_BPP (1 << 3)
277#define DRM_EDID_DSC_NATIVE_420 (1 << 6)
278#define DRM_EDID_DSC_1P2 (1 << 7)
279#define DRM_EDID_DSC_MAX_FRL_RATE_MASK 0xf0
280#define DRM_EDID_DSC_MAX_SLICES 0xf
281#define DRM_EDID_DSC_TOTAL_CHUNK_KBYTES 0x3f
282
283struct drm_edid_product_id {
284 __be16 manufacturer_name;
285 __le16 product_code;
286 __le32 serial_number;
287 u8 week_of_manufacture;
288 u8 year_of_manufacture;
289} __packed;
290
291struct edid {
292 u8 header[8];
293 /* Vendor & product info */
294 union {
295 struct drm_edid_product_id product_id;
296 struct {
297 u8 mfg_id[2];
298 u8 prod_code[2];
299 u32 serial; /* FIXME: byte order */
300 u8 mfg_week;
301 u8 mfg_year;
302 } __packed;
303 } __packed;
304 /* EDID version */
305 u8 version;
306 u8 revision;
307 /* Display info: */
308 u8 input;
309 u8 width_cm;
310 u8 height_cm;
311 u8 gamma;
312 u8 features;
313 /* Color characteristics */
314 u8 red_green_lo;
315 u8 blue_white_lo;
316 u8 red_x;
317 u8 red_y;
318 u8 green_x;
319 u8 green_y;
320 u8 blue_x;
321 u8 blue_y;
322 u8 white_x;
323 u8 white_y;
324 /* Est. timings and mfg rsvd timings*/
325 struct est_timings established_timings;
326 /* Standard timings 1-8*/
327 struct std_timing standard_timings[8];
328 /* Detailing timings 1-4 */
329 struct detailed_timing detailed_timings[4];
330 /* Number of 128 byte ext. blocks */
331 u8 extensions;
332 /* Checksum */
333 u8 checksum;
334} __packed;
335
336/* EDID matching */
337struct drm_edid_ident {
338 /* ID encoded by drm_edid_encode_panel_id() */
339 u32 panel_id;
340 const char *name;
341};
342
343#define DRM_EDID_IDENT_INIT(_vend_chr_0, _vend_chr_1, _vend_chr_2, _product_id, _name) \
344{ \
345 .panel_id = drm_edid_encode_panel_id(_vend_chr_0, _vend_chr_1, _vend_chr_2, _product_id), \
346 .name = _name, \
347}
348
349#define EDID_PRODUCT_ID(e) ((e)->prod_code[0] | ((e)->prod_code[1] << 8))
350
351/* Short Audio Descriptor */
352struct cea_sad {
353 u8 format;
354 u8 channels; /* max number of channels - 1 */
355 u8 freq;
356 u8 byte2; /* meaning depends on format */
357};
358
359int drm_edid_to_sad(const struct edid *edid, struct cea_sad **sads);
360int drm_edid_to_speaker_allocation(const struct edid *edid, u8 **sadb);
361int drm_av_sync_delay(struct drm_connector *connector,
362 const struct drm_display_mode *mode);
363
364int
365drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
366 const struct drm_connector *connector,
367 const struct drm_display_mode *mode);
368int
369drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
370 const struct drm_connector *connector,
371 const struct drm_display_mode *mode);
372
373void
374drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
375 const struct drm_connector *connector,
376 const struct drm_display_mode *mode,
377 enum hdmi_quantization_range rgb_quant_range);
378
379/**
380 * drm_edid_decode_mfg_id - Decode the manufacturer ID
381 * @mfg_id: The manufacturer ID
382 * @vend: A 4-byte buffer to store the 3-letter vendor string plus a '\0'
383 * termination
384 */
385static inline const char *drm_edid_decode_mfg_id(u16 mfg_id, char vend[4])
386{
387 vend[0] = '@' + ((mfg_id >> 10) & 0x1f);
388 vend[1] = '@' + ((mfg_id >> 5) & 0x1f);
389 vend[2] = '@' + ((mfg_id >> 0) & 0x1f);
390 vend[3] = '\0';
391
392 return vend;
393}
394
395/**
396 * drm_edid_encode_panel_id - Encode an ID for matching against drm_edid_get_panel_id()
397 * @vend_chr_0: First character of the vendor string.
398 * @vend_chr_1: Second character of the vendor string.
399 * @vend_chr_2: Third character of the vendor string.
400 * @product_id: The 16-bit product ID.
401 *
402 * This is a macro so that it can be calculated at compile time and used
403 * as an initializer.
404 *
405 * For instance:
406 * drm_edid_encode_panel_id('B', 'O', 'E', 0x2d08) => 0x09e52d08
407 *
408 * Return: a 32-bit ID per panel.
409 */
410#define drm_edid_encode_panel_id(vend_chr_0, vend_chr_1, vend_chr_2, product_id) \
411 ((((u32)(vend_chr_0) - '@') & 0x1f) << 26 | \
412 (((u32)(vend_chr_1) - '@') & 0x1f) << 21 | \
413 (((u32)(vend_chr_2) - '@') & 0x1f) << 16 | \
414 ((product_id) & 0xffff))
415
416/**
417 * drm_edid_decode_panel_id - Decode a panel ID from drm_edid_encode_panel_id()
418 * @panel_id: The panel ID to decode.
419 * @vend: A 4-byte buffer to store the 3-letter vendor string plus a '\0'
420 * termination
421 * @product_id: The product ID will be returned here.
422 *
423 * For instance, after:
424 * drm_edid_decode_panel_id(0x09e52d08, vend, &product_id)
425 * These will be true:
426 * vend[0] = 'B'
427 * vend[1] = 'O'
428 * vend[2] = 'E'
429 * vend[3] = '\0'
430 * product_id = 0x2d08
431 */
432static inline void drm_edid_decode_panel_id(u32 panel_id, char vend[4], u16 *product_id)
433{
434 *product_id = (u16)(panel_id & 0xffff);
435 drm_edid_decode_mfg_id(mfg_id: panel_id >> 16, vend);
436}
437
438bool drm_probe_ddc(struct i2c_adapter *adapter);
439struct edid *drm_get_edid(struct drm_connector *connector,
440 struct i2c_adapter *adapter);
441struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
442 struct i2c_adapter *adapter);
443struct edid *drm_edid_duplicate(const struct edid *edid);
444int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid);
445int drm_edid_override_connector_update(struct drm_connector *connector);
446
447u8 drm_match_cea_mode(const struct drm_display_mode *to_match);
448bool drm_detect_hdmi_monitor(const struct edid *edid);
449bool drm_detect_monitor_audio(const struct edid *edid);
450enum hdmi_quantization_range
451drm_default_rgb_quant_range(const struct drm_display_mode *mode);
452int drm_add_modes_noedid(struct drm_connector *connector,
453 unsigned int hdisplay, unsigned int vdisplay);
454
455int drm_edid_header_is_valid(const void *edid);
456bool drm_edid_is_valid(struct edid *edid);
457void drm_edid_get_monitor_name(const struct edid *edid, char *name,
458 int buflen);
459struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
460 int hsize, int vsize, int fresh,
461 bool rb);
462struct drm_display_mode *
463drm_display_mode_from_cea_vic(struct drm_device *dev,
464 u8 video_code);
465
466/* Interface based on struct drm_edid */
467const struct drm_edid *drm_edid_alloc(const void *edid, size_t size);
468const struct drm_edid *drm_edid_dup(const struct drm_edid *drm_edid);
469void drm_edid_free(const struct drm_edid *drm_edid);
470bool drm_edid_valid(const struct drm_edid *drm_edid);
471const struct edid *drm_edid_raw(const struct drm_edid *drm_edid);
472const struct drm_edid *drm_edid_read(struct drm_connector *connector);
473const struct drm_edid *drm_edid_read_ddc(struct drm_connector *connector,
474 struct i2c_adapter *adapter);
475const struct drm_edid *drm_edid_read_custom(struct drm_connector *connector,
476 int (*read_block)(void *context, u8 *buf, unsigned int block, size_t len),
477 void *context);
478const struct drm_edid *drm_edid_read_base_block(struct i2c_adapter *adapter);
479const struct drm_edid *drm_edid_read_switcheroo(struct drm_connector *connector,
480 struct i2c_adapter *adapter);
481int drm_edid_connector_update(struct drm_connector *connector,
482 const struct drm_edid *edid);
483int drm_edid_connector_add_modes(struct drm_connector *connector);
484bool drm_edid_is_digital(const struct drm_edid *drm_edid);
485void drm_edid_get_product_id(const struct drm_edid *drm_edid,
486 struct drm_edid_product_id *id);
487void drm_edid_print_product_id(struct drm_printer *p,
488 const struct drm_edid_product_id *id, bool raw);
489u32 drm_edid_get_panel_id(const struct drm_edid *drm_edid);
490bool drm_edid_match(const struct drm_edid *drm_edid,
491 const struct drm_edid_ident *ident);
492bool drm_edid_has_quirk(struct drm_connector *connector, enum drm_edid_quirk quirk);
493
494#endif /* __DRM_EDID_H__ */
495

source code of linux/include/drm/drm_edid.h