| 1 | /* SPDX-License-Identifier: MIT */ |
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| 2 | /* |
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| 3 | * Copyright © 2024 Intel Corporation |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef __INTEL_CRT_REGS_H__ |
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| 7 | #define __INTEL_CRT_REGS_H__ |
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| 8 | |
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| 9 | #include "intel_display_reg_defs.h" |
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| 10 | |
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| 11 | #define ADPA _MMIO(0x61100) |
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| 12 | #define PCH_ADPA _MMIO(0xe1100) |
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| 13 | #define VLV_ADPA _MMIO(VLV_DISPLAY_BASE + 0x61100) |
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| 14 | #define ADPA_DAC_ENABLE REG_BIT(31) |
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| 15 | #define ADPA_PIPE_SEL_MASK REG_BIT(30) |
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| 16 | #define ADPA_PIPE_SEL(pipe) REG_FIELD_PREP(ADPA_PIPE_SEL_MASK, (pipe)) |
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| 17 | #define ADPA_PIPE_SEL_MASK_CPT REG_GENMASK(30, 29) |
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| 18 | #define ADPA_PIPE_SEL_CPT(pipe) REG_FIELD_PREP(ADPA_PIPE_SEL_MASK_CPT, (pipe)) |
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| 19 | #define ADPA_CRT_HOTPLUG_MONITOR_MASK REG_GENMASK(25, 24) |
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| 20 | #define ADPA_CRT_HOTPLUG_MONITOR_NONE REG_FIELD_PREP(ADPA_CRT_HOTPLUG_MONITOR_MASK, 0) |
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| 21 | #define ADPA_CRT_HOTPLUG_MONITOR_COLOR REG_FIELD_PREP(ADPA_CRT_HOTPLUG_MONITOR_MASK, 3) |
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| 22 | #define ADPA_CRT_HOTPLUG_MONITOR_MONO REG_FIELD_PREP(ADPA_CRT_HOTPLUG_MONITOR_MASK, 2) |
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| 23 | #define ADPA_CRT_HOTPLUG_ENABLE REG_BIT(23) |
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| 24 | #define ADPA_CRT_HOTPLUG_PERIOD_MASK REG_BIT(22) |
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| 25 | #define ADPA_CRT_HOTPLUG_PERIOD_64 REG_FIELD_PREP(ADPA_CRT_HOTPLUG_PERIOD_MASK, 0) |
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| 26 | #define ADPA_CRT_HOTPLUG_PERIOD_128 REG_FIELD_PREP(ADPA_CRT_HOTPLUG_PERIOD_MASK, 1) |
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| 27 | #define ADPA_CRT_HOTPLUG_WARMUP_MASK REG_BIT(21) |
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| 28 | #define ADPA_CRT_HOTPLUG_WARMUP_5MS REG_FIELD_PREP(ADPA_CRT_HOTPLUG_WARMUP_MASK, 0) |
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| 29 | #define ADPA_CRT_HOTPLUG_WARMUP_10MS REG_FIELD_PREP(ADPA_CRT_HOTPLUG_WARMUP_MASK, 1) |
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| 30 | #define ADPA_CRT_HOTPLUG_SAMPLE_MASK REG_BIT(20) |
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| 31 | #define ADPA_CRT_HOTPLUG_SAMPLE_2S REG_FIELD_PREP(ADPA_CRT_HOTPLUG_SAMPLE_MASK, 0) |
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| 32 | #define ADPA_CRT_HOTPLUG_SAMPLE_4S REG_FIELD_PREP(ADPA_CRT_HOTPLUG_SAMPLE_MASK, 1) |
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| 33 | #define ADPA_CRT_HOTPLUG_VOLTAGE_MASK REG_GENMASK(19, 18) |
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| 34 | #define ADPA_CRT_HOTPLUG_VOLTAGE_40 REG_FIELD_PREP(ADPA_CRT_HOTPLUG_VOLTAGE_MASK, 0) |
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| 35 | #define ADPA_CRT_HOTPLUG_VOLTAGE_50 REG_FIELD_PREP(ADPA_CRT_HOTPLUG_VOLTAGE_MASK, 1) |
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| 36 | #define ADPA_CRT_HOTPLUG_VOLTAGE_60 REG_FIELD_PREP(ADPA_CRT_HOTPLUG_VOLTAGE_MASK, 2) |
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| 37 | #define ADPA_CRT_HOTPLUG_VOLTAGE_70 REG_FIELD_PREP(ADPA_CRT_HOTPLUG_VOLTAGE_MASK, 3) |
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| 38 | #define ADPA_CRT_HOTPLUG_VOLREF_MASK REG_BIT(17) |
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| 39 | #define ADPA_CRT_HOTPLUG_VOLREF_325MV REG_FIELD_PREP(ADPA_CRT_HOTPLUG_VOLREF_MASK, 0) |
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| 40 | #define ADPA_CRT_HOTPLUG_VOLREF_475MV REG_FIELD_PREP(ADPA_CRT_HOTPLUG_VOLREF_MASK, 1) |
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| 41 | #define ADPA_CRT_HOTPLUG_FORCE_TRIGGER REG_BIT(16) |
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| 42 | #define ADPA_USE_VGA_HVPOLARITY REG_BIT(15) |
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| 43 | #define ADPA_HSYNC_CNTL_DISABLE REG_BIT(11) |
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| 44 | #define ADPA_VSYNC_CNTL_DISABLE REG_BIT(10) |
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| 45 | #define ADPA_VSYNC_ACTIVE_HIGH REG_BIT(4) |
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| 46 | #define ADPA_HSYNC_ACTIVE_HIGH REG_BIT(3) |
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| 47 | |
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| 48 | #define _VGA_MSR_WRITE _MMIO(0x3c2) |
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| 49 | |
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| 50 | #endif /* __INTEL_CRT_REGS_H__ */ |
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| 51 | |
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