1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2023 Intel Corporation
4 */
5
6#include <drm/drm_print.h>
7
8#include "i915_reg.h"
9#include "intel_de.h"
10#include "intel_display_irq.h"
11#include "intel_display_regs.h"
12#include "intel_display_types.h"
13#include "intel_display_utils.h"
14#include "intel_dp_aux.h"
15#include "intel_gmbus.h"
16#include "intel_hotplug.h"
17#include "intel_hotplug_irq.h"
18
19typedef bool (*long_pulse_detect_func)(enum hpd_pin pin, u32 val);
20typedef u32 (*hotplug_enables_func)(struct intel_encoder *encoder);
21typedef u32 (*hotplug_mask_func)(enum hpd_pin pin);
22
23static const u32 hpd_ilk[HPD_NUM_PINS] = {
24 [HPD_PORT_A] = DE_DP_A_HOTPLUG,
25};
26
27static const u32 hpd_ivb[HPD_NUM_PINS] = {
28 [HPD_PORT_A] = DE_DP_A_HOTPLUG_IVB,
29};
30
31static const u32 hpd_bdw[HPD_NUM_PINS] = {
32 [HPD_PORT_A] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_A),
33};
34
35static const u32 hpd_ibx[HPD_NUM_PINS] = {
36 [HPD_CRT] = SDE_CRT_HOTPLUG,
37 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
38 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
39 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
40 [HPD_PORT_D] = SDE_PORTD_HOTPLUG,
41};
42
43static const u32 hpd_cpt[HPD_NUM_PINS] = {
44 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
45 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
46 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
47 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
48 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
49};
50
51static const u32 hpd_spt[HPD_NUM_PINS] = {
52 [HPD_PORT_A] = SDE_PORTA_HOTPLUG_SPT,
53 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
54 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
55 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
56 [HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT,
57};
58
59static const u32 hpd_mask_i915[HPD_NUM_PINS] = {
60 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
61 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
62 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
63 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
64 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
65 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN,
66};
67
68static const u32 hpd_status_g4x[HPD_NUM_PINS] = {
69 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
70 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
71 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
72 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
73 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
74 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS,
75};
76
77static const u32 hpd_status_i915[HPD_NUM_PINS] = {
78 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
79 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
80 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
81 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
82 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
83 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS,
84};
85
86static const u32 hpd_bxt[HPD_NUM_PINS] = {
87 [HPD_PORT_A] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_A),
88 [HPD_PORT_B] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_B),
89 [HPD_PORT_C] = GEN8_DE_PORT_HOTPLUG(HPD_PORT_C),
90};
91
92static const u32 hpd_gen11[HPD_NUM_PINS] = {
93 [HPD_PORT_TC1] = GEN11_TC_HOTPLUG(HPD_PORT_TC1) | GEN11_TBT_HOTPLUG(HPD_PORT_TC1),
94 [HPD_PORT_TC2] = GEN11_TC_HOTPLUG(HPD_PORT_TC2) | GEN11_TBT_HOTPLUG(HPD_PORT_TC2),
95 [HPD_PORT_TC3] = GEN11_TC_HOTPLUG(HPD_PORT_TC3) | GEN11_TBT_HOTPLUG(HPD_PORT_TC3),
96 [HPD_PORT_TC4] = GEN11_TC_HOTPLUG(HPD_PORT_TC4) | GEN11_TBT_HOTPLUG(HPD_PORT_TC4),
97 [HPD_PORT_TC5] = GEN11_TC_HOTPLUG(HPD_PORT_TC5) | GEN11_TBT_HOTPLUG(HPD_PORT_TC5),
98 [HPD_PORT_TC6] = GEN11_TC_HOTPLUG(HPD_PORT_TC6) | GEN11_TBT_HOTPLUG(HPD_PORT_TC6),
99};
100
101static const u32 hpd_xelpdp[HPD_NUM_PINS] = {
102 [HPD_PORT_TC1] = XELPDP_TBT_HOTPLUG(HPD_PORT_TC1) | XELPDP_DP_ALT_HOTPLUG(HPD_PORT_TC1),
103 [HPD_PORT_TC2] = XELPDP_TBT_HOTPLUG(HPD_PORT_TC2) | XELPDP_DP_ALT_HOTPLUG(HPD_PORT_TC2),
104 [HPD_PORT_TC3] = XELPDP_TBT_HOTPLUG(HPD_PORT_TC3) | XELPDP_DP_ALT_HOTPLUG(HPD_PORT_TC3),
105 [HPD_PORT_TC4] = XELPDP_TBT_HOTPLUG(HPD_PORT_TC4) | XELPDP_DP_ALT_HOTPLUG(HPD_PORT_TC4),
106};
107
108static const u32 hpd_icp[HPD_NUM_PINS] = {
109 [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_A),
110 [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B),
111 [HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_C),
112 [HPD_PORT_TC1] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1),
113 [HPD_PORT_TC2] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2),
114 [HPD_PORT_TC3] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3),
115 [HPD_PORT_TC4] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4),
116 [HPD_PORT_TC5] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC5),
117 [HPD_PORT_TC6] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC6),
118};
119
120static const u32 hpd_sde_dg1[HPD_NUM_PINS] = {
121 [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_A),
122 [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B),
123 [HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_C),
124 [HPD_PORT_D] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_D),
125 [HPD_PORT_TC1] = SDE_TC_HOTPLUG_DG2(HPD_PORT_TC1),
126};
127
128static const u32 hpd_mtp[HPD_NUM_PINS] = {
129 [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_A),
130 [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(HPD_PORT_B),
131 [HPD_PORT_TC1] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1),
132 [HPD_PORT_TC2] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2),
133 [HPD_PORT_TC3] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC3),
134 [HPD_PORT_TC4] = SDE_TC_HOTPLUG_ICP(HPD_PORT_TC4),
135};
136
137static void intel_hpd_init_pins(struct intel_display *display)
138{
139 struct intel_hotplug *hpd = &display->hotplug;
140
141 if (HAS_GMCH(display)) {
142 if (display->platform.g4x || display->platform.valleyview ||
143 display->platform.cherryview)
144 hpd->hpd = hpd_status_g4x;
145 else
146 hpd->hpd = hpd_status_i915;
147 return;
148 }
149
150 if (DISPLAY_VER(display) >= 14)
151 hpd->hpd = hpd_xelpdp;
152 else if (DISPLAY_VER(display) >= 11)
153 hpd->hpd = hpd_gen11;
154 else if (display->platform.geminilake || display->platform.broxton)
155 hpd->hpd = hpd_bxt;
156 else if (DISPLAY_VER(display) == 9)
157 hpd->hpd = NULL; /* no north HPD on SKL */
158 else if (DISPLAY_VER(display) >= 8)
159 hpd->hpd = hpd_bdw;
160 else if (DISPLAY_VER(display) >= 7)
161 hpd->hpd = hpd_ivb;
162 else
163 hpd->hpd = hpd_ilk;
164
165 if ((INTEL_PCH_TYPE(display) < PCH_DG1) &&
166 (!HAS_PCH_SPLIT(display) || HAS_PCH_NOP(display)))
167 return;
168
169 if (INTEL_PCH_TYPE(display) >= PCH_MTL)
170 hpd->pch_hpd = hpd_mtp;
171 else if (INTEL_PCH_TYPE(display) >= PCH_DG1)
172 hpd->pch_hpd = hpd_sde_dg1;
173 else if (INTEL_PCH_TYPE(display) >= PCH_ICP)
174 hpd->pch_hpd = hpd_icp;
175 else if (HAS_PCH_CNP(display) || HAS_PCH_SPT(display))
176 hpd->pch_hpd = hpd_spt;
177 else if (HAS_PCH_LPT(display) || HAS_PCH_CPT(display))
178 hpd->pch_hpd = hpd_cpt;
179 else if (HAS_PCH_IBX(display))
180 hpd->pch_hpd = hpd_ibx;
181 else
182 MISSING_CASE(INTEL_PCH_TYPE(display));
183}
184
185/* For display hotplug interrupt */
186void i915_hotplug_interrupt_update_locked(struct intel_display *display,
187 u32 mask, u32 bits)
188{
189 lockdep_assert_held(&display->irq.lock);
190 drm_WARN_ON(display->drm, bits & ~mask);
191
192 intel_de_rmw(display, PORT_HOTPLUG_EN(display), clear: mask, set: bits);
193}
194
195/**
196 * i915_hotplug_interrupt_update - update hotplug interrupt enable
197 * @display: display device
198 * @mask: bits to update
199 * @bits: bits to enable
200 * NOTE: the HPD enable bits are modified both inside and outside
201 * of an interrupt context. To avoid that read-modify-write cycles
202 * interfere, these bits are protected by a spinlock. Since this
203 * function is usually not called from a context where the lock is
204 * held already, this function acquires the lock itself. A non-locking
205 * version is also available.
206 */
207void i915_hotplug_interrupt_update(struct intel_display *display,
208 u32 mask,
209 u32 bits)
210{
211 spin_lock_irq(lock: &display->irq.lock);
212 i915_hotplug_interrupt_update_locked(display, mask, bits);
213 spin_unlock_irq(lock: &display->irq.lock);
214}
215
216static bool gen11_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
217{
218 switch (pin) {
219 case HPD_PORT_TC1:
220 case HPD_PORT_TC2:
221 case HPD_PORT_TC3:
222 case HPD_PORT_TC4:
223 case HPD_PORT_TC5:
224 case HPD_PORT_TC6:
225 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(pin);
226 default:
227 return false;
228 }
229}
230
231static bool bxt_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
232{
233 switch (pin) {
234 case HPD_PORT_A:
235 return val & PORTA_HOTPLUG_LONG_DETECT;
236 case HPD_PORT_B:
237 return val & PORTB_HOTPLUG_LONG_DETECT;
238 case HPD_PORT_C:
239 return val & PORTC_HOTPLUG_LONG_DETECT;
240 default:
241 return false;
242 }
243}
244
245static bool icp_ddi_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
246{
247 switch (pin) {
248 case HPD_PORT_A:
249 case HPD_PORT_B:
250 case HPD_PORT_C:
251 case HPD_PORT_D:
252 return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(pin);
253 default:
254 return false;
255 }
256}
257
258static bool icp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
259{
260 switch (pin) {
261 case HPD_PORT_TC1:
262 case HPD_PORT_TC2:
263 case HPD_PORT_TC3:
264 case HPD_PORT_TC4:
265 case HPD_PORT_TC5:
266 case HPD_PORT_TC6:
267 return val & ICP_TC_HPD_LONG_DETECT(pin);
268 default:
269 return false;
270 }
271}
272
273static bool spt_port_hotplug2_long_detect(enum hpd_pin pin, u32 val)
274{
275 switch (pin) {
276 case HPD_PORT_E:
277 return val & PORTE_HOTPLUG_LONG_DETECT;
278 default:
279 return false;
280 }
281}
282
283static bool spt_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
284{
285 switch (pin) {
286 case HPD_PORT_A:
287 return val & PORTA_HOTPLUG_LONG_DETECT;
288 case HPD_PORT_B:
289 return val & PORTB_HOTPLUG_LONG_DETECT;
290 case HPD_PORT_C:
291 return val & PORTC_HOTPLUG_LONG_DETECT;
292 case HPD_PORT_D:
293 return val & PORTD_HOTPLUG_LONG_DETECT;
294 default:
295 return false;
296 }
297}
298
299static bool ilk_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
300{
301 switch (pin) {
302 case HPD_PORT_A:
303 return val & DIGITAL_PORTA_HOTPLUG_LONG_DETECT;
304 default:
305 return false;
306 }
307}
308
309static bool pch_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
310{
311 switch (pin) {
312 case HPD_PORT_B:
313 return val & PORTB_HOTPLUG_LONG_DETECT;
314 case HPD_PORT_C:
315 return val & PORTC_HOTPLUG_LONG_DETECT;
316 case HPD_PORT_D:
317 return val & PORTD_HOTPLUG_LONG_DETECT;
318 default:
319 return false;
320 }
321}
322
323static bool i9xx_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
324{
325 switch (pin) {
326 case HPD_PORT_B:
327 return val & PORTB_HOTPLUG_INT_LONG_PULSE;
328 case HPD_PORT_C:
329 return val & PORTC_HOTPLUG_INT_LONG_PULSE;
330 case HPD_PORT_D:
331 return val & PORTD_HOTPLUG_INT_LONG_PULSE;
332 default:
333 return false;
334 }
335}
336
337/*
338 * Get a bit mask of pins that have triggered, and which ones may be long.
339 * This can be called multiple times with the same masks to accumulate
340 * hotplug detection results from several registers.
341 *
342 * Note that the caller is expected to zero out the masks initially.
343 */
344static void intel_get_hpd_pins(struct intel_display *display,
345 u32 *pin_mask, u32 *long_mask,
346 u32 hotplug_trigger, u32 dig_hotplug_reg,
347 const u32 hpd[HPD_NUM_PINS],
348 bool long_pulse_detect(enum hpd_pin pin, u32 val))
349{
350 enum hpd_pin pin;
351
352 BUILD_BUG_ON(BITS_PER_TYPE(*pin_mask) < HPD_NUM_PINS);
353
354 for_each_hpd_pin(pin) {
355 if ((hpd[pin] & hotplug_trigger) == 0)
356 continue;
357
358 *pin_mask |= BIT(pin);
359
360 if (long_pulse_detect(pin, dig_hotplug_reg))
361 *long_mask |= BIT(pin);
362 }
363
364 drm_dbg_kms(display->drm,
365 "hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x, long 0x%08x\n",
366 hotplug_trigger, dig_hotplug_reg, *pin_mask, *long_mask);
367}
368
369static u32 intel_hpd_enabled_irqs(struct intel_display *display,
370 const u32 hpd[HPD_NUM_PINS])
371{
372 struct intel_encoder *encoder;
373 u32 enabled_irqs = 0;
374
375 for_each_intel_encoder(display->drm, encoder)
376 if (display->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
377 enabled_irqs |= hpd[encoder->hpd_pin];
378
379 return enabled_irqs;
380}
381
382static u32 intel_hpd_hotplug_irqs(struct intel_display *display,
383 const u32 hpd[HPD_NUM_PINS])
384{
385 struct intel_encoder *encoder;
386 u32 hotplug_irqs = 0;
387
388 for_each_intel_encoder(display->drm, encoder)
389 hotplug_irqs |= hpd[encoder->hpd_pin];
390
391 return hotplug_irqs;
392}
393
394static u32 intel_hpd_hotplug_mask(struct intel_display *display,
395 hotplug_mask_func hotplug_mask)
396{
397 enum hpd_pin pin;
398 u32 hotplug = 0;
399
400 for_each_hpd_pin(pin)
401 hotplug |= hotplug_mask(pin);
402
403 return hotplug;
404}
405
406static u32 intel_hpd_hotplug_enables(struct intel_display *display,
407 hotplug_enables_func hotplug_enables)
408{
409 struct intel_encoder *encoder;
410 u32 hotplug = 0;
411
412 for_each_intel_encoder(display->drm, encoder)
413 hotplug |= hotplug_enables(encoder);
414
415 return hotplug;
416}
417
418u32 i9xx_hpd_irq_ack(struct intel_display *display)
419{
420 u32 hotplug_status = 0, hotplug_status_mask;
421 int i;
422
423 if (!HAS_HOTPLUG(display))
424 return 0;
425
426 if (display->platform.g4x ||
427 display->platform.valleyview || display->platform.cherryview)
428 hotplug_status_mask = HOTPLUG_INT_STATUS_G4X |
429 DP_AUX_CHANNEL_MASK_INT_STATUS_G4X;
430 else
431 hotplug_status_mask = HOTPLUG_INT_STATUS_I915;
432
433 /*
434 * We absolutely have to clear all the pending interrupt
435 * bits in PORT_HOTPLUG_STAT. Otherwise the ISR port
436 * interrupt bit won't have an edge, and the i965/g4x
437 * edge triggered IIR will not notice that an interrupt
438 * is still pending. We can't use PORT_HOTPLUG_EN to
439 * guarantee the edge as the act of toggling the enable
440 * bits can itself generate a new hotplug interrupt :(
441 */
442 for (i = 0; i < 10; i++) {
443 u32 tmp = intel_de_read(display,
444 PORT_HOTPLUG_STAT(display)) & hotplug_status_mask;
445
446 if (tmp == 0)
447 return hotplug_status;
448
449 hotplug_status |= tmp;
450 intel_de_write(display, PORT_HOTPLUG_STAT(display),
451 val: hotplug_status);
452 }
453
454 drm_WARN_ONCE(display->drm, 1,
455 "PORT_HOTPLUG_STAT did not clear (0x%08x)\n",
456 intel_de_read(display, PORT_HOTPLUG_STAT(display)));
457
458 return hotplug_status;
459}
460
461void i9xx_hpd_irq_handler(struct intel_display *display, u32 hotplug_status)
462{
463 u32 pin_mask = 0, long_mask = 0;
464 u32 hotplug_trigger;
465
466 if (display->platform.g4x ||
467 display->platform.valleyview || display->platform.cherryview)
468 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
469 else
470 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
471
472 if (hotplug_trigger) {
473 intel_get_hpd_pins(display, pin_mask: &pin_mask, long_mask: &long_mask,
474 hotplug_trigger, dig_hotplug_reg: hotplug_trigger,
475 hpd: display->hotplug.hpd,
476 long_pulse_detect: i9xx_port_hotplug_long_detect);
477
478 intel_hpd_irq_handler(display, pin_mask, long_mask);
479 }
480
481 if ((display->platform.g4x ||
482 display->platform.valleyview || display->platform.cherryview) &&
483 hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
484 intel_dp_aux_irq_handler(display);
485}
486
487void ibx_hpd_irq_handler(struct intel_display *display, u32 hotplug_trigger)
488{
489 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
490
491 /*
492 * Somehow the PCH doesn't seem to really ack the interrupt to the CPU
493 * unless we touch the hotplug register, even if hotplug_trigger is
494 * zero. Not acking leads to "The master control interrupt lied (SDE)!"
495 * errors.
496 */
497 dig_hotplug_reg = intel_de_read(display, PCH_PORT_HOTPLUG);
498 if (!hotplug_trigger) {
499 u32 mask = PORTA_HOTPLUG_STATUS_MASK |
500 PORTD_HOTPLUG_STATUS_MASK |
501 PORTC_HOTPLUG_STATUS_MASK |
502 PORTB_HOTPLUG_STATUS_MASK;
503 dig_hotplug_reg &= ~mask;
504 }
505
506 intel_de_write(display, PCH_PORT_HOTPLUG, val: dig_hotplug_reg);
507 if (!hotplug_trigger)
508 return;
509
510 intel_get_hpd_pins(display, pin_mask: &pin_mask, long_mask: &long_mask,
511 hotplug_trigger, dig_hotplug_reg,
512 hpd: display->hotplug.pch_hpd,
513 long_pulse_detect: pch_port_hotplug_long_detect);
514
515 intel_hpd_irq_handler(display, pin_mask, long_mask);
516}
517
518void xelpdp_pica_irq_handler(struct intel_display *display, u32 iir)
519{
520 enum hpd_pin pin;
521 u32 hotplug_trigger = iir & (XELPDP_DP_ALT_HOTPLUG_MASK | XELPDP_TBT_HOTPLUG_MASK);
522 u32 trigger_aux = iir & XELPDP_AUX_TC_MASK;
523 u32 pin_mask = 0, long_mask = 0;
524
525 if (DISPLAY_VER(display) >= 20)
526 trigger_aux |= iir & XE2LPD_AUX_DDI_MASK;
527
528 for (pin = HPD_PORT_TC1; pin <= HPD_PORT_TC4; pin++) {
529 u32 val;
530
531 if (!(display->hotplug.hpd[pin] & hotplug_trigger))
532 continue;
533
534 pin_mask |= BIT(pin);
535
536 val = intel_de_read(display, XELPDP_PORT_HOTPLUG_CTL(pin));
537 intel_de_write(display, XELPDP_PORT_HOTPLUG_CTL(pin), val);
538
539 if (val & (XELPDP_DP_ALT_HPD_LONG_DETECT | XELPDP_TBT_HPD_LONG_DETECT))
540 long_mask |= BIT(pin);
541 }
542
543 if (pin_mask) {
544 drm_dbg_kms(display->drm,
545 "pica hotplug event received, stat 0x%08x, pins 0x%08x, long 0x%08x\n",
546 hotplug_trigger, pin_mask, long_mask);
547
548 intel_hpd_irq_handler(display, pin_mask, long_mask);
549 }
550
551 if (trigger_aux)
552 intel_dp_aux_irq_handler(display);
553
554 if (!pin_mask && !trigger_aux)
555 drm_err(display->drm,
556 "Unexpected DE HPD/AUX interrupt 0x%08x\n", iir);
557}
558
559void icp_irq_handler(struct intel_display *display, u32 pch_iir)
560{
561 u32 ddi_hotplug_trigger = pch_iir & SDE_DDI_HOTPLUG_MASK_ICP;
562 u32 tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_MASK_ICP;
563 u32 pin_mask = 0, long_mask = 0;
564
565 if (ddi_hotplug_trigger) {
566 u32 dig_hotplug_reg;
567
568 /* Locking due to DSI native GPIO sequences */
569 spin_lock(lock: &display->irq.lock);
570 dig_hotplug_reg = intel_de_rmw(display, SHOTPLUG_CTL_DDI, clear: 0, set: 0);
571 spin_unlock(lock: &display->irq.lock);
572
573 intel_get_hpd_pins(display, pin_mask: &pin_mask, long_mask: &long_mask,
574 hotplug_trigger: ddi_hotplug_trigger, dig_hotplug_reg,
575 hpd: display->hotplug.pch_hpd,
576 long_pulse_detect: icp_ddi_port_hotplug_long_detect);
577 }
578
579 if (tc_hotplug_trigger) {
580 u32 dig_hotplug_reg;
581
582 dig_hotplug_reg = intel_de_rmw(display, SHOTPLUG_CTL_TC, clear: 0, set: 0);
583
584 intel_get_hpd_pins(display, pin_mask: &pin_mask, long_mask: &long_mask,
585 hotplug_trigger: tc_hotplug_trigger, dig_hotplug_reg,
586 hpd: display->hotplug.pch_hpd,
587 long_pulse_detect: icp_tc_port_hotplug_long_detect);
588 }
589
590 if (pin_mask)
591 intel_hpd_irq_handler(display, pin_mask, long_mask);
592
593 if (pch_iir & SDE_GMBUS_ICP)
594 intel_gmbus_irq_handler(display);
595}
596
597void spt_irq_handler(struct intel_display *display, u32 pch_iir)
598{
599 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
600 ~SDE_PORTE_HOTPLUG_SPT;
601 u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT;
602 u32 pin_mask = 0, long_mask = 0;
603
604 if (hotplug_trigger) {
605 u32 dig_hotplug_reg;
606
607 dig_hotplug_reg = intel_de_rmw(display, PCH_PORT_HOTPLUG, clear: 0, set: 0);
608
609 intel_get_hpd_pins(display, pin_mask: &pin_mask, long_mask: &long_mask,
610 hotplug_trigger, dig_hotplug_reg,
611 hpd: display->hotplug.pch_hpd,
612 long_pulse_detect: spt_port_hotplug_long_detect);
613 }
614
615 if (hotplug2_trigger) {
616 u32 dig_hotplug_reg;
617
618 dig_hotplug_reg = intel_de_rmw(display, PCH_PORT_HOTPLUG2, clear: 0, set: 0);
619
620 intel_get_hpd_pins(display, pin_mask: &pin_mask, long_mask: &long_mask,
621 hotplug_trigger: hotplug2_trigger, dig_hotplug_reg,
622 hpd: display->hotplug.pch_hpd,
623 long_pulse_detect: spt_port_hotplug2_long_detect);
624 }
625
626 if (pin_mask)
627 intel_hpd_irq_handler(display, pin_mask, long_mask);
628
629 if (pch_iir & SDE_GMBUS_CPT)
630 intel_gmbus_irq_handler(display);
631}
632
633void ilk_hpd_irq_handler(struct intel_display *display, u32 hotplug_trigger)
634{
635 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
636
637 dig_hotplug_reg = intel_de_rmw(display, DIGITAL_PORT_HOTPLUG_CNTRL, clear: 0, set: 0);
638
639 intel_get_hpd_pins(display, pin_mask: &pin_mask, long_mask: &long_mask,
640 hotplug_trigger, dig_hotplug_reg,
641 hpd: display->hotplug.hpd,
642 long_pulse_detect: ilk_port_hotplug_long_detect);
643
644 intel_hpd_irq_handler(display, pin_mask, long_mask);
645}
646
647void bxt_hpd_irq_handler(struct intel_display *display, u32 hotplug_trigger)
648{
649 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
650
651 dig_hotplug_reg = intel_de_rmw(display, PCH_PORT_HOTPLUG, clear: 0, set: 0);
652
653 intel_get_hpd_pins(display, pin_mask: &pin_mask, long_mask: &long_mask,
654 hotplug_trigger, dig_hotplug_reg,
655 hpd: display->hotplug.hpd,
656 long_pulse_detect: bxt_port_hotplug_long_detect);
657
658 intel_hpd_irq_handler(display, pin_mask, long_mask);
659}
660
661void gen11_hpd_irq_handler(struct intel_display *display, u32 iir)
662{
663 u32 pin_mask = 0, long_mask = 0;
664 u32 trigger_tc = iir & GEN11_DE_TC_HOTPLUG_MASK;
665 u32 trigger_tbt = iir & GEN11_DE_TBT_HOTPLUG_MASK;
666
667 if (trigger_tc) {
668 u32 dig_hotplug_reg;
669
670 dig_hotplug_reg = intel_de_rmw(display, GEN11_TC_HOTPLUG_CTL, clear: 0, set: 0);
671
672 intel_get_hpd_pins(display, pin_mask: &pin_mask, long_mask: &long_mask,
673 hotplug_trigger: trigger_tc, dig_hotplug_reg,
674 hpd: display->hotplug.hpd,
675 long_pulse_detect: gen11_port_hotplug_long_detect);
676 }
677
678 if (trigger_tbt) {
679 u32 dig_hotplug_reg;
680
681 dig_hotplug_reg = intel_de_rmw(display, GEN11_TBT_HOTPLUG_CTL, clear: 0, set: 0);
682
683 intel_get_hpd_pins(display, pin_mask: &pin_mask, long_mask: &long_mask,
684 hotplug_trigger: trigger_tbt, dig_hotplug_reg,
685 hpd: display->hotplug.hpd,
686 long_pulse_detect: gen11_port_hotplug_long_detect);
687 }
688
689 if (pin_mask)
690 intel_hpd_irq_handler(display, pin_mask, long_mask);
691 else
692 drm_err(display->drm,
693 "Unexpected DE HPD interrupt 0x%08x\n", iir);
694}
695
696static u32 ibx_hotplug_mask(enum hpd_pin hpd_pin)
697{
698 switch (hpd_pin) {
699 case HPD_PORT_A:
700 return PORTA_HOTPLUG_ENABLE;
701 case HPD_PORT_B:
702 return PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_MASK;
703 case HPD_PORT_C:
704 return PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_MASK;
705 case HPD_PORT_D:
706 return PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_MASK;
707 default:
708 return 0;
709 }
710}
711
712static u32 ibx_hotplug_enables(struct intel_encoder *encoder)
713{
714 struct intel_display *display = to_intel_display(encoder);
715
716 switch (encoder->hpd_pin) {
717 case HPD_PORT_A:
718 /*
719 * When CPU and PCH are on the same package, port A
720 * HPD must be enabled in both north and south.
721 */
722 return HAS_PCH_LPT_LP(display) ?
723 PORTA_HOTPLUG_ENABLE : 0;
724 case HPD_PORT_B:
725 return PORTB_HOTPLUG_ENABLE |
726 PORTB_PULSE_DURATION_2ms;
727 case HPD_PORT_C:
728 return PORTC_HOTPLUG_ENABLE |
729 PORTC_PULSE_DURATION_2ms;
730 case HPD_PORT_D:
731 return PORTD_HOTPLUG_ENABLE |
732 PORTD_PULSE_DURATION_2ms;
733 default:
734 return 0;
735 }
736}
737
738static void ibx_hpd_detection_setup(struct intel_display *display)
739{
740 /*
741 * Enable digital hotplug on the PCH, and configure the DP short pulse
742 * duration to 2ms (which is the minimum in the Display Port spec).
743 * The pulse duration bits are reserved on LPT+.
744 */
745 intel_de_rmw(display, PCH_PORT_HOTPLUG,
746 clear: intel_hpd_hotplug_mask(display, hotplug_mask: ibx_hotplug_mask),
747 set: intel_hpd_hotplug_enables(display, hotplug_enables: ibx_hotplug_enables));
748}
749
750static void ibx_hpd_enable_detection(struct intel_encoder *encoder)
751{
752 struct intel_display *display = to_intel_display(encoder);
753
754 intel_de_rmw(display, PCH_PORT_HOTPLUG,
755 clear: ibx_hotplug_mask(hpd_pin: encoder->hpd_pin),
756 set: ibx_hotplug_enables(encoder));
757}
758
759static void ibx_hpd_irq_setup(struct intel_display *display)
760{
761 u32 hotplug_irqs, enabled_irqs;
762
763 enabled_irqs = intel_hpd_enabled_irqs(display, hpd: display->hotplug.pch_hpd);
764 hotplug_irqs = intel_hpd_hotplug_irqs(display, hpd: display->hotplug.pch_hpd);
765
766 ibx_display_interrupt_update(display, interrupt_mask: hotplug_irqs, enabled_irq_mask: enabled_irqs);
767
768 ibx_hpd_detection_setup(display);
769}
770
771static u32 icp_ddi_hotplug_mask(enum hpd_pin hpd_pin)
772{
773 switch (hpd_pin) {
774 case HPD_PORT_A:
775 case HPD_PORT_B:
776 case HPD_PORT_C:
777 case HPD_PORT_D:
778 return SHOTPLUG_CTL_DDI_HPD_ENABLE(hpd_pin);
779 default:
780 return 0;
781 }
782}
783
784static u32 icp_ddi_hotplug_enables(struct intel_encoder *encoder)
785{
786 return icp_ddi_hotplug_mask(hpd_pin: encoder->hpd_pin);
787}
788
789static u32 icp_tc_hotplug_mask(enum hpd_pin hpd_pin)
790{
791 switch (hpd_pin) {
792 case HPD_PORT_TC1:
793 case HPD_PORT_TC2:
794 case HPD_PORT_TC3:
795 case HPD_PORT_TC4:
796 case HPD_PORT_TC5:
797 case HPD_PORT_TC6:
798 return ICP_TC_HPD_ENABLE(hpd_pin);
799 default:
800 return 0;
801 }
802}
803
804static u32 icp_tc_hotplug_enables(struct intel_encoder *encoder)
805{
806 return icp_tc_hotplug_mask(hpd_pin: encoder->hpd_pin);
807}
808
809static void icp_ddi_hpd_detection_setup(struct intel_display *display)
810{
811 intel_de_rmw(display, SHOTPLUG_CTL_DDI,
812 clear: intel_hpd_hotplug_mask(display, hotplug_mask: icp_ddi_hotplug_mask),
813 set: intel_hpd_hotplug_enables(display, hotplug_enables: icp_ddi_hotplug_enables));
814}
815
816static void icp_ddi_hpd_enable_detection(struct intel_encoder *encoder)
817{
818 struct intel_display *display = to_intel_display(encoder);
819
820 intel_de_rmw(display, SHOTPLUG_CTL_DDI,
821 clear: icp_ddi_hotplug_mask(hpd_pin: encoder->hpd_pin),
822 set: icp_ddi_hotplug_enables(encoder));
823}
824
825static void icp_tc_hpd_detection_setup(struct intel_display *display)
826{
827 intel_de_rmw(display, SHOTPLUG_CTL_TC,
828 clear: intel_hpd_hotplug_mask(display, hotplug_mask: icp_tc_hotplug_mask),
829 set: intel_hpd_hotplug_enables(display, hotplug_enables: icp_tc_hotplug_enables));
830}
831
832static void icp_tc_hpd_enable_detection(struct intel_encoder *encoder)
833{
834 struct intel_display *display = to_intel_display(encoder);
835
836 intel_de_rmw(display, SHOTPLUG_CTL_TC,
837 clear: icp_tc_hotplug_mask(hpd_pin: encoder->hpd_pin),
838 set: icp_tc_hotplug_enables(encoder));
839}
840
841static void icp_hpd_enable_detection(struct intel_encoder *encoder)
842{
843 icp_ddi_hpd_enable_detection(encoder);
844 icp_tc_hpd_enable_detection(encoder);
845}
846
847static void icp_hpd_irq_setup(struct intel_display *display)
848{
849 u32 hotplug_irqs, enabled_irqs;
850
851 enabled_irqs = intel_hpd_enabled_irqs(display, hpd: display->hotplug.pch_hpd);
852 hotplug_irqs = intel_hpd_hotplug_irqs(display, hpd: display->hotplug.pch_hpd);
853
854 /*
855 * We reduce the value to 250us to be able to detect SHPD when an external display
856 * is connected. This is also expected of us as stated in DP1.4a Table 3-4.
857 */
858 intel_de_write(display, SHPD_FILTER_CNT, SHPD_FILTER_CNT_250);
859
860 ibx_display_interrupt_update(display, interrupt_mask: hotplug_irqs, enabled_irq_mask: enabled_irqs);
861
862 icp_ddi_hpd_detection_setup(display);
863 icp_tc_hpd_detection_setup(display);
864}
865
866static u32 gen11_hotplug_mask(enum hpd_pin hpd_pin)
867{
868 switch (hpd_pin) {
869 case HPD_PORT_TC1:
870 case HPD_PORT_TC2:
871 case HPD_PORT_TC3:
872 case HPD_PORT_TC4:
873 case HPD_PORT_TC5:
874 case HPD_PORT_TC6:
875 return GEN11_HOTPLUG_CTL_ENABLE(hpd_pin);
876 default:
877 return 0;
878 }
879}
880
881static u32 gen11_hotplug_enables(struct intel_encoder *encoder)
882{
883 return gen11_hotplug_mask(hpd_pin: encoder->hpd_pin);
884}
885
886static void dg1_hpd_invert(struct intel_display *display)
887{
888 u32 val = (INVERT_DDIA_HPD |
889 INVERT_DDIB_HPD |
890 INVERT_DDIC_HPD |
891 INVERT_DDID_HPD);
892 intel_de_rmw(display, SOUTH_CHICKEN1, clear: 0, set: val);
893}
894
895static void dg1_hpd_enable_detection(struct intel_encoder *encoder)
896{
897 struct intel_display *display = to_intel_display(encoder);
898
899 dg1_hpd_invert(display);
900 icp_hpd_enable_detection(encoder);
901}
902
903static void dg1_hpd_irq_setup(struct intel_display *display)
904{
905 dg1_hpd_invert(display);
906 icp_hpd_irq_setup(display);
907}
908
909static void gen11_tc_hpd_detection_setup(struct intel_display *display)
910{
911 intel_de_rmw(display, GEN11_TC_HOTPLUG_CTL,
912 clear: intel_hpd_hotplug_mask(display, hotplug_mask: gen11_hotplug_mask),
913 set: intel_hpd_hotplug_enables(display, hotplug_enables: gen11_hotplug_enables));
914}
915
916static void gen11_tc_hpd_enable_detection(struct intel_encoder *encoder)
917{
918 struct intel_display *display = to_intel_display(encoder);
919
920 intel_de_rmw(display, GEN11_TC_HOTPLUG_CTL,
921 clear: gen11_hotplug_mask(hpd_pin: encoder->hpd_pin),
922 set: gen11_hotplug_enables(encoder));
923}
924
925static void gen11_tbt_hpd_detection_setup(struct intel_display *display)
926{
927 intel_de_rmw(display, GEN11_TBT_HOTPLUG_CTL,
928 clear: intel_hpd_hotplug_mask(display, hotplug_mask: gen11_hotplug_mask),
929 set: intel_hpd_hotplug_enables(display, hotplug_enables: gen11_hotplug_enables));
930}
931
932static void gen11_tbt_hpd_enable_detection(struct intel_encoder *encoder)
933{
934 struct intel_display *display = to_intel_display(encoder);
935
936 intel_de_rmw(display, GEN11_TBT_HOTPLUG_CTL,
937 clear: gen11_hotplug_mask(hpd_pin: encoder->hpd_pin),
938 set: gen11_hotplug_enables(encoder));
939}
940
941static void gen11_hpd_enable_detection(struct intel_encoder *encoder)
942{
943 struct intel_display *display = to_intel_display(encoder);
944
945 gen11_tc_hpd_enable_detection(encoder);
946 gen11_tbt_hpd_enable_detection(encoder);
947
948 if (INTEL_PCH_TYPE(display) >= PCH_ICP)
949 icp_hpd_enable_detection(encoder);
950}
951
952static void gen11_hpd_irq_setup(struct intel_display *display)
953{
954 u32 hotplug_irqs, enabled_irqs;
955
956 enabled_irqs = intel_hpd_enabled_irqs(display, hpd: display->hotplug.hpd);
957 hotplug_irqs = intel_hpd_hotplug_irqs(display, hpd: display->hotplug.hpd);
958
959 intel_de_rmw(display, GEN11_DE_HPD_IMR, clear: hotplug_irqs,
960 set: ~enabled_irqs & hotplug_irqs);
961 intel_de_posting_read(display, GEN11_DE_HPD_IMR);
962
963 gen11_tc_hpd_detection_setup(display);
964 gen11_tbt_hpd_detection_setup(display);
965
966 if (INTEL_PCH_TYPE(display) >= PCH_ICP)
967 icp_hpd_irq_setup(display);
968}
969
970static u32 mtp_ddi_hotplug_mask(enum hpd_pin hpd_pin)
971{
972 switch (hpd_pin) {
973 case HPD_PORT_A:
974 case HPD_PORT_B:
975 return SHOTPLUG_CTL_DDI_HPD_ENABLE(hpd_pin);
976 default:
977 return 0;
978 }
979}
980
981static u32 mtp_ddi_hotplug_enables(struct intel_encoder *encoder)
982{
983 return mtp_ddi_hotplug_mask(hpd_pin: encoder->hpd_pin);
984}
985
986static u32 mtp_tc_hotplug_mask(enum hpd_pin hpd_pin)
987{
988 switch (hpd_pin) {
989 case HPD_PORT_TC1:
990 case HPD_PORT_TC2:
991 case HPD_PORT_TC3:
992 case HPD_PORT_TC4:
993 return ICP_TC_HPD_ENABLE(hpd_pin);
994 default:
995 return 0;
996 }
997}
998
999static u32 mtp_tc_hotplug_enables(struct intel_encoder *encoder)
1000{
1001 return mtp_tc_hotplug_mask(hpd_pin: encoder->hpd_pin);
1002}
1003
1004static void mtp_ddi_hpd_detection_setup(struct intel_display *display)
1005{
1006 intel_de_rmw(display, SHOTPLUG_CTL_DDI,
1007 clear: intel_hpd_hotplug_mask(display, hotplug_mask: mtp_ddi_hotplug_mask),
1008 set: intel_hpd_hotplug_enables(display, hotplug_enables: mtp_ddi_hotplug_enables));
1009}
1010
1011static void mtp_ddi_hpd_enable_detection(struct intel_encoder *encoder)
1012{
1013 struct intel_display *display = to_intel_display(encoder);
1014
1015 intel_de_rmw(display, SHOTPLUG_CTL_DDI,
1016 clear: mtp_ddi_hotplug_mask(hpd_pin: encoder->hpd_pin),
1017 set: mtp_ddi_hotplug_enables(encoder));
1018}
1019
1020static void mtp_tc_hpd_detection_setup(struct intel_display *display)
1021{
1022 intel_de_rmw(display, SHOTPLUG_CTL_TC,
1023 clear: intel_hpd_hotplug_mask(display, hotplug_mask: mtp_tc_hotplug_mask),
1024 set: intel_hpd_hotplug_enables(display, hotplug_enables: mtp_tc_hotplug_enables));
1025}
1026
1027static void mtp_tc_hpd_enable_detection(struct intel_encoder *encoder)
1028{
1029 struct intel_display *display = to_intel_display(encoder);
1030
1031 intel_de_rmw(display, SHOTPLUG_CTL_TC,
1032 clear: mtp_tc_hotplug_mask(hpd_pin: encoder->hpd_pin),
1033 set: mtp_tc_hotplug_enables(encoder));
1034}
1035
1036static void mtp_hpd_invert(struct intel_display *display)
1037{
1038 u32 val = (INVERT_DDIA_HPD |
1039 INVERT_DDIB_HPD |
1040 INVERT_DDIC_HPD |
1041 INVERT_TC1_HPD |
1042 INVERT_TC2_HPD |
1043 INVERT_TC3_HPD |
1044 INVERT_TC4_HPD |
1045 INVERT_DDID_HPD_MTP |
1046 INVERT_DDIE_HPD);
1047 intel_de_rmw(display, SOUTH_CHICKEN1, clear: 0, set: val);
1048}
1049
1050static void mtp_hpd_enable_detection(struct intel_encoder *encoder)
1051{
1052 struct intel_display *display = to_intel_display(encoder);
1053
1054 mtp_hpd_invert(display);
1055 mtp_ddi_hpd_enable_detection(encoder);
1056 mtp_tc_hpd_enable_detection(encoder);
1057}
1058
1059static void mtp_hpd_irq_setup(struct intel_display *display)
1060{
1061 u32 hotplug_irqs, enabled_irqs;
1062
1063 enabled_irqs = intel_hpd_enabled_irqs(display, hpd: display->hotplug.pch_hpd);
1064 hotplug_irqs = intel_hpd_hotplug_irqs(display, hpd: display->hotplug.pch_hpd);
1065
1066 /*
1067 * Use 250us here to align with the DP1.4a(Table 3-4) spec as to what the
1068 * SHPD_FILTER_CNT value should be.
1069 */
1070 intel_de_write(display, SHPD_FILTER_CNT, SHPD_FILTER_CNT_250);
1071
1072 mtp_hpd_invert(display);
1073 ibx_display_interrupt_update(display, interrupt_mask: hotplug_irqs, enabled_irq_mask: enabled_irqs);
1074
1075 mtp_ddi_hpd_detection_setup(display);
1076 mtp_tc_hpd_detection_setup(display);
1077}
1078
1079static void xe2lpd_sde_hpd_irq_setup(struct intel_display *display)
1080{
1081 u32 hotplug_irqs, enabled_irqs;
1082
1083 enabled_irqs = intel_hpd_enabled_irqs(display, hpd: display->hotplug.pch_hpd);
1084 hotplug_irqs = intel_hpd_hotplug_irqs(display, hpd: display->hotplug.pch_hpd);
1085
1086 ibx_display_interrupt_update(display, interrupt_mask: hotplug_irqs, enabled_irq_mask: enabled_irqs);
1087
1088 mtp_ddi_hpd_detection_setup(display);
1089 mtp_tc_hpd_detection_setup(display);
1090}
1091
1092static bool is_xelpdp_pica_hpd_pin(enum hpd_pin hpd_pin)
1093{
1094 return hpd_pin >= HPD_PORT_TC1 && hpd_pin <= HPD_PORT_TC4;
1095}
1096
1097static void _xelpdp_pica_hpd_detection_setup(struct intel_display *display,
1098 enum hpd_pin hpd_pin, bool enable)
1099{
1100 u32 mask = XELPDP_TBT_HOTPLUG_ENABLE |
1101 XELPDP_DP_ALT_HOTPLUG_ENABLE;
1102
1103 if (!is_xelpdp_pica_hpd_pin(hpd_pin))
1104 return;
1105
1106 intel_de_rmw(display, XELPDP_PORT_HOTPLUG_CTL(hpd_pin),
1107 clear: mask, set: enable ? mask : 0);
1108}
1109
1110static void xelpdp_pica_hpd_enable_detection(struct intel_encoder *encoder)
1111{
1112 struct intel_display *display = to_intel_display(encoder);
1113
1114 _xelpdp_pica_hpd_detection_setup(display, hpd_pin: encoder->hpd_pin, enable: true);
1115}
1116
1117static void xelpdp_pica_hpd_detection_setup(struct intel_display *display)
1118{
1119 struct intel_encoder *encoder;
1120 u32 available_pins = 0;
1121 enum hpd_pin pin;
1122
1123 BUILD_BUG_ON(BITS_PER_TYPE(available_pins) < HPD_NUM_PINS);
1124
1125 for_each_intel_encoder(display->drm, encoder)
1126 available_pins |= BIT(encoder->hpd_pin);
1127
1128 for_each_hpd_pin(pin)
1129 _xelpdp_pica_hpd_detection_setup(display, hpd_pin: pin, enable: available_pins & BIT(pin));
1130}
1131
1132static void xelpdp_hpd_enable_detection(struct intel_encoder *encoder)
1133{
1134 xelpdp_pica_hpd_enable_detection(encoder);
1135 mtp_hpd_enable_detection(encoder);
1136}
1137
1138static void xelpdp_hpd_irq_setup(struct intel_display *display)
1139{
1140 u32 hotplug_irqs, enabled_irqs;
1141
1142 enabled_irqs = intel_hpd_enabled_irqs(display, hpd: display->hotplug.hpd);
1143 hotplug_irqs = intel_hpd_hotplug_irqs(display, hpd: display->hotplug.hpd);
1144
1145 intel_de_rmw(display, PICAINTERRUPT_IMR, clear: hotplug_irqs,
1146 set: ~enabled_irqs & hotplug_irqs);
1147 intel_de_posting_read(display, PICAINTERRUPT_IMR);
1148
1149 xelpdp_pica_hpd_detection_setup(display);
1150
1151 if (INTEL_PCH_TYPE(display) >= PCH_LNL)
1152 xe2lpd_sde_hpd_irq_setup(display);
1153 else if (INTEL_PCH_TYPE(display) >= PCH_MTL)
1154 mtp_hpd_irq_setup(display);
1155}
1156
1157static u32 spt_hotplug_mask(enum hpd_pin hpd_pin)
1158{
1159 switch (hpd_pin) {
1160 case HPD_PORT_A:
1161 return PORTA_HOTPLUG_ENABLE;
1162 case HPD_PORT_B:
1163 return PORTB_HOTPLUG_ENABLE;
1164 case HPD_PORT_C:
1165 return PORTC_HOTPLUG_ENABLE;
1166 case HPD_PORT_D:
1167 return PORTD_HOTPLUG_ENABLE;
1168 default:
1169 return 0;
1170 }
1171}
1172
1173static u32 spt_hotplug_enables(struct intel_encoder *encoder)
1174{
1175 return spt_hotplug_mask(hpd_pin: encoder->hpd_pin);
1176}
1177
1178static u32 spt_hotplug2_mask(enum hpd_pin hpd_pin)
1179{
1180 switch (hpd_pin) {
1181 case HPD_PORT_E:
1182 return PORTE_HOTPLUG_ENABLE;
1183 default:
1184 return 0;
1185 }
1186}
1187
1188static u32 spt_hotplug2_enables(struct intel_encoder *encoder)
1189{
1190 return spt_hotplug2_mask(hpd_pin: encoder->hpd_pin);
1191}
1192
1193static void spt_hpd_detection_setup(struct intel_display *display)
1194{
1195 /* Display WA #1179 WaHardHangonHotPlug: cnp */
1196 if (HAS_PCH_CNP(display)) {
1197 intel_de_rmw(display, SOUTH_CHICKEN1, CHASSIS_CLK_REQ_DURATION_MASK,
1198 CHASSIS_CLK_REQ_DURATION(0xf));
1199 }
1200
1201 /* Enable digital hotplug on the PCH */
1202 intel_de_rmw(display, PCH_PORT_HOTPLUG,
1203 clear: intel_hpd_hotplug_mask(display, hotplug_mask: spt_hotplug_mask),
1204 set: intel_hpd_hotplug_enables(display, hotplug_enables: spt_hotplug_enables));
1205
1206 intel_de_rmw(display, PCH_PORT_HOTPLUG2,
1207 clear: intel_hpd_hotplug_mask(display, hotplug_mask: spt_hotplug2_mask),
1208 set: intel_hpd_hotplug_enables(display, hotplug_enables: spt_hotplug2_enables));
1209}
1210
1211static void spt_hpd_enable_detection(struct intel_encoder *encoder)
1212{
1213 struct intel_display *display = to_intel_display(encoder);
1214
1215 /* Display WA #1179 WaHardHangonHotPlug: cnp */
1216 if (HAS_PCH_CNP(display)) {
1217 intel_de_rmw(display, SOUTH_CHICKEN1,
1218 CHASSIS_CLK_REQ_DURATION_MASK,
1219 CHASSIS_CLK_REQ_DURATION(0xf));
1220 }
1221
1222 intel_de_rmw(display, PCH_PORT_HOTPLUG,
1223 clear: spt_hotplug_mask(hpd_pin: encoder->hpd_pin),
1224 set: spt_hotplug_enables(encoder));
1225
1226 intel_de_rmw(display, PCH_PORT_HOTPLUG2,
1227 clear: spt_hotplug2_mask(hpd_pin: encoder->hpd_pin),
1228 set: spt_hotplug2_enables(encoder));
1229}
1230
1231static void spt_hpd_irq_setup(struct intel_display *display)
1232{
1233 u32 hotplug_irqs, enabled_irqs;
1234
1235 if (INTEL_PCH_TYPE(display) >= PCH_CNP)
1236 intel_de_write(display, SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ);
1237
1238 enabled_irqs = intel_hpd_enabled_irqs(display, hpd: display->hotplug.pch_hpd);
1239 hotplug_irqs = intel_hpd_hotplug_irqs(display, hpd: display->hotplug.pch_hpd);
1240
1241 ibx_display_interrupt_update(display, interrupt_mask: hotplug_irqs, enabled_irq_mask: enabled_irqs);
1242
1243 spt_hpd_detection_setup(display);
1244}
1245
1246static u32 ilk_hotplug_mask(enum hpd_pin hpd_pin)
1247{
1248 switch (hpd_pin) {
1249 case HPD_PORT_A:
1250 return DIGITAL_PORTA_HOTPLUG_ENABLE |
1251 DIGITAL_PORTA_PULSE_DURATION_MASK;
1252 default:
1253 return 0;
1254 }
1255}
1256
1257static u32 ilk_hotplug_enables(struct intel_encoder *encoder)
1258{
1259 switch (encoder->hpd_pin) {
1260 case HPD_PORT_A:
1261 return DIGITAL_PORTA_HOTPLUG_ENABLE |
1262 DIGITAL_PORTA_PULSE_DURATION_2ms;
1263 default:
1264 return 0;
1265 }
1266}
1267
1268static void ilk_hpd_detection_setup(struct intel_display *display)
1269{
1270 /*
1271 * Enable digital hotplug on the CPU, and configure the DP short pulse
1272 * duration to 2ms (which is the minimum in the Display Port spec)
1273 * The pulse duration bits are reserved on HSW+.
1274 */
1275 intel_de_rmw(display, DIGITAL_PORT_HOTPLUG_CNTRL,
1276 clear: intel_hpd_hotplug_mask(display, hotplug_mask: ilk_hotplug_mask),
1277 set: intel_hpd_hotplug_enables(display, hotplug_enables: ilk_hotplug_enables));
1278}
1279
1280static void ilk_hpd_enable_detection(struct intel_encoder *encoder)
1281{
1282 struct intel_display *display = to_intel_display(encoder);
1283
1284 intel_de_rmw(display, DIGITAL_PORT_HOTPLUG_CNTRL,
1285 clear: ilk_hotplug_mask(hpd_pin: encoder->hpd_pin),
1286 set: ilk_hotplug_enables(encoder));
1287
1288 ibx_hpd_enable_detection(encoder);
1289}
1290
1291static void ilk_hpd_irq_setup(struct intel_display *display)
1292{
1293 u32 hotplug_irqs, enabled_irqs;
1294
1295 enabled_irqs = intel_hpd_enabled_irqs(display, hpd: display->hotplug.hpd);
1296 hotplug_irqs = intel_hpd_hotplug_irqs(display, hpd: display->hotplug.hpd);
1297
1298 if (DISPLAY_VER(display) >= 8)
1299 bdw_update_port_irq(display, interrupt_mask: hotplug_irqs, enabled_irq_mask: enabled_irqs);
1300 else
1301 ilk_update_display_irq(display, interrupt_mask: hotplug_irqs, enabled_irq_mask: enabled_irqs);
1302
1303 ilk_hpd_detection_setup(display);
1304
1305 ibx_hpd_irq_setup(display);
1306}
1307
1308static u32 bxt_hotplug_mask(enum hpd_pin hpd_pin)
1309{
1310 switch (hpd_pin) {
1311 case HPD_PORT_A:
1312 return PORTA_HOTPLUG_ENABLE | BXT_DDIA_HPD_INVERT;
1313 case HPD_PORT_B:
1314 return PORTB_HOTPLUG_ENABLE | BXT_DDIB_HPD_INVERT;
1315 case HPD_PORT_C:
1316 return PORTC_HOTPLUG_ENABLE | BXT_DDIC_HPD_INVERT;
1317 default:
1318 return 0;
1319 }
1320}
1321
1322static u32 bxt_hotplug_enables(struct intel_encoder *encoder)
1323{
1324 u32 hotplug;
1325
1326 switch (encoder->hpd_pin) {
1327 case HPD_PORT_A:
1328 hotplug = PORTA_HOTPLUG_ENABLE;
1329 if (intel_bios_encoder_hpd_invert(devdata: encoder->devdata))
1330 hotplug |= BXT_DDIA_HPD_INVERT;
1331 return hotplug;
1332 case HPD_PORT_B:
1333 hotplug = PORTB_HOTPLUG_ENABLE;
1334 if (intel_bios_encoder_hpd_invert(devdata: encoder->devdata))
1335 hotplug |= BXT_DDIB_HPD_INVERT;
1336 return hotplug;
1337 case HPD_PORT_C:
1338 hotplug = PORTC_HOTPLUG_ENABLE;
1339 if (intel_bios_encoder_hpd_invert(devdata: encoder->devdata))
1340 hotplug |= BXT_DDIC_HPD_INVERT;
1341 return hotplug;
1342 default:
1343 return 0;
1344 }
1345}
1346
1347static void bxt_hpd_detection_setup(struct intel_display *display)
1348{
1349 intel_de_rmw(display, PCH_PORT_HOTPLUG,
1350 clear: intel_hpd_hotplug_mask(display, hotplug_mask: bxt_hotplug_mask),
1351 set: intel_hpd_hotplug_enables(display, hotplug_enables: bxt_hotplug_enables));
1352}
1353
1354static void bxt_hpd_enable_detection(struct intel_encoder *encoder)
1355{
1356 struct intel_display *display = to_intel_display(encoder);
1357
1358 intel_de_rmw(display, PCH_PORT_HOTPLUG,
1359 clear: bxt_hotplug_mask(hpd_pin: encoder->hpd_pin),
1360 set: bxt_hotplug_enables(encoder));
1361}
1362
1363static void bxt_hpd_irq_setup(struct intel_display *display)
1364{
1365 u32 hotplug_irqs, enabled_irqs;
1366
1367 enabled_irqs = intel_hpd_enabled_irqs(display, hpd: display->hotplug.hpd);
1368 hotplug_irqs = intel_hpd_hotplug_irqs(display, hpd: display->hotplug.hpd);
1369
1370 bdw_update_port_irq(display, interrupt_mask: hotplug_irqs, enabled_irq_mask: enabled_irqs);
1371
1372 bxt_hpd_detection_setup(display);
1373}
1374
1375static void g45_hpd_peg_band_gap_wa(struct intel_display *display)
1376{
1377 /*
1378 * For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1379 * 0xd. Failure to do so will result in spurious interrupts being
1380 * generated on the port when a cable is not attached.
1381 */
1382 intel_de_rmw(display, PEG_BAND_GAP_DATA, clear: 0xf, set: 0xd);
1383}
1384
1385static void i915_hpd_enable_detection(struct intel_encoder *encoder)
1386{
1387 struct intel_display *display = to_intel_display(encoder);
1388 u32 hotplug_en = hpd_mask_i915[encoder->hpd_pin];
1389
1390 if (display->platform.g45)
1391 g45_hpd_peg_band_gap_wa(display);
1392
1393 /* HPD sense and interrupt enable are one and the same */
1394 i915_hotplug_interrupt_update(display, mask: hotplug_en, bits: hotplug_en);
1395}
1396
1397static void i915_hpd_irq_setup(struct intel_display *display)
1398{
1399 u32 hotplug_en;
1400
1401 lockdep_assert_held(&display->irq.lock);
1402
1403 /*
1404 * Note HDMI and DP share hotplug bits. Enable bits are the same for all
1405 * generations.
1406 */
1407 hotplug_en = intel_hpd_enabled_irqs(display, hpd: hpd_mask_i915);
1408 /*
1409 * Programming the CRT detection parameters tends to generate a spurious
1410 * hotplug event about three seconds later. So just do it once.
1411 */
1412 if (display->platform.g4x)
1413 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
1414 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
1415
1416 if (display->platform.g45)
1417 g45_hpd_peg_band_gap_wa(display);
1418
1419 /* Ignore TV since it's buggy */
1420 i915_hotplug_interrupt_update_locked(display,
1421 HOTPLUG_INT_EN_MASK |
1422 CRT_HOTPLUG_VOLTAGE_COMPARE_MASK |
1423 CRT_HOTPLUG_ACTIVATION_PERIOD_64,
1424 bits: hotplug_en);
1425}
1426
1427struct intel_hotplug_funcs {
1428 /* Enable HPD sense and interrupts for all present encoders */
1429 void (*hpd_irq_setup)(struct intel_display *display);
1430 /* Enable HPD sense for a single encoder */
1431 void (*hpd_enable_detection)(struct intel_encoder *encoder);
1432};
1433
1434#define HPD_FUNCS(platform) \
1435static const struct intel_hotplug_funcs platform##_hpd_funcs = { \
1436 .hpd_irq_setup = platform##_hpd_irq_setup, \
1437 .hpd_enable_detection = platform##_hpd_enable_detection, \
1438}
1439
1440HPD_FUNCS(i915);
1441HPD_FUNCS(xelpdp);
1442HPD_FUNCS(dg1);
1443HPD_FUNCS(gen11);
1444HPD_FUNCS(bxt);
1445HPD_FUNCS(icp);
1446HPD_FUNCS(spt);
1447HPD_FUNCS(ilk);
1448#undef HPD_FUNCS
1449
1450void intel_hpd_enable_detection(struct intel_encoder *encoder)
1451{
1452 struct intel_display *display = to_intel_display(encoder);
1453
1454 if (display->funcs.hotplug)
1455 display->funcs.hotplug->hpd_enable_detection(encoder);
1456}
1457
1458void intel_hpd_irq_setup(struct intel_display *display)
1459{
1460 if ((display->platform.valleyview || display->platform.cherryview) &&
1461 !display->irq.vlv_display_irqs_enabled)
1462 return;
1463
1464 if (display->funcs.hotplug)
1465 display->funcs.hotplug->hpd_irq_setup(display);
1466}
1467
1468void intel_hotplug_irq_init(struct intel_display *display)
1469{
1470 intel_hpd_init_pins(display);
1471
1472 intel_hpd_init_early(display);
1473
1474 if (HAS_GMCH(display)) {
1475 if (HAS_HOTPLUG(display))
1476 display->funcs.hotplug = &i915_hpd_funcs;
1477 } else {
1478 if (HAS_PCH_DG2(display))
1479 display->funcs.hotplug = &icp_hpd_funcs;
1480 else if (HAS_PCH_DG1(display))
1481 display->funcs.hotplug = &dg1_hpd_funcs;
1482 else if (DISPLAY_VER(display) >= 14)
1483 display->funcs.hotplug = &xelpdp_hpd_funcs;
1484 else if (DISPLAY_VER(display) >= 11)
1485 display->funcs.hotplug = &gen11_hpd_funcs;
1486 else if (display->platform.geminilake || display->platform.broxton)
1487 display->funcs.hotplug = &bxt_hpd_funcs;
1488 else if (INTEL_PCH_TYPE(display) >= PCH_ICP)
1489 display->funcs.hotplug = &icp_hpd_funcs;
1490 else if (INTEL_PCH_TYPE(display) >= PCH_SPT)
1491 display->funcs.hotplug = &spt_hpd_funcs;
1492 else
1493 display->funcs.hotplug = &ilk_hpd_funcs;
1494 }
1495}
1496

source code of linux/drivers/gpu/drm/i915/display/intel_hotplug_irq.c