| 1 | /* SPDX-License-Identifier: MIT */ |
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| 2 | /* |
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| 3 | * Copyright © 2023 Intel Corporation |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef __INTEL_DISPLAY_IRQ_H__ |
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| 7 | #define __INTEL_DISPLAY_IRQ_H__ |
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| 8 | |
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| 9 | #include <linux/types.h> |
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| 10 | |
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| 11 | #include "intel_display_limits.h" |
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| 12 | |
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| 13 | enum pipe; |
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| 14 | struct drm_crtc; |
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| 15 | struct drm_printer; |
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| 16 | struct intel_display; |
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| 17 | struct intel_display_irq_snapshot; |
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| 18 | |
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| 19 | void valleyview_enable_display_irqs(struct intel_display *display); |
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| 20 | void valleyview_disable_display_irqs(struct intel_display *display); |
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| 21 | |
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| 22 | void ilk_update_display_irq(struct intel_display *display, |
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| 23 | u32 interrupt_mask, u32 enabled_irq_mask); |
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| 24 | void ilk_enable_display_irq(struct intel_display *display, u32 bits); |
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| 25 | void ilk_disable_display_irq(struct intel_display *display, u32 bits); |
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| 26 | |
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| 27 | void bdw_update_port_irq(struct intel_display *display, u32 interrupt_mask, u32 enabled_irq_mask); |
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| 28 | void bdw_enable_pipe_irq(struct intel_display *display, enum pipe pipe, u32 bits); |
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| 29 | void bdw_disable_pipe_irq(struct intel_display *display, enum pipe pipe, u32 bits); |
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| 30 | |
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| 31 | void ibx_display_interrupt_update(struct intel_display *display, |
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| 32 | u32 interrupt_mask, u32 enabled_irq_mask); |
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| 33 | void ibx_enable_display_interrupt(struct intel_display *display, u32 bits); |
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| 34 | void ibx_disable_display_interrupt(struct intel_display *display, u32 bits); |
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| 35 | |
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| 36 | void gen8_irq_power_well_post_enable(struct intel_display *display, u8 pipe_mask); |
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| 37 | void gen8_irq_power_well_pre_disable(struct intel_display *display, u8 pipe_mask); |
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| 38 | |
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| 39 | int i8xx_enable_vblank(struct drm_crtc *crtc); |
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| 40 | int i915gm_enable_vblank(struct drm_crtc *crtc); |
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| 41 | int i965_enable_vblank(struct drm_crtc *crtc); |
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| 42 | int ilk_enable_vblank(struct drm_crtc *crtc); |
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| 43 | int bdw_enable_vblank(struct drm_crtc *crtc); |
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| 44 | void i8xx_disable_vblank(struct drm_crtc *crtc); |
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| 45 | void i915gm_disable_vblank(struct drm_crtc *crtc); |
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| 46 | void i965_disable_vblank(struct drm_crtc *crtc); |
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| 47 | void ilk_disable_vblank(struct drm_crtc *crtc); |
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| 48 | void bdw_disable_vblank(struct drm_crtc *crtc); |
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| 49 | |
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| 50 | void ilk_display_irq_master_disable(struct intel_display *display, u32 *de_ier, u32 *sde_ier); |
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| 51 | void ilk_display_irq_master_enable(struct intel_display *display, u32 de_ier, u32 sde_ier); |
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| 52 | bool ilk_display_irq_handler(struct intel_display *display); |
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| 53 | void gen8_de_irq_handler(struct intel_display *display, u32 master_ctl); |
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| 54 | void gen11_display_irq_handler(struct intel_display *display); |
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| 55 | |
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| 56 | u32 gen11_gu_misc_irq_ack(struct intel_display *display, const u32 master_ctl); |
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| 57 | void gen11_gu_misc_irq_handler(struct intel_display *display, const u32 iir); |
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| 58 | |
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| 59 | void i9xx_display_irq_reset(struct intel_display *display); |
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| 60 | void ilk_display_irq_reset(struct intel_display *display); |
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| 61 | void vlv_display_irq_reset(struct intel_display *display); |
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| 62 | void gen8_display_irq_reset(struct intel_display *display); |
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| 63 | void gen11_display_irq_reset(struct intel_display *display); |
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| 64 | |
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| 65 | u32 i9xx_display_irq_enable_mask(struct intel_display *display); |
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| 66 | void i915_display_irq_postinstall(struct intel_display *display); |
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| 67 | void i965_display_irq_postinstall(struct intel_display *display); |
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| 68 | void vlv_display_irq_postinstall(struct intel_display *display); |
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| 69 | void ilk_de_irq_postinstall(struct intel_display *display); |
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| 70 | void gen8_de_irq_postinstall(struct intel_display *display); |
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| 71 | void gen11_de_irq_postinstall(struct intel_display *display); |
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| 72 | void dg1_de_irq_postinstall(struct intel_display *display); |
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| 73 | |
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| 74 | u32 i915_pipestat_enable_mask(struct intel_display *display, enum pipe pipe); |
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| 75 | void i915_enable_pipestat(struct intel_display *display, enum pipe pipe, u32 status_mask); |
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| 76 | void i915_disable_pipestat(struct intel_display *display, enum pipe pipe, u32 status_mask); |
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| 77 | |
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| 78 | void i9xx_pipestat_irq_ack(struct intel_display *display, u32 iir, u32 pipe_stats[I915_MAX_PIPES]); |
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| 79 | |
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| 80 | void i915_pipestat_irq_handler(struct intel_display *display, u32 iir, u32 pipe_stats[I915_MAX_PIPES]); |
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| 81 | void i965_pipestat_irq_handler(struct intel_display *display, u32 iir, u32 pipe_stats[I915_MAX_PIPES]); |
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| 82 | void valleyview_pipestat_irq_handler(struct intel_display *display, u32 pipe_stats[I915_MAX_PIPES]); |
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| 83 | |
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| 84 | void vlv_display_error_irq_ack(struct intel_display *display, u32 *eir, u32 *dpinvgtt); |
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| 85 | void vlv_display_error_irq_handler(struct intel_display *display, u32 eir, u32 dpinvgtt); |
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| 86 | |
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| 87 | void intel_display_irq_init(struct intel_display *display); |
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| 88 | |
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| 89 | void i915gm_irq_cstate_wa(struct intel_display *display, bool enable); |
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| 90 | |
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| 91 | struct intel_display_irq_snapshot *intel_display_irq_snapshot_capture(struct intel_display *display); |
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| 92 | void intel_display_irq_snapshot_print(const struct intel_display_irq_snapshot *snapshot, struct drm_printer *p); |
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| 93 | |
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| 94 | #endif /* __INTEL_DISPLAY_IRQ_H__ */ |
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| 95 | |
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