| 1 | /* SPDX-License-Identifier: MIT */ |
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| 2 | /* |
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| 3 | * Copyright 2025 Intel Corporation. |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef __INTEL_PCH__ |
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| 7 | #define __INTEL_PCH__ |
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| 8 | |
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| 9 | struct intel_display; |
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| 10 | |
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| 11 | /* |
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| 12 | * Sorted by south display engine compatibility. |
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| 13 | * If the new PCH comes with a south display engine that is not |
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| 14 | * inherited from the latest item, please do not add it to the |
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| 15 | * end. Instead, add it right after its "parent" PCH. |
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| 16 | */ |
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| 17 | enum intel_pch { |
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| 18 | PCH_NOP = -1, /* PCH without south display */ |
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| 19 | PCH_NONE = 0, /* No PCH present */ |
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| 20 | PCH_IBX, /* Ibexpeak PCH */ |
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| 21 | PCH_CPT, /* Cougarpoint/Pantherpoint PCH */ |
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| 22 | PCH_LPT_H, /* Lynxpoint/Wildcatpoint H PCH */ |
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| 23 | PCH_LPT_LP, /* Lynxpoint/Wildcatpoint LP PCH */ |
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| 24 | PCH_SPT, /* Sunrisepoint/Kaby Lake PCH */ |
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| 25 | PCH_CNP, /* Cannon/Comet Lake PCH */ |
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| 26 | PCH_ICP, /* Ice Lake/Jasper Lake PCH */ |
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| 27 | PCH_TGP, /* Tiger Lake/Mule Creek Canyon PCH */ |
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| 28 | PCH_ADP, /* Alder Lake PCH */ |
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| 29 | |
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| 30 | /* Fake PCHs, functionality handled on the same PCI dev */ |
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| 31 | PCH_DG1 = 1024, |
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| 32 | PCH_DG2, |
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| 33 | PCH_MTL, |
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| 34 | PCH_LNL, |
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| 35 | }; |
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| 36 | |
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| 37 | #define INTEL_PCH_TYPE(_display) ((_display)->pch_type) |
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| 38 | #define HAS_PCH_DG2(display) (INTEL_PCH_TYPE(display) == PCH_DG2) |
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| 39 | #define HAS_PCH_ADP(display) (INTEL_PCH_TYPE(display) == PCH_ADP) |
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| 40 | #define HAS_PCH_DG1(display) (INTEL_PCH_TYPE(display) == PCH_DG1) |
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| 41 | #define HAS_PCH_TGP(display) (INTEL_PCH_TYPE(display) == PCH_TGP) |
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| 42 | #define HAS_PCH_ICP(display) (INTEL_PCH_TYPE(display) == PCH_ICP) |
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| 43 | #define HAS_PCH_CNP(display) (INTEL_PCH_TYPE(display) == PCH_CNP) |
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| 44 | #define HAS_PCH_SPT(display) (INTEL_PCH_TYPE(display) == PCH_SPT) |
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| 45 | #define HAS_PCH_LPT_H(display) (INTEL_PCH_TYPE(display) == PCH_LPT_H) |
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| 46 | #define HAS_PCH_LPT_LP(display) (INTEL_PCH_TYPE(display) == PCH_LPT_LP) |
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| 47 | #define HAS_PCH_LPT(display) (INTEL_PCH_TYPE(display) == PCH_LPT_H || \ |
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| 48 | INTEL_PCH_TYPE(display) == PCH_LPT_LP) |
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| 49 | #define HAS_PCH_CPT(display) (INTEL_PCH_TYPE(display) == PCH_CPT) |
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| 50 | #define HAS_PCH_IBX(display) (INTEL_PCH_TYPE(display) == PCH_IBX) |
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| 51 | #define HAS_PCH_NOP(display) (INTEL_PCH_TYPE(display) == PCH_NOP) |
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| 52 | #define HAS_PCH_SPLIT(display) (INTEL_PCH_TYPE(display) != PCH_NONE) |
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| 53 | |
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| 54 | void intel_pch_detect(struct intel_display *display); |
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| 55 | |
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| 56 | #endif /* __INTEL_PCH__ */ |
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| 57 | |
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