1	/*
2	* Copyright © 2008 Intel Corporation
3	*
4	* Permission is hereby granted, free of charge, to any person obtaining a
5	* copy of this software and associated documentation files (the "Software"),
6	* to deal in the Software without restriction, including without limitation
7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8	* and/or sell copies of the Software, and to permit persons to whom the
9	* Software is furnished to do so, subject to the following conditions:
10	*
11	* The above copyright notice and this permission notice (including the next
12	* paragraph) shall be included in all copies or substantial portions of the
13	* Software.
14	*
15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21	* IN THE SOFTWARE.
22	*
23	* Authors:
24	* Keith Packard <keithp@keithp.com>
25	*
26	*/
27
28	#include <linux/export.h>
29	#include <linux/i2c.h>
30	#include <linux/iopoll.h>
31	#include <linux/log2.h>
32	#include <linux/math.h>
33	#include <linux/notifier.h>
34	#include <linux/seq_buf.h>
35	#include <linux/slab.h>
36	#include <linux/sort.h>
37	#include <linux/string_helpers.h>
38	#include <linux/timekeeping.h>
39	#include <linux/types.h>
40	#include <asm/byteorder.h>
41
42	#include <drm/display/drm_dp_helper.h>
43	#include <drm/display/drm_dp_tunnel.h>
44	#include <drm/display/drm_dsc_helper.h>
45	#include <drm/display/drm_hdmi_helper.h>
46	#include <drm/drm_atomic_helper.h>
47	#include <drm/drm_crtc.h>
48	#include <drm/drm_edid.h>
49	#include <drm/drm_fixed.h>
50	#include <drm/drm_print.h>
51	#include <drm/drm_probe_helper.h>
52
53	#include "g4x_dp.h"
54	#include "intel_alpm.h"
55	#include "intel_atomic.h"
56	#include "intel_audio.h"
57	#include "intel_backlight.h"
58	#include "intel_combo_phy_regs.h"
59	#include "intel_connector.h"
60	#include "intel_crtc.h"
61	#include "intel_crtc_state_dump.h"
62	#include "intel_cx0_phy.h"
63	#include "intel_ddi.h"
64	#include "intel_de.h"
65	#include "intel_display_driver.h"
66	#include "intel_display_jiffies.h"
67	#include "intel_display_utils.h"
68	#include "intel_display_regs.h"
69	#include "intel_display_rpm.h"
70	#include "intel_display_types.h"
71	#include "intel_dp.h"
72	#include "intel_dp_aux.h"
73	#include "intel_dp_hdcp.h"
74	#include "intel_dp_link_training.h"
75	#include "intel_dp_mst.h"
76	#include "intel_dp_test.h"
77	#include "intel_dp_tunnel.h"
78	#include "intel_dpio_phy.h"
79	#include "intel_dpll.h"
80	#include "intel_drrs.h"
81	#include "intel_encoder.h"
82	#include "intel_fifo_underrun.h"
83	#include "intel_hdcp.h"
84	#include "intel_hdmi.h"
85	#include "intel_hotplug.h"
86	#include "intel_hotplug_irq.h"
87	#include "intel_lspcon.h"
88	#include "intel_lvds.h"
89	#include "intel_modeset_lock.h"
90	#include "intel_panel.h"
91	#include "intel_pch_display.h"
92	#include "intel_pfit.h"
93	#include "intel_pps.h"
94	#include "intel_psr.h"
95	#include "intel_quirks.h"
96	#include "intel_tc.h"
97	#include "intel_vblank.h"
98	#include "intel_vdsc.h"
99	#include "intel_vrr.h"
100
101	/* Max DSC line buffer depth supported by HW. */
102	#define INTEL_DP_DSC_MAX_LINE_BUF_DEPTH 13
103
104	/* DP DSC FEC Overhead factor in ppm = 1/(0.972261) = 1.028530 */
105	#define DP_DSC_FEC_OVERHEAD_FACTOR 1028530
106
107	/* Constants for DP DSC configurations */
108	static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
109
110	/*
111	* With Single pipe configuration, HW is capable of supporting maximum of:
112	* 2 slices per line for ICL, BMG
113	* 4 slices per line for other platforms.
114	* For now consider a max of 2 slices per line, which works for all platforms.
115	* With this we can have max of 4 DSC Slices per pipe.
116	*
117	* For higher resolutions where 12 slice support is required with
118	* ultrajoiner, only then each pipe can support 3 slices.
119	*
120	* #TODO Split this better to use 4 slices/dsc engine where supported.
121	*/
122	static const u8 valid_dsc_slicecount[] = {1, 2, 3, 4};
123
124	/**
125	* intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
126	* @intel_dp: DP struct
127	*
128	* If a CPU or PCH DP output is attached to an eDP panel, this function
129	* will return true, and false otherwise.
130	*
131	* This function is not safe to use prior to encoder type being set.
132	*/
133	bool intel_dp_is_edp(struct intel_dp *intel_dp)
134	{
135	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
136
137	return dig_port->base.type == INTEL_OUTPUT_EDP;
138	}
139
140	static void intel_dp_unset_edid(struct intel_dp *intel_dp);
141
142	/* Is link rate UHBR and thus 128b/132b? */
143	bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state)
144	{
145	return drm_dp_is_uhbr_rate(link_rate: crtc_state->port_clock);
146	}
147
148	/**
149	* intel_dp_link_symbol_size - get the link symbol size for a given link rate
150	* @rate: link rate in 10kbit/s units
151	*
152	* Returns the link symbol size in bits/symbol units depending on the link
153	* rate -> channel coding.
154	*/
155	int intel_dp_link_symbol_size(int rate)
156	{
157	return drm_dp_is_uhbr_rate(link_rate: rate) ? 32 : 10;
158	}
159
160	/**
161	* intel_dp_link_symbol_clock - convert link rate to link symbol clock
162	* @rate: link rate in 10kbit/s units
163	*
164	* Returns the link symbol clock frequency in kHz units depending on the
165	* link rate and channel coding.
166	*/
167	int intel_dp_link_symbol_clock(int rate)
168	{
169	return DIV_ROUND_CLOSEST(rate * 10, intel_dp_link_symbol_size(rate));
170	}
171
172	static int max_dprx_rate(struct intel_dp *intel_dp)
173	{
174	struct intel_display *display = to_intel_display(intel_dp);
175	int max_rate;
176
177	if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp))
178	max_rate = drm_dp_tunnel_max_dprx_rate(tunnel: intel_dp->tunnel);
179	else
180	max_rate = drm_dp_bw_code_to_link_rate(link_bw: intel_dp->dpcd[DP_MAX_LINK_RATE]);
181
182	/*
183	* Some platforms + eDP panels may not reliably support HBR3
184	* due to signal integrity limitations, despite advertising it.
185	* Cap the link rate to HBR2 to avoid unstable configurations for the
186	* known machines.
187	*/
188	if (intel_dp_is_edp(intel_dp) && intel_has_quirk(display, quirk: QUIRK_EDP_LIMIT_RATE_HBR2))
189	max_rate = min(max_rate, 540000);
190
191	return max_rate;
192	}
193
194	static int max_dprx_lane_count(struct intel_dp *intel_dp)
195	{
196	if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp))
197	return drm_dp_tunnel_max_dprx_lane_count(tunnel: intel_dp->tunnel);
198
199	return drm_dp_max_lane_count(dpcd: intel_dp->dpcd);
200	}
201
202	static void intel_dp_set_default_sink_rates(struct intel_dp *intel_dp)
203	{
204	intel_dp->sink_rates[0] = 162000;
205	intel_dp->num_sink_rates = 1;
206	}
207
208	/* update sink rates from dpcd */
209	static void intel_dp_set_dpcd_sink_rates(struct intel_dp *intel_dp)
210	{
211	static const int dp_rates[] = {
212	162000, 270000, 540000, 810000
213	};
214	int i, max_rate;
215	int max_lttpr_rate;
216
217	if (drm_dp_has_quirk(desc: &intel_dp->desc, quirk: DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) {
218	/* Needed, e.g., for Apple MBP 2017, 15 inch eDP Retina panel */
219	static const int quirk_rates[] = { 162000, 270000, 324000 };
220
221	memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates));
222	intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates);
223
224	return;
225	}
226
227	/*
228	* Sink rates for 8b/10b.
229	*/
230	max_rate = max_dprx_rate(intel_dp);
231	max_lttpr_rate = drm_dp_lttpr_max_link_rate(caps: intel_dp->lttpr_common_caps);
232	if (max_lttpr_rate)
233	max_rate = min(max_rate, max_lttpr_rate);
234
235	for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
236	if (dp_rates[i] > max_rate)
237	break;
238	intel_dp->sink_rates[i] = dp_rates[i];
239	}
240
241	/*
242	* Sink rates for 128b/132b. If set, sink should support all 8b/10b
243	* rates and 10 Gbps.
244	*/
245	if (drm_dp_128b132b_supported(dpcd: intel_dp->dpcd)) {
246	u8 uhbr_rates = 0;
247
248	BUILD_BUG_ON(ARRAY_SIZE(intel_dp->sink_rates) < ARRAY_SIZE(dp_rates) + 3);
249
250	drm_dp_dpcd_readb(aux: &intel_dp->aux,
251	DP_128B132B_SUPPORTED_LINK_RATES, valuep: &uhbr_rates);
252
253	if (drm_dp_lttpr_count(cap: intel_dp->lttpr_common_caps)) {
254	/* We have a repeater */
255	if (intel_dp->lttpr_common_caps[0] >= 0x20 &&
256	intel_dp->lttpr_common_caps[DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER -
257	DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] &
258	DP_PHY_REPEATER_128B132B_SUPPORTED) {
259	/* Repeater supports 128b/132b, valid UHBR rates */
260	uhbr_rates &= intel_dp->lttpr_common_caps[DP_PHY_REPEATER_128B132B_RATES -
261	DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
262	} else {
263	/* Does not support 128b/132b */
264	uhbr_rates = 0;
265	}
266	}
267
268	if (uhbr_rates & DP_UHBR10)
269	intel_dp->sink_rates[i++] = 1000000;
270	if (uhbr_rates & DP_UHBR13_5)
271	intel_dp->sink_rates[i++] = 1350000;
272	if (uhbr_rates & DP_UHBR20)
273	intel_dp->sink_rates[i++] = 2000000;
274	}
275
276	intel_dp->num_sink_rates = i;
277	}
278
279	static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
280	{
281	struct intel_display *display = to_intel_display(intel_dp);
282	struct intel_connector *connector = intel_dp->attached_connector;
283	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
284	struct intel_encoder *encoder = &intel_dig_port->base;
285
286	intel_dp_set_dpcd_sink_rates(intel_dp);
287
288	if (intel_dp->num_sink_rates)
289	return;
290
291	drm_err(display->drm,
292	"[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD with no link rates, using defaults\n",
293	connector->base.base.id, connector->base.name,
294	encoder->base.base.id, encoder->base.name);
295
296	intel_dp_set_default_sink_rates(intel_dp);
297	}
298
299	static void intel_dp_set_default_max_sink_lane_count(struct intel_dp *intel_dp)
300	{
301	intel_dp->max_sink_lane_count = 1;
302	}
303
304	static void intel_dp_set_max_sink_lane_count(struct intel_dp *intel_dp)
305	{
306	struct intel_display *display = to_intel_display(intel_dp);
307	struct intel_connector *connector = intel_dp->attached_connector;
308	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
309	struct intel_encoder *encoder = &intel_dig_port->base;
310
311	intel_dp->max_sink_lane_count = max_dprx_lane_count(intel_dp);
312
313	switch (intel_dp->max_sink_lane_count) {
314	case 1:
315	case 2:
316	case 4:
317	return;
318	}
319
320	drm_err(display->drm,
321	"[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD max lane count (%d), using default\n",
322	connector->base.base.id, connector->base.name,
323	encoder->base.base.id, encoder->base.name,
324	intel_dp->max_sink_lane_count);
325
326	intel_dp_set_default_max_sink_lane_count(intel_dp);
327	}
328
329	/* Get length of rates array potentially limited by max_rate. */
330	static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
331	{
332	int i;
333
334	/* Limit results by potentially reduced max rate */
335	for (i = 0; i < len; i++) {
336	if (rates[len - i - 1] <= max_rate)
337	return len - i;
338	}
339
340	return 0;
341	}
342
343	/* Get length of common rates array potentially limited by max_rate. */
344	static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
345	int max_rate)
346	{
347	return intel_dp_rate_limit_len(rates: intel_dp->common_rates,
348	len: intel_dp->num_common_rates, max_rate);
349	}
350
351	int intel_dp_common_rate(struct intel_dp *intel_dp, int index)
352	{
353	struct intel_display *display = to_intel_display(intel_dp);
354
355	if (drm_WARN_ON(display->drm,
356	index < 0 || index >= intel_dp->num_common_rates))
357	return 162000;
358
359	return intel_dp->common_rates[index];
360	}
361
362	/* Theoretical max between source and sink */
363	int intel_dp_max_common_rate(struct intel_dp *intel_dp)
364	{
365	return intel_dp_common_rate(intel_dp, index: intel_dp->num_common_rates - 1);
366	}
367
368	int intel_dp_max_source_lane_count(struct intel_digital_port *dig_port)
369	{
370	int vbt_max_lanes = intel_bios_dp_max_lane_count(devdata: dig_port->base.devdata);
371	int max_lanes = dig_port->max_lanes;
372
373	if (vbt_max_lanes)
374	max_lanes = min(max_lanes, vbt_max_lanes);
375
376	return max_lanes;
377	}
378
379	/* Theoretical max between source and sink */
380	int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
381	{
382	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
383	int source_max = intel_dp_max_source_lane_count(dig_port);
384	int sink_max = intel_dp->max_sink_lane_count;
385	int lane_max = intel_tc_port_max_lane_count(dig_port);
386	int lttpr_max = drm_dp_lttpr_max_lane_count(caps: intel_dp->lttpr_common_caps);
387
388	if (lttpr_max)
389	sink_max = min(sink_max, lttpr_max);
390
391	return min3(source_max, sink_max, lane_max);
392	}
393
394	static int forced_lane_count(struct intel_dp *intel_dp)
395	{
396	return clamp(intel_dp->link.force_lane_count, 1, intel_dp_max_common_lane_count(intel_dp));
397	}
398
399	int intel_dp_max_lane_count(struct intel_dp *intel_dp)
400	{
401	int lane_count;
402
403	if (intel_dp->link.force_lane_count)
404	lane_count = forced_lane_count(intel_dp);
405	else
406	lane_count = intel_dp->link.max_lane_count;
407
408	switch (lane_count) {
409	case 1:
410	case 2:
411	case 4:
412	return lane_count;
413	default:
414	MISSING_CASE(lane_count);
415	return 1;
416	}
417	}
418
419	static int intel_dp_min_lane_count(struct intel_dp *intel_dp)
420	{
421	if (intel_dp->link.force_lane_count)
422	return forced_lane_count(intel_dp);
423
424	return 1;
425	}
426
427	/*
428	* The required data bandwidth for a mode with given pixel clock and bpp. This
429	* is the required net bandwidth independent of the data bandwidth efficiency.
430	*
431	* TODO: check if callers of this functions should use
432	* intel_dp_effective_data_rate() instead.
433	*/
434	int
435	intel_dp_link_required(int pixel_clock, int bpp)
436	{
437	/* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
438	return DIV_ROUND_UP(pixel_clock * bpp, 8);
439	}
440
441	/**
442	* intel_dp_effective_data_rate - Return the pixel data rate accounting for BW allocation overhead
443	* @pixel_clock: pixel clock in kHz
444	* @bpp_x16: bits per pixel .4 fixed point format
445	* @bw_overhead: BW allocation overhead in 1ppm units
446	*
447	* Return the effective pixel data rate in kB/sec units taking into account
448	* the provided SSC, FEC, DSC BW allocation overhead.
449	*/
450	int intel_dp_effective_data_rate(int pixel_clock, int bpp_x16,
451	int bw_overhead)
452	{
453	return DIV_ROUND_UP_ULL(mul_u32_u32(pixel_clock * bpp_x16, bw_overhead),
454	1000000 * 16 * 8);
455	}
456
457	/**
458	* intel_dp_max_link_data_rate: Calculate the maximum rate for the given link params
459	* @intel_dp: Intel DP object
460	* @max_dprx_rate: Maximum data rate of the DPRX
461	* @max_dprx_lanes: Maximum lane count of the DPRX
462	*
463	* Calculate the maximum data rate for the provided link parameters taking into
464	* account any BW limitations by a DP tunnel attached to @intel_dp.
465	*
466	* Returns the maximum data rate in kBps units.
467	*/
468	int intel_dp_max_link_data_rate(struct intel_dp *intel_dp,
469	int max_dprx_rate, int max_dprx_lanes)
470	{
471	int max_rate = drm_dp_max_dprx_data_rate(max_link_rate: max_dprx_rate, max_lanes: max_dprx_lanes);
472
473	if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp))
474	max_rate = min(max_rate,
475	drm_dp_tunnel_available_bw(intel_dp->tunnel));
476
477	return max_rate;
478	}
479
480	bool intel_dp_has_joiner(struct intel_dp *intel_dp)
481	{
482	struct intel_display *display = to_intel_display(intel_dp);
483	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
484	struct intel_encoder *encoder = &intel_dig_port->base;
485
486	/* eDP MSO is not compatible with joiner */
487	if (intel_dp->mso_link_count)
488	return false;
489
490	return DISPLAY_VER(display) >= 12 ||
491	(DISPLAY_VER(display) == 11 &&
492	encoder->port != PORT_A);
493	}
494
495	static int dg2_max_source_rate(struct intel_dp *intel_dp)
496	{
497	return intel_dp_is_edp(intel_dp) ? 810000 : 1350000;
498	}
499
500	static int icl_max_source_rate(struct intel_dp *intel_dp)
501	{
502	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
503
504	if (intel_encoder_is_combo(encoder) && !intel_dp_is_edp(intel_dp))
505	return 540000;
506
507	return 810000;
508	}
509
510	static int ehl_max_source_rate(struct intel_dp *intel_dp)
511	{
512	if (intel_dp_is_edp(intel_dp))
513	return 540000;
514
515	return 810000;
516	}
517
518	static int mtl_max_source_rate(struct intel_dp *intel_dp)
519	{
520	struct intel_display *display = to_intel_display(intel_dp);
521	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
522
523	if (intel_encoder_is_c10phy(encoder))
524	return 810000;
525
526	if (DISPLAY_VERx100(display) == 1401)
527	return 1350000;
528
529	return 2000000;
530	}
531
532	static int vbt_max_link_rate(struct intel_dp *intel_dp)
533	{
534	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
535	int max_rate;
536
537	max_rate = intel_bios_dp_max_link_rate(devdata: encoder->devdata);
538
539	if (intel_dp_is_edp(intel_dp)) {
540	struct intel_connector *connector = intel_dp->attached_connector;
541	int edp_max_rate = connector->panel.vbt.edp.max_link_rate;
542
543	if (max_rate && edp_max_rate)
544	max_rate = min(max_rate, edp_max_rate);
545	else if (edp_max_rate)
546	max_rate = edp_max_rate;
547	}
548
549	return max_rate;
550	}
551
552	static void
553	intel_dp_set_source_rates(struct intel_dp *intel_dp)
554	{
555	/* The values must be in increasing order */
556	static const int bmg_rates[] = {
557	162000, 216000, 243000, 270000, 324000, 432000, 540000, 675000,
558	810000, 1000000, 1350000,
559	};
560	static const int mtl_rates[] = {
561	162000, 216000, 243000, 270000, 324000, 432000, 540000, 675000,
562	810000, 1000000, 2000000,
563	};
564	static const int icl_rates[] = {
565	162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000,
566	1000000, 1350000,
567	};
568	static const int bxt_rates[] = {
569	162000, 216000, 243000, 270000, 324000, 432000, 540000
570	};
571	static const int skl_rates[] = {
572	162000, 216000, 270000, 324000, 432000, 540000
573	};
574	static const int hsw_rates[] = {
575	162000, 270000, 540000
576	};
577	static const int g4x_rates[] = {
578	162000, 270000
579	};
580	struct intel_display *display = to_intel_display(intel_dp);
581	const int *source_rates;
582	int size, max_rate = 0, vbt_max_rate;
583
584	/* This should only be done once */
585	drm_WARN_ON(display->drm,
586	intel_dp->source_rates || intel_dp->num_source_rates);
587
588	if (DISPLAY_VER(display) >= 14) {
589	if (display->platform.battlemage) {
590	source_rates = bmg_rates;
591	size = ARRAY_SIZE(bmg_rates);
592	} else {
593	source_rates = mtl_rates;
594	size = ARRAY_SIZE(mtl_rates);
595	}
596	max_rate = mtl_max_source_rate(intel_dp);
597	} else if (DISPLAY_VER(display) >= 11) {
598	source_rates = icl_rates;
599	size = ARRAY_SIZE(icl_rates);
600	if (display->platform.dg2)
601	max_rate = dg2_max_source_rate(intel_dp);
602	else if (display->platform.alderlake_p || display->platform.alderlake_s ||
603	display->platform.dg1 || display->platform.rocketlake)
604	max_rate = 810000;
605	else if (display->platform.jasperlake || display->platform.elkhartlake)
606	max_rate = ehl_max_source_rate(intel_dp);
607	else
608	max_rate = icl_max_source_rate(intel_dp);
609	} else if (display->platform.geminilake || display->platform.broxton) {
610	source_rates = bxt_rates;
611	size = ARRAY_SIZE(bxt_rates);
612	} else if (DISPLAY_VER(display) == 9) {
613	source_rates = skl_rates;
614	size = ARRAY_SIZE(skl_rates);
615	} else if ((display->platform.haswell && !display->platform.haswell_ulx) ||
616	display->platform.broadwell) {
617	source_rates = hsw_rates;
618	size = ARRAY_SIZE(hsw_rates);
619	} else {
620	source_rates = g4x_rates;
621	size = ARRAY_SIZE(g4x_rates);
622	}
623
624	vbt_max_rate = vbt_max_link_rate(intel_dp);
625	if (max_rate && vbt_max_rate)
626	max_rate = min(max_rate, vbt_max_rate);
627	else if (vbt_max_rate)
628	max_rate = vbt_max_rate;
629
630	if (max_rate)
631	size = intel_dp_rate_limit_len(rates: source_rates, len: size, max_rate);
632
633	intel_dp->source_rates = source_rates;
634	intel_dp->num_source_rates = size;
635	}
636
637	static int intersect_rates(const int *source_rates, int source_len,
638	const int *sink_rates, int sink_len,
639	int *common_rates)
640	{
641	int i = 0, j = 0, k = 0;
642
643	while (i < source_len && j < sink_len) {
644	if (source_rates[i] == sink_rates[j]) {
645	if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
646	return k;
647	common_rates[k] = source_rates[i];
648	++k;
649	++i;
650	++j;
651	} else if (source_rates[i] < sink_rates[j]) {
652	++i;
653	} else {
654	++j;
655	}
656	}
657	return k;
658	}
659
660	/* return index of rate in rates array, or -1 if not found */
661	int intel_dp_rate_index(const int *rates, int len, int rate)
662	{
663	int i;
664
665	for (i = 0; i < len; i++)
666	if (rate == rates[i])
667	return i;
668
669	return -1;
670	}
671
672	static int intel_dp_link_config_rate(struct intel_dp *intel_dp,
673	const struct intel_dp_link_config *lc)
674	{
675	return intel_dp_common_rate(intel_dp, index: lc->link_rate_idx);
676	}
677
678	static int intel_dp_link_config_lane_count(const struct intel_dp_link_config *lc)
679	{
680	return 1 << lc->lane_count_exp;
681	}
682
683	static int intel_dp_link_config_bw(struct intel_dp *intel_dp,
684	const struct intel_dp_link_config *lc)
685	{
686	return drm_dp_max_dprx_data_rate(max_link_rate: intel_dp_link_config_rate(intel_dp, lc),
687	max_lanes: intel_dp_link_config_lane_count(lc));
688	}
689
690	static int link_config_cmp_by_bw(const void *a, const void *b, const void *p)
691	{
692	struct intel_dp *intel_dp = (struct intel_dp *)p; /* remove const */
693	const struct intel_dp_link_config *lc_a = a;
694	const struct intel_dp_link_config *lc_b = b;
695	int bw_a = intel_dp_link_config_bw(intel_dp, lc: lc_a);
696	int bw_b = intel_dp_link_config_bw(intel_dp, lc: lc_b);
697
698	if (bw_a != bw_b)
699	return bw_a - bw_b;
700
701	return intel_dp_link_config_rate(intel_dp, lc: lc_a) -
702	intel_dp_link_config_rate(intel_dp, lc: lc_b);
703	}
704
705	static void intel_dp_link_config_init(struct intel_dp *intel_dp)
706	{
707	struct intel_display *display = to_intel_display(intel_dp);
708	struct intel_dp_link_config *lc;
709	int num_common_lane_configs;
710	int i;
711	int j;
712
713	if (drm_WARN_ON(display->drm, !is_power_of_2(intel_dp_max_common_lane_count(intel_dp))))
714	return;
715
716	num_common_lane_configs = ilog2(intel_dp_max_common_lane_count(intel_dp)) + 1;
717
718	if (drm_WARN_ON(display->drm, intel_dp->num_common_rates * num_common_lane_configs >
719	ARRAY_SIZE(intel_dp->link.configs)))
720	return;
721
722	intel_dp->link.num_configs = intel_dp->num_common_rates * num_common_lane_configs;
723
724	lc = &intel_dp->link.configs[0];
725	for (i = 0; i < intel_dp->num_common_rates; i++) {
726	for (j = 0; j < num_common_lane_configs; j++) {
727	lc->lane_count_exp = j;
728	lc->link_rate_idx = i;
729
730	lc++;
731	}
732	}
733
734	sort_r(base: intel_dp->link.configs, num: intel_dp->link.num_configs,
735	size: sizeof(intel_dp->link.configs[0]),
736	cmp_func: link_config_cmp_by_bw, NULL,
737	priv: intel_dp);
738	}
739
740	void intel_dp_link_config_get(struct intel_dp *intel_dp, int idx, int *link_rate, int *lane_count)
741	{
742	struct intel_display *display = to_intel_display(intel_dp);
743	const struct intel_dp_link_config *lc;
744
745	if (drm_WARN_ON(display->drm, idx < 0 || idx >= intel_dp->link.num_configs))
746	idx = 0;
747
748	lc = &intel_dp->link.configs[idx];
749
750	*link_rate = intel_dp_link_config_rate(intel_dp, lc);
751	*lane_count = intel_dp_link_config_lane_count(lc);
752	}
753
754	int intel_dp_link_config_index(struct intel_dp *intel_dp, int link_rate, int lane_count)
755	{
756	int link_rate_idx = intel_dp_rate_index(rates: intel_dp->common_rates, len: intel_dp->num_common_rates,
757	rate: link_rate);
758	int lane_count_exp = ilog2(lane_count);
759	int i;
760
761	for (i = 0; i < intel_dp->link.num_configs; i++) {
762	const struct intel_dp_link_config *lc = &intel_dp->link.configs[i];
763
764	if (lc->lane_count_exp == lane_count_exp &&
765	lc->link_rate_idx == link_rate_idx)
766	return i;
767	}
768
769	return -1;
770	}
771
772	static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
773	{
774	struct intel_display *display = to_intel_display(intel_dp);
775
776	drm_WARN_ON(display->drm,
777	!intel_dp->num_source_rates || !intel_dp->num_sink_rates);
778
779	intel_dp->num_common_rates = intersect_rates(source_rates: intel_dp->source_rates,
780	source_len: intel_dp->num_source_rates,
781	sink_rates: intel_dp->sink_rates,
782	sink_len: intel_dp->num_sink_rates,
783	common_rates: intel_dp->common_rates);
784
785	/* Paranoia, there should always be something in common. */
786	if (drm_WARN_ON(display->drm, intel_dp->num_common_rates == 0)) {
787	intel_dp->common_rates[0] = 162000;
788	intel_dp->num_common_rates = 1;
789	}
790
791	intel_dp_link_config_init(intel_dp);
792	}
793
794	bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
795	u8 lane_count)
796	{
797	/*
798	* FIXME: we need to synchronize the current link parameters with
799	* hardware readout. Currently fast link training doesn't work on
800	* boot-up.
801	*/
802	if (link_rate == 0 ||
803	link_rate > intel_dp->link.max_rate)
804	return false;
805
806	if (lane_count == 0 ||
807	lane_count > intel_dp_max_lane_count(intel_dp))
808	return false;
809
810	return true;
811	}
812
813	u32 intel_dp_mode_to_fec_clock(u32 mode_clock)
814	{
815	return div_u64(dividend: mul_u32_u32(a: mode_clock, DP_DSC_FEC_OVERHEAD_FACTOR),
816	divisor: 1000000U);
817	}
818
819	int intel_dp_bw_fec_overhead(bool fec_enabled)
820	{
821	/*
822	* TODO: Calculate the actual overhead for a given mode.
823	* The hard-coded 1/0.972261=2.853% overhead factor
824	* corresponds (for instance) to the 8b/10b DP FEC 2.4% +
825	* 0.453% DSC overhead. This is enough for a 3840 width mode,
826	* which has a DSC overhead of up to ~0.2%, but may not be
827	* enough for a 1024 width mode where this is ~0.8% (on a 4
828	* lane DP link, with 2 DSC slices and 8 bpp color depth).
829	*/
830	return fec_enabled ? DP_DSC_FEC_OVERHEAD_FACTOR : 1000000;
831	}
832
833	static int
834	small_joiner_ram_size_bits(struct intel_display *display)
835	{
836	if (DISPLAY_VER(display) >= 13)
837	return 17280 * 8;
838	else if (DISPLAY_VER(display) >= 11)
839	return 7680 * 8;
840	else
841	return 6144 * 8;
842	}
843
844	static u32 intel_dp_dsc_nearest_valid_bpp(struct intel_display *display, u32 bpp, u32 pipe_bpp)
845	{
846	u32 bits_per_pixel = bpp;
847	int i;
848
849	/* Error out if the max bpp is less than smallest allowed valid bpp */
850	if (bits_per_pixel < valid_dsc_bpp[0]) {
851	drm_dbg_kms(display->drm, "Unsupported BPP %u, min %u\n",
852	bits_per_pixel, valid_dsc_bpp[0]);
853	return 0;
854	}
855
856	/* From XE_LPD onwards we support from bpc upto uncompressed bpp-1 BPPs */
857	if (DISPLAY_VER(display) >= 13) {
858	bits_per_pixel = min(bits_per_pixel, pipe_bpp - 1);
859
860	/*
861	* According to BSpec, 27 is the max DSC output bpp,
862	* 8 is the min DSC output bpp.
863	* While we can still clamp higher bpp values to 27, saving bandwidth,
864	* if it is required to oompress up to bpp < 8, means we can't do
865	* that and probably means we can't fit the required mode, even with
866	* DSC enabled.
867	*/
868	if (bits_per_pixel < 8) {
869	drm_dbg_kms(display->drm,
870	"Unsupported BPP %u, min 8\n",
871	bits_per_pixel);
872	return 0;
873	}
874	bits_per_pixel = min_t(u32, bits_per_pixel, 27);
875	} else {
876	/* Find the nearest match in the array of known BPPs from VESA */
877	for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
878	if (bits_per_pixel < valid_dsc_bpp[i + 1])
879	break;
880	}
881	drm_dbg_kms(display->drm, "Set dsc bpp from %d to VESA %d\n",
882	bits_per_pixel, valid_dsc_bpp[i]);
883
884	bits_per_pixel = valid_dsc_bpp[i];
885	}
886
887	return bits_per_pixel;
888	}
889
890	static int bigjoiner_interface_bits(struct intel_display *display)
891	{
892	return DISPLAY_VER(display) >= 14 ? 36 : 24;
893	}
894
895	static u32 bigjoiner_bw_max_bpp(struct intel_display *display, u32 mode_clock,
896	int num_joined_pipes)
897	{
898	u32 max_bpp;
899	/* With bigjoiner multiple dsc engines are used in parallel so PPC is 2 */
900	int ppc = 2;
901	int num_big_joiners = num_joined_pipes / 2;
902
903	max_bpp = display->cdclk.max_cdclk_freq * ppc * bigjoiner_interface_bits(display) /
904	intel_dp_mode_to_fec_clock(mode_clock);
905
906	max_bpp *= num_big_joiners;
907
908	return max_bpp;
909
910	}
911
912	static u32 small_joiner_ram_max_bpp(struct intel_display *display,
913	u32 mode_hdisplay,
914	int num_joined_pipes)
915	{
916	u32 max_bpp;
917
918	/* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
919	max_bpp = small_joiner_ram_size_bits(display) / mode_hdisplay;
920
921	max_bpp *= num_joined_pipes;
922
923	return max_bpp;
924	}
925
926	static int ultrajoiner_ram_bits(void)
927	{
928	return 4 * 72 * 512;
929	}
930
931	static u32 ultrajoiner_ram_max_bpp(u32 mode_hdisplay)
932	{
933	return ultrajoiner_ram_bits() / mode_hdisplay;
934	}
935
936	/* TODO: return a bpp_x16 value */
937	static
938	u32 get_max_compressed_bpp_with_joiner(struct intel_display *display,
939	u32 mode_clock, u32 mode_hdisplay,
940	int num_joined_pipes)
941	{
942	u32 max_bpp = small_joiner_ram_max_bpp(display, mode_hdisplay, num_joined_pipes);
943
944	if (num_joined_pipes > 1)
945	max_bpp = min(max_bpp, bigjoiner_bw_max_bpp(display, mode_clock,
946	num_joined_pipes));
947	if (num_joined_pipes == 4)
948	max_bpp = min(max_bpp, ultrajoiner_ram_max_bpp(mode_hdisplay));
949
950	return max_bpp;
951	}
952
953	/* TODO: return a bpp_x16 value */
954	u16 intel_dp_dsc_get_max_compressed_bpp(struct intel_display *display,
955	u32 link_clock, u32 lane_count,
956	u32 mode_clock, u32 mode_hdisplay,
957	int num_joined_pipes,
958	enum intel_output_format output_format,
959	u32 pipe_bpp,
960	u32 timeslots)
961	{
962	u32 bits_per_pixel, joiner_max_bpp;
963
964	/*
965	* Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
966	* (LinkSymbolClock)* 8 * (TimeSlots / 64)
967	* for SST -> TimeSlots is 64(i.e all TimeSlots that are available)
968	* for MST -> TimeSlots has to be calculated, based on mode requirements
969	*
970	* Due to FEC overhead, the available bw is reduced to 97.2261%.
971	* To support the given mode:
972	* Bandwidth required should be <= Available link Bandwidth * FEC Overhead
973	* =>ModeClock * bits_per_pixel <= Available Link Bandwidth * FEC Overhead
974	* =>bits_per_pixel <= Available link Bandwidth * FEC Overhead / ModeClock
975	* =>bits_per_pixel <= (NumberOfLanes * LinkSymbolClock) * 8 (TimeSlots / 64) /
976	* (ModeClock / FEC Overhead)
977	* =>bits_per_pixel <= (NumberOfLanes * LinkSymbolClock * TimeSlots) /
978	* (ModeClock / FEC Overhead * 8)
979	*/
980	bits_per_pixel = ((link_clock * lane_count) * timeslots) /
981	(intel_dp_mode_to_fec_clock(mode_clock) * 8);
982
983	/* Bandwidth required for 420 is half, that of 444 format */
984	if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
985	bits_per_pixel *= 2;
986
987	/*
988	* According to DSC 1.2a Section 4.1.1 Table 4.1 the maximum
989	* supported PPS value can be 63.9375 and with the further
990	* mention that for 420, 422 formats, bpp should be programmed double
991	* the target bpp restricting our target bpp to be 31.9375 at max.
992	*/
993	if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
994	bits_per_pixel = min_t(u32, bits_per_pixel, 31);
995
996	drm_dbg_kms(display->drm, "Max link bpp is %u for %u timeslots "
997	"total bw %u pixel clock %u\n",
998	bits_per_pixel, timeslots,
999	(link_clock * lane_count * 8),
1000	intel_dp_mode_to_fec_clock(mode_clock));
1001
1002	joiner_max_bpp = get_max_compressed_bpp_with_joiner(display, mode_clock,
1003	mode_hdisplay, num_joined_pipes);
1004	bits_per_pixel = min(bits_per_pixel, joiner_max_bpp);
1005
1006	bits_per_pixel = intel_dp_dsc_nearest_valid_bpp(display, bpp: bits_per_pixel, pipe_bpp);
1007
1008	return bits_per_pixel;
1009	}
1010
1011	u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector,
1012	int mode_clock, int mode_hdisplay,
1013	int num_joined_pipes)
1014	{
1015	struct intel_display *display = to_intel_display(connector);
1016	u8 min_slice_count, i;
1017	int max_slice_width;
1018	int tp_rgb_yuv444;
1019	int tp_yuv422_420;
1020
1021	/*
1022	* TODO: Use the throughput value specific to the actual RGB/YUV
1023	* format of the output.
1024	* The RGB/YUV444 throughput value should be always either equal
1025	* or smaller than the YUV422/420 value, but let's not depend on
1026	* this assumption.
1027	*/
1028	if (mode_clock > max(connector->dp.dsc_branch_caps.overall_throughput.rgb_yuv444,
1029	connector->dp.dsc_branch_caps.overall_throughput.yuv422_420))
1030	return 0;
1031
1032	if (mode_hdisplay > connector->dp.dsc_branch_caps.max_line_width)
1033	return 0;
1034
1035	/*
1036	* TODO: Pass the total pixel rate of all the streams transferred to
1037	* an MST tiled display, calculate the total slice count for all tiles
1038	* from this and the per-tile slice count from the total slice count.
1039	*/
1040	tp_rgb_yuv444 = drm_dp_dsc_sink_max_slice_throughput(dsc_dpcd: connector->dp.dsc_dpcd,
1041	peak_pixel_rate: mode_clock, is_rgb_yuv444: true);
1042	tp_yuv422_420 = drm_dp_dsc_sink_max_slice_throughput(dsc_dpcd: connector->dp.dsc_dpcd,
1043	peak_pixel_rate: mode_clock, is_rgb_yuv444: false);
1044
1045	/*
1046	* TODO: Use the throughput value specific to the actual RGB/YUV
1047	* format of the output.
1048	* For now use the smaller of these, which is ok, potentially
1049	* resulting in a higher than required minimum slice count.
1050	* The RGB/YUV444 throughput value should be always either equal
1051	* or smaller than the YUV422/420 value, but let's not depend on
1052	* this assumption.
1053	*/
1054	min_slice_count = DIV_ROUND_UP(mode_clock, min(tp_rgb_yuv444, tp_yuv422_420));
1055
1056	/*
1057	* Due to some DSC engine BW limitations, we need to enable second
1058	* slice and VDSC engine, whenever we approach close enough to max CDCLK
1059	*/
1060	if (mode_clock >= ((display->cdclk.max_cdclk_freq * 85) / 100))
1061	min_slice_count = max_t(u8, min_slice_count, 2);
1062
1063	max_slice_width = drm_dp_dsc_sink_max_slice_width(dsc_dpcd: connector->dp.dsc_dpcd);
1064	if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
1065	drm_dbg_kms(display->drm,
1066	"Unsupported slice width %d by DP DSC Sink device\n",
1067	max_slice_width);
1068	return 0;
1069	}
1070	/* Also take into account max slice width */
1071	min_slice_count = max_t(u8, min_slice_count,
1072	DIV_ROUND_UP(mode_hdisplay,
1073	max_slice_width));
1074
1075	/* Find the closest match to the valid slice count values */
1076	for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
1077	u8 test_slice_count = valid_dsc_slicecount[i] * num_joined_pipes;
1078
1079	/*
1080	* 3 DSC Slices per pipe need 3 DSC engines, which is supported only
1081	* with Ultrajoiner only for some platforms.
1082	*/
1083	if (valid_dsc_slicecount[i] == 3 &&
1084	(!HAS_DSC_3ENGINES(display) || num_joined_pipes != 4))
1085	continue;
1086
1087	if (test_slice_count >
1088	drm_dp_dsc_sink_max_slice_count(dsc_dpcd: connector->dp.dsc_dpcd, is_edp: false))
1089	break;
1090
1091	/*
1092	* Bigjoiner needs small joiner to be enabled.
1093	* So there should be at least 2 dsc slices per pipe,
1094	* whenever bigjoiner is enabled.
1095	*/
1096	if (num_joined_pipes > 1 && valid_dsc_slicecount[i] < 2)
1097	continue;
1098
1099	if (mode_hdisplay % test_slice_count)
1100	continue;
1101
1102	if (min_slice_count <= test_slice_count)
1103	return test_slice_count;
1104	}
1105
1106	drm_dbg_kms(display->drm, "Unsupported Slice Count %d\n",
1107	min_slice_count);
1108	return 0;
1109	}
1110
1111	static bool source_can_output(struct intel_dp *intel_dp,
1112	enum intel_output_format format)
1113	{
1114	struct intel_display *display = to_intel_display(intel_dp);
1115
1116	switch (format) {
1117	case INTEL_OUTPUT_FORMAT_RGB:
1118	return true;
1119
1120	case INTEL_OUTPUT_FORMAT_YCBCR444:
1121	/*
1122	* No YCbCr output support on gmch platforms.
1123	* Also, ILK doesn't seem capable of DP YCbCr output.
1124	* The displayed image is severely corrupted. SNB+ is fine.
1125	*/
1126	return !HAS_GMCH(display) && !display->platform.ironlake;
1127
1128	case INTEL_OUTPUT_FORMAT_YCBCR420:
1129	/* Platform < Gen 11 cannot output YCbCr420 format */
1130	return DISPLAY_VER(display) >= 11;
1131
1132	default:
1133	MISSING_CASE(format);
1134	return false;
1135	}
1136	}
1137
1138	static bool
1139	dfp_can_convert_from_rgb(struct intel_dp *intel_dp,
1140	enum intel_output_format sink_format)
1141	{
1142	if (!drm_dp_is_branch(dpcd: intel_dp->dpcd))
1143	return false;
1144
1145	if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR444)
1146	return intel_dp->dfp.rgb_to_ycbcr;
1147
1148	if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1149	return intel_dp->dfp.rgb_to_ycbcr &&
1150	intel_dp->dfp.ycbcr_444_to_420;
1151
1152	return false;
1153	}
1154
1155	static bool
1156	dfp_can_convert_from_ycbcr444(struct intel_dp *intel_dp,
1157	enum intel_output_format sink_format)
1158	{
1159	if (!drm_dp_is_branch(dpcd: intel_dp->dpcd))
1160	return false;
1161
1162	if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1163	return intel_dp->dfp.ycbcr_444_to_420;
1164
1165	return false;
1166	}
1167
1168	static bool
1169	dfp_can_convert(struct intel_dp *intel_dp,
1170	enum intel_output_format output_format,
1171	enum intel_output_format sink_format)
1172	{
1173	switch (output_format) {
1174	case INTEL_OUTPUT_FORMAT_RGB:
1175	return dfp_can_convert_from_rgb(intel_dp, sink_format);
1176	case INTEL_OUTPUT_FORMAT_YCBCR444:
1177	return dfp_can_convert_from_ycbcr444(intel_dp, sink_format);
1178	default:
1179	MISSING_CASE(output_format);
1180	return false;
1181	}
1182
1183	return false;
1184	}
1185
1186	static enum intel_output_format
1187	intel_dp_output_format(struct intel_connector *connector,
1188	enum intel_output_format sink_format)
1189	{
1190	struct intel_display *display = to_intel_display(connector);
1191	struct intel_dp *intel_dp = intel_attached_dp(connector);
1192	enum intel_output_format force_dsc_output_format =
1193	intel_dp->force_dsc_output_format;
1194	enum intel_output_format output_format;
1195	if (force_dsc_output_format) {
1196	if (source_can_output(intel_dp, format: force_dsc_output_format) &&
1197	(!drm_dp_is_branch(dpcd: intel_dp->dpcd) ||
1198	sink_format != force_dsc_output_format ||
1199	dfp_can_convert(intel_dp, output_format: force_dsc_output_format, sink_format)))
1200	return force_dsc_output_format;
1201
1202	drm_dbg_kms(display->drm, "Cannot force DSC output format\n");
1203	}
1204
1205	if (sink_format == INTEL_OUTPUT_FORMAT_RGB ||
1206	dfp_can_convert_from_rgb(intel_dp, sink_format))
1207	output_format = INTEL_OUTPUT_FORMAT_RGB;
1208
1209	else if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR444 ||
1210	dfp_can_convert_from_ycbcr444(intel_dp, sink_format))
1211	output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
1212
1213	else
1214	output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
1215
1216	drm_WARN_ON(display->drm, !source_can_output(intel_dp, output_format));
1217
1218	return output_format;
1219	}
1220
1221	int intel_dp_min_bpp(enum intel_output_format output_format)
1222	{
1223	if (output_format == INTEL_OUTPUT_FORMAT_RGB)
1224	return intel_display_min_pipe_bpp();
1225	else
1226	return 8 * 3;
1227	}
1228
1229	int intel_dp_output_bpp(enum intel_output_format output_format, int bpp)
1230	{
1231	/*
1232	* bpp value was assumed to RGB format. And YCbCr 4:2:0 output
1233	* format of the number of bytes per pixel will be half the number
1234	* of bytes of RGB pixel.
1235	*/
1236	if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1237	bpp /= 2;
1238
1239	return bpp;
1240	}
1241
1242	static enum intel_output_format
1243	intel_dp_sink_format(struct intel_connector *connector,
1244	const struct drm_display_mode *mode)
1245	{
1246	const struct drm_display_info *info = &connector->base.display_info;
1247
1248	if (drm_mode_is_420_only(display: info, mode))
1249	return INTEL_OUTPUT_FORMAT_YCBCR420;
1250
1251	return INTEL_OUTPUT_FORMAT_RGB;
1252	}
1253
1254	static int
1255	intel_dp_mode_min_output_bpp(struct intel_connector *connector,
1256	const struct drm_display_mode *mode)
1257	{
1258	enum intel_output_format output_format, sink_format;
1259
1260	sink_format = intel_dp_sink_format(connector, mode);
1261
1262	output_format = intel_dp_output_format(connector, sink_format);
1263
1264	return intel_dp_output_bpp(output_format, bpp: intel_dp_min_bpp(output_format));
1265	}
1266
1267	static bool intel_dp_hdisplay_bad(struct intel_display *display,
1268	int hdisplay)
1269	{
1270	/*
1271	* Older platforms don't like hdisplay==4096 with DP.
1272	*
1273	* On ILK/SNB/IVB the pipe seems to be somewhat running (scanline
1274	* and frame counter increment), but we don't get vblank interrupts,
1275	* and the pipe underruns immediately. The link also doesn't seem
1276	* to get trained properly.
1277	*
1278	* On CHV the vblank interrupts don't seem to disappear but
1279	* otherwise the symptoms are similar.
1280	*
1281	* TODO: confirm the behaviour on HSW+
1282	*/
1283	return hdisplay == 4096 && !HAS_DDI(display);
1284	}
1285
1286	static int intel_dp_max_tmds_clock(struct intel_dp *intel_dp)
1287	{
1288	struct intel_connector *connector = intel_dp->attached_connector;
1289	const struct drm_display_info *info = &connector->base.display_info;
1290	int max_tmds_clock = intel_dp->dfp.max_tmds_clock;
1291
1292	/* Only consider the sink's max TMDS clock if we know this is a HDMI DFP */
1293	if (max_tmds_clock && info->max_tmds_clock)
1294	max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock);
1295
1296	return max_tmds_clock;
1297	}
1298
1299	static enum drm_mode_status
1300	intel_dp_tmds_clock_valid(struct intel_dp *intel_dp,
1301	int clock, int bpc,
1302	enum intel_output_format sink_format,
1303	bool respect_downstream_limits)
1304	{
1305	int tmds_clock, min_tmds_clock, max_tmds_clock;
1306
1307	if (!respect_downstream_limits)
1308	return MODE_OK;
1309
1310	tmds_clock = intel_hdmi_tmds_clock(clock, bpc, sink_format);
1311
1312	min_tmds_clock = intel_dp->dfp.min_tmds_clock;
1313	max_tmds_clock = intel_dp_max_tmds_clock(intel_dp);
1314
1315	if (min_tmds_clock && tmds_clock < min_tmds_clock)
1316	return MODE_CLOCK_LOW;
1317
1318	if (max_tmds_clock && tmds_clock > max_tmds_clock)
1319	return MODE_CLOCK_HIGH;
1320
1321	return MODE_OK;
1322	}
1323
1324	static enum drm_mode_status
1325	intel_dp_mode_valid_downstream(struct intel_connector *connector,
1326	const struct drm_display_mode *mode,
1327	int target_clock)
1328	{
1329	struct intel_dp *intel_dp = intel_attached_dp(connector);
1330	const struct drm_display_info *info = &connector->base.display_info;
1331	enum drm_mode_status status;
1332	enum intel_output_format sink_format;
1333
1334	/* If PCON supports FRL MODE, check FRL bandwidth constraints */
1335	if (intel_dp->dfp.pcon_max_frl_bw) {
1336	int target_bw;
1337	int max_frl_bw;
1338	int bpp = intel_dp_mode_min_output_bpp(connector, mode);
1339
1340	target_bw = bpp * target_clock;
1341
1342	max_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
1343
1344	/* converting bw from Gbps to Kbps*/
1345	max_frl_bw = max_frl_bw * 1000000;
1346
1347	if (target_bw > max_frl_bw)
1348	return MODE_CLOCK_HIGH;
1349
1350	return MODE_OK;
1351	}
1352
1353	if (intel_dp->dfp.max_dotclock &&
1354	target_clock > intel_dp->dfp.max_dotclock)
1355	return MODE_CLOCK_HIGH;
1356
1357	sink_format = intel_dp_sink_format(connector, mode);
1358
1359	/* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */
1360	status = intel_dp_tmds_clock_valid(intel_dp, clock: target_clock,
1361	bpc: 8, sink_format, respect_downstream_limits: true);
1362
1363	if (status != MODE_OK) {
1364	if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
1365	!connector->base.ycbcr_420_allowed ||
1366	!drm_mode_is_420_also(display: info, mode))
1367	return status;
1368	sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
1369	status = intel_dp_tmds_clock_valid(intel_dp, clock: target_clock,
1370	bpc: 8, sink_format, respect_downstream_limits: true);
1371	if (status != MODE_OK)
1372	return status;
1373	}
1374
1375	return MODE_OK;
1376	}
1377
1378	static
1379	bool intel_dp_needs_joiner(struct intel_dp *intel_dp,
1380	struct intel_connector *connector,
1381	int hdisplay, int clock,
1382	int num_joined_pipes)
1383	{
1384	struct intel_display *display = to_intel_display(intel_dp);
1385	int hdisplay_limit;
1386
1387	if (!intel_dp_has_joiner(intel_dp))
1388	return false;
1389
1390	num_joined_pipes /= 2;
1391
1392	hdisplay_limit = DISPLAY_VER(display) >= 30 ? 6144 : 5120;
1393
1394	return clock > num_joined_pipes * display->cdclk.max_dotclk_freq ||
1395	hdisplay > num_joined_pipes * hdisplay_limit;
1396	}
1397
1398	int intel_dp_num_joined_pipes(struct intel_dp *intel_dp,
1399	struct intel_connector *connector,
1400	int hdisplay, int clock)
1401	{
1402	struct intel_display *display = to_intel_display(intel_dp);
1403
1404	if (connector->force_joined_pipes)
1405	return connector->force_joined_pipes;
1406
1407	if (HAS_ULTRAJOINER(display) &&
1408	intel_dp_needs_joiner(intel_dp, connector, hdisplay, clock, num_joined_pipes: 4))
1409	return 4;
1410
1411	if ((HAS_BIGJOINER(display) || HAS_UNCOMPRESSED_JOINER(display)) &&
1412	intel_dp_needs_joiner(intel_dp, connector, hdisplay, clock, num_joined_pipes: 2))
1413	return 2;
1414
1415	return 1;
1416	}
1417
1418	bool intel_dp_has_dsc(const struct intel_connector *connector)
1419	{
1420	struct intel_display *display = to_intel_display(connector);
1421
1422	if (!HAS_DSC(display))
1423	return false;
1424
1425	if (connector->mst.dp && !HAS_DSC_MST(display))
1426	return false;
1427
1428	if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP &&
1429	connector->panel.vbt.edp.dsc_disable)
1430	return false;
1431
1432	if (!drm_dp_sink_supports_dsc(dsc_dpcd: connector->dp.dsc_dpcd))
1433	return false;
1434
1435	return true;
1436	}
1437
1438	static enum drm_mode_status
1439	intel_dp_mode_valid(struct drm_connector *_connector,
1440	const struct drm_display_mode *mode)
1441	{
1442	struct intel_display *display = to_intel_display(_connector->dev);
1443	struct intel_connector *connector = to_intel_connector(_connector);
1444	struct intel_dp *intel_dp = intel_attached_dp(connector);
1445	enum intel_output_format sink_format, output_format;
1446	const struct drm_display_mode *fixed_mode;
1447	int target_clock = mode->clock;
1448	int max_rate, mode_rate, max_lanes, max_link_clock;
1449	int max_dotclk = display->cdclk.max_dotclk_freq;
1450	u16 dsc_max_compressed_bpp = 0;
1451	u8 dsc_slice_count = 0;
1452	enum drm_mode_status status;
1453	bool dsc = false;
1454	int num_joined_pipes;
1455
1456	status = intel_cpu_transcoder_mode_valid(display, mode);
1457	if (status != MODE_OK)
1458	return status;
1459
1460	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1461	return MODE_H_ILLEGAL;
1462
1463	if (mode->clock < 10000)
1464	return MODE_CLOCK_LOW;
1465
1466	fixed_mode = intel_panel_fixed_mode(connector, mode);
1467	if (intel_dp_is_edp(intel_dp) && fixed_mode) {
1468	status = intel_panel_mode_valid(connector, mode);
1469	if (status != MODE_OK)
1470	return status;
1471
1472	target_clock = fixed_mode->clock;
1473	}
1474
1475	num_joined_pipes = intel_dp_num_joined_pipes(intel_dp, connector,
1476	hdisplay: mode->hdisplay, clock: target_clock);
1477	max_dotclk *= num_joined_pipes;
1478
1479	sink_format = intel_dp_sink_format(connector, mode);
1480	output_format = intel_dp_output_format(connector, sink_format);
1481
1482	status = intel_pfit_mode_valid(display, mode, output_format, num_joined_pipes);
1483	if (status != MODE_OK)
1484	return status;
1485
1486	if (target_clock > max_dotclk)
1487	return MODE_CLOCK_HIGH;
1488
1489	if (intel_dp_hdisplay_bad(display, hdisplay: mode->hdisplay))
1490	return MODE_H_ILLEGAL;
1491
1492	max_link_clock = intel_dp_max_link_rate(intel_dp);
1493	max_lanes = intel_dp_max_lane_count(intel_dp);
1494
1495	max_rate = intel_dp_max_link_data_rate(intel_dp, max_dprx_rate: max_link_clock, max_dprx_lanes: max_lanes);
1496
1497	mode_rate = intel_dp_link_required(pixel_clock: target_clock,
1498	bpp: intel_dp_mode_min_output_bpp(connector, mode));
1499
1500	if (intel_dp_has_dsc(connector)) {
1501	int pipe_bpp;
1502
1503	/*
1504	* TBD pass the connector BPC,
1505	* for now U8_MAX so that max BPC on that platform would be picked
1506	*/
1507	pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, U8_MAX);
1508
1509	/*
1510	* Output bpp is stored in 6.4 format so right shift by 4 to get the
1511	* integer value since we support only integer values of bpp.
1512	*/
1513	if (intel_dp_is_edp(intel_dp)) {
1514	dsc_max_compressed_bpp =
1515	drm_edp_dsc_sink_output_bpp(dsc_dpcd: connector->dp.dsc_dpcd) >> 4;
1516	dsc_slice_count =
1517	drm_dp_dsc_sink_max_slice_count(dsc_dpcd: connector->dp.dsc_dpcd,
1518	is_edp: true);
1519	} else if (drm_dp_sink_supports_fec(fec_capable: connector->dp.fec_capability)) {
1520	dsc_max_compressed_bpp =
1521	intel_dp_dsc_get_max_compressed_bpp(display,
1522	link_clock: max_link_clock,
1523	lane_count: max_lanes,
1524	mode_clock: target_clock,
1525	mode_hdisplay: mode->hdisplay,
1526	num_joined_pipes,
1527	output_format,
1528	pipe_bpp, timeslots: 64);
1529	dsc_slice_count =
1530	intel_dp_dsc_get_slice_count(connector,
1531	mode_clock: target_clock,
1532	mode_hdisplay: mode->hdisplay,
1533	num_joined_pipes);
1534	}
1535
1536	dsc = dsc_max_compressed_bpp && dsc_slice_count;
1537	}
1538
1539	if (intel_dp_joiner_needs_dsc(display, num_joined_pipes) && !dsc)
1540	return MODE_CLOCK_HIGH;
1541
1542	if (mode_rate > max_rate && !dsc)
1543	return MODE_CLOCK_HIGH;
1544
1545	status = intel_dp_mode_valid_downstream(connector, mode, target_clock);
1546	if (status != MODE_OK)
1547	return status;
1548
1549	return intel_mode_valid_max_plane_size(display, mode, num_joined_pipes);
1550	}
1551
1552	bool intel_dp_source_supports_tps3(struct intel_display *display)
1553	{
1554	return DISPLAY_VER(display) >= 9 ||
1555	display->platform.broadwell || display->platform.haswell;
1556	}
1557
1558	bool intel_dp_source_supports_tps4(struct intel_display *display)
1559	{
1560	return DISPLAY_VER(display) >= 10;
1561	}
1562
1563	static void seq_buf_print_array(struct seq_buf *s, const int *array, int nelem)
1564	{
1565	int i;
1566
1567	for (i = 0; i < nelem; i++)
1568	seq_buf_printf(s, fmt: "%s%d", i ? ", " : "", array[i]);
1569	}
1570
1571	static void intel_dp_print_rates(struct intel_dp *intel_dp)
1572	{
1573	struct intel_display *display = to_intel_display(intel_dp);
1574	DECLARE_SEQ_BUF(s, 128); /* FIXME: too big for stack? */
1575
1576	if (!drm_debug_enabled(DRM_UT_KMS))
1577	return;
1578
1579	seq_buf_print_array(s: &s, array: intel_dp->source_rates, nelem: intel_dp->num_source_rates);
1580	drm_dbg_kms(display->drm, "source rates: %s\n", seq_buf_str(&s));
1581
1582	seq_buf_clear(s: &s);
1583	seq_buf_print_array(s: &s, array: intel_dp->sink_rates, nelem: intel_dp->num_sink_rates);
1584	drm_dbg_kms(display->drm, "sink rates: %s\n", seq_buf_str(&s));
1585
1586	seq_buf_clear(s: &s);
1587	seq_buf_print_array(s: &s, array: intel_dp->common_rates, nelem: intel_dp->num_common_rates);
1588	drm_dbg_kms(display->drm, "common rates: %s\n", seq_buf_str(&s));
1589	}
1590
1591	static int forced_link_rate(struct intel_dp *intel_dp)
1592	{
1593	int len = intel_dp_common_len_rate_limit(intel_dp, max_rate: intel_dp->link.force_rate);
1594
1595	if (len == 0)
1596	return intel_dp_common_rate(intel_dp, index: 0);
1597
1598	return intel_dp_common_rate(intel_dp, index: len - 1);
1599	}
1600
1601	int
1602	intel_dp_max_link_rate(struct intel_dp *intel_dp)
1603	{
1604	int len;
1605
1606	if (intel_dp->link.force_rate)
1607	return forced_link_rate(intel_dp);
1608
1609	len = intel_dp_common_len_rate_limit(intel_dp, max_rate: intel_dp->link.max_rate);
1610
1611	return intel_dp_common_rate(intel_dp, index: len - 1);
1612	}
1613
1614	static int
1615	intel_dp_min_link_rate(struct intel_dp *intel_dp)
1616	{
1617	if (intel_dp->link.force_rate)
1618	return forced_link_rate(intel_dp);
1619
1620	return intel_dp_common_rate(intel_dp, index: 0);
1621	}
1622
1623	int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1624	{
1625	struct intel_display *display = to_intel_display(intel_dp);
1626	int i = intel_dp_rate_index(rates: intel_dp->sink_rates,
1627	len: intel_dp->num_sink_rates, rate);
1628
1629	if (drm_WARN_ON(display->drm, i < 0))
1630	i = 0;
1631
1632	return i;
1633	}
1634
1635	void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1636	u8 *link_bw, u8 *rate_select)
1637	{
1638	struct intel_display *display = to_intel_display(intel_dp);
1639
1640	/* FIXME g4x can't generate an exact 2.7GHz with the 96MHz non-SSC refclk */
1641	if (display->platform.g4x && port_clock == 268800)
1642	port_clock = 270000;
1643
1644	/* eDP 1.4 rate select method. */
1645	if (intel_dp->use_rate_select) {
1646	*link_bw = 0;
1647	*rate_select =
1648	intel_dp_rate_select(intel_dp, rate: port_clock);
1649	} else {
1650	*link_bw = drm_dp_link_rate_to_bw_code(link_rate: port_clock);
1651	*rate_select = 0;
1652	}
1653	}
1654
1655	bool intel_dp_has_hdmi_sink(struct intel_dp *intel_dp)
1656	{
1657	struct intel_connector *connector = intel_dp->attached_connector;
1658
1659	return connector->base.display_info.is_hdmi;
1660	}
1661
1662	static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
1663	const struct intel_crtc_state *pipe_config)
1664	{
1665	struct intel_display *display = to_intel_display(intel_dp);
1666	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1667
1668	if (DISPLAY_VER(display) >= 12)
1669	return true;
1670
1671	if (DISPLAY_VER(display) == 11 && encoder->port != PORT_A &&
1672	!intel_crtc_has_type(crtc_state: pipe_config, type: INTEL_OUTPUT_DP_MST))
1673	return true;
1674
1675	return false;
1676	}
1677
1678	bool intel_dp_supports_fec(struct intel_dp *intel_dp,
1679	const struct intel_connector *connector,
1680	const struct intel_crtc_state *pipe_config)
1681	{
1682	return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
1683	drm_dp_sink_supports_fec(fec_capable: connector->dp.fec_capability);
1684	}
1685
1686	bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
1687	const struct intel_connector *connector,
1688	const struct intel_crtc_state *crtc_state)
1689	{
1690	if (!intel_dp_has_dsc(connector))
1691	return false;
1692
1693	if (intel_crtc_has_type(crtc_state, type: INTEL_OUTPUT_DP) &&
1694	!intel_dp_supports_fec(intel_dp, connector, pipe_config: crtc_state))
1695	return false;
1696
1697	return intel_dsc_source_support(crtc_state);
1698	}
1699
1700	static int intel_dp_hdmi_compute_bpc(struct intel_dp *intel_dp,
1701	const struct intel_crtc_state *crtc_state,
1702	int bpc, bool respect_downstream_limits)
1703	{
1704	int clock = crtc_state->hw.adjusted_mode.crtc_clock;
1705
1706	/*
1707	* Current bpc could already be below 8bpc due to
1708	* FDI bandwidth constraints or other limits.
1709	* HDMI minimum is 8bpc however.
1710	*/
1711	bpc = max(bpc, 8);
1712
1713	/*
1714	* We will never exceed downstream TMDS clock limits while
1715	* attempting deep color. If the user insists on forcing an
1716	* out of spec mode they will have to be satisfied with 8bpc.
1717	*/
1718	if (!respect_downstream_limits)
1719	bpc = 8;
1720
1721	for (; bpc >= 8; bpc -= 2) {
1722	if (intel_hdmi_bpc_possible(crtc_state, bpc,
1723	has_hdmi_sink: intel_dp_has_hdmi_sink(intel_dp)) &&
1724	intel_dp_tmds_clock_valid(intel_dp, clock, bpc, sink_format: crtc_state->sink_format,
1725	respect_downstream_limits) == MODE_OK)
1726	return bpc;
1727	}
1728
1729	return -EINVAL;
1730	}
1731
1732	static int intel_dp_max_bpp(struct intel_dp *intel_dp,
1733	const struct intel_crtc_state *crtc_state,
1734	bool respect_downstream_limits)
1735	{
1736	struct intel_display *display = to_intel_display(intel_dp);
1737	struct intel_connector *connector = intel_dp->attached_connector;
1738	int bpp, bpc;
1739
1740	bpc = crtc_state->pipe_bpp / 3;
1741
1742	if (intel_dp->dfp.max_bpc)
1743	bpc = min_t(int, bpc, intel_dp->dfp.max_bpc);
1744
1745	if (intel_dp->dfp.min_tmds_clock) {
1746	int max_hdmi_bpc;
1747
1748	max_hdmi_bpc = intel_dp_hdmi_compute_bpc(intel_dp, crtc_state, bpc,
1749	respect_downstream_limits);
1750	if (max_hdmi_bpc < 0)
1751	return 0;
1752
1753	bpc = min(bpc, max_hdmi_bpc);
1754	}
1755
1756	bpp = bpc * 3;
1757	if (intel_dp_is_edp(intel_dp)) {
1758	/* Get bpp from vbt only for panels that dont have bpp in edid */
1759	if (connector->base.display_info.bpc == 0 &&
1760	connector->panel.vbt.edp.bpp &&
1761	connector->panel.vbt.edp.bpp < bpp) {
1762	drm_dbg_kms(display->drm,
1763	"clamping bpp for eDP panel to BIOS-provided %i\n",
1764	connector->panel.vbt.edp.bpp);
1765	bpp = connector->panel.vbt.edp.bpp;
1766	}
1767	}
1768
1769	return bpp;
1770	}
1771
1772	static bool has_seamless_m_n(struct intel_connector *connector)
1773	{
1774	struct intel_display *display = to_intel_display(connector);
1775
1776	/*
1777	* Seamless M/N reprogramming only implemented
1778	* for BDW+ double buffered M/N registers so far.
1779	*/
1780	return HAS_DOUBLE_BUFFERED_M_N(display) &&
1781	intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS;
1782	}
1783
1784	static int intel_dp_mode_clock(const struct intel_crtc_state *crtc_state,
1785	const struct drm_connector_state *conn_state)
1786	{
1787	struct intel_connector *connector = to_intel_connector(conn_state->connector);
1788	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
1789
1790	/* FIXME a bit of a mess wrt clock vs. crtc_clock */
1791	if (has_seamless_m_n(connector))
1792	return intel_panel_highest_mode(connector, adjusted_mode)->clock;
1793	else
1794	return adjusted_mode->crtc_clock;
1795	}
1796
1797	/* Optimize link config in order: max bpp, min clock, min lanes */
1798	static int
1799	intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
1800	struct intel_crtc_state *pipe_config,
1801	const struct drm_connector_state *conn_state,
1802	const struct link_config_limits *limits)
1803	{
1804	int bpp, i, lane_count, clock = intel_dp_mode_clock(crtc_state: pipe_config, conn_state);
1805	int mode_rate, link_rate, link_avail;
1806
1807	for (bpp = fxp_q4_to_int(val_q4: limits->link.max_bpp_x16);
1808	bpp >= fxp_q4_to_int(val_q4: limits->link.min_bpp_x16);
1809	bpp -= 2 * 3) {
1810	int link_bpp = intel_dp_output_bpp(output_format: pipe_config->output_format, bpp);
1811
1812	mode_rate = intel_dp_link_required(pixel_clock: clock, bpp: link_bpp);
1813
1814	for (i = 0; i < intel_dp->num_common_rates; i++) {
1815	link_rate = intel_dp_common_rate(intel_dp, index: i);
1816	if (link_rate < limits->min_rate ||
1817	link_rate > limits->max_rate)
1818	continue;
1819
1820	for (lane_count = limits->min_lane_count;
1821	lane_count <= limits->max_lane_count;
1822	lane_count <<= 1) {
1823	link_avail = intel_dp_max_link_data_rate(intel_dp,
1824	max_dprx_rate: link_rate,
1825	max_dprx_lanes: lane_count);
1826
1827
1828	if (mode_rate <= link_avail) {
1829	pipe_config->lane_count = lane_count;
1830	pipe_config->pipe_bpp = bpp;
1831	pipe_config->port_clock = link_rate;
1832
1833	return 0;
1834	}
1835	}
1836	}
1837	}
1838
1839	return -EINVAL;
1840	}
1841
1842	int intel_dp_dsc_max_src_input_bpc(struct intel_display *display)
1843	{
1844	/* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
1845	if (DISPLAY_VER(display) >= 12)
1846	return 12;
1847	if (DISPLAY_VER(display) == 11)
1848	return 10;
1849
1850	return intel_dp_dsc_min_src_input_bpc();
1851	}
1852
1853	int intel_dp_dsc_compute_max_bpp(const struct intel_connector *connector,
1854	u8 max_req_bpc)
1855	{
1856	struct intel_display *display = to_intel_display(connector);
1857	int i, num_bpc;
1858	u8 dsc_bpc[3] = {};
1859	int dsc_max_bpc;
1860
1861	dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(display);
1862
1863	if (!dsc_max_bpc)
1864	return dsc_max_bpc;
1865
1866	dsc_max_bpc = min(dsc_max_bpc, max_req_bpc);
1867
1868	num_bpc = drm_dp_dsc_sink_supported_input_bpcs(dsc_dpc: connector->dp.dsc_dpcd,
1869	dsc_bpc);
1870	for (i = 0; i < num_bpc; i++) {
1871	if (dsc_max_bpc >= dsc_bpc[i])
1872	return dsc_bpc[i] * 3;
1873	}
1874
1875	return 0;
1876	}
1877
1878	static int intel_dp_source_dsc_version_minor(struct intel_display *display)
1879	{
1880	return DISPLAY_VER(display) >= 14 ? 2 : 1;
1881	}
1882
1883	static int intel_dp_sink_dsc_version_minor(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
1884	{
1885	return (dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & DP_DSC_MINOR_MASK) >>
1886	DP_DSC_MINOR_SHIFT;
1887	}
1888
1889	static int intel_dp_get_slice_height(int vactive)
1890	{
1891	int slice_height;
1892
1893	/*
1894	* VDSC 1.2a spec in Section 3.8 Options for Slices implies that 108
1895	* lines is an optimal slice height, but any size can be used as long as
1896	* vertical active integer multiple and maximum vertical slice count
1897	* requirements are met.
1898	*/
1899	for (slice_height = 108; slice_height <= vactive; slice_height += 2)
1900	if (vactive % slice_height == 0)
1901	return slice_height;
1902
1903	/*
1904	* Highly unlikely we reach here as most of the resolutions will end up
1905	* finding appropriate slice_height in above loop but returning
1906	* slice_height as 2 here as it should work with all resolutions.
1907	*/
1908	return 2;
1909	}
1910
1911	static int intel_dp_dsc_compute_params(const struct intel_connector *connector,
1912	struct intel_crtc_state *crtc_state)
1913	{
1914	struct intel_display *display = to_intel_display(connector);
1915	struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
1916	int ret;
1917
1918	/*
1919	* RC_MODEL_SIZE is currently a constant across all configurations.
1920	*
1921	* FIXME: Look into using sink defined DPCD DP_DSC_RC_BUF_BLK_SIZE and
1922	* DP_DSC_RC_BUF_SIZE for this.
1923	*/
1924	vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
1925	vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay;
1926
1927	vdsc_cfg->slice_height = intel_dp_get_slice_height(vactive: vdsc_cfg->pic_height);
1928
1929	ret = intel_dsc_compute_params(pipe_config: crtc_state);
1930	if (ret)
1931	return ret;
1932
1933	vdsc_cfg->dsc_version_major =
1934	(connector->dp.dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
1935	DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
1936	vdsc_cfg->dsc_version_minor =
1937	min(intel_dp_source_dsc_version_minor(display),
1938	intel_dp_sink_dsc_version_minor(connector->dp.dsc_dpcd));
1939	if (vdsc_cfg->convert_rgb)
1940	vdsc_cfg->convert_rgb =
1941	connector->dp.dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
1942	DP_DSC_RGB;
1943
1944	vdsc_cfg->line_buf_depth = min(INTEL_DP_DSC_MAX_LINE_BUF_DEPTH,
1945	drm_dp_dsc_sink_line_buf_depth(connector->dp.dsc_dpcd));
1946	if (!vdsc_cfg->line_buf_depth) {
1947	drm_dbg_kms(display->drm,
1948	"DSC Sink Line Buffer Depth invalid\n");
1949	return -EINVAL;
1950	}
1951
1952	vdsc_cfg->block_pred_enable =
1953	connector->dp.dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] &
1954	DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
1955
1956	return drm_dsc_compute_rc_parameters(vdsc_cfg);
1957	}
1958
1959	static bool intel_dp_dsc_supports_format(const struct intel_connector *connector,
1960	enum intel_output_format output_format)
1961	{
1962	struct intel_display *display = to_intel_display(connector);
1963	u8 sink_dsc_format;
1964
1965	switch (output_format) {
1966	case INTEL_OUTPUT_FORMAT_RGB:
1967	sink_dsc_format = DP_DSC_RGB;
1968	break;
1969	case INTEL_OUTPUT_FORMAT_YCBCR444:
1970	sink_dsc_format = DP_DSC_YCbCr444;
1971	break;
1972	case INTEL_OUTPUT_FORMAT_YCBCR420:
1973	if (min(intel_dp_source_dsc_version_minor(display),
1974	intel_dp_sink_dsc_version_minor(connector->dp.dsc_dpcd)) < 2)
1975	return false;
1976	sink_dsc_format = DP_DSC_YCbCr420_Native;
1977	break;
1978	default:
1979	return false;
1980	}
1981
1982	return drm_dp_dsc_sink_supports_format(dsc_dpcd: connector->dp.dsc_dpcd, output_format: sink_dsc_format);
1983	}
1984
1985	static bool is_bw_sufficient_for_dsc_config(int dsc_bpp_x16, u32 link_clock,
1986	u32 lane_count, u32 mode_clock,
1987	enum intel_output_format output_format,
1988	int timeslots)
1989	{
1990	u32 available_bw, required_bw;
1991
1992	available_bw = (link_clock * lane_count * timeslots * 16) / 8;
1993	required_bw = dsc_bpp_x16 * (intel_dp_mode_to_fec_clock(mode_clock));
1994
1995	return available_bw > required_bw;
1996	}
1997
1998	static int dsc_compute_link_config(struct intel_dp *intel_dp,
1999	struct intel_crtc_state *pipe_config,
2000	struct drm_connector_state *conn_state,
2001	const struct link_config_limits *limits,
2002	int dsc_bpp_x16,
2003	int timeslots)
2004	{
2005	const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2006	int link_rate, lane_count;
2007	int i;
2008
2009	for (i = 0; i < intel_dp->num_common_rates; i++) {
2010	link_rate = intel_dp_common_rate(intel_dp, index: i);
2011	if (link_rate < limits->min_rate || link_rate > limits->max_rate)
2012	continue;
2013
2014	for (lane_count = limits->min_lane_count;
2015	lane_count <= limits->max_lane_count;
2016	lane_count <<= 1) {
2017
2018	/*
2019	* FIXME: intel_dp_mtp_tu_compute_config() requires
2020	* ->lane_count and ->port_clock set before we know
2021	* they'll work. If we end up failing altogether,
2022	* they'll remain in crtc state. This shouldn't matter,
2023	* as we'd then bail out from compute config, but it's
2024	* just ugly.
2025	*/
2026	pipe_config->lane_count = lane_count;
2027	pipe_config->port_clock = link_rate;
2028
2029	if (drm_dp_is_uhbr_rate(link_rate)) {
2030	int ret;
2031
2032	ret = intel_dp_mtp_tu_compute_config(intel_dp,
2033	crtc_state: pipe_config,
2034	conn_state,
2035	min_bpp_x16: dsc_bpp_x16,
2036	max_bpp_x16: dsc_bpp_x16,
2037	bpp_step_x16: 0, dsc: true);
2038	if (ret)
2039	continue;
2040	} else {
2041	if (!is_bw_sufficient_for_dsc_config(dsc_bpp_x16, link_clock: link_rate,
2042	lane_count, mode_clock: adjusted_mode->clock,
2043	output_format: pipe_config->output_format,
2044	timeslots))
2045	continue;
2046	}
2047
2048	return 0;
2049	}
2050	}
2051
2052	return -EINVAL;
2053	}
2054
2055	static
2056	u16 intel_dp_dsc_max_sink_compressed_bppx16(const struct intel_connector *connector,
2057	const struct intel_crtc_state *pipe_config,
2058	int bpc)
2059	{
2060	u16 max_bppx16 = drm_edp_dsc_sink_output_bpp(dsc_dpcd: connector->dp.dsc_dpcd);
2061
2062	if (max_bppx16)
2063	return max_bppx16;
2064	/*
2065	* If support not given in DPCD 67h, 68h use the Maximum Allowed bit rate
2066	* values as given in spec Table 2-157 DP v2.0
2067	*/
2068	switch (pipe_config->output_format) {
2069	case INTEL_OUTPUT_FORMAT_RGB:
2070	case INTEL_OUTPUT_FORMAT_YCBCR444:
2071	return (3 * bpc) << 4;
2072	case INTEL_OUTPUT_FORMAT_YCBCR420:
2073	return (3 * (bpc / 2)) << 4;
2074	default:
2075	MISSING_CASE(pipe_config->output_format);
2076	break;
2077	}
2078
2079	return 0;
2080	}
2081
2082	int intel_dp_dsc_sink_min_compressed_bpp(const struct intel_crtc_state *pipe_config)
2083	{
2084	/* From Mandatory bit rate range Support Table 2-157 (DP v2.0) */
2085	switch (pipe_config->output_format) {
2086	case INTEL_OUTPUT_FORMAT_RGB:
2087	case INTEL_OUTPUT_FORMAT_YCBCR444:
2088	return 8;
2089	case INTEL_OUTPUT_FORMAT_YCBCR420:
2090	return 6;
2091	default:
2092	MISSING_CASE(pipe_config->output_format);
2093	break;
2094	}
2095
2096	return 0;
2097	}
2098
2099	int intel_dp_dsc_sink_max_compressed_bpp(const struct intel_connector *connector,
2100	const struct intel_crtc_state *pipe_config,
2101	int bpc)
2102	{
2103	return intel_dp_dsc_max_sink_compressed_bppx16(connector,
2104	pipe_config, bpc) >> 4;
2105	}
2106
2107	int intel_dp_dsc_min_src_compressed_bpp(void)
2108	{
2109	/* Min Compressed bpp supported by source is 8 */
2110	return 8;
2111	}
2112
2113	static int dsc_src_max_compressed_bpp(struct intel_dp *intel_dp)
2114	{
2115	struct intel_display *display = to_intel_display(intel_dp);
2116
2117	/*
2118	* Forcing DSC and using the platform's max compressed bpp is seen to cause
2119	* underruns. Since DSC isn't needed in these cases, limit the
2120	* max compressed bpp to 18, which is a safe value across platforms with different
2121	* pipe bpps.
2122	*/
2123	if (intel_dp->force_dsc_en)
2124	return 18;
2125
2126	/*
2127	* Max Compressed bpp for Gen 13+ is 27bpp.
2128	* For earlier platform is 23bpp. (Bspec:49259).
2129	*/
2130	if (DISPLAY_VER(display) < 13)
2131	return 23;
2132	else
2133	return 27;
2134	}
2135
2136	/*
2137	* Note: for pre-13 display you still need to check the validity of each step.
2138	*/
2139	int intel_dp_dsc_bpp_step_x16(const struct intel_connector *connector)
2140	{
2141	struct intel_display *display = to_intel_display(connector);
2142	u8 incr = drm_dp_dsc_sink_bpp_incr(dsc_dpcd: connector->dp.dsc_dpcd);
2143
2144	if (DISPLAY_VER(display) < 14 || !incr)
2145	return fxp_q4_from_int(val_int: 1);
2146
2147	if (connector->mst.dp &&
2148	!connector->link.force_bpp_x16 && !connector->mst.dp->force_dsc_fractional_bpp_en)
2149	return fxp_q4_from_int(val_int: 1);
2150
2151	/* fxp q4 */
2152	return fxp_q4_from_int(val_int: 1) / incr;
2153	}
2154
2155	/*
2156	* Note: for bpp_x16 to be valid it must be also within the source/sink's
2157	* min..max bpp capability range.
2158	*/
2159	bool intel_dp_dsc_valid_compressed_bpp(struct intel_dp *intel_dp, int bpp_x16)
2160	{
2161	struct intel_display *display = to_intel_display(intel_dp);
2162	int i;
2163
2164	if (DISPLAY_VER(display) >= 13) {
2165	if (intel_dp->force_dsc_fractional_bpp_en && !fxp_q4_to_frac(val_q4: bpp_x16))
2166	return false;
2167
2168	return true;
2169	}
2170
2171	if (fxp_q4_to_frac(val_q4: bpp_x16))
2172	return false;
2173
2174	for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp); i++) {
2175	if (fxp_q4_to_int(val_q4: bpp_x16) == valid_dsc_bpp[i])
2176	return true;
2177	}
2178
2179	return false;
2180	}
2181
2182	/*
2183	* Find the max compressed BPP we can find a link configuration for. The BPPs to
2184	* try depend on the source (platform) and sink.
2185	*/
2186	static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp,
2187	struct intel_crtc_state *pipe_config,
2188	struct drm_connector_state *conn_state,
2189	const struct link_config_limits *limits,
2190	int pipe_bpp,
2191	int timeslots)
2192	{
2193	struct intel_display *display = to_intel_display(intel_dp);
2194	const struct intel_connector *connector = to_intel_connector(conn_state->connector);
2195	const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2196	int output_bpp;
2197	int min_bpp_x16, max_bpp_x16, bpp_step_x16;
2198	int dsc_joiner_max_bpp;
2199	int num_joined_pipes = intel_crtc_num_joined_pipes(crtc_state: pipe_config);
2200	int bpp_x16;
2201	int ret;
2202
2203	dsc_joiner_max_bpp = get_max_compressed_bpp_with_joiner(display, mode_clock: adjusted_mode->clock,
2204	mode_hdisplay: adjusted_mode->hdisplay,
2205	num_joined_pipes);
2206	max_bpp_x16 = min(fxp_q4_from_int(dsc_joiner_max_bpp), limits->link.max_bpp_x16);
2207
2208	bpp_step_x16 = intel_dp_dsc_bpp_step_x16(connector);
2209
2210	/* Compressed BPP should be less than the Input DSC bpp */
2211	output_bpp = intel_dp_output_bpp(output_format: pipe_config->output_format, bpp: pipe_bpp);
2212	max_bpp_x16 = min(max_bpp_x16, fxp_q4_from_int(output_bpp) - bpp_step_x16);
2213
2214	drm_WARN_ON(display->drm, !is_power_of_2(bpp_step_x16));
2215	min_bpp_x16 = round_up(limits->link.min_bpp_x16, bpp_step_x16);
2216	max_bpp_x16 = round_down(max_bpp_x16, bpp_step_x16);
2217
2218	for (bpp_x16 = max_bpp_x16; bpp_x16 >= min_bpp_x16; bpp_x16 -= bpp_step_x16) {
2219	if (!intel_dp_dsc_valid_compressed_bpp(intel_dp, bpp_x16))
2220	continue;
2221
2222	ret = dsc_compute_link_config(intel_dp,
2223	pipe_config,
2224	conn_state,
2225	limits,
2226	dsc_bpp_x16: bpp_x16,
2227	timeslots);
2228	if (ret == 0) {
2229	pipe_config->dsc.compressed_bpp_x16 = bpp_x16;
2230	if (intel_dp->force_dsc_fractional_bpp_en &&
2231	fxp_q4_to_frac(val_q4: bpp_x16))
2232	drm_dbg_kms(display->drm,
2233	"Forcing DSC fractional bpp\n");
2234
2235	return 0;
2236	}
2237	}
2238
2239	return -EINVAL;
2240	}
2241
2242	int intel_dp_dsc_min_src_input_bpc(void)
2243	{
2244	/* Min DSC Input BPC for ICL+ is 8 */
2245	return 8;
2246	}
2247
2248	static
2249	bool is_dsc_pipe_bpp_sufficient(const struct link_config_limits *limits,
2250	int pipe_bpp)
2251	{
2252	return pipe_bpp >= limits->pipe.min_bpp &&
2253	pipe_bpp <= limits->pipe.max_bpp;
2254	}
2255
2256	static
2257	int intel_dp_force_dsc_pipe_bpp(struct intel_dp *intel_dp,
2258	const struct link_config_limits *limits)
2259	{
2260	struct intel_display *display = to_intel_display(intel_dp);
2261	int forced_bpp;
2262
2263	if (!intel_dp->force_dsc_bpc)
2264	return 0;
2265
2266	forced_bpp = intel_dp->force_dsc_bpc * 3;
2267
2268	if (is_dsc_pipe_bpp_sufficient(limits, pipe_bpp: forced_bpp)) {
2269	drm_dbg_kms(display->drm, "Input DSC BPC forced to %d\n",
2270	intel_dp->force_dsc_bpc);
2271	return forced_bpp;
2272	}
2273
2274	drm_dbg_kms(display->drm,
2275	"Cannot force DSC BPC:%d, due to DSC BPC limits\n",
2276	intel_dp->force_dsc_bpc);
2277
2278	return 0;
2279	}
2280
2281	static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
2282	struct intel_crtc_state *pipe_config,
2283	struct drm_connector_state *conn_state,
2284	const struct link_config_limits *limits,
2285	int timeslots)
2286	{
2287	const struct intel_connector *connector =
2288	to_intel_connector(conn_state->connector);
2289	u8 dsc_bpc[3] = {};
2290	int forced_bpp, pipe_bpp;
2291	int num_bpc, i, ret;
2292
2293	forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, limits);
2294
2295	if (forced_bpp) {
2296	ret = dsc_compute_compressed_bpp(intel_dp, pipe_config, conn_state,
2297	limits, pipe_bpp: forced_bpp, timeslots);
2298	if (ret == 0) {
2299	pipe_config->pipe_bpp = forced_bpp;
2300	return 0;
2301	}
2302	}
2303
2304	/*
2305	* Get the maximum DSC bpc that will be supported by any valid
2306	* link configuration and compressed bpp.
2307	*/
2308	num_bpc = drm_dp_dsc_sink_supported_input_bpcs(dsc_dpc: connector->dp.dsc_dpcd, dsc_bpc);
2309	for (i = 0; i < num_bpc; i++) {
2310	pipe_bpp = dsc_bpc[i] * 3;
2311	if (pipe_bpp < limits->pipe.min_bpp || pipe_bpp > limits->pipe.max_bpp)
2312	continue;
2313
2314	ret = dsc_compute_compressed_bpp(intel_dp, pipe_config, conn_state,
2315	limits, pipe_bpp, timeslots);
2316	if (ret == 0) {
2317	pipe_config->pipe_bpp = pipe_bpp;
2318	return 0;
2319	}
2320	}
2321
2322	return -EINVAL;
2323	}
2324
2325	static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
2326	struct intel_crtc_state *pipe_config,
2327	struct drm_connector_state *conn_state,
2328	const struct link_config_limits *limits)
2329	{
2330	struct intel_display *display = to_intel_display(intel_dp);
2331	struct intel_connector *connector =
2332	to_intel_connector(conn_state->connector);
2333	int pipe_bpp, forced_bpp;
2334	int dsc_min_bpp;
2335	int dsc_max_bpp;
2336
2337	forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, limits);
2338
2339	if (forced_bpp) {
2340	pipe_bpp = forced_bpp;
2341	} else {
2342	int max_bpc = limits->pipe.max_bpp / 3;
2343
2344	/* For eDP use max bpp that can be supported with DSC. */
2345	pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, max_req_bpc: max_bpc);
2346	if (!is_dsc_pipe_bpp_sufficient(limits, pipe_bpp)) {
2347	drm_dbg_kms(display->drm,
2348	"Computed BPC is not in DSC BPC limits\n");
2349	return -EINVAL;
2350	}
2351	}
2352	pipe_config->port_clock = limits->max_rate;
2353	pipe_config->lane_count = limits->max_lane_count;
2354
2355	dsc_min_bpp = fxp_q4_to_int_roundup(val_q4: limits->link.min_bpp_x16);
2356
2357	dsc_max_bpp = fxp_q4_to_int(val_q4: limits->link.max_bpp_x16);
2358
2359	/* Compressed BPP should be less than the Input DSC bpp */
2360	dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);
2361
2362	pipe_config->dsc.compressed_bpp_x16 =
2363	fxp_q4_from_int(max(dsc_min_bpp, dsc_max_bpp));
2364
2365	pipe_config->pipe_bpp = pipe_bpp;
2366
2367	return 0;
2368	}
2369
2370	/*
2371	* Return whether FEC must be enabled for 8b10b SST or MST links. On 128b132b
2372	* links FEC is always enabled implicitly by the HW, so this function returns
2373	* false for that case.
2374	*/
2375	bool intel_dp_needs_8b10b_fec(const struct intel_crtc_state *crtc_state,
2376	bool dsc_enabled_on_crtc)
2377	{
2378	if (intel_dp_is_uhbr(crtc_state))
2379	return false;
2380
2381	/*
2382	* Though eDP v1.5 supports FEC with DSC, unlike DP, it is optional.
2383	* Since, FEC is a bandwidth overhead, continue to not enable it for
2384	* eDP. Until, there is a good reason to do so.
2385	*/
2386	if (intel_crtc_has_type(crtc_state, type: INTEL_OUTPUT_EDP))
2387	return false;
2388
2389	return dsc_enabled_on_crtc || intel_dsc_enabled_on_link(crtc_state);
2390	}
2391
2392	int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
2393	struct intel_crtc_state *pipe_config,
2394	struct drm_connector_state *conn_state,
2395	const struct link_config_limits *limits,
2396	int timeslots)
2397	{
2398	struct intel_display *display = to_intel_display(intel_dp);
2399	const struct intel_connector *connector =
2400	to_intel_connector(conn_state->connector);
2401	const struct drm_display_mode *adjusted_mode =
2402	&pipe_config->hw.adjusted_mode;
2403	int num_joined_pipes = intel_crtc_num_joined_pipes(crtc_state: pipe_config);
2404	bool is_mst = intel_crtc_has_type(crtc_state: pipe_config, type: INTEL_OUTPUT_DP_MST);
2405	int ret;
2406
2407	/*
2408	* FIXME: set the FEC enabled state once pipe_config->port_clock is
2409	* already known, so the UHBR/non-UHBR mode can be determined.
2410	*/
2411	pipe_config->fec_enable = intel_dp_needs_8b10b_fec(crtc_state: pipe_config, dsc_enabled_on_crtc: true);
2412
2413	if (!intel_dp_dsc_supports_format(connector, output_format: pipe_config->output_format))
2414	return -EINVAL;
2415
2416	/*
2417	* Link parameters, pipe bpp and compressed bpp have already been
2418	* figured out for DP MST DSC.
2419	*/
2420	if (!is_mst) {
2421	if (intel_dp_is_edp(intel_dp))
2422	ret = intel_edp_dsc_compute_pipe_bpp(intel_dp, pipe_config,
2423	conn_state, limits);
2424	else
2425	ret = intel_dp_dsc_compute_pipe_bpp(intel_dp, pipe_config,
2426	conn_state, limits, timeslots);
2427	if (ret) {
2428	drm_dbg_kms(display->drm,
2429	"No Valid pipe bpp for given mode ret = %d\n", ret);
2430	return ret;
2431	}
2432	}
2433
2434	/* Calculate Slice count */
2435	if (intel_dp_is_edp(intel_dp)) {
2436	pipe_config->dsc.slice_count =
2437	drm_dp_dsc_sink_max_slice_count(dsc_dpcd: connector->dp.dsc_dpcd,
2438	is_edp: true);
2439	if (!pipe_config->dsc.slice_count) {
2440	drm_dbg_kms(display->drm,
2441	"Unsupported Slice Count %d\n",
2442	pipe_config->dsc.slice_count);
2443	return -EINVAL;
2444	}
2445	} else {
2446	u8 dsc_dp_slice_count;
2447
2448	dsc_dp_slice_count =
2449	intel_dp_dsc_get_slice_count(connector,
2450	mode_clock: adjusted_mode->crtc_clock,
2451	mode_hdisplay: adjusted_mode->crtc_hdisplay,
2452	num_joined_pipes);
2453	if (!dsc_dp_slice_count) {
2454	drm_dbg_kms(display->drm,
2455	"Compressed Slice Count not supported\n");
2456	return -EINVAL;
2457	}
2458
2459	pipe_config->dsc.slice_count = dsc_dp_slice_count;
2460	}
2461	/*
2462	* VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
2463	* is greater than the maximum Cdclock and if slice count is even
2464	* then we need to use 2 VDSC instances.
2465	* In case of Ultrajoiner along with 12 slices we need to use 3
2466	* VDSC instances.
2467	*/
2468	if (pipe_config->joiner_pipes && num_joined_pipes == 4 &&
2469	pipe_config->dsc.slice_count == 12)
2470	pipe_config->dsc.num_streams = 3;
2471	else if (pipe_config->joiner_pipes || pipe_config->dsc.slice_count > 1)
2472	pipe_config->dsc.num_streams = 2;
2473	else
2474	pipe_config->dsc.num_streams = 1;
2475
2476	ret = intel_dp_dsc_compute_params(connector, crtc_state: pipe_config);
2477	if (ret < 0) {
2478	drm_dbg_kms(display->drm,
2479	"Cannot compute valid DSC parameters for Input Bpp = %d"
2480	"Compressed BPP = " FXP_Q4_FMT "\n",
2481	pipe_config->pipe_bpp,
2482	FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16));
2483	return ret;
2484	}
2485
2486	intel_dsc_enable_on_crtc(crtc_state: pipe_config);
2487
2488	drm_dbg_kms(display->drm, "DP DSC computed with Input Bpp = %d "
2489	"Compressed Bpp = " FXP_Q4_FMT " Slice Count = %d\n",
2490	pipe_config->pipe_bpp,
2491	FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16),
2492	pipe_config->dsc.slice_count);
2493
2494	return 0;
2495	}
2496
2497	static int
2498	dsc_throughput_quirk_max_bpp_x16(const struct intel_connector *connector,
2499	const struct intel_crtc_state *crtc_state)
2500	{
2501	const struct drm_display_mode *adjusted_mode =
2502	&crtc_state->hw.adjusted_mode;
2503
2504	if (!connector->dp.dsc_throughput_quirk)
2505	return INT_MAX;
2506
2507	/*
2508	* Synaptics Panamera branch devices have a problem decompressing a
2509	* stream with a compressed link-bpp higher than 12, if the pixel
2510	* clock is higher than ~50 % of the maximum overall throughput
2511	* reported by the branch device. Work around this by limiting the
2512	* maximum link bpp for such pixel clocks.
2513	*
2514	* TODO: Use the throughput value specific to the actual RGB/YUV
2515	* format of the output, after determining the pixel clock limit for
2516	* YUV modes. For now use the smaller of the throughput values, which
2517	* may result in limiting the link-bpp value already at a lower than
2518	* required mode clock in case of native YUV422/420 output formats.
2519	* The RGB/YUV444 throughput value should be always either equal or
2520	* smaller than the YUV422/420 value, but let's not depend on this
2521	* assumption.
2522	*/
2523	if (adjusted_mode->crtc_clock <
2524	min(connector->dp.dsc_branch_caps.overall_throughput.rgb_yuv444,
2525	connector->dp.dsc_branch_caps.overall_throughput.yuv422_420) / 2)
2526	return INT_MAX;
2527
2528	return fxp_q4_from_int(val_int: 12);
2529	}
2530
2531	/*
2532	* Calculate the output link min, max bpp values in limits based on the pipe bpp
2533	* range, crtc_state and dsc mode. Return true on success.
2534	*/
2535	static bool
2536	intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp,
2537	const struct intel_connector *connector,
2538	const struct intel_crtc_state *crtc_state,
2539	bool dsc,
2540	struct link_config_limits *limits)
2541	{
2542	struct intel_display *display = to_intel_display(intel_dp);
2543	const struct drm_display_mode *adjusted_mode =
2544	&crtc_state->hw.adjusted_mode;
2545	const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2546	const struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
2547	int max_link_bpp_x16;
2548
2549	max_link_bpp_x16 = min(crtc_state->max_link_bpp_x16,
2550	fxp_q4_from_int(limits->pipe.max_bpp));
2551
2552	if (!dsc) {
2553	max_link_bpp_x16 = rounddown(max_link_bpp_x16, fxp_q4_from_int(2 * 3));
2554
2555	if (max_link_bpp_x16 < fxp_q4_from_int(val_int: limits->pipe.min_bpp))
2556	return false;
2557
2558	limits->link.min_bpp_x16 = fxp_q4_from_int(val_int: limits->pipe.min_bpp);
2559	} else {
2560	int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp;
2561	int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp;
2562	int throughput_max_bpp_x16;
2563
2564	dsc_src_min_bpp = intel_dp_dsc_min_src_compressed_bpp();
2565	dsc_sink_min_bpp = intel_dp_dsc_sink_min_compressed_bpp(pipe_config: crtc_state);
2566	dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp);
2567	limits->link.min_bpp_x16 = fxp_q4_from_int(val_int: dsc_min_bpp);
2568
2569	dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);
2570	dsc_sink_max_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector,
2571	pipe_config: crtc_state,
2572	bpc: limits->pipe.max_bpp / 3);
2573	dsc_max_bpp = dsc_sink_max_bpp ?
2574	min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp;
2575
2576	max_link_bpp_x16 = min(max_link_bpp_x16, fxp_q4_from_int(dsc_max_bpp));
2577
2578	throughput_max_bpp_x16 = dsc_throughput_quirk_max_bpp_x16(connector, crtc_state);
2579	throughput_max_bpp_x16 = clamp(throughput_max_bpp_x16,
2580	limits->link.min_bpp_x16, max_link_bpp_x16);
2581	if (throughput_max_bpp_x16 < max_link_bpp_x16) {
2582	max_link_bpp_x16 = throughput_max_bpp_x16;
2583
2584	drm_dbg_kms(display->drm,
2585	"[CRTC:%d:%s][CONNECTOR:%d:%s] Decreasing link max bpp to " FXP_Q4_FMT " due to DSC throughput quirk\n",
2586	crtc->base.base.id, crtc->base.name,
2587	connector->base.base.id, connector->base.name,
2588	FXP_Q4_ARGS(max_link_bpp_x16));
2589	}
2590	}
2591
2592	limits->link.max_bpp_x16 = max_link_bpp_x16;
2593
2594	drm_dbg_kms(display->drm,
2595	"[ENCODER:%d:%s][CRTC:%d:%s] DP link limits: pixel clock %d kHz DSC %s max lanes %d max rate %d max pipe_bpp %d max link_bpp " FXP_Q4_FMT "\n",
2596	encoder->base.base.id, encoder->base.name,
2597	crtc->base.base.id, crtc->base.name,
2598	adjusted_mode->crtc_clock,
2599	str_on_off(dsc),
2600	limits->max_lane_count,
2601	limits->max_rate,
2602	limits->pipe.max_bpp,
2603	FXP_Q4_ARGS(limits->link.max_bpp_x16));
2604
2605	return true;
2606	}
2607
2608	static void
2609	intel_dp_dsc_compute_pipe_bpp_limits(struct intel_dp *intel_dp,
2610	struct link_config_limits *limits)
2611	{
2612	struct intel_display *display = to_intel_display(intel_dp);
2613	int dsc_min_bpc = intel_dp_dsc_min_src_input_bpc();
2614	int dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(display);
2615
2616	limits->pipe.max_bpp = clamp(limits->pipe.max_bpp, dsc_min_bpc * 3, dsc_max_bpc * 3);
2617	limits->pipe.min_bpp = clamp(limits->pipe.min_bpp, dsc_min_bpc * 3, dsc_max_bpc * 3);
2618	}
2619
2620	bool
2621	intel_dp_compute_config_limits(struct intel_dp *intel_dp,
2622	struct drm_connector_state *conn_state,
2623	struct intel_crtc_state *crtc_state,
2624	bool respect_downstream_limits,
2625	bool dsc,
2626	struct link_config_limits *limits)
2627	{
2628	bool is_mst = intel_crtc_has_type(crtc_state, type: INTEL_OUTPUT_DP_MST);
2629	struct intel_connector *connector =
2630	to_intel_connector(conn_state->connector);
2631
2632	limits->min_rate = intel_dp_min_link_rate(intel_dp);
2633	limits->max_rate = intel_dp_max_link_rate(intel_dp);
2634
2635	limits->min_rate = min(limits->min_rate, limits->max_rate);
2636
2637	limits->min_lane_count = intel_dp_min_lane_count(intel_dp);
2638	limits->max_lane_count = intel_dp_max_lane_count(intel_dp);
2639
2640	limits->pipe.min_bpp = intel_dp_in_hdr_mode(conn_state) ? 30 :
2641	intel_dp_min_bpp(output_format: crtc_state->output_format);
2642	if (is_mst) {
2643	/*
2644	* FIXME: If all the streams can't fit into the link with their
2645	* current pipe_bpp we should reduce pipe_bpp across the board
2646	* until things start to fit. Until then we limit to <= 8bpc
2647	* since that's what was hardcoded for all MST streams
2648	* previously. This hack should be removed once we have the
2649	* proper retry logic in place.
2650	*/
2651	limits->pipe.max_bpp = min(crtc_state->pipe_bpp, 24);
2652	} else {
2653	limits->pipe.max_bpp = intel_dp_max_bpp(intel_dp, crtc_state,
2654	respect_downstream_limits);
2655	}
2656
2657	if (dsc)
2658	intel_dp_dsc_compute_pipe_bpp_limits(intel_dp, limits);
2659
2660	if (is_mst || intel_dp->use_max_params) {
2661	/*
2662	* For MST we always configure max link bw - the spec doesn't
2663	* seem to suggest we should do otherwise.
2664	*
2665	* Use the maximum clock and number of lanes the eDP panel
2666	* advertizes being capable of in case the initial fast
2667	* optimal params failed us. The panels are generally
2668	* designed to support only a single clock and lane
2669	* configuration, and typically on older panels these
2670	* values correspond to the native resolution of the panel.
2671	*/
2672	limits->min_lane_count = limits->max_lane_count;
2673	limits->min_rate = limits->max_rate;
2674	}
2675
2676	intel_dp_test_compute_config(intel_dp, pipe_config: crtc_state, limits);
2677
2678	return intel_dp_compute_config_link_bpp_limits(intel_dp,
2679	connector,
2680	crtc_state,
2681	dsc,
2682	limits);
2683	}
2684
2685	int intel_dp_config_required_rate(const struct intel_crtc_state *crtc_state)
2686	{
2687	const struct drm_display_mode *adjusted_mode =
2688	&crtc_state->hw.adjusted_mode;
2689	int bpp = crtc_state->dsc.compression_enable ?
2690	fxp_q4_to_int_roundup(val_q4: crtc_state->dsc.compressed_bpp_x16) :
2691	crtc_state->pipe_bpp;
2692
2693	return intel_dp_link_required(pixel_clock: adjusted_mode->crtc_clock, bpp);
2694	}
2695
2696	bool intel_dp_joiner_needs_dsc(struct intel_display *display,
2697	int num_joined_pipes)
2698	{
2699	/*
2700	* Pipe joiner needs compression up to display 12 due to bandwidth
2701	* limitation. DG2 onwards pipe joiner can be enabled without
2702	* compression.
2703	* Ultrajoiner always needs compression.
2704	*/
2705	return (!HAS_UNCOMPRESSED_JOINER(display) && num_joined_pipes == 2) ||
2706	num_joined_pipes == 4;
2707	}
2708
2709	static int
2710	intel_dp_compute_link_config(struct intel_encoder *encoder,
2711	struct intel_crtc_state *pipe_config,
2712	struct drm_connector_state *conn_state,
2713	bool respect_downstream_limits)
2714	{
2715	struct intel_display *display = to_intel_display(encoder);
2716	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
2717	struct intel_connector *connector =
2718	to_intel_connector(conn_state->connector);
2719	const struct drm_display_mode *adjusted_mode =
2720	&pipe_config->hw.adjusted_mode;
2721	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2722	struct link_config_limits limits;
2723	bool dsc_needed, joiner_needs_dsc;
2724	int num_joined_pipes;
2725	int ret = 0;
2726
2727	if (pipe_config->fec_enable &&
2728	!intel_dp_supports_fec(intel_dp, connector, pipe_config))
2729	return -EINVAL;
2730
2731	num_joined_pipes = intel_dp_num_joined_pipes(intel_dp, connector,
2732	hdisplay: adjusted_mode->crtc_hdisplay,
2733	clock: adjusted_mode->crtc_clock);
2734	if (num_joined_pipes > 1)
2735	pipe_config->joiner_pipes = GENMASK(crtc->pipe + num_joined_pipes - 1, crtc->pipe);
2736
2737	joiner_needs_dsc = intel_dp_joiner_needs_dsc(display, num_joined_pipes);
2738
2739	dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en ||
2740	!intel_dp_compute_config_limits(intel_dp, conn_state, crtc_state: pipe_config,
2741	respect_downstream_limits,
2742	dsc: false,
2743	limits: &limits);
2744
2745	if (!dsc_needed) {
2746	/*
2747	* Optimize for slow and wide for everything, because there are some
2748	* eDP 1.3 and 1.4 panels don't work well with fast and narrow.
2749	*/
2750	ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config,
2751	conn_state, limits: &limits);
2752	if (!ret && intel_dp_is_uhbr(crtc_state: pipe_config))
2753	ret = intel_dp_mtp_tu_compute_config(intel_dp,
2754	crtc_state: pipe_config,
2755	conn_state,
2756	min_bpp_x16: fxp_q4_from_int(val_int: pipe_config->pipe_bpp),
2757	max_bpp_x16: fxp_q4_from_int(val_int: pipe_config->pipe_bpp),
2758	bpp_step_x16: 0, dsc: false);
2759	if (ret)
2760	dsc_needed = true;
2761	}
2762
2763	if (dsc_needed && !intel_dp_supports_dsc(intel_dp, connector, crtc_state: pipe_config)) {
2764	drm_dbg_kms(display->drm, "DSC required but not available\n");
2765	return -EINVAL;
2766	}
2767
2768	if (dsc_needed) {
2769	drm_dbg_kms(display->drm,
2770	"Try DSC (fallback=%s, joiner=%s, force=%s)\n",
2771	str_yes_no(ret), str_yes_no(joiner_needs_dsc),
2772	str_yes_no(intel_dp->force_dsc_en));
2773
2774	if (!intel_dp_compute_config_limits(intel_dp, conn_state, crtc_state: pipe_config,
2775	respect_downstream_limits,
2776	dsc: true,
2777	limits: &limits))
2778	return -EINVAL;
2779
2780	ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
2781	conn_state, limits: &limits, timeslots: 64);
2782	if (ret < 0)
2783	return ret;
2784	}
2785
2786	drm_dbg_kms(display->drm,
2787	"DP lane count %d clock %d bpp input %d compressed " FXP_Q4_FMT " link rate required %d available %d\n",
2788	pipe_config->lane_count, pipe_config->port_clock,
2789	pipe_config->pipe_bpp,
2790	FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16),
2791	intel_dp_config_required_rate(pipe_config),
2792	intel_dp_max_link_data_rate(intel_dp,
2793	pipe_config->port_clock,
2794	pipe_config->lane_count));
2795
2796	return 0;
2797	}
2798
2799	bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
2800	const struct drm_connector_state *conn_state)
2801	{
2802	const struct intel_digital_connector_state *intel_conn_state =
2803	to_intel_digital_connector_state(conn_state);
2804	const struct drm_display_mode *adjusted_mode =
2805	&crtc_state->hw.adjusted_mode;
2806
2807	/*
2808	* Our YCbCr output is always limited range.
2809	* crtc_state->limited_color_range only applies to RGB,
2810	* and it must never be set for YCbCr or we risk setting
2811	* some conflicting bits in TRANSCONF which will mess up
2812	* the colors on the monitor.
2813	*/
2814	if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
2815	return false;
2816
2817	if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2818	/*
2819	* See:
2820	* CEA-861-E - 5.1 Default Encoding Parameters
2821	* VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
2822	*/
2823	return crtc_state->pipe_bpp != 18 &&
2824	drm_default_rgb_quant_range(mode: adjusted_mode) ==
2825	HDMI_QUANTIZATION_RANGE_LIMITED;
2826	} else {
2827	return intel_conn_state->broadcast_rgb ==
2828	INTEL_BROADCAST_RGB_LIMITED;
2829	}
2830	}
2831
2832	static bool intel_dp_port_has_audio(struct intel_display *display, enum port port)
2833	{
2834	if (display->platform.g4x)
2835	return false;
2836	if (DISPLAY_VER(display) < 12 && port == PORT_A)
2837	return false;
2838
2839	return true;
2840	}
2841
2842	static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc_state,
2843	const struct drm_connector_state *conn_state,
2844	struct drm_dp_vsc_sdp *vsc)
2845	{
2846	struct intel_display *display = to_intel_display(crtc_state);
2847
2848	if (crtc_state->has_panel_replay) {
2849	/*
2850	* Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
2851	* VSC SDP supporting 3D stereo, Panel Replay, and Pixel
2852	* Encoding/Colorimetry Format indication.
2853	*/
2854	vsc->revision = 0x7;
2855	} else {
2856	/*
2857	* Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
2858	* VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
2859	* Colorimetry Format indication.
2860	*/
2861	vsc->revision = 0x5;
2862	}
2863
2864	vsc->length = 0x13;
2865
2866	/* DP 1.4a spec, Table 2-120 */
2867	switch (crtc_state->output_format) {
2868	case INTEL_OUTPUT_FORMAT_YCBCR444:
2869	vsc->pixelformat = DP_PIXELFORMAT_YUV444;
2870	break;
2871	case INTEL_OUTPUT_FORMAT_YCBCR420:
2872	vsc->pixelformat = DP_PIXELFORMAT_YUV420;
2873	break;
2874	case INTEL_OUTPUT_FORMAT_RGB:
2875	default:
2876	vsc->pixelformat = DP_PIXELFORMAT_RGB;
2877	}
2878
2879	switch (conn_state->colorspace) {
2880	case DRM_MODE_COLORIMETRY_BT709_YCC:
2881	vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
2882	break;
2883	case DRM_MODE_COLORIMETRY_XVYCC_601:
2884	vsc->colorimetry = DP_COLORIMETRY_XVYCC_601;
2885	break;
2886	case DRM_MODE_COLORIMETRY_XVYCC_709:
2887	vsc->colorimetry = DP_COLORIMETRY_XVYCC_709;
2888	break;
2889	case DRM_MODE_COLORIMETRY_SYCC_601:
2890	vsc->colorimetry = DP_COLORIMETRY_SYCC_601;
2891	break;
2892	case DRM_MODE_COLORIMETRY_OPYCC_601:
2893	vsc->colorimetry = DP_COLORIMETRY_OPYCC_601;
2894	break;
2895	case DRM_MODE_COLORIMETRY_BT2020_CYCC:
2896	vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC;
2897	break;
2898	case DRM_MODE_COLORIMETRY_BT2020_RGB:
2899	vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB;
2900	break;
2901	case DRM_MODE_COLORIMETRY_BT2020_YCC:
2902	vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC;
2903	break;
2904	case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
2905	case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
2906	vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB;
2907	break;
2908	default:
2909	/*
2910	* RGB->YCBCR color conversion uses the BT.709
2911	* color space.
2912	*/
2913	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
2914	vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
2915	else
2916	vsc->colorimetry = DP_COLORIMETRY_DEFAULT;
2917	break;
2918	}
2919
2920	vsc->bpc = crtc_state->pipe_bpp / 3;
2921
2922	/* only RGB pixelformat supports 6 bpc */
2923	drm_WARN_ON(display->drm,
2924	vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB);
2925
2926	/* all YCbCr are always limited range */
2927	vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA;
2928	vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
2929	}
2930
2931	static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
2932	struct intel_crtc_state *crtc_state)
2933	{
2934	struct drm_dp_as_sdp *as_sdp = &crtc_state->infoframes.as_sdp;
2935	const struct drm_display_mode *adjusted_mode =
2936	&crtc_state->hw.adjusted_mode;
2937
2938	if (!crtc_state->vrr.enable || !intel_dp->as_sdp_supported)
2939	return;
2940
2941	crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC);
2942
2943	as_sdp->sdp_type = DP_SDP_ADAPTIVE_SYNC;
2944	as_sdp->length = 0x9;
2945	as_sdp->duration_incr_ms = 0;
2946	as_sdp->vtotal = intel_vrr_vmin_vtotal(crtc_state);
2947
2948	if (crtc_state->cmrr.enable) {
2949	as_sdp->mode = DP_AS_SDP_FAVT_TRR_REACHED;
2950	as_sdp->target_rr = drm_mode_vrefresh(mode: adjusted_mode);
2951	as_sdp->target_rr_divider = true;
2952	} else {
2953	as_sdp->mode = DP_AS_SDP_AVT_DYNAMIC_VTOTAL;
2954	as_sdp->target_rr = 0;
2955	}
2956	}
2957
2958	static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
2959	struct intel_crtc_state *crtc_state,
2960	const struct drm_connector_state *conn_state)
2961	{
2962	struct drm_dp_vsc_sdp *vsc;
2963
2964	if ((!intel_dp->colorimetry_support ||
2965	!intel_dp_needs_vsc_sdp(crtc_state, conn_state)) &&
2966	!crtc_state->has_psr)
2967	return;
2968
2969	vsc = &crtc_state->infoframes.vsc;
2970
2971	crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
2972	vsc->sdp_type = DP_SDP_VSC;
2973
2974	/* Needs colorimetry */
2975	if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
2976	intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
2977	vsc);
2978	} else if (crtc_state->has_panel_replay) {
2979	/*
2980	* [Panel Replay without colorimetry info]
2981	* Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
2982	* VSC SDP supporting 3D stereo + Panel Replay.
2983	*/
2984	vsc->revision = 0x6;
2985	vsc->length = 0x10;
2986	} else if (crtc_state->has_sel_update) {
2987	/*
2988	* [PSR2 without colorimetry]
2989	* Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11
2990	* 3D stereo + PSR/PSR2 + Y-coordinate.
2991	*/
2992	vsc->revision = 0x4;
2993	vsc->length = 0xe;
2994	} else {
2995	/*
2996	* [PSR1]
2997	* Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
2998	* VSC SDP supporting 3D stereo + PSR (applies to eDP v1.3 or
2999	* higher).
3000	*/
3001	vsc->revision = 0x2;
3002	vsc->length = 0x8;
3003	}
3004	}
3005
3006	bool
3007	intel_dp_in_hdr_mode(const struct drm_connector_state *conn_state)
3008	{
3009	struct hdr_output_metadata *hdr_metadata;
3010
3011	if (!conn_state->hdr_output_metadata)
3012	return false;
3013
3014	hdr_metadata = conn_state->hdr_output_metadata->data;
3015
3016	return hdr_metadata->hdmi_metadata_type1.eotf == HDMI_EOTF_SMPTE_ST2084;
3017	}
3018
3019	static void
3020	intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
3021	struct intel_crtc_state *crtc_state,
3022	const struct drm_connector_state *conn_state)
3023	{
3024	struct intel_display *display = to_intel_display(intel_dp);
3025	int ret;
3026	struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm;
3027
3028	if (!conn_state->hdr_output_metadata)
3029	return;
3030
3031	ret = drm_hdmi_infoframe_set_hdr_metadata(frame: drm_infoframe, conn_state);
3032
3033	if (ret) {
3034	drm_dbg_kms(display->drm,
3035	"couldn't set HDR metadata in infoframe\n");
3036	return;
3037	}
3038
3039	crtc_state->infoframes.enable |=
3040	intel_hdmi_infoframe_enable(type: HDMI_PACKET_TYPE_GAMUT_METADATA);
3041	}
3042
3043	static bool can_enable_drrs(struct intel_connector *connector,
3044	const struct intel_crtc_state *pipe_config,
3045	const struct drm_display_mode *downclock_mode)
3046	{
3047	struct intel_display *display = to_intel_display(connector);
3048
3049	if (pipe_config->vrr.enable)
3050	return false;
3051
3052	/*
3053	* DRRS and PSR can't be enable together, so giving preference to PSR
3054	* as it allows more power-savings by complete shutting down display,
3055	* so to guarantee this, intel_drrs_compute_config() must be called
3056	* after intel_psr_compute_config().
3057	*/
3058	if (pipe_config->has_psr)
3059	return false;
3060
3061	/* FIXME missing FDI M2/N2 etc. */
3062	if (pipe_config->has_pch_encoder)
3063	return false;
3064
3065	if (!intel_cpu_transcoder_has_drrs(display, cpu_transcoder: pipe_config->cpu_transcoder))
3066	return false;
3067
3068	return downclock_mode &&
3069	intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS;
3070	}
3071
3072	static void
3073	intel_dp_drrs_compute_config(struct intel_connector *connector,
3074	struct intel_crtc_state *pipe_config,
3075	int link_bpp_x16)
3076	{
3077	struct intel_display *display = to_intel_display(connector);
3078	const struct drm_display_mode *downclock_mode =
3079	intel_panel_downclock_mode(connector, adjusted_mode: &pipe_config->hw.adjusted_mode);
3080	int pixel_clock;
3081
3082	/*
3083	* FIXME all joined pipes share the same transcoder.
3084	* Need to account for that when updating M/N live.
3085	*/
3086	if (has_seamless_m_n(connector) && !pipe_config->joiner_pipes)
3087	pipe_config->update_m_n = true;
3088
3089	if (!can_enable_drrs(connector, pipe_config, downclock_mode)) {
3090	if (intel_cpu_transcoder_has_m2_n2(display, transcoder: pipe_config->cpu_transcoder))
3091	intel_zero_m_n(m_n: &pipe_config->dp_m2_n2);
3092	return;
3093	}
3094
3095	if (display->platform.ironlake || display->platform.sandybridge ||
3096	display->platform.ivybridge)
3097	pipe_config->msa_timing_delay = connector->panel.vbt.edp.drrs_msa_timing_delay;
3098
3099	pipe_config->has_drrs = true;
3100
3101	pixel_clock = downclock_mode->clock;
3102	if (pipe_config->splitter.enable)
3103	pixel_clock /= pipe_config->splitter.link_count;
3104
3105	intel_link_compute_m_n(bpp: link_bpp_x16, nlanes: pipe_config->lane_count, pixel_clock,
3106	link_clock: pipe_config->port_clock,
3107	bw_overhead: intel_dp_bw_fec_overhead(fec_enabled: pipe_config->fec_enable),
3108	m_n: &pipe_config->dp_m2_n2);
3109
3110	/* FIXME: abstract this better */
3111	if (pipe_config->splitter.enable)
3112	pipe_config->dp_m2_n2.data_m *= pipe_config->splitter.link_count;
3113	}
3114
3115	static bool intel_dp_has_audio(struct intel_encoder *encoder,
3116	const struct drm_connector_state *conn_state)
3117	{
3118	struct intel_display *display = to_intel_display(encoder);
3119	const struct intel_digital_connector_state *intel_conn_state =
3120	to_intel_digital_connector_state(conn_state);
3121	struct intel_connector *connector =
3122	to_intel_connector(conn_state->connector);
3123
3124	if (!intel_dp_port_has_audio(display, port: encoder->port))
3125	return false;
3126
3127	if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
3128	return connector->base.display_info.has_audio;
3129	else
3130	return intel_conn_state->force_audio == HDMI_AUDIO_ON;
3131	}
3132
3133	static int
3134	intel_dp_compute_output_format(struct intel_encoder *encoder,
3135	struct intel_crtc_state *crtc_state,
3136	struct drm_connector_state *conn_state,
3137	bool respect_downstream_limits)
3138	{
3139	struct intel_display *display = to_intel_display(encoder);
3140	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3141	struct intel_connector *connector = intel_dp->attached_connector;
3142	const struct drm_display_info *info = &connector->base.display_info;
3143	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
3144	bool ycbcr_420_only;
3145	int ret;
3146
3147	ycbcr_420_only = drm_mode_is_420_only(display: info, mode: adjusted_mode);
3148
3149	if (ycbcr_420_only && !connector->base.ycbcr_420_allowed) {
3150	drm_dbg_kms(display->drm,
3151	"YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n");
3152	crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB;
3153	} else {
3154	crtc_state->sink_format = intel_dp_sink_format(connector, mode: adjusted_mode);
3155	}
3156
3157	crtc_state->output_format = intel_dp_output_format(connector, sink_format: crtc_state->sink_format);
3158
3159	ret = intel_dp_compute_link_config(encoder, pipe_config: crtc_state, conn_state,
3160	respect_downstream_limits);
3161	if (ret) {
3162	if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
3163	!connector->base.ycbcr_420_allowed ||
3164	!drm_mode_is_420_also(display: info, mode: adjusted_mode))
3165	return ret;
3166
3167	crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
3168	crtc_state->output_format = intel_dp_output_format(connector,
3169	sink_format: crtc_state->sink_format);
3170	ret = intel_dp_compute_link_config(encoder, pipe_config: crtc_state, conn_state,
3171	respect_downstream_limits);
3172	}
3173
3174	return ret;
3175	}
3176
3177	void
3178	intel_dp_audio_compute_config(struct intel_encoder *encoder,
3179	struct intel_crtc_state *pipe_config,
3180	struct drm_connector_state *conn_state)
3181	{
3182	pipe_config->has_audio =
3183	intel_dp_has_audio(encoder, conn_state) &&
3184	intel_audio_compute_config(encoder, crtc_state: pipe_config, conn_state);
3185
3186	pipe_config->sdp_split_enable = pipe_config->has_audio &&
3187	intel_dp_is_uhbr(crtc_state: pipe_config);
3188	}
3189
3190	void
3191	intel_dp_queue_modeset_retry_for_link(struct intel_atomic_state *state,
3192	struct intel_encoder *encoder,
3193	const struct intel_crtc_state *crtc_state)
3194	{
3195	struct intel_connector *connector;
3196	struct intel_digital_connector_state *conn_state;
3197	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3198	int i;
3199
3200	if (intel_dp->needs_modeset_retry)
3201	return;
3202
3203	intel_dp->needs_modeset_retry = true;
3204
3205	if (!intel_crtc_has_type(crtc_state, type: INTEL_OUTPUT_DP_MST)) {
3206	intel_connector_queue_modeset_retry_work(connector: intel_dp->attached_connector);
3207
3208	return;
3209	}
3210
3211	for_each_new_intel_connector_in_state(state, connector, conn_state, i) {
3212	if (!conn_state->base.crtc)
3213	continue;
3214
3215	if (connector->mst.dp == intel_dp)
3216	intel_connector_queue_modeset_retry_work(connector);
3217	}
3218	}
3219
3220	int intel_dp_compute_min_hblank(struct intel_crtc_state *crtc_state,
3221	const struct drm_connector_state *conn_state)
3222	{
3223	struct intel_display *display = to_intel_display(crtc_state);
3224	const struct drm_display_mode *adjusted_mode =
3225	&crtc_state->hw.adjusted_mode;
3226	struct intel_connector *connector = to_intel_connector(conn_state->connector);
3227	int symbol_size = intel_dp_is_uhbr(crtc_state) ? 32 : 8;
3228	/*
3229	* min symbol cycles is 3(BS,VBID, BE) for 128b/132b and
3230	* 5(BS, VBID, MVID, MAUD, BE) for 8b/10b
3231	*/
3232	int min_sym_cycles = intel_dp_is_uhbr(crtc_state) ? 3 : 5;
3233	bool is_mst = intel_crtc_has_type(crtc_state, type: INTEL_OUTPUT_DP_MST);
3234	int num_joined_pipes = intel_crtc_num_joined_pipes(crtc_state);
3235	int min_hblank;
3236	int max_lane_count = 4;
3237	int hactive_sym_cycles, htotal_sym_cycles;
3238	int dsc_slices = 0;
3239	int link_bpp_x16;
3240
3241	if (DISPLAY_VER(display) < 30)
3242	return 0;
3243
3244	/* MIN_HBLANK should be set only for 8b/10b MST or for 128b/132b SST/MST */
3245	if (!is_mst && !intel_dp_is_uhbr(crtc_state))
3246	return 0;
3247
3248	if (crtc_state->dsc.compression_enable) {
3249	dsc_slices = intel_dp_dsc_get_slice_count(connector,
3250	mode_clock: adjusted_mode->crtc_clock,
3251	mode_hdisplay: adjusted_mode->crtc_hdisplay,
3252	num_joined_pipes);
3253	if (!dsc_slices) {
3254	drm_dbg(display->drm, "failed to calculate dsc slice count\n");
3255	return -EINVAL;
3256	}
3257	}
3258
3259	if (crtc_state->dsc.compression_enable)
3260	link_bpp_x16 = crtc_state->dsc.compressed_bpp_x16;
3261	else
3262	link_bpp_x16 = fxp_q4_from_int(val_int: intel_dp_output_bpp(output_format: crtc_state->output_format,
3263	bpp: crtc_state->pipe_bpp));
3264
3265	/* Calculate min Hblank Link Layer Symbol Cycle Count for 8b/10b MST & 128b/132b */
3266	hactive_sym_cycles = drm_dp_link_symbol_cycles(lane_count: max_lane_count,
3267	pixels: adjusted_mode->hdisplay,
3268	dsc_slice_count: dsc_slices,
3269	bpp_x16: link_bpp_x16,
3270	symbol_size, is_mst);
3271	htotal_sym_cycles = adjusted_mode->htotal * hactive_sym_cycles /
3272	adjusted_mode->hdisplay;
3273
3274	min_hblank = htotal_sym_cycles - hactive_sym_cycles;
3275	/* minimum Hblank calculation: https://groups.vesa.org/wg/DP/document/20494 */
3276	min_hblank = max(min_hblank, min_sym_cycles);
3277
3278	/*
3279	* adjust the BlankingStart/BlankingEnd framing control from
3280	* the calculated value
3281	*/
3282	min_hblank = min_hblank - 2;
3283
3284	/*
3285	* min_hblank formula is undergoing a change, to avoid underrun use the
3286	* recomended value in spec to compare with the calculated one and use the
3287	* minimum value
3288	*/
3289	if (intel_dp_is_uhbr(crtc_state)) {
3290	/*
3291	* Note: Bspec requires a min_hblank of 2 for YCBCR420
3292	* with compressed bpp 6, but the minimum compressed bpp
3293	* supported by the driver is 8.
3294	*/
3295	drm_WARN_ON(display->drm,
3296	(crtc_state->dsc.compression_enable &&
3297	crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
3298	crtc_state->dsc.compressed_bpp_x16 < fxp_q4_from_int(8)));
3299	min_hblank = min(3, min_hblank);
3300	} else {
3301	min_hblank = min(10, min_hblank);
3302	}
3303
3304	crtc_state->min_hblank = min_hblank;
3305
3306	return 0;
3307	}
3308
3309	int
3310	intel_dp_compute_config(struct intel_encoder *encoder,
3311	struct intel_crtc_state *pipe_config,
3312	struct drm_connector_state *conn_state)
3313	{
3314	struct intel_display *display = to_intel_display(encoder);
3315	struct intel_atomic_state *state = to_intel_atomic_state(conn_state->state);
3316	struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
3317	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3318	const struct drm_display_mode *fixed_mode;
3319	struct intel_connector *connector = intel_dp->attached_connector;
3320	int ret = 0, link_bpp_x16;
3321
3322	fixed_mode = intel_panel_fixed_mode(connector, mode: adjusted_mode);
3323	if (intel_dp_is_edp(intel_dp) && fixed_mode) {
3324	ret = intel_panel_compute_config(connector, adjusted_mode);
3325	if (ret)
3326	return ret;
3327	}
3328
3329	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
3330	return -EINVAL;
3331
3332	if (!connector->base.interlace_allowed &&
3333	adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
3334	return -EINVAL;
3335
3336	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
3337	return -EINVAL;
3338
3339	if (intel_dp_hdisplay_bad(display, hdisplay: adjusted_mode->crtc_hdisplay))
3340	return -EINVAL;
3341
3342	/*
3343	* Try to respect downstream TMDS clock limits first, if
3344	* that fails assume the user might know something we don't.
3345	*/
3346	ret = intel_dp_compute_output_format(encoder, crtc_state: pipe_config, conn_state, respect_downstream_limits: true);
3347	if (ret)
3348	ret = intel_dp_compute_output_format(encoder, crtc_state: pipe_config, conn_state, respect_downstream_limits: false);
3349	if (ret)
3350	return ret;
3351
3352	if ((intel_dp_is_edp(intel_dp) && fixed_mode) ||
3353	pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
3354	ret = intel_pfit_compute_config(crtc_state: pipe_config, conn_state);
3355	if (ret)
3356	return ret;
3357	}
3358
3359	pipe_config->limited_color_range =
3360	intel_dp_limited_color_range(crtc_state: pipe_config, conn_state);
3361
3362	if (intel_dp_is_uhbr(crtc_state: pipe_config)) {
3363	/* 128b/132b SST also needs this */
3364	pipe_config->mst_master_transcoder = pipe_config->cpu_transcoder;
3365	} else {
3366	pipe_config->enhanced_framing =
3367	drm_dp_enhanced_frame_cap(dpcd: intel_dp->dpcd);
3368	}
3369
3370	if (pipe_config->dsc.compression_enable)
3371	link_bpp_x16 = pipe_config->dsc.compressed_bpp_x16;
3372	else
3373	link_bpp_x16 = fxp_q4_from_int(val_int: intel_dp_output_bpp(output_format: pipe_config->output_format,
3374	bpp: pipe_config->pipe_bpp));
3375
3376	if (intel_dp->mso_link_count) {
3377	int n = intel_dp->mso_link_count;
3378	int overlap = intel_dp->mso_pixel_overlap;
3379
3380	pipe_config->splitter.enable = true;
3381	pipe_config->splitter.link_count = n;
3382	pipe_config->splitter.pixel_overlap = overlap;
3383
3384	drm_dbg_kms(display->drm,
3385	"MSO link count %d, pixel overlap %d\n",
3386	n, overlap);
3387
3388	adjusted_mode->crtc_hdisplay = adjusted_mode->crtc_hdisplay / n + overlap;
3389	adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hblank_start / n + overlap;
3390	adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_hblank_end / n + overlap;
3391	adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hsync_start / n + overlap;
3392	adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_end / n + overlap;
3393	adjusted_mode->crtc_htotal = adjusted_mode->crtc_htotal / n + overlap;
3394	adjusted_mode->crtc_clock /= n;
3395	}
3396
3397	intel_dp_audio_compute_config(encoder, pipe_config, conn_state);
3398
3399	if (!intel_dp_is_uhbr(crtc_state: pipe_config)) {
3400	intel_link_compute_m_n(bpp: link_bpp_x16,
3401	nlanes: pipe_config->lane_count,
3402	pixel_clock: adjusted_mode->crtc_clock,
3403	link_clock: pipe_config->port_clock,
3404	bw_overhead: intel_dp_bw_fec_overhead(fec_enabled: pipe_config->fec_enable),
3405	m_n: &pipe_config->dp_m_n);
3406	}
3407
3408	ret = intel_dp_compute_min_hblank(crtc_state: pipe_config, conn_state);
3409	if (ret)
3410	return ret;
3411
3412	/* FIXME: abstract this better */
3413	if (pipe_config->splitter.enable)
3414	pipe_config->dp_m_n.data_m *= pipe_config->splitter.link_count;
3415
3416	intel_vrr_compute_config(crtc_state: pipe_config, conn_state);
3417	intel_dp_compute_as_sdp(intel_dp, crtc_state: pipe_config);
3418	intel_psr_compute_config(intel_dp, crtc_state: pipe_config, conn_state);
3419	intel_alpm_lobf_compute_config(intel_dp, crtc_state: pipe_config, conn_state);
3420	intel_dp_drrs_compute_config(connector, pipe_config, link_bpp_x16);
3421	intel_dp_compute_vsc_sdp(intel_dp, crtc_state: pipe_config, conn_state);
3422	intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, crtc_state: pipe_config, conn_state);
3423
3424	return intel_dp_tunnel_atomic_compute_stream_bw(state, intel_dp, connector,
3425	crtc_state: pipe_config);
3426	}
3427
3428	void intel_dp_set_link_params(struct intel_dp *intel_dp,
3429	int link_rate, int lane_count)
3430	{
3431	memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
3432	intel_dp->link.active = false;
3433	intel_dp->needs_modeset_retry = false;
3434	intel_dp->link_rate = link_rate;
3435	intel_dp->lane_count = lane_count;
3436	}
3437
3438	void intel_dp_reset_link_params(struct intel_dp *intel_dp)
3439	{
3440	intel_dp->link.max_lane_count = intel_dp_max_common_lane_count(intel_dp);
3441	intel_dp->link.max_rate = intel_dp_max_common_rate(intel_dp);
3442	intel_dp->link.mst_probed_lane_count = 0;
3443	intel_dp->link.mst_probed_rate = 0;
3444	intel_dp->link.retrain_disabled = false;
3445	intel_dp->link.seq_train_failures = 0;
3446	}
3447
3448	/* Enable backlight PWM and backlight PP control. */
3449	void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
3450	const struct drm_connector_state *conn_state)
3451	{
3452	struct intel_display *display = to_intel_display(crtc_state);
3453	struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder));
3454
3455	if (!intel_dp_is_edp(intel_dp))
3456	return;
3457
3458	drm_dbg_kms(display->drm, "\n");
3459
3460	intel_backlight_enable(crtc_state, conn_state);
3461	intel_pps_backlight_on(intel_dp);
3462	}
3463
3464	/* Disable backlight PP control and backlight PWM. */
3465	void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
3466	{
3467	struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder));
3468	struct intel_display *display = to_intel_display(intel_dp);
3469
3470	if (!intel_dp_is_edp(intel_dp))
3471	return;
3472
3473	drm_dbg_kms(display->drm, "\n");
3474
3475	intel_pps_backlight_off(intel_dp);
3476	intel_backlight_disable(old_conn_state);
3477	}
3478
3479	static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
3480	{
3481	/*
3482	* DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
3483	* be capable of signalling downstream hpd with a long pulse.
3484	* Whether or not that means D3 is safe to use is not clear,
3485	* but let's assume so until proven otherwise.
3486	*
3487	* FIXME should really check all downstream ports...
3488	*/
3489	return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
3490	drm_dp_is_branch(dpcd: intel_dp->dpcd) &&
3491	intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
3492	}
3493
3494	static int
3495	write_dsc_decompression_flag(struct drm_dp_aux *aux, u8 flag, bool set)
3496	{
3497	int err;
3498	u8 val;
3499
3500	err = drm_dp_dpcd_readb(aux, DP_DSC_ENABLE, valuep: &val);
3501	if (err < 0)
3502	return err;
3503
3504	if (set)
3505	val |= flag;
3506	else
3507	val &= ~flag;
3508
3509	return drm_dp_dpcd_writeb(aux, DP_DSC_ENABLE, value: val);
3510	}
3511
3512	static void
3513	intel_dp_sink_set_dsc_decompression(struct intel_connector *connector,
3514	bool enable)
3515	{
3516	struct intel_display *display = to_intel_display(connector);
3517
3518	if (write_dsc_decompression_flag(aux: connector->dp.dsc_decompression_aux,
3519	DP_DECOMPRESSION_EN, set: enable) < 0)
3520	drm_dbg_kms(display->drm,
3521	"Failed to %s sink decompression state\n",
3522	str_enable_disable(enable));
3523	}
3524
3525	static void
3526	intel_dp_sink_set_dsc_passthrough(const struct intel_connector *connector,
3527	bool enable)
3528	{
3529	struct intel_display *display = to_intel_display(connector);
3530	struct drm_dp_aux *aux = connector->mst.port ?
3531	connector->mst.port->passthrough_aux : NULL;
3532
3533	if (!aux)
3534	return;
3535
3536	if (write_dsc_decompression_flag(aux,
3537	DP_DSC_PASSTHROUGH_EN, set: enable) < 0)
3538	drm_dbg_kms(display->drm,
3539	"Failed to %s sink compression passthrough state\n",
3540	str_enable_disable(enable));
3541	}
3542
3543	static int intel_dp_dsc_aux_ref_count(struct intel_atomic_state *state,
3544	const struct intel_connector *connector,
3545	bool for_get_ref)
3546	{
3547	struct intel_display *display = to_intel_display(state);
3548	struct drm_connector *_connector_iter;
3549	struct drm_connector_state *old_conn_state;
3550	struct drm_connector_state *new_conn_state;
3551	int ref_count = 0;
3552	int i;
3553
3554	/*
3555	* On SST the decompression AUX device won't be shared, each connector
3556	* uses for this its own AUX targeting the sink device.
3557	*/
3558	if (!connector->mst.dp)
3559	return connector->dp.dsc_decompression_enabled ? 1 : 0;
3560
3561	for_each_oldnew_connector_in_state(&state->base, _connector_iter,
3562	old_conn_state, new_conn_state, i) {
3563	const struct intel_connector *
3564	connector_iter = to_intel_connector(_connector_iter);
3565
3566	if (connector_iter->mst.dp != connector->mst.dp)
3567	continue;
3568
3569	if (!connector_iter->dp.dsc_decompression_enabled)
3570	continue;
3571
3572	drm_WARN_ON(display->drm,
3573	(for_get_ref && !new_conn_state->crtc) ||
3574	(!for_get_ref && !old_conn_state->crtc));
3575
3576	if (connector_iter->dp.dsc_decompression_aux ==
3577	connector->dp.dsc_decompression_aux)
3578	ref_count++;
3579	}
3580
3581	return ref_count;
3582	}
3583
3584	static bool intel_dp_dsc_aux_get_ref(struct intel_atomic_state *state,
3585	struct intel_connector *connector)
3586	{
3587	bool ret = intel_dp_dsc_aux_ref_count(state, connector, for_get_ref: true) == 0;
3588
3589	connector->dp.dsc_decompression_enabled = true;
3590
3591	return ret;
3592	}
3593
3594	static bool intel_dp_dsc_aux_put_ref(struct intel_atomic_state *state,
3595	struct intel_connector *connector)
3596	{
3597	connector->dp.dsc_decompression_enabled = false;
3598
3599	return intel_dp_dsc_aux_ref_count(state, connector, for_get_ref: false) == 0;
3600	}
3601
3602	/**
3603	* intel_dp_sink_enable_decompression - Enable DSC decompression in sink/last branch device
3604	* @state: atomic state
3605	* @connector: connector to enable the decompression for
3606	* @new_crtc_state: new state for the CRTC driving @connector
3607	*
3608	* Enable the DSC decompression if required in the %DP_DSC_ENABLE DPCD
3609	* register of the appropriate sink/branch device. On SST this is always the
3610	* sink device, whereas on MST based on each device's DSC capabilities it's
3611	* either the last branch device (enabling decompression in it) or both the
3612	* last branch device (enabling passthrough in it) and the sink device
3613	* (enabling decompression in it).
3614	*/
3615	void intel_dp_sink_enable_decompression(struct intel_atomic_state *state,
3616	struct intel_connector *connector,
3617	const struct intel_crtc_state *new_crtc_state)
3618	{
3619	struct intel_display *display = to_intel_display(state);
3620
3621	if (!new_crtc_state->dsc.compression_enable)
3622	return;
3623
3624	if (drm_WARN_ON(display->drm,
3625	!connector->dp.dsc_decompression_aux ||
3626	connector->dp.dsc_decompression_enabled))
3627	return;
3628
3629	if (!intel_dp_dsc_aux_get_ref(state, connector))
3630	return;
3631
3632	intel_dp_sink_set_dsc_passthrough(connector, enable: true);
3633	intel_dp_sink_set_dsc_decompression(connector, enable: true);
3634	}
3635
3636	/**
3637	* intel_dp_sink_disable_decompression - Disable DSC decompression in sink/last branch device
3638	* @state: atomic state
3639	* @connector: connector to disable the decompression for
3640	* @old_crtc_state: old state for the CRTC driving @connector
3641	*
3642	* Disable the DSC decompression if required in the %DP_DSC_ENABLE DPCD
3643	* register of the appropriate sink/branch device, corresponding to the
3644	* sequence in intel_dp_sink_enable_decompression().
3645	*/
3646	void intel_dp_sink_disable_decompression(struct intel_atomic_state *state,
3647	struct intel_connector *connector,
3648	const struct intel_crtc_state *old_crtc_state)
3649	{
3650	struct intel_display *display = to_intel_display(state);
3651
3652	if (!old_crtc_state->dsc.compression_enable)
3653	return;
3654
3655	if (drm_WARN_ON(display->drm,
3656	!connector->dp.dsc_decompression_aux ||
3657	!connector->dp.dsc_decompression_enabled))
3658	return;
3659
3660	if (!intel_dp_dsc_aux_put_ref(state, connector))
3661	return;
3662
3663	intel_dp_sink_set_dsc_decompression(connector, enable: false);
3664	intel_dp_sink_set_dsc_passthrough(connector, enable: false);
3665	}
3666
3667	static void
3668	intel_dp_init_source_oui(struct intel_dp *intel_dp)
3669	{
3670	struct intel_display *display = to_intel_display(intel_dp);
3671	u8 oui[] = { 0x00, 0xaa, 0x01 };
3672	u8 buf[3] = {};
3673
3674	if (READ_ONCE(intel_dp->oui_valid))
3675	return;
3676
3677	WRITE_ONCE(intel_dp->oui_valid, true);
3678
3679	/*
3680	* During driver init, we want to be careful and avoid changing the source OUI if it's
3681	* already set to what we want, so as to avoid clearing any state by accident
3682	*/
3683	if (drm_dp_dpcd_read(aux: &intel_dp->aux, DP_SOURCE_OUI, buffer: buf, size: sizeof(buf)) < 0)
3684	drm_dbg_kms(display->drm, "Failed to read source OUI\n");
3685
3686	if (memcmp(p: oui, q: buf, size: sizeof(oui)) == 0) {
3687	/* Assume the OUI was written now. */
3688	intel_dp->last_oui_write = jiffies;
3689	return;
3690	}
3691
3692	if (drm_dp_dpcd_write(aux: &intel_dp->aux, DP_SOURCE_OUI, buffer: oui, size: sizeof(oui)) < 0) {
3693	drm_dbg_kms(display->drm, "Failed to write source OUI\n");
3694	WRITE_ONCE(intel_dp->oui_valid, false);
3695	}
3696
3697	intel_dp->last_oui_write = jiffies;
3698	}
3699
3700	void intel_dp_invalidate_source_oui(struct intel_dp *intel_dp)
3701	{
3702	WRITE_ONCE(intel_dp->oui_valid, false);
3703	}
3704
3705	void intel_dp_wait_source_oui(struct intel_dp *intel_dp)
3706	{
3707	struct intel_display *display = to_intel_display(intel_dp);
3708	struct intel_connector *connector = intel_dp->attached_connector;
3709
3710	drm_dbg_kms(display->drm,
3711	"[CONNECTOR:%d:%s] Performing OUI wait (%u ms)\n",
3712	connector->base.base.id, connector->base.name,
3713	connector->panel.vbt.backlight.hdr_dpcd_refresh_timeout);
3714
3715	wait_remaining_ms_from_jiffies(timestamp_jiffies: intel_dp->last_oui_write,
3716	to_wait_ms: connector->panel.vbt.backlight.hdr_dpcd_refresh_timeout);
3717	}
3718
3719	/* If the device supports it, try to set the power state appropriately */
3720	void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode)
3721	{
3722	struct intel_display *display = to_intel_display(intel_dp);
3723	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3724	int ret, i;
3725
3726	/* Should have a valid DPCD by this point */
3727	if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
3728	return;
3729
3730	if (mode != DP_SET_POWER_D0) {
3731	if (downstream_hpd_needs_d0(intel_dp))
3732	return;
3733
3734	ret = drm_dp_dpcd_writeb(aux: &intel_dp->aux, DP_SET_POWER, value: mode);
3735	} else {
3736	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3737
3738	intel_lspcon_resume(dig_port);
3739
3740	/* Write the source OUI as early as possible */
3741	intel_dp_init_source_oui(intel_dp);
3742
3743	/*
3744	* When turning on, we need to retry for 1ms to give the sink
3745	* time to wake up.
3746	*/
3747	for (i = 0; i < 3; i++) {
3748	ret = drm_dp_dpcd_writeb(aux: &intel_dp->aux, DP_SET_POWER, value: mode);
3749	if (ret == 1)
3750	break;
3751	msleep(msecs: 1);
3752	}
3753
3754	if (ret == 1 && intel_lspcon_active(dig_port))
3755	intel_lspcon_wait_pcon_mode(dig_port);
3756	}
3757
3758	if (ret != 1)
3759	drm_dbg_kms(display->drm,
3760	"[ENCODER:%d:%s] Set power to %s failed\n",
3761	encoder->base.base.id, encoder->base.name,
3762	mode == DP_SET_POWER_D0 ? "D0" : "D3");
3763	}
3764
3765	static bool
3766	intel_dp_get_dpcd(struct intel_dp *intel_dp);
3767
3768	/**
3769	* intel_dp_sync_state - sync the encoder state during init/resume
3770	* @encoder: intel encoder to sync
3771	* @crtc_state: state for the CRTC connected to the encoder
3772	*
3773	* Sync any state stored in the encoder wrt. HW state during driver init
3774	* and system resume.
3775	*/
3776	void intel_dp_sync_state(struct intel_encoder *encoder,
3777	const struct intel_crtc_state *crtc_state)
3778	{
3779	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3780	bool dpcd_updated = false;
3781
3782	/*
3783	* Don't clobber DPCD if it's been already read out during output
3784	* setup (eDP) or detect.
3785	*/
3786	if (crtc_state && intel_dp->dpcd[DP_DPCD_REV] == 0) {
3787	intel_dp_get_dpcd(intel_dp);
3788	dpcd_updated = true;
3789	}
3790
3791	intel_dp_tunnel_resume(intel_dp, crtc_state, dpcd_updated);
3792
3793	if (crtc_state) {
3794	intel_dp_reset_link_params(intel_dp);
3795	intel_dp_set_link_params(intel_dp, link_rate: crtc_state->port_clock, lane_count: crtc_state->lane_count);
3796	intel_dp->link.active = true;
3797	}
3798	}
3799
3800	bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
3801	struct intel_crtc_state *crtc_state)
3802	{
3803	struct intel_display *display = to_intel_display(encoder);
3804	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3805	bool fastset = true;
3806
3807	/*
3808	* If BIOS has set an unsupported or non-standard link rate for some
3809	* reason force an encoder recompute and full modeset.
3810	*/
3811	if (intel_dp_rate_index(rates: intel_dp->source_rates, len: intel_dp->num_source_rates,
3812	rate: crtc_state->port_clock) < 0) {
3813	drm_dbg_kms(display->drm,
3814	"[ENCODER:%d:%s] Forcing full modeset due to unsupported link rate\n",
3815	encoder->base.base.id, encoder->base.name);
3816	crtc_state->uapi.connectors_changed = true;
3817	fastset = false;
3818	}
3819
3820	/*
3821	* FIXME hack to force full modeset when DSC is being used.
3822	*
3823	* As long as we do not have full state readout and config comparison
3824	* of crtc_state->dsc, we have no way to ensure reliable fastset.
3825	* Remove once we have readout for DSC.
3826	*/
3827	if (crtc_state->dsc.compression_enable) {
3828	drm_dbg_kms(display->drm,
3829	"[ENCODER:%d:%s] Forcing full modeset due to DSC being enabled\n",
3830	encoder->base.base.id, encoder->base.name);
3831	crtc_state->uapi.mode_changed = true;
3832	fastset = false;
3833	}
3834
3835	if (CAN_PANEL_REPLAY(intel_dp)) {
3836	drm_dbg_kms(display->drm,
3837	"[ENCODER:%d:%s] Forcing full modeset to compute panel replay state\n",
3838	encoder->base.base.id, encoder->base.name);
3839	crtc_state->uapi.mode_changed = true;
3840	fastset = false;
3841	}
3842
3843	return fastset;
3844	}
3845
3846	static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp)
3847	{
3848	struct intel_display *display = to_intel_display(intel_dp);
3849
3850	/* Clear the cached register set to avoid using stale values */
3851
3852	memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd));
3853
3854	if (!drm_dp_is_branch(dpcd: intel_dp->dpcd))
3855	return;
3856
3857	if (drm_dp_dpcd_read(aux: &intel_dp->aux, DP_PCON_DSC_ENCODER,
3858	buffer: intel_dp->pcon_dsc_dpcd,
3859	size: sizeof(intel_dp->pcon_dsc_dpcd)) < 0)
3860	drm_err(display->drm, "Failed to read DPCD register 0x%x\n",
3861	DP_PCON_DSC_ENCODER);
3862
3863	drm_dbg_kms(display->drm, "PCON ENCODER DSC DPCD: %*ph\n",
3864	(int)sizeof(intel_dp->pcon_dsc_dpcd), intel_dp->pcon_dsc_dpcd);
3865	}
3866
3867	static int intel_dp_pcon_get_frl_mask(u8 frl_bw_mask)
3868	{
3869	static const int bw_gbps[] = {9, 18, 24, 32, 40, 48};
3870	int i;
3871
3872	for (i = ARRAY_SIZE(bw_gbps) - 1; i >= 0; i--) {
3873	if (frl_bw_mask & (1 << i))
3874	return bw_gbps[i];
3875	}
3876	return 0;
3877	}
3878
3879	static int intel_dp_pcon_set_frl_mask(int max_frl)
3880	{
3881	switch (max_frl) {
3882	case 48:
3883	return DP_PCON_FRL_BW_MASK_48GBPS;
3884	case 40:
3885	return DP_PCON_FRL_BW_MASK_40GBPS;
3886	case 32:
3887	return DP_PCON_FRL_BW_MASK_32GBPS;
3888	case 24:
3889	return DP_PCON_FRL_BW_MASK_24GBPS;
3890	case 18:
3891	return DP_PCON_FRL_BW_MASK_18GBPS;
3892	case 9:
3893	return DP_PCON_FRL_BW_MASK_9GBPS;
3894	}
3895
3896	return 0;
3897	}
3898
3899	static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp)
3900	{
3901	struct intel_connector *connector = intel_dp->attached_connector;
3902	const struct drm_display_info *info = &connector->base.display_info;
3903	int max_frl_rate;
3904	int max_lanes, rate_per_lane;
3905	int max_dsc_lanes, dsc_rate_per_lane;
3906
3907	max_lanes = info->hdmi.max_lanes;
3908	rate_per_lane = info->hdmi.max_frl_rate_per_lane;
3909	max_frl_rate = max_lanes * rate_per_lane;
3910
3911	if (info->hdmi.dsc_cap.v_1p2) {
3912	max_dsc_lanes = info->hdmi.dsc_cap.max_lanes;
3913	dsc_rate_per_lane = info->hdmi.dsc_cap.max_frl_rate_per_lane;
3914	if (max_dsc_lanes && dsc_rate_per_lane)
3915	max_frl_rate = min(max_frl_rate, max_dsc_lanes * dsc_rate_per_lane);
3916	}
3917
3918	return max_frl_rate;
3919	}
3920
3921	static bool
3922	intel_dp_pcon_is_frl_trained(struct intel_dp *intel_dp,
3923	u8 max_frl_bw_mask, u8 *frl_trained_mask)
3924	{
3925	if (drm_dp_pcon_hdmi_link_active(aux: &intel_dp->aux) &&
3926	drm_dp_pcon_hdmi_link_mode(aux: &intel_dp->aux, frl_trained_mask) == DP_PCON_HDMI_MODE_FRL &&
3927	*frl_trained_mask >= max_frl_bw_mask)
3928	return true;
3929
3930	return false;
3931	}
3932
3933	static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp)
3934	{
3935	struct intel_display *display = to_intel_display(intel_dp);
3936	#define TIMEOUT_FRL_READY_MS 500
3937	#define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000
3938	int max_frl_bw, max_pcon_frl_bw, max_edid_frl_bw, ret;
3939	u8 max_frl_bw_mask = 0, frl_trained_mask;
3940	bool is_active;
3941
3942	max_pcon_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
3943	drm_dbg(display->drm, "PCON max rate = %d Gbps\n", max_pcon_frl_bw);
3944
3945	max_edid_frl_bw = intel_dp_hdmi_sink_max_frl(intel_dp);
3946	drm_dbg(display->drm, "Sink max rate from EDID = %d Gbps\n",
3947	max_edid_frl_bw);
3948
3949	max_frl_bw = min(max_edid_frl_bw, max_pcon_frl_bw);
3950
3951	if (max_frl_bw <= 0)
3952	return -EINVAL;
3953
3954	max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl: max_frl_bw);
3955	drm_dbg(display->drm, "MAX_FRL_BW_MASK = %u\n", max_frl_bw_mask);
3956
3957	if (intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, frl_trained_mask: &frl_trained_mask))
3958	goto frl_trained;
3959
3960	ret = drm_dp_pcon_frl_prepare(aux: &intel_dp->aux, enable_frl_ready_hpd: false);
3961	if (ret < 0)
3962	return ret;
3963	/* Wait for PCON to be FRL Ready */
3964	ret = poll_timeout_us(is_active = drm_dp_pcon_is_frl_ready(&intel_dp->aux),
3965	is_active,
3966	1000, TIMEOUT_FRL_READY_MS * 1000, false);
3967	if (ret)
3968	return ret;
3969
3970	ret = drm_dp_pcon_frl_configure_1(aux: &intel_dp->aux, max_frl_gbps: max_frl_bw,
3971	DP_PCON_ENABLE_SEQUENTIAL_LINK);
3972	if (ret < 0)
3973	return ret;
3974	ret = drm_dp_pcon_frl_configure_2(aux: &intel_dp->aux, max_frl_mask: max_frl_bw_mask,
3975	DP_PCON_FRL_LINK_TRAIN_NORMAL);
3976	if (ret < 0)
3977	return ret;
3978	ret = drm_dp_pcon_frl_enable(aux: &intel_dp->aux);
3979	if (ret < 0)
3980	return ret;
3981	/*
3982	* Wait for FRL to be completed
3983	* Check if the HDMI Link is up and active.
3984	*/
3985	ret = poll_timeout_us(is_active = intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask),
3986	is_active,
3987	1000, TIMEOUT_HDMI_LINK_ACTIVE_MS * 1000, false);
3988	if (ret)
3989	return ret;
3990
3991	frl_trained:
3992	drm_dbg(display->drm, "FRL_TRAINED_MASK = %u\n", frl_trained_mask);
3993	intel_dp->frl.trained_rate_gbps = intel_dp_pcon_get_frl_mask(frl_bw_mask: frl_trained_mask);
3994	intel_dp->frl.is_trained = true;
3995	drm_dbg(display->drm, "FRL trained with : %d Gbps\n",
3996	intel_dp->frl.trained_rate_gbps);
3997
3998	return 0;
3999	}
4000
4001	static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp)
4002	{
4003	if (drm_dp_is_branch(dpcd: intel_dp->dpcd) &&
4004	intel_dp_has_hdmi_sink(intel_dp) &&
4005	intel_dp_hdmi_sink_max_frl(intel_dp) > 0)
4006	return true;
4007
4008	return false;
4009	}
4010
4011	static
4012	int intel_dp_pcon_set_tmds_mode(struct intel_dp *intel_dp)
4013	{
4014	int ret;
4015	u8 buf = 0;
4016
4017	/* Set PCON source control mode */
4018	buf |= DP_PCON_ENABLE_SOURCE_CTL_MODE;
4019
4020	ret = drm_dp_dpcd_writeb(aux: &intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, value: buf);
4021	if (ret < 0)
4022	return ret;
4023
4024	/* Set HDMI LINK ENABLE */
4025	buf |= DP_PCON_ENABLE_HDMI_LINK;
4026	ret = drm_dp_dpcd_writeb(aux: &intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, value: buf);
4027	if (ret < 0)
4028	return ret;
4029
4030	return 0;
4031	}
4032
4033	void intel_dp_check_frl_training(struct intel_dp *intel_dp)
4034	{
4035	struct intel_display *display = to_intel_display(intel_dp);
4036
4037	/*
4038	* Always go for FRL training if:
4039	* -PCON supports SRC_CTL_MODE (VESA DP2.0-HDMI2.1 PCON Spec Draft-1 Sec-7)
4040	* -sink is HDMI2.1
4041	*/
4042	if (!(intel_dp->downstream_ports[2] & DP_PCON_SOURCE_CTL_MODE) ||
4043	!intel_dp_is_hdmi_2_1_sink(intel_dp) ||
4044	intel_dp->frl.is_trained)
4045	return;
4046
4047	if (intel_dp_pcon_start_frl_training(intel_dp) < 0) {
4048	int ret, mode;
4049
4050	drm_dbg(display->drm,
4051	"Couldn't set FRL mode, continuing with TMDS mode\n");
4052	ret = intel_dp_pcon_set_tmds_mode(intel_dp);
4053	mode = drm_dp_pcon_hdmi_link_mode(aux: &intel_dp->aux, NULL);
4054
4055	if (ret < 0 || mode != DP_PCON_HDMI_MODE_TMDS)
4056	drm_dbg(display->drm,
4057	"Issue with PCON, cannot set TMDS mode\n");
4058	} else {
4059	drm_dbg(display->drm, "FRL training Completed\n");
4060	}
4061	}
4062
4063	static int
4064	intel_dp_pcon_dsc_enc_slice_height(const struct intel_crtc_state *crtc_state)
4065	{
4066	int vactive = crtc_state->hw.adjusted_mode.vdisplay;
4067
4068	return intel_hdmi_dsc_get_slice_height(vactive);
4069	}
4070
4071	static int
4072	intel_dp_pcon_dsc_enc_slices(struct intel_dp *intel_dp,
4073	const struct intel_crtc_state *crtc_state)
4074	{
4075	struct intel_connector *connector = intel_dp->attached_connector;
4076	const struct drm_display_info *info = &connector->base.display_info;
4077	int hdmi_throughput = info->hdmi.dsc_cap.clk_per_slice;
4078	int hdmi_max_slices = info->hdmi.dsc_cap.max_slices;
4079	int pcon_max_slices = drm_dp_pcon_dsc_max_slices(pcon_dsc_dpcd: intel_dp->pcon_dsc_dpcd);
4080	int pcon_max_slice_width = drm_dp_pcon_dsc_max_slice_width(pcon_dsc_dpcd: intel_dp->pcon_dsc_dpcd);
4081
4082	return intel_hdmi_dsc_get_num_slices(crtc_state, src_max_slices: pcon_max_slices,
4083	src_max_slice_width: pcon_max_slice_width,
4084	hdmi_max_slices, hdmi_throughput);
4085	}
4086
4087	static int
4088	intel_dp_pcon_dsc_enc_bpp(struct intel_dp *intel_dp,
4089	const struct intel_crtc_state *crtc_state,
4090	int num_slices, int slice_width)
4091	{
4092	struct intel_connector *connector = intel_dp->attached_connector;
4093	const struct drm_display_info *info = &connector->base.display_info;
4094	int output_format = crtc_state->output_format;
4095	bool hdmi_all_bpp = info->hdmi.dsc_cap.all_bpp;
4096	int pcon_fractional_bpp = drm_dp_pcon_dsc_bpp_incr(pcon_dsc_dpcd: intel_dp->pcon_dsc_dpcd);
4097	int hdmi_max_chunk_bytes =
4098	info->hdmi.dsc_cap.total_chunk_kbytes * 1024;
4099
4100	return intel_hdmi_dsc_get_bpp(src_fractional_bpp: pcon_fractional_bpp, slice_width,
4101	num_slices, output_format, hdmi_all_bpp,
4102	hdmi_max_chunk_bytes);
4103	}
4104
4105	void
4106	intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp,
4107	const struct intel_crtc_state *crtc_state)
4108	{
4109	struct intel_display *display = to_intel_display(intel_dp);
4110	struct intel_connector *connector = intel_dp->attached_connector;
4111	const struct drm_display_info *info;
4112	u8 pps_param[6];
4113	int slice_height;
4114	int slice_width;
4115	int num_slices;
4116	int bits_per_pixel;
4117	int ret;
4118	bool hdmi_is_dsc_1_2;
4119
4120	if (!intel_dp_is_hdmi_2_1_sink(intel_dp))
4121	return;
4122
4123	if (!connector)
4124	return;
4125
4126	info = &connector->base.display_info;
4127
4128	hdmi_is_dsc_1_2 = info->hdmi.dsc_cap.v_1p2;
4129
4130	if (!drm_dp_pcon_enc_is_dsc_1_2(pcon_dsc_dpcd: intel_dp->pcon_dsc_dpcd) ||
4131	!hdmi_is_dsc_1_2)
4132	return;
4133
4134	slice_height = intel_dp_pcon_dsc_enc_slice_height(crtc_state);
4135	if (!slice_height)
4136	return;
4137
4138	num_slices = intel_dp_pcon_dsc_enc_slices(intel_dp, crtc_state);
4139	if (!num_slices)
4140	return;
4141
4142	slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay,
4143	num_slices);
4144
4145	bits_per_pixel = intel_dp_pcon_dsc_enc_bpp(intel_dp, crtc_state,
4146	num_slices, slice_width);
4147	if (!bits_per_pixel)
4148	return;
4149
4150	pps_param[0] = slice_height & 0xFF;
4151	pps_param[1] = slice_height >> 8;
4152	pps_param[2] = slice_width & 0xFF;
4153	pps_param[3] = slice_width >> 8;
4154	pps_param[4] = bits_per_pixel & 0xFF;
4155	pps_param[5] = (bits_per_pixel >> 8) & 0x3;
4156
4157	ret = drm_dp_pcon_pps_override_param(aux: &intel_dp->aux, pps_param);
4158	if (ret < 0)
4159	drm_dbg_kms(display->drm, "Failed to set pcon DSC\n");
4160	}
4161
4162	void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
4163	const struct intel_crtc_state *crtc_state)
4164	{
4165	struct intel_display *display = to_intel_display(intel_dp);
4166	bool ycbcr444_to_420 = false;
4167	bool rgb_to_ycbcr = false;
4168	u8 tmp;
4169
4170	if (intel_dp->dpcd[DP_DPCD_REV] < 0x13)
4171	return;
4172
4173	if (!drm_dp_is_branch(dpcd: intel_dp->dpcd))
4174	return;
4175
4176	tmp = intel_dp_has_hdmi_sink(intel_dp) ? DP_HDMI_DVI_OUTPUT_CONFIG : 0;
4177
4178	if (drm_dp_dpcd_writeb(aux: &intel_dp->aux,
4179	DP_PROTOCOL_CONVERTER_CONTROL_0, value: tmp) != 1)
4180	drm_dbg_kms(display->drm,
4181	"Failed to %s protocol converter HDMI mode\n",
4182	str_enable_disable(intel_dp_has_hdmi_sink(intel_dp)));
4183
4184	if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
4185	switch (crtc_state->output_format) {
4186	case INTEL_OUTPUT_FORMAT_YCBCR420:
4187	break;
4188	case INTEL_OUTPUT_FORMAT_YCBCR444:
4189	ycbcr444_to_420 = true;
4190	break;
4191	case INTEL_OUTPUT_FORMAT_RGB:
4192	rgb_to_ycbcr = true;
4193	ycbcr444_to_420 = true;
4194	break;
4195	default:
4196	MISSING_CASE(crtc_state->output_format);
4197	break;
4198	}
4199	} else if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR444) {
4200	switch (crtc_state->output_format) {
4201	case INTEL_OUTPUT_FORMAT_YCBCR444:
4202	break;
4203	case INTEL_OUTPUT_FORMAT_RGB:
4204	rgb_to_ycbcr = true;
4205	break;
4206	default:
4207	MISSING_CASE(crtc_state->output_format);
4208	break;
4209	}
4210	}
4211
4212	tmp = ycbcr444_to_420 ? DP_CONVERSION_TO_YCBCR420_ENABLE : 0;
4213
4214	if (drm_dp_dpcd_writeb(aux: &intel_dp->aux,
4215	DP_PROTOCOL_CONVERTER_CONTROL_1, value: tmp) != 1)
4216	drm_dbg_kms(display->drm,
4217	"Failed to %s protocol converter YCbCr 4:2:0 conversion mode\n",
4218	str_enable_disable(intel_dp->dfp.ycbcr_444_to_420));
4219
4220	tmp = rgb_to_ycbcr ? DP_CONVERSION_BT709_RGB_YCBCR_ENABLE : 0;
4221
4222	if (drm_dp_pcon_convert_rgb_to_ycbcr(aux: &intel_dp->aux, color_spc: tmp) < 0)
4223	drm_dbg_kms(display->drm,
4224	"Failed to %s protocol converter RGB->YCbCr conversion mode\n",
4225	str_enable_disable(tmp));
4226	}
4227
4228	static bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
4229	{
4230	u8 dprx = 0;
4231
4232	if (drm_dp_dpcd_readb(aux: &intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
4233	valuep: &dprx) != 1)
4234	return false;
4235	return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
4236	}
4237
4238	static void intel_dp_read_dsc_dpcd(struct drm_dp_aux *aux,
4239	u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
4240	{
4241	if (drm_dp_dpcd_read(aux, DP_DSC_SUPPORT, buffer: dsc_dpcd,
4242	DP_DSC_RECEIVER_CAP_SIZE) < 0) {
4243	drm_err(aux->drm_dev,
4244	"Failed to read DPCD register 0x%x\n",
4245	DP_DSC_SUPPORT);
4246	return;
4247	}
4248
4249	drm_dbg_kms(aux->drm_dev, "DSC DPCD: %*ph\n",
4250	DP_DSC_RECEIVER_CAP_SIZE,
4251	dsc_dpcd);
4252	}
4253
4254	static void init_dsc_overall_throughput_limits(struct intel_connector *connector, bool is_branch)
4255	{
4256	u8 branch_caps[DP_DSC_BRANCH_CAP_SIZE];
4257	int line_width;
4258
4259	connector->dp.dsc_branch_caps.overall_throughput.rgb_yuv444 = INT_MAX;
4260	connector->dp.dsc_branch_caps.overall_throughput.yuv422_420 = INT_MAX;
4261	connector->dp.dsc_branch_caps.max_line_width = INT_MAX;
4262
4263	if (!is_branch)
4264	return;
4265
4266	if (drm_dp_dpcd_read_data(aux: connector->dp.dsc_decompression_aux,
4267	DP_DSC_BRANCH_OVERALL_THROUGHPUT_0, buffer: branch_caps,
4268	size: sizeof(branch_caps)) != 0)
4269	return;
4270
4271	connector->dp.dsc_branch_caps.overall_throughput.rgb_yuv444 =
4272	drm_dp_dsc_branch_max_overall_throughput(dsc_branch_dpcd: branch_caps, is_rgb_yuv444: true) ? : INT_MAX;
4273
4274	connector->dp.dsc_branch_caps.overall_throughput.yuv422_420 =
4275	drm_dp_dsc_branch_max_overall_throughput(dsc_branch_dpcd: branch_caps, is_rgb_yuv444: false) ? : INT_MAX;
4276
4277	line_width = drm_dp_dsc_branch_max_line_width(dsc_branch_dpcd: branch_caps);
4278	connector->dp.dsc_branch_caps.max_line_width = line_width > 0 ? line_width : INT_MAX;
4279	}
4280
4281	void intel_dp_get_dsc_sink_cap(u8 dpcd_rev,
4282	const struct drm_dp_desc *desc, bool is_branch,
4283	struct intel_connector *connector)
4284	{
4285	struct intel_display *display = to_intel_display(connector);
4286
4287	/*
4288	* Clear the cached register set to avoid using stale values
4289	* for the sinks that do not support DSC.
4290	*/
4291	memset(connector->dp.dsc_dpcd, 0, sizeof(connector->dp.dsc_dpcd));
4292
4293	/* Clear fec_capable to avoid using stale values */
4294	connector->dp.fec_capability = 0;
4295
4296	memset(&connector->dp.dsc_branch_caps, 0, sizeof(connector->dp.dsc_branch_caps));
4297	connector->dp.dsc_throughput_quirk = false;
4298
4299	if (dpcd_rev < DP_DPCD_REV_14)
4300	return;
4301
4302	intel_dp_read_dsc_dpcd(aux: connector->dp.dsc_decompression_aux,
4303	dsc_dpcd: connector->dp.dsc_dpcd);
4304
4305	if (drm_dp_dpcd_readb(aux: connector->dp.dsc_decompression_aux, DP_FEC_CAPABILITY,
4306	valuep: &connector->dp.fec_capability) < 0) {
4307	drm_err(display->drm, "Failed to read FEC DPCD register\n");
4308	return;
4309	}
4310
4311	drm_dbg_kms(display->drm, "FEC CAPABILITY: %x\n",
4312	connector->dp.fec_capability);
4313
4314	if (!(connector->dp.dsc_dpcd[0] & DP_DSC_DECOMPRESSION_IS_SUPPORTED))
4315	return;
4316
4317	init_dsc_overall_throughput_limits(connector, is_branch);
4318
4319	/*
4320	* TODO: Move the HW rev check as well to the DRM core quirk table if
4321	* that's required after clarifying the list of affected devices.
4322	*/
4323	if (drm_dp_has_quirk(desc, quirk: DP_DPCD_QUIRK_DSC_THROUGHPUT_BPP_LIMIT) &&
4324	desc->ident.hw_rev == 0x10)
4325	connector->dp.dsc_throughput_quirk = true;
4326	}
4327
4328	static void intel_edp_get_dsc_sink_cap(u8 edp_dpcd_rev, struct intel_connector *connector)
4329	{
4330	if (edp_dpcd_rev < DP_EDP_14)
4331	return;
4332
4333	intel_dp_read_dsc_dpcd(aux: connector->dp.dsc_decompression_aux, dsc_dpcd: connector->dp.dsc_dpcd);
4334
4335	if (connector->dp.dsc_dpcd[0] & DP_DSC_DECOMPRESSION_IS_SUPPORTED)
4336	init_dsc_overall_throughput_limits(connector, is_branch: false);
4337	}
4338
4339	static void
4340	intel_dp_detect_dsc_caps(struct intel_dp *intel_dp, struct intel_connector *connector)
4341	{
4342	struct intel_display *display = to_intel_display(intel_dp);
4343
4344	/* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
4345	if (!HAS_DSC(display))
4346	return;
4347
4348	if (intel_dp_is_edp(intel_dp))
4349	intel_edp_get_dsc_sink_cap(edp_dpcd_rev: intel_dp->edp_dpcd[0],
4350	connector);
4351	else
4352	intel_dp_get_dsc_sink_cap(dpcd_rev: intel_dp->dpcd[DP_DPCD_REV],
4353	desc: &intel_dp->desc, is_branch: drm_dp_is_branch(dpcd: intel_dp->dpcd),
4354	connector);
4355	}
4356
4357	static void intel_edp_mso_mode_fixup(struct intel_connector *connector,
4358	struct drm_display_mode *mode)
4359	{
4360	struct intel_display *display = to_intel_display(connector);
4361	struct intel_dp *intel_dp = intel_attached_dp(connector);
4362	int n = intel_dp->mso_link_count;
4363	int overlap = intel_dp->mso_pixel_overlap;
4364
4365	if (!mode || !n)
4366	return;
4367
4368	mode->hdisplay = (mode->hdisplay - overlap) * n;
4369	mode->hsync_start = (mode->hsync_start - overlap) * n;
4370	mode->hsync_end = (mode->hsync_end - overlap) * n;
4371	mode->htotal = (mode->htotal - overlap) * n;
4372	mode->clock *= n;
4373
4374	drm_mode_set_name(mode);
4375
4376	drm_dbg_kms(display->drm,
4377	"[CONNECTOR:%d:%s] using generated MSO mode: " DRM_MODE_FMT "\n",
4378	connector->base.base.id, connector->base.name,
4379	DRM_MODE_ARG(mode));
4380	}
4381
4382	void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp)
4383	{
4384	struct intel_display *display = to_intel_display(encoder);
4385	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4386	struct intel_connector *connector = intel_dp->attached_connector;
4387
4388	if (connector->panel.vbt.edp.bpp && pipe_bpp > connector->panel.vbt.edp.bpp) {
4389	/*
4390	* This is a big fat ugly hack.
4391	*
4392	* Some machines in UEFI boot mode provide us a VBT that has 18
4393	* bpp and 1.62 GHz link bandwidth for eDP, which for reasons
4394	* unknown we fail to light up. Yet the same BIOS boots up with
4395	* 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
4396	* max, not what it tells us to use.
4397	*
4398	* Note: This will still be broken if the eDP panel is not lit
4399	* up by the BIOS, and thus we can't get the mode at module
4400	* load.
4401	*/
4402	drm_dbg_kms(display->drm,
4403	"pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
4404	pipe_bpp, connector->panel.vbt.edp.bpp);
4405	connector->panel.vbt.edp.bpp = pipe_bpp;
4406	}
4407	}
4408
4409	static void intel_edp_mso_init(struct intel_dp *intel_dp)
4410	{
4411	struct intel_display *display = to_intel_display(intel_dp);
4412	struct intel_connector *connector = intel_dp->attached_connector;
4413	struct drm_display_info *info = &connector->base.display_info;
4414	u8 mso;
4415
4416	if (intel_dp->edp_dpcd[0] < DP_EDP_14)
4417	return;
4418
4419	if (drm_dp_dpcd_readb(aux: &intel_dp->aux, DP_EDP_MSO_LINK_CAPABILITIES, valuep: &mso) != 1) {
4420	drm_err(display->drm, "Failed to read MSO cap\n");
4421	return;
4422	}
4423
4424	/* Valid configurations are SST or MSO 2x1, 2x2, 4x1 */
4425	mso &= DP_EDP_MSO_NUMBER_OF_LINKS_MASK;
4426	if (mso % 2 || mso > drm_dp_max_lane_count(dpcd: intel_dp->dpcd)) {
4427	drm_err(display->drm, "Invalid MSO link count cap %u\n", mso);
4428	mso = 0;
4429	}
4430
4431	if (mso) {
4432	drm_dbg_kms(display->drm,
4433	"Sink MSO %ux%u configuration, pixel overlap %u\n",
4434	mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso,
4435	info->mso_pixel_overlap);
4436	if (!HAS_MSO(display)) {
4437	drm_err(display->drm,
4438	"No source MSO support, disabling\n");
4439	mso = 0;
4440	}
4441	}
4442
4443	intel_dp->mso_link_count = mso;
4444	intel_dp->mso_pixel_overlap = mso ? info->mso_pixel_overlap : 0;
4445	}
4446
4447	static void
4448	intel_edp_set_data_override_rates(struct intel_dp *intel_dp)
4449	{
4450	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4451	int *sink_rates = intel_dp->sink_rates;
4452	int i, count = 0;
4453
4454	for (i = 0; i < intel_dp->num_sink_rates; i++) {
4455	if (intel_bios_encoder_reject_edp_rate(devdata: encoder->devdata,
4456	rate: intel_dp->sink_rates[i]))
4457	continue;
4458
4459	sink_rates[count++] = intel_dp->sink_rates[i];
4460	}
4461	intel_dp->num_sink_rates = count;
4462	}
4463
4464	static void
4465	intel_edp_set_sink_rates(struct intel_dp *intel_dp)
4466	{
4467	struct intel_display *display = to_intel_display(intel_dp);
4468
4469	intel_dp->num_sink_rates = 0;
4470
4471	if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
4472	__le16 sink_rates[DP_MAX_SUPPORTED_RATES];
4473	int i;
4474
4475	drm_dp_dpcd_read(aux: &intel_dp->aux, DP_SUPPORTED_LINK_RATES,
4476	buffer: sink_rates, size: sizeof(sink_rates));
4477
4478	for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
4479	int rate;
4480
4481	/* Value read multiplied by 200kHz gives the per-lane
4482	* link rate in kHz. The source rates are, however,
4483	* stored in terms of LS_Clk kHz. The full conversion
4484	* back to symbols is
4485	* (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
4486	*/
4487	rate = le16_to_cpu(sink_rates[i]) * 200 / 10;
4488
4489	if (rate == 0)
4490	break;
4491
4492	/*
4493	* Some platforms cannot reliably drive HBR3 rates due to PHY limitations,
4494	* even if the sink advertises support. Reject any sink rates above HBR2 on
4495	* the known machines for stable output.
4496	*/
4497	if (rate > 540000 &&
4498	intel_has_quirk(display, quirk: QUIRK_EDP_LIMIT_RATE_HBR2))
4499	break;
4500
4501	intel_dp->sink_rates[i] = rate;
4502	}
4503	intel_dp->num_sink_rates = i;
4504	}
4505
4506	/*
4507	* Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
4508	* default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
4509	*/
4510	if (intel_dp->num_sink_rates)
4511	intel_dp->use_rate_select = true;
4512	else
4513	intel_dp_set_sink_rates(intel_dp);
4514
4515	intel_edp_set_data_override_rates(intel_dp);
4516	}
4517
4518	static bool
4519	intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector)
4520	{
4521	struct intel_display *display = to_intel_display(intel_dp);
4522
4523	/* this function is meant to be called only once */
4524	drm_WARN_ON(display->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
4525
4526	if (drm_dp_read_dpcd_caps(aux: &intel_dp->aux, dpcd: intel_dp->dpcd) != 0)
4527	return false;
4528
4529	drm_dp_read_desc(aux: &intel_dp->aux, desc: &intel_dp->desc,
4530	is_branch: drm_dp_is_branch(dpcd: intel_dp->dpcd));
4531	intel_init_dpcd_quirks(intel_dp, ident: &intel_dp->desc.ident);
4532
4533	intel_dp->colorimetry_support =
4534	intel_dp_get_colorimetry_status(intel_dp);
4535
4536	/*
4537	* Read the eDP display control registers.
4538	*
4539	* Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
4540	* DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
4541	* set, but require eDP 1.4+ detection (e.g. for supported link rates
4542	* method). The display control registers should read zero if they're
4543	* not supported anyway.
4544	*/
4545	if (drm_dp_dpcd_read(aux: &intel_dp->aux, DP_EDP_DPCD_REV,
4546	buffer: intel_dp->edp_dpcd, size: sizeof(intel_dp->edp_dpcd)) ==
4547	sizeof(intel_dp->edp_dpcd)) {
4548	drm_dbg_kms(display->drm, "eDP DPCD: %*ph\n",
4549	(int)sizeof(intel_dp->edp_dpcd),
4550	intel_dp->edp_dpcd);
4551
4552	intel_dp->use_max_params = intel_dp->edp_dpcd[0] < DP_EDP_14;
4553	}
4554
4555	/*
4556	* If needed, program our source OUI so we can make various Intel-specific AUX services
4557	* available (such as HDR backlight controls)
4558	*/
4559	intel_dp_init_source_oui(intel_dp);
4560
4561	/*
4562	* This has to be called after intel_dp->edp_dpcd is filled, PSR checks
4563	* for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
4564	*/
4565	intel_psr_init_dpcd(intel_dp);
4566
4567	intel_edp_set_sink_rates(intel_dp);
4568	intel_dp_set_max_sink_lane_count(intel_dp);
4569
4570	/* Read the eDP DSC DPCD registers */
4571	intel_dp_detect_dsc_caps(intel_dp, connector);
4572
4573	return true;
4574	}
4575
4576	static bool
4577	intel_dp_has_sink_count(struct intel_dp *intel_dp)
4578	{
4579	if (!intel_dp->attached_connector)
4580	return false;
4581
4582	return drm_dp_read_sink_count_cap(connector: &intel_dp->attached_connector->base,
4583	dpcd: intel_dp->dpcd,
4584	desc: &intel_dp->desc);
4585	}
4586
4587	void intel_dp_update_sink_caps(struct intel_dp *intel_dp)
4588	{
4589	intel_dp_set_sink_rates(intel_dp);
4590	intel_dp_set_max_sink_lane_count(intel_dp);
4591	intel_dp_set_common_rates(intel_dp);
4592	}
4593
4594	static bool
4595	intel_dp_get_dpcd(struct intel_dp *intel_dp)
4596	{
4597	int ret;
4598
4599	if (intel_dp_init_lttpr_and_dprx_caps(intel_dp) < 0)
4600	return false;
4601
4602	/*
4603	* Don't clobber cached eDP rates. Also skip re-reading
4604	* the OUI/ID since we know it won't change.
4605	*/
4606	if (!intel_dp_is_edp(intel_dp)) {
4607	drm_dp_read_desc(aux: &intel_dp->aux, desc: &intel_dp->desc,
4608	is_branch: drm_dp_is_branch(dpcd: intel_dp->dpcd));
4609
4610	intel_init_dpcd_quirks(intel_dp, ident: &intel_dp->desc.ident);
4611
4612	intel_dp->colorimetry_support =
4613	intel_dp_get_colorimetry_status(intel_dp);
4614
4615	intel_dp_update_sink_caps(intel_dp);
4616	}
4617
4618	if (intel_dp_has_sink_count(intel_dp)) {
4619	ret = drm_dp_read_sink_count(aux: &intel_dp->aux);
4620	if (ret < 0)
4621	return false;
4622
4623	/*
4624	* Sink count can change between short pulse hpd hence
4625	* a member variable in intel_dp will track any changes
4626	* between short pulse interrupts.
4627	*/
4628	intel_dp->sink_count = ret;
4629
4630	/*
4631	* SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
4632	* a dongle is present but no display. Unless we require to know
4633	* if a dongle is present or not, we don't need to update
4634	* downstream port information. So, an early return here saves
4635	* time from performing other operations which are not required.
4636	*/
4637	if (!intel_dp->sink_count)
4638	return false;
4639	}
4640
4641	return drm_dp_read_downstream_info(aux: &intel_dp->aux, dpcd: intel_dp->dpcd,
4642	downstream_ports: intel_dp->downstream_ports) == 0;
4643	}
4644
4645	static const char *intel_dp_mst_mode_str(enum drm_dp_mst_mode mst_mode)
4646	{
4647	if (mst_mode == DRM_DP_MST)
4648	return "MST";
4649	else if (mst_mode == DRM_DP_SST_SIDEBAND_MSG)
4650	return "SST w/ sideband messaging";
4651	else
4652	return "SST";
4653	}
4654
4655	static enum drm_dp_mst_mode
4656	intel_dp_mst_mode_choose(struct intel_dp *intel_dp,
4657	enum drm_dp_mst_mode sink_mst_mode)
4658	{
4659	struct intel_display *display = to_intel_display(intel_dp);
4660
4661	if (!display->params.enable_dp_mst)
4662	return DRM_DP_SST;
4663
4664	if (!intel_dp_mst_source_support(intel_dp))
4665	return DRM_DP_SST;
4666
4667	if (sink_mst_mode == DRM_DP_SST_SIDEBAND_MSG &&
4668	!(intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B))
4669	return DRM_DP_SST;
4670
4671	return sink_mst_mode;
4672	}
4673
4674	static enum drm_dp_mst_mode
4675	intel_dp_mst_detect(struct intel_dp *intel_dp)
4676	{
4677	struct intel_display *display = to_intel_display(intel_dp);
4678	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4679	enum drm_dp_mst_mode sink_mst_mode;
4680	enum drm_dp_mst_mode mst_detect;
4681
4682	sink_mst_mode = drm_dp_read_mst_cap(aux: &intel_dp->aux, dpcd: intel_dp->dpcd);
4683
4684	mst_detect = intel_dp_mst_mode_choose(intel_dp, sink_mst_mode);
4685
4686	drm_dbg_kms(display->drm,
4687	"[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s -> enable: %s\n",
4688	encoder->base.base.id, encoder->base.name,
4689	str_yes_no(intel_dp_mst_source_support(intel_dp)),
4690	intel_dp_mst_mode_str(sink_mst_mode),
4691	str_yes_no(display->params.enable_dp_mst),
4692	intel_dp_mst_mode_str(mst_detect));
4693
4694	return mst_detect;
4695	}
4696
4697	static void
4698	intel_dp_mst_configure(struct intel_dp *intel_dp)
4699	{
4700	if (!intel_dp_mst_source_support(intel_dp))
4701	return;
4702
4703	intel_dp->is_mst = intel_dp->mst_detect != DRM_DP_SST;
4704
4705	if (intel_dp->is_mst)
4706	intel_dp_mst_prepare_probe(intel_dp);
4707
4708	drm_dp_mst_topology_mgr_set_mst(mgr: &intel_dp->mst.mgr, mst_state: intel_dp->is_mst);
4709
4710	/* Avoid stale info on the next detect cycle. */
4711	intel_dp->mst_detect = DRM_DP_SST;
4712	}
4713
4714	static void
4715	intel_dp_mst_disconnect(struct intel_dp *intel_dp)
4716	{
4717	struct intel_display *display = to_intel_display(intel_dp);
4718
4719	if (!intel_dp->is_mst)
4720	return;
4721
4722	drm_dbg_kms(display->drm,
4723	"MST device may have disappeared %d vs %d\n",
4724	intel_dp->is_mst, intel_dp->mst.mgr.mst_state);
4725	intel_dp->is_mst = false;
4726	drm_dp_mst_topology_mgr_set_mst(mgr: &intel_dp->mst.mgr, mst_state: intel_dp->is_mst);
4727	}
4728
4729	static bool
4730	intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *esi)
4731	{
4732	struct intel_display *display = to_intel_display(intel_dp);
4733
4734	/*
4735	* Display WA for HSD #13013007775: mtl/arl/lnl
4736	* Read the sink count and link service IRQ registers in separate
4737	* transactions to prevent disconnecting the sink on a TBT link
4738	* inadvertently.
4739	*/
4740	if (IS_DISPLAY_VER(display, 14, 20) && !display->platform.battlemage) {
4741	if (drm_dp_dpcd_read(aux: &intel_dp->aux, DP_SINK_COUNT_ESI, buffer: esi, size: 3) != 3)
4742	return false;
4743
4744	/* DP_SINK_COUNT_ESI + 3 == DP_LINK_SERVICE_IRQ_VECTOR_ESI0 */
4745	return drm_dp_dpcd_readb(aux: &intel_dp->aux, DP_LINK_SERVICE_IRQ_VECTOR_ESI0,
4746	valuep: &esi[3]) == 1;
4747	}
4748
4749	return drm_dp_dpcd_read(aux: &intel_dp->aux, DP_SINK_COUNT_ESI, buffer: esi, size: 4) == 4;
4750	}
4751
4752	static bool intel_dp_ack_sink_irq_esi(struct intel_dp *intel_dp, u8 esi[4])
4753	{
4754	int retry;
4755
4756	for (retry = 0; retry < 3; retry++) {
4757	if (drm_dp_dpcd_write(aux: &intel_dp->aux, DP_SINK_COUNT_ESI + 1,
4758	buffer: &esi[1], size: 3) == 3)
4759	return true;
4760	}
4761
4762	return false;
4763	}
4764
4765	bool
4766	intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
4767	const struct drm_connector_state *conn_state)
4768	{
4769	/*
4770	* As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
4771	* of Color Encoding Format and Content Color Gamut], in order to
4772	* sending YCBCR 420 or HDR BT.2020 signals we should use DP VSC SDP.
4773	*/
4774	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
4775	return true;
4776
4777	switch (conn_state->colorspace) {
4778	case DRM_MODE_COLORIMETRY_SYCC_601:
4779	case DRM_MODE_COLORIMETRY_OPYCC_601:
4780	case DRM_MODE_COLORIMETRY_BT2020_YCC:
4781	case DRM_MODE_COLORIMETRY_BT2020_RGB:
4782	case DRM_MODE_COLORIMETRY_BT2020_CYCC:
4783	return true;
4784	default:
4785	break;
4786	}
4787
4788	return false;
4789	}
4790
4791	static ssize_t intel_dp_as_sdp_pack(const struct drm_dp_as_sdp *as_sdp,
4792	struct dp_sdp *sdp, size_t size)
4793	{
4794	size_t length = sizeof(struct dp_sdp);
4795
4796	if (size < length)
4797	return -ENOSPC;
4798
4799	memset(sdp, 0, size);
4800
4801	/* Prepare AS (Adaptive Sync) SDP Header */
4802	sdp->sdp_header.HB0 = 0;
4803	sdp->sdp_header.HB1 = as_sdp->sdp_type;
4804	sdp->sdp_header.HB2 = 0x02;
4805	sdp->sdp_header.HB3 = as_sdp->length;
4806
4807	/* Fill AS (Adaptive Sync) SDP Payload */
4808	sdp->db[0] = as_sdp->mode;
4809	sdp->db[1] = as_sdp->vtotal & 0xFF;
4810	sdp->db[2] = (as_sdp->vtotal >> 8) & 0xFF;
4811	sdp->db[3] = as_sdp->target_rr & 0xFF;
4812	sdp->db[4] = (as_sdp->target_rr >> 8) & 0x3;
4813
4814	if (as_sdp->target_rr_divider)
4815	sdp->db[4] |= 0x20;
4816
4817	return length;
4818	}
4819
4820	static ssize_t
4821	intel_dp_hdr_metadata_infoframe_sdp_pack(struct intel_display *display,
4822	const struct hdmi_drm_infoframe *drm_infoframe,
4823	struct dp_sdp *sdp,
4824	size_t size)
4825	{
4826	size_t length = sizeof(struct dp_sdp);
4827	const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE;
4828	unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];
4829	ssize_t len;
4830
4831	if (size < length)
4832	return -ENOSPC;
4833
4834	memset(sdp, 0, size);
4835
4836	len = hdmi_drm_infoframe_pack_only(frame: drm_infoframe, buffer: buf, size: sizeof(buf));
4837	if (len < 0) {
4838	drm_dbg_kms(display->drm,
4839	"buffer size is smaller than hdr metadata infoframe\n");
4840	return -ENOSPC;
4841	}
4842
4843	if (len != infoframe_size) {
4844	drm_dbg_kms(display->drm, "wrong static hdr metadata size\n");
4845	return -ENOSPC;
4846	}
4847
4848	/*
4849	* Set up the infoframe sdp packet for HDR static metadata.
4850	* Prepare VSC Header for SU as per DP 1.4a spec,
4851	* Table 2-100 and Table 2-101
4852	*/
4853
4854	/* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */
4855	sdp->sdp_header.HB0 = 0;
4856	/*
4857	* Packet Type 80h + Non-audio INFOFRAME Type value
4858	* HDMI_INFOFRAME_TYPE_DRM: 0x87
4859	* - 80h + Non-audio INFOFRAME Type value
4860	* - InfoFrame Type: 0x07
4861	* [CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame]
4862	*/
4863	sdp->sdp_header.HB1 = drm_infoframe->type;
4864	/*
4865	* Least Significant Eight Bits of (Data Byte Count – 1)
4866	* infoframe_size - 1
4867	*/
4868	sdp->sdp_header.HB2 = 0x1D;
4869	/* INFOFRAME SDP Version Number */
4870	sdp->sdp_header.HB3 = (0x13 << 2);
4871	/* CTA Header Byte 2 (INFOFRAME Version Number) */
4872	sdp->db[0] = drm_infoframe->version;
4873	/* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
4874	sdp->db[1] = drm_infoframe->length;
4875	/*
4876	* Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
4877	* HDMI_INFOFRAME_HEADER_SIZE
4878	*/
4879	BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2);
4880	memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
4881	HDMI_DRM_INFOFRAME_SIZE);
4882
4883	/*
4884	* Size of DP infoframe sdp packet for HDR static metadata consists of
4885	* - DP SDP Header(struct dp_sdp_header): 4 bytes
4886	* - Two Data Blocks: 2 bytes
4887	* CTA Header Byte2 (INFOFRAME Version Number)
4888	* CTA Header Byte3 (Length of INFOFRAME)
4889	* - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
4890	*
4891	* Prior to GEN11's GMP register size is identical to DP HDR static metadata
4892	* infoframe size. But GEN11+ has larger than that size, write_infoframe
4893	* will pad rest of the size.
4894	*/
4895	return sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE;
4896	}
4897
4898	static void intel_write_dp_sdp(struct intel_encoder *encoder,
4899	const struct intel_crtc_state *crtc_state,
4900	unsigned int type)
4901	{
4902	struct intel_display *display = to_intel_display(encoder);
4903	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4904	struct dp_sdp sdp = {};
4905	ssize_t len;
4906
4907	if ((crtc_state->infoframes.enable &
4908	intel_hdmi_infoframe_enable(type)) == 0)
4909	return;
4910
4911	switch (type) {
4912	case DP_SDP_VSC:
4913	len = drm_dp_vsc_sdp_pack(vsc: &crtc_state->infoframes.vsc, sdp: &sdp);
4914	break;
4915	case HDMI_PACKET_TYPE_GAMUT_METADATA:
4916	len = intel_dp_hdr_metadata_infoframe_sdp_pack(display,
4917	drm_infoframe: &crtc_state->infoframes.drm.drm,
4918	sdp: &sdp, size: sizeof(sdp));
4919	break;
4920	case DP_SDP_ADAPTIVE_SYNC:
4921	len = intel_dp_as_sdp_pack(as_sdp: &crtc_state->infoframes.as_sdp, sdp: &sdp,
4922	size: sizeof(sdp));
4923	break;
4924	default:
4925	MISSING_CASE(type);
4926	return;
4927	}
4928
4929	if (drm_WARN_ON(display->drm, len < 0))
4930	return;
4931
4932	dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);
4933	}
4934
4935	void intel_dp_set_infoframes(struct intel_encoder *encoder,
4936	bool enable,
4937	const struct intel_crtc_state *crtc_state,
4938	const struct drm_connector_state *conn_state)
4939	{
4940	struct intel_display *display = to_intel_display(encoder);
4941	i915_reg_t reg = HSW_TVIDEO_DIP_CTL(display, crtc_state->cpu_transcoder);
4942	u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
4943	VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |
4944	VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;
4945
4946	if (HAS_AS_SDP(display))
4947	dip_enable |= VIDEO_DIP_ENABLE_AS_ADL;
4948
4949	u32 val = intel_de_read(display, reg) & ~dip_enable;
4950
4951	/* TODO: Sanitize DSC enabling wrt. intel_dsc_dp_pps_write(). */
4952	if (!enable && HAS_DSC(display))
4953	val &= ~VDIP_ENABLE_PPS;
4954
4955	/*
4956	* This routine disables VSC DIP if the function is called
4957	* to disable SDP or if it does not have PSR
4958	*/
4959	if (!enable || !crtc_state->has_psr)
4960	val &= ~VIDEO_DIP_ENABLE_VSC_HSW;
4961
4962	intel_de_write(display, reg, val);
4963	intel_de_posting_read(display, reg);
4964
4965	if (!enable)
4966	return;
4967
4968	intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
4969	intel_write_dp_sdp(encoder, crtc_state, DP_SDP_ADAPTIVE_SYNC);
4970
4971	intel_write_dp_sdp(encoder, crtc_state, type: HDMI_PACKET_TYPE_GAMUT_METADATA);
4972	}
4973
4974	static
4975	int intel_dp_as_sdp_unpack(struct drm_dp_as_sdp *as_sdp,
4976	const void *buffer, size_t size)
4977	{
4978	const struct dp_sdp *sdp = buffer;
4979
4980	if (size < sizeof(struct dp_sdp))
4981	return -EINVAL;
4982
4983	memset(as_sdp, 0, sizeof(*as_sdp));
4984
4985	if (sdp->sdp_header.HB0 != 0)
4986	return -EINVAL;
4987
4988	if (sdp->sdp_header.HB1 != DP_SDP_ADAPTIVE_SYNC)
4989	return -EINVAL;
4990
4991	if (sdp->sdp_header.HB2 != 0x02)
4992	return -EINVAL;
4993
4994	if ((sdp->sdp_header.HB3 & 0x3F) != 9)
4995	return -EINVAL;
4996
4997	as_sdp->length = sdp->sdp_header.HB3 & DP_ADAPTIVE_SYNC_SDP_LENGTH;
4998	as_sdp->mode = sdp->db[0] & DP_ADAPTIVE_SYNC_SDP_OPERATION_MODE;
4999	as_sdp->vtotal = (sdp->db[2] << 8) | sdp->db[1];
5000	as_sdp->target_rr = (u64)sdp->db[3] | ((u64)sdp->db[4] & 0x3);
5001	as_sdp->target_rr_divider = sdp->db[4] & 0x20 ? true : false;
5002
5003	return 0;
5004	}
5005
5006	static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc,
5007	const void *buffer, size_t size)
5008	{
5009	const struct dp_sdp *sdp = buffer;
5010
5011	if (size < sizeof(struct dp_sdp))
5012	return -EINVAL;
5013
5014	memset(vsc, 0, sizeof(*vsc));
5015
5016	if (sdp->sdp_header.HB0 != 0)
5017	return -EINVAL;
5018
5019	if (sdp->sdp_header.HB1 != DP_SDP_VSC)
5020	return -EINVAL;
5021
5022	vsc->sdp_type = sdp->sdp_header.HB1;
5023	vsc->revision = sdp->sdp_header.HB2;
5024	vsc->length = sdp->sdp_header.HB3;
5025
5026	if ((sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) ||
5027	(sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe) ||
5028	(sdp->sdp_header.HB2 == 0x6 && sdp->sdp_header.HB3 == 0x10)) {
5029	/*
5030	* - HB2 = 0x2, HB3 = 0x8
5031	* VSC SDP supporting 3D stereo + PSR
5032	* - HB2 = 0x4, HB3 = 0xe
5033	* VSC SDP supporting 3D stereo + PSR2 with Y-coordinate of
5034	* first scan line of the SU region (applies to eDP v1.4b
5035	* and higher).
5036	* - HB2 = 0x6, HB3 = 0x10
5037	* VSC SDP supporting 3D stereo + Panel Replay.
5038	*/
5039	return 0;
5040	} else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) {
5041	/*
5042	* - HB2 = 0x5, HB3 = 0x13
5043	* VSC SDP supporting 3D stereo + PSR2 + Pixel Encoding/Colorimetry
5044	* Format.
5045	*/
5046	vsc->pixelformat = (sdp->db[16] >> 4) & 0xf;
5047	vsc->colorimetry = sdp->db[16] & 0xf;
5048	vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1;
5049
5050	switch (sdp->db[17] & 0x7) {
5051	case 0x0:
5052	vsc->bpc = 6;
5053	break;
5054	case 0x1:
5055	vsc->bpc = 8;
5056	break;
5057	case 0x2:
5058	vsc->bpc = 10;
5059	break;
5060	case 0x3:
5061	vsc->bpc = 12;
5062	break;
5063	case 0x4:
5064	vsc->bpc = 16;
5065	break;
5066	default:
5067	MISSING_CASE(sdp->db[17] & 0x7);
5068	return -EINVAL;
5069	}
5070
5071	vsc->content_type = sdp->db[18] & 0x7;
5072	} else {
5073	return -EINVAL;
5074	}
5075
5076	return 0;
5077	}
5078
5079	static void
5080	intel_read_dp_as_sdp(struct intel_encoder *encoder,
5081	struct intel_crtc_state *crtc_state,
5082	struct drm_dp_as_sdp *as_sdp)
5083	{
5084	struct intel_display *display = to_intel_display(encoder);
5085	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
5086	unsigned int type = DP_SDP_ADAPTIVE_SYNC;
5087	struct dp_sdp sdp = {};
5088	int ret;
5089
5090	if ((crtc_state->infoframes.enable &
5091	intel_hdmi_infoframe_enable(type)) == 0)
5092	return;
5093
5094	dig_port->read_infoframe(encoder, crtc_state, type, &sdp,
5095	sizeof(sdp));
5096
5097	ret = intel_dp_as_sdp_unpack(as_sdp, buffer: &sdp, size: sizeof(sdp));
5098	if (ret)
5099	drm_dbg_kms(display->drm, "Failed to unpack DP AS SDP\n");
5100	}
5101
5102	static int
5103	intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe *drm_infoframe,
5104	const void *buffer, size_t size)
5105	{
5106	int ret;
5107
5108	const struct dp_sdp *sdp = buffer;
5109
5110	if (size < sizeof(struct dp_sdp))
5111	return -EINVAL;
5112
5113	if (sdp->sdp_header.HB0 != 0)
5114	return -EINVAL;
5115
5116	if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM)
5117	return -EINVAL;
5118
5119	/*
5120	* Least Significant Eight Bits of (Data Byte Count – 1)
5121	* 1Dh (i.e., Data Byte Count = 30 bytes).
5122	*/
5123	if (sdp->sdp_header.HB2 != 0x1D)
5124	return -EINVAL;
5125
5126	/* Most Significant Two Bits of (Data Byte Count – 1), Clear to 00b. */
5127	if ((sdp->sdp_header.HB3 & 0x3) != 0)
5128	return -EINVAL;
5129
5130	/* INFOFRAME SDP Version Number */
5131	if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13)
5132	return -EINVAL;
5133
5134	/* CTA Header Byte 2 (INFOFRAME Version Number) */
5135	if (sdp->db[0] != 1)
5136	return -EINVAL;
5137
5138	/* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
5139	if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE)
5140	return -EINVAL;
5141
5142	ret = hdmi_drm_infoframe_unpack_only(frame: drm_infoframe, buffer: &sdp->db[2],
5143	HDMI_DRM_INFOFRAME_SIZE);
5144
5145	return ret;
5146	}
5147
5148	static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder,
5149	struct intel_crtc_state *crtc_state,
5150	struct drm_dp_vsc_sdp *vsc)
5151	{
5152	struct intel_display *display = to_intel_display(encoder);
5153	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
5154	unsigned int type = DP_SDP_VSC;
5155	struct dp_sdp sdp = {};
5156	int ret;
5157
5158	if ((crtc_state->infoframes.enable &
5159	intel_hdmi_infoframe_enable(type)) == 0)
5160	return;
5161
5162	dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp));
5163
5164	ret = intel_dp_vsc_sdp_unpack(vsc, buffer: &sdp, size: sizeof(sdp));
5165
5166	if (ret)
5167	drm_dbg_kms(display->drm, "Failed to unpack DP VSC SDP\n");
5168	}
5169
5170	static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encoder,
5171	struct intel_crtc_state *crtc_state,
5172	struct hdmi_drm_infoframe *drm_infoframe)
5173	{
5174	struct intel_display *display = to_intel_display(encoder);
5175	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
5176	unsigned int type = HDMI_PACKET_TYPE_GAMUT_METADATA;
5177	struct dp_sdp sdp = {};
5178	int ret;
5179
5180	if ((crtc_state->infoframes.enable &
5181	intel_hdmi_infoframe_enable(type)) == 0)
5182	return;
5183
5184	dig_port->read_infoframe(encoder, crtc_state, type, &sdp,
5185	sizeof(sdp));
5186
5187	ret = intel_dp_hdr_metadata_infoframe_sdp_unpack(drm_infoframe, buffer: &sdp,
5188	size: sizeof(sdp));
5189
5190	if (ret)
5191	drm_dbg_kms(display->drm,
5192	"Failed to unpack DP HDR Metadata Infoframe SDP\n");
5193	}
5194
5195	void intel_read_dp_sdp(struct intel_encoder *encoder,
5196	struct intel_crtc_state *crtc_state,
5197	unsigned int type)
5198	{
5199	switch (type) {
5200	case DP_SDP_VSC:
5201	intel_read_dp_vsc_sdp(encoder, crtc_state,
5202	vsc: &crtc_state->infoframes.vsc);
5203	break;
5204	case HDMI_PACKET_TYPE_GAMUT_METADATA:
5205	intel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state,
5206	drm_infoframe: &crtc_state->infoframes.drm.drm);
5207	break;
5208	case DP_SDP_ADAPTIVE_SYNC:
5209	intel_read_dp_as_sdp(encoder, crtc_state,
5210	as_sdp: &crtc_state->infoframes.as_sdp);
5211	break;
5212	default:
5213	MISSING_CASE(type);
5214	break;
5215	}
5216	}
5217
5218	static bool intel_dp_link_ok(struct intel_dp *intel_dp,
5219	u8 link_status[DP_LINK_STATUS_SIZE])
5220	{
5221	struct intel_display *display = to_intel_display(intel_dp);
5222	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
5223	bool uhbr = intel_dp->link_rate >= 1000000;
5224	bool ok;
5225
5226	if (uhbr)
5227	ok = drm_dp_128b132b_lane_channel_eq_done(link_status,
5228	lane_count: intel_dp->lane_count);
5229	else
5230	ok = drm_dp_channel_eq_ok(link_status, lane_count: intel_dp->lane_count);
5231
5232	if (ok)
5233	return true;
5234
5235	intel_dp_dump_link_status(intel_dp, dp_phy: DP_PHY_DPRX, link_status);
5236	drm_dbg_kms(display->drm,
5237	"[ENCODER:%d:%s] %s link not ok, retraining\n",
5238	encoder->base.base.id, encoder->base.name,
5239	uhbr ? "128b/132b" : "8b/10b");
5240
5241	return false;
5242	}
5243
5244	static void
5245	intel_dp_mst_hpd_irq(struct intel_dp *intel_dp, u8 *esi, u8 *ack)
5246	{
5247	bool handled = false;
5248
5249	drm_dp_mst_hpd_irq_handle_event(mgr: &intel_dp->mst.mgr, esi, ack, handled: &handled);
5250
5251	if (esi[1] & DP_CP_IRQ) {
5252	intel_hdcp_handle_cp_irq(connector: intel_dp->attached_connector);
5253	ack[1] |= DP_CP_IRQ;
5254	}
5255	}
5256
5257	static bool intel_dp_mst_link_status(struct intel_dp *intel_dp)
5258	{
5259	struct intel_display *display = to_intel_display(intel_dp);
5260	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
5261	u8 link_status[DP_LINK_STATUS_SIZE] = {};
5262	const size_t esi_link_status_size = DP_LINK_STATUS_SIZE - 2;
5263
5264	if (drm_dp_dpcd_read(aux: &intel_dp->aux, DP_LANE0_1_STATUS_ESI, buffer: link_status,
5265	size: esi_link_status_size) != esi_link_status_size) {
5266	drm_err(display->drm,
5267	"[ENCODER:%d:%s] Failed to read link status\n",
5268	encoder->base.base.id, encoder->base.name);
5269	return false;
5270	}
5271
5272	return intel_dp_link_ok(intel_dp, link_status);
5273	}
5274
5275	/**
5276	* intel_dp_check_mst_status - service any pending MST interrupts, check link status
5277	* @intel_dp: Intel DP struct
5278	*
5279	* Read any pending MST interrupts, call MST core to handle these and ack the
5280	* interrupts. Check if the main and AUX link state is ok.
5281	*
5282	* Returns:
5283	* - %true if pending interrupts were serviced (or no interrupts were
5284	* pending) w/o detecting an error condition.
5285	* - %false if an error condition - like AUX failure or a loss of link - is
5286	* detected, or another condition - like a DP tunnel BW state change - needs
5287	* servicing from the hotplug work.
5288	*/
5289	static bool
5290	intel_dp_check_mst_status(struct intel_dp *intel_dp)
5291	{
5292	struct intel_display *display = to_intel_display(intel_dp);
5293	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5294	struct intel_encoder *encoder = &dig_port->base;
5295	bool link_ok = true;
5296	bool reprobe_needed = false;
5297
5298	for (;;) {
5299	u8 esi[4] = {};
5300	u8 ack[4] = {};
5301
5302	if (!intel_dp_get_sink_irq_esi(intel_dp, esi)) {
5303	drm_dbg_kms(display->drm,
5304	"failed to get ESI - device may have failed\n");
5305	link_ok = false;
5306
5307	break;
5308	}
5309
5310	drm_dbg_kms(display->drm, "DPRX ESI: %4ph\n", esi);
5311
5312	if (intel_dp_mst_active_streams(intel_dp) > 0 && link_ok &&
5313	esi[3] & LINK_STATUS_CHANGED) {
5314	if (!intel_dp_mst_link_status(intel_dp))
5315	link_ok = false;
5316	ack[3] |= LINK_STATUS_CHANGED;
5317	}
5318
5319	intel_dp_mst_hpd_irq(intel_dp, esi, ack);
5320
5321	if (esi[3] & DP_TUNNELING_IRQ) {
5322	if (drm_dp_tunnel_handle_irq(mgr: display->dp_tunnel_mgr,
5323	aux: &intel_dp->aux))
5324	reprobe_needed = true;
5325	ack[3] |= DP_TUNNELING_IRQ;
5326	}
5327
5328	if (mem_is_zero(s: ack, n: sizeof(ack)))
5329	break;
5330
5331	if (!intel_dp_ack_sink_irq_esi(intel_dp, esi: ack))
5332	drm_dbg_kms(display->drm, "Failed to ack ESI\n");
5333
5334	if (ack[1] & (DP_DOWN_REP_MSG_RDY | DP_UP_REQ_MSG_RDY))
5335	drm_dp_mst_hpd_irq_send_new_request(mgr: &intel_dp->mst.mgr);
5336	}
5337
5338	if (!link_ok || intel_dp->link.force_retrain)
5339	intel_encoder_link_check_queue_work(encoder, delay_ms: 0);
5340
5341	return !reprobe_needed;
5342	}
5343
5344	static void
5345	intel_dp_handle_hdmi_link_status_change(struct intel_dp *intel_dp)
5346	{
5347	bool is_active;
5348	u8 buf = 0;
5349
5350	is_active = drm_dp_pcon_hdmi_link_active(aux: &intel_dp->aux);
5351	if (intel_dp->frl.is_trained && !is_active) {
5352	if (drm_dp_dpcd_readb(aux: &intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, valuep: &buf) < 0)
5353	return;
5354
5355	buf &= ~DP_PCON_ENABLE_HDMI_LINK;
5356	if (drm_dp_dpcd_writeb(aux: &intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, value: buf) < 0)
5357	return;
5358
5359	drm_dp_pcon_hdmi_frl_link_error_count(aux: &intel_dp->aux, connector: &intel_dp->attached_connector->base);
5360
5361	intel_dp->frl.is_trained = false;
5362
5363	/* Restart FRL training or fall back to TMDS mode */
5364	intel_dp_check_frl_training(intel_dp);
5365	}
5366	}
5367
5368	static bool
5369	intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
5370	{
5371	u8 link_status[DP_LINK_STATUS_SIZE];
5372
5373	if (!intel_dp->link.active)
5374	return false;
5375
5376	/*
5377	* While PSR source HW is enabled, it will control main-link sending
5378	* frames, enabling and disabling it so trying to do a retrain will fail
5379	* as the link would or not be on or it could mix training patterns
5380	* and frame data at the same time causing retrain to fail.
5381	* Also when exiting PSR, HW will retrain the link anyways fixing
5382	* any link status error.
5383	*/
5384	if (intel_psr_enabled(intel_dp))
5385	return false;
5386
5387	if (intel_dp->link.force_retrain)
5388	return true;
5389
5390	if (drm_dp_dpcd_read_phy_link_status(aux: &intel_dp->aux, dp_phy: DP_PHY_DPRX,
5391	link_status) < 0)
5392	return false;
5393
5394	/*
5395	* Validate the cached values of intel_dp->link_rate and
5396	* intel_dp->lane_count before attempting to retrain.
5397	*
5398	* FIXME would be nice to user the crtc state here, but since
5399	* we need to call this from the short HPD handler that seems
5400	* a bit hard.
5401	*/
5402	if (!intel_dp_link_params_valid(intel_dp, link_rate: intel_dp->link_rate,
5403	lane_count: intel_dp->lane_count))
5404	return false;
5405
5406	if (intel_dp->link.retrain_disabled)
5407	return false;
5408
5409	if (intel_dp->link.seq_train_failures)
5410	return true;
5411
5412	/* Retrain if link not ok */
5413	return !intel_dp_link_ok(intel_dp, link_status) &&
5414	!intel_psr_link_ok(intel_dp);
5415	}
5416
5417	bool intel_dp_has_connector(struct intel_dp *intel_dp,
5418	const struct drm_connector_state *conn_state)
5419	{
5420	struct intel_display *display = to_intel_display(intel_dp);
5421	struct intel_encoder *encoder;
5422	enum pipe pipe;
5423
5424	if (!conn_state->best_encoder)
5425	return false;
5426
5427	/* SST */
5428	encoder = &dp_to_dig_port(intel_dp)->base;
5429	if (conn_state->best_encoder == &encoder->base)
5430	return true;
5431
5432	/* MST */
5433	for_each_pipe(display, pipe) {
5434	encoder = &intel_dp->mst.stream_encoders[pipe]->base;
5435	if (conn_state->best_encoder == &encoder->base)
5436	return true;
5437	}
5438
5439	return false;
5440	}
5441
5442	static void wait_for_connector_hw_done(const struct drm_connector_state *conn_state)
5443	{
5444	struct intel_connector *connector = to_intel_connector(conn_state->connector);
5445	struct intel_display *display = to_intel_display(connector);
5446
5447	drm_modeset_lock_assert_held(lock: &display->drm->mode_config.connection_mutex);
5448
5449	if (!conn_state->commit)
5450	return;
5451
5452	drm_WARN_ON(display->drm,
5453	!wait_for_completion_timeout(&conn_state->commit->hw_done,
5454	msecs_to_jiffies(5000)));
5455	}
5456
5457	int intel_dp_get_active_pipes(struct intel_dp *intel_dp,
5458	struct drm_modeset_acquire_ctx *ctx,
5459	u8 *pipe_mask)
5460	{
5461	struct intel_display *display = to_intel_display(intel_dp);
5462	struct drm_connector_list_iter conn_iter;
5463	struct intel_connector *connector;
5464	int ret = 0;
5465
5466	*pipe_mask = 0;
5467
5468	drm_connector_list_iter_begin(dev: display->drm, iter: &conn_iter);
5469	for_each_intel_connector_iter(connector, &conn_iter) {
5470	struct drm_connector_state *conn_state =
5471	connector->base.state;
5472	struct intel_crtc_state *crtc_state;
5473	struct intel_crtc *crtc;
5474
5475	if (!intel_dp_has_connector(intel_dp, conn_state))
5476	continue;
5477
5478	crtc = to_intel_crtc(conn_state->crtc);
5479	if (!crtc)
5480	continue;
5481
5482	ret = drm_modeset_lock(lock: &crtc->base.mutex, ctx);
5483	if (ret)
5484	break;
5485
5486	crtc_state = to_intel_crtc_state(crtc->base.state);
5487
5488	drm_WARN_ON(display->drm,
5489	!intel_crtc_has_dp_encoder(crtc_state));
5490
5491	if (!crtc_state->hw.active)
5492	continue;
5493
5494	wait_for_connector_hw_done(conn_state);
5495
5496	*pipe_mask |= BIT(crtc->pipe);
5497	}
5498	drm_connector_list_iter_end(iter: &conn_iter);
5499
5500	return ret;
5501	}
5502
5503	void intel_dp_flush_connector_commits(struct intel_connector *connector)
5504	{
5505	wait_for_connector_hw_done(conn_state: connector->base.state);
5506	}
5507
5508	static bool intel_dp_is_connected(struct intel_dp *intel_dp)
5509	{
5510	struct intel_connector *connector = intel_dp->attached_connector;
5511
5512	return connector->base.status == connector_status_connected ||
5513	intel_dp->is_mst;
5514	}
5515
5516	static int intel_dp_retrain_link(struct intel_encoder *encoder,
5517	struct drm_modeset_acquire_ctx *ctx)
5518	{
5519	struct intel_display *display = to_intel_display(encoder);
5520	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5521	u8 pipe_mask;
5522	int ret;
5523
5524	if (!intel_dp_is_connected(intel_dp))
5525	return 0;
5526
5527	ret = drm_modeset_lock(lock: &display->drm->mode_config.connection_mutex,
5528	ctx);
5529	if (ret)
5530	return ret;
5531
5532	if (!intel_dp_needs_link_retrain(intel_dp))
5533	return 0;
5534
5535	ret = intel_dp_get_active_pipes(intel_dp, ctx, pipe_mask: &pipe_mask);
5536	if (ret)
5537	return ret;
5538
5539	if (pipe_mask == 0)
5540	return 0;
5541
5542	if (!intel_dp_needs_link_retrain(intel_dp))
5543	return 0;
5544
5545	drm_dbg_kms(display->drm,
5546	"[ENCODER:%d:%s] retraining link (forced %s)\n",
5547	encoder->base.base.id, encoder->base.name,
5548	str_yes_no(intel_dp->link.force_retrain));
5549
5550	ret = intel_modeset_commit_pipes(display, pipe_mask, ctx);
5551	if (ret == -EDEADLK)
5552	return ret;
5553
5554	intel_dp->link.force_retrain = false;
5555
5556	if (ret)
5557	drm_dbg_kms(display->drm,
5558	"[ENCODER:%d:%s] link retraining failed: %pe\n",
5559	encoder->base.base.id, encoder->base.name,
5560	ERR_PTR(ret));
5561
5562	return ret;
5563	}
5564
5565	void intel_dp_link_check(struct intel_encoder *encoder)
5566	{
5567	struct drm_modeset_acquire_ctx ctx;
5568	int ret;
5569
5570	intel_modeset_lock_ctx_retry(&ctx, NULL, 0, ret)
5571	ret = intel_dp_retrain_link(encoder, ctx: &ctx);
5572	}
5573
5574	void intel_dp_check_link_state(struct intel_dp *intel_dp)
5575	{
5576	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5577	struct intel_encoder *encoder = &dig_port->base;
5578
5579	if (!intel_dp_is_connected(intel_dp))
5580	return;
5581
5582	if (!intel_dp_needs_link_retrain(intel_dp))
5583	return;
5584
5585	intel_encoder_link_check_queue_work(encoder, delay_ms: 0);
5586	}
5587
5588	static void intel_dp_check_device_service_irq(struct intel_dp *intel_dp)
5589	{
5590	struct intel_display *display = to_intel_display(intel_dp);
5591	u8 val;
5592
5593	if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
5594	return;
5595
5596	if (drm_dp_dpcd_readb(aux: &intel_dp->aux,
5597	DP_DEVICE_SERVICE_IRQ_VECTOR, valuep: &val) != 1 || !val)
5598	return;
5599
5600	drm_dp_dpcd_writeb(aux: &intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, value: val);
5601
5602	if (val & DP_AUTOMATED_TEST_REQUEST)
5603	intel_dp_test_request(intel_dp);
5604
5605	if (val & DP_CP_IRQ)
5606	intel_hdcp_handle_cp_irq(connector: intel_dp->attached_connector);
5607
5608	if (val & DP_SINK_SPECIFIC_IRQ)
5609	drm_dbg_kms(display->drm, "Sink specific irq unhandled\n");
5610	}
5611
5612	static bool intel_dp_check_link_service_irq(struct intel_dp *intel_dp)
5613	{
5614	struct intel_display *display = to_intel_display(intel_dp);
5615	bool reprobe_needed = false;
5616	u8 val;
5617
5618	if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
5619	return false;
5620
5621	if (drm_dp_dpcd_readb(aux: &intel_dp->aux,
5622	DP_LINK_SERVICE_IRQ_VECTOR_ESI0, valuep: &val) != 1 || !val)
5623	return false;
5624
5625	if ((val & DP_TUNNELING_IRQ) &&
5626	drm_dp_tunnel_handle_irq(mgr: display->dp_tunnel_mgr,
5627	aux: &intel_dp->aux))
5628	reprobe_needed = true;
5629
5630	if (drm_dp_dpcd_writeb(aux: &intel_dp->aux,
5631	DP_LINK_SERVICE_IRQ_VECTOR_ESI0, value: val) != 1)
5632	return reprobe_needed;
5633
5634	if (val & HDMI_LINK_STATUS_CHANGED)
5635	intel_dp_handle_hdmi_link_status_change(intel_dp);
5636
5637	return reprobe_needed;
5638	}
5639
5640	/*
5641	* According to DP spec
5642	* 5.1.2:
5643	* 1. Read DPCD
5644	* 2. Configure link according to Receiver Capabilities
5645	* 3. Use Link Training from 2.5.3.3 and 3.5.1.3
5646	* 4. Check link status on receipt of hot-plug interrupt
5647	*
5648	* intel_dp_short_pulse - handles short pulse interrupts
5649	* when full detection is not required.
5650	* Returns %true if short pulse is handled and full detection
5651	* is NOT required and %false otherwise.
5652	*/
5653	static bool
5654	intel_dp_short_pulse(struct intel_dp *intel_dp)
5655	{
5656	u8 old_sink_count = intel_dp->sink_count;
5657	bool reprobe_needed = false;
5658	bool ret;
5659
5660	intel_dp_test_reset(intel_dp);
5661
5662	/*
5663	* Now read the DPCD to see if it's actually running
5664	* If the current value of sink count doesn't match with
5665	* the value that was stored earlier or dpcd read failed
5666	* we need to do full detection
5667	*/
5668	ret = intel_dp_get_dpcd(intel_dp);
5669
5670	if ((old_sink_count != intel_dp->sink_count) || !ret) {
5671	/* No need to proceed if we are going to do full detect */
5672	return false;
5673	}
5674
5675	intel_dp_check_device_service_irq(intel_dp);
5676	reprobe_needed = intel_dp_check_link_service_irq(intel_dp);
5677
5678	/* Handle CEC interrupts, if any */
5679	drm_dp_cec_irq(aux: &intel_dp->aux);
5680
5681	intel_dp_check_link_state(intel_dp);
5682
5683	intel_psr_short_pulse(intel_dp);
5684
5685	if (intel_alpm_get_error(intel_dp)) {
5686	intel_alpm_disable(intel_dp);
5687	intel_dp->alpm.sink_alpm_error = true;
5688	}
5689
5690	if (intel_dp_test_short_pulse(intel_dp))
5691	reprobe_needed = true;
5692
5693	return !reprobe_needed;
5694	}
5695
5696	/* XXX this is probably wrong for multiple downstream ports */
5697	static enum drm_connector_status
5698	intel_dp_detect_dpcd(struct intel_dp *intel_dp)
5699	{
5700	struct intel_display *display = to_intel_display(intel_dp);
5701	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5702	u8 *dpcd = intel_dp->dpcd;
5703	u8 type;
5704
5705	if (drm_WARN_ON(display->drm, intel_dp_is_edp(intel_dp)))
5706	return connector_status_connected;
5707
5708	intel_lspcon_resume(dig_port);
5709
5710	if (!intel_dp_get_dpcd(intel_dp))
5711	return connector_status_disconnected;
5712
5713	intel_dp->mst_detect = intel_dp_mst_detect(intel_dp);
5714
5715	/* if there's no downstream port, we're done */
5716	if (!drm_dp_is_branch(dpcd))
5717	return connector_status_connected;
5718
5719	/* If we're HPD-aware, SINK_COUNT changes dynamically */
5720	if (intel_dp_has_sink_count(intel_dp) &&
5721	intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
5722	return intel_dp->sink_count ?
5723	connector_status_connected : connector_status_disconnected;
5724	}
5725
5726	if (intel_dp->mst_detect == DRM_DP_MST)
5727	return connector_status_connected;
5728
5729	/* If no HPD, poke DDC gently */
5730	if (drm_probe_ddc(adapter: &intel_dp->aux.ddc))
5731	return connector_status_connected;
5732
5733	/* Well we tried, say unknown for unreliable port types */
5734	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
5735	type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
5736	if (type == DP_DS_PORT_TYPE_VGA ||
5737	type == DP_DS_PORT_TYPE_NON_EDID)
5738	return connector_status_unknown;
5739	} else {
5740	type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
5741	DP_DWN_STRM_PORT_TYPE_MASK;
5742	if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
5743	type == DP_DWN_STRM_PORT_TYPE_OTHER)
5744	return connector_status_unknown;
5745	}
5746
5747	/* Anything else is out of spec, warn and ignore */
5748	drm_dbg_kms(display->drm, "Broken DP branch device, ignoring\n");
5749	return connector_status_disconnected;
5750	}
5751
5752	static enum drm_connector_status
5753	edp_detect(struct intel_dp *intel_dp)
5754	{
5755	return connector_status_connected;
5756	}
5757
5758	void intel_digital_port_lock(struct intel_encoder *encoder)
5759	{
5760	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
5761
5762	if (dig_port->lock)
5763	dig_port->lock(dig_port);
5764	}
5765
5766	void intel_digital_port_unlock(struct intel_encoder *encoder)
5767	{
5768	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
5769
5770	if (dig_port->unlock)
5771	dig_port->unlock(dig_port);
5772	}
5773
5774	/*
5775	* intel_digital_port_connected_locked - is the specified port connected?
5776	* @encoder: intel_encoder
5777	*
5778	* In cases where there's a connector physically connected but it can't be used
5779	* by our hardware we also return false, since the rest of the driver should
5780	* pretty much treat the port as disconnected. This is relevant for type-C
5781	* (starting on ICL) where there's ownership involved.
5782	*
5783	* The caller must hold the lock acquired by calling intel_digital_port_lock()
5784	* when calling this function.
5785	*
5786	* Return %true if port is connected, %false otherwise.
5787	*/
5788	bool intel_digital_port_connected_locked(struct intel_encoder *encoder)
5789	{
5790	struct intel_display *display = to_intel_display(encoder);
5791	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
5792	bool is_glitch_free = intel_tc_port_handles_hpd_glitches(dig_port);
5793	bool is_connected = false;
5794	intel_wakeref_t wakeref;
5795
5796	with_intel_display_power(display, POWER_DOMAIN_DISPLAY_CORE, wakeref) {
5797	poll_timeout_us(is_connected = dig_port->connected(encoder),
5798	is_connected || is_glitch_free,
5799	30, 4000, false);
5800	}
5801
5802	return is_connected;
5803	}
5804
5805	bool intel_digital_port_connected(struct intel_encoder *encoder)
5806	{
5807	bool ret;
5808
5809	intel_digital_port_lock(encoder);
5810	ret = intel_digital_port_connected_locked(encoder);
5811	intel_digital_port_unlock(encoder);
5812
5813	return ret;
5814	}
5815
5816	static const struct drm_edid *
5817	intel_dp_get_edid(struct intel_dp *intel_dp)
5818	{
5819	struct intel_connector *connector = intel_dp->attached_connector;
5820	const struct drm_edid *fixed_edid = connector->panel.fixed_edid;
5821
5822	/* Use panel fixed edid if we have one */
5823	if (fixed_edid) {
5824	/* invalid edid */
5825	if (IS_ERR(ptr: fixed_edid))
5826	return NULL;
5827
5828	return drm_edid_dup(drm_edid: fixed_edid);
5829	}
5830
5831	return drm_edid_read_ddc(connector: &connector->base, adapter: &intel_dp->aux.ddc);
5832	}
5833
5834	static void
5835	intel_dp_update_dfp(struct intel_dp *intel_dp,
5836	const struct drm_edid *drm_edid)
5837	{
5838	struct intel_display *display = to_intel_display(intel_dp);
5839	struct intel_connector *connector = intel_dp->attached_connector;
5840
5841	intel_dp->dfp.max_bpc =
5842	drm_dp_downstream_max_bpc(dpcd: intel_dp->dpcd,
5843	port_cap: intel_dp->downstream_ports, drm_edid);
5844
5845	intel_dp->dfp.max_dotclock =
5846	drm_dp_downstream_max_dotclock(dpcd: intel_dp->dpcd,
5847	port_cap: intel_dp->downstream_ports);
5848
5849	intel_dp->dfp.min_tmds_clock =
5850	drm_dp_downstream_min_tmds_clock(dpcd: intel_dp->dpcd,
5851	port_cap: intel_dp->downstream_ports,
5852	drm_edid);
5853	intel_dp->dfp.max_tmds_clock =
5854	drm_dp_downstream_max_tmds_clock(dpcd: intel_dp->dpcd,
5855	port_cap: intel_dp->downstream_ports,
5856	drm_edid);
5857
5858	intel_dp->dfp.pcon_max_frl_bw =
5859	drm_dp_get_pcon_max_frl_bw(dpcd: intel_dp->dpcd,
5860	port_cap: intel_dp->downstream_ports);
5861
5862	drm_dbg_kms(display->drm,
5863	"[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, TMDS clock %d-%d, PCON Max FRL BW %dGbps\n",
5864	connector->base.base.id, connector->base.name,
5865	intel_dp->dfp.max_bpc,
5866	intel_dp->dfp.max_dotclock,
5867	intel_dp->dfp.min_tmds_clock,
5868	intel_dp->dfp.max_tmds_clock,
5869	intel_dp->dfp.pcon_max_frl_bw);
5870
5871	intel_dp_get_pcon_dsc_cap(intel_dp);
5872	}
5873
5874	static bool
5875	intel_dp_can_ycbcr420(struct intel_dp *intel_dp)
5876	{
5877	if (source_can_output(intel_dp, format: INTEL_OUTPUT_FORMAT_YCBCR420) &&
5878	(!drm_dp_is_branch(dpcd: intel_dp->dpcd) || intel_dp->dfp.ycbcr420_passthrough))
5879	return true;
5880
5881	if (source_can_output(intel_dp, format: INTEL_OUTPUT_FORMAT_RGB) &&
5882	dfp_can_convert_from_rgb(intel_dp, sink_format: INTEL_OUTPUT_FORMAT_YCBCR420))
5883	return true;
5884
5885	if (source_can_output(intel_dp, format: INTEL_OUTPUT_FORMAT_YCBCR444) &&
5886	dfp_can_convert_from_ycbcr444(intel_dp, sink_format: INTEL_OUTPUT_FORMAT_YCBCR420))
5887	return true;
5888
5889	return false;
5890	}
5891
5892	static void
5893	intel_dp_update_420(struct intel_dp *intel_dp)
5894	{
5895	struct intel_display *display = to_intel_display(intel_dp);
5896	struct intel_connector *connector = intel_dp->attached_connector;
5897
5898	intel_dp->dfp.ycbcr420_passthrough =
5899	drm_dp_downstream_420_passthrough(dpcd: intel_dp->dpcd,
5900	port_cap: intel_dp->downstream_ports);
5901	/* on-board LSPCON always assumed to support 4:4:4->4:2:0 conversion */
5902	intel_dp->dfp.ycbcr_444_to_420 =
5903	intel_lspcon_active(dig_port: dp_to_dig_port(intel_dp)) ||
5904	drm_dp_downstream_444_to_420_conversion(dpcd: intel_dp->dpcd,
5905	port_cap: intel_dp->downstream_ports);
5906	intel_dp->dfp.rgb_to_ycbcr =
5907	drm_dp_downstream_rgb_to_ycbcr_conversion(dpcd: intel_dp->dpcd,
5908	port_cap: intel_dp->downstream_ports,
5909	DP_DS_HDMI_BT709_RGB_YCBCR_CONV);
5910
5911	connector->base.ycbcr_420_allowed = intel_dp_can_ycbcr420(intel_dp);
5912
5913	drm_dbg_kms(display->drm,
5914	"[CONNECTOR:%d:%s] RGB->YcbCr conversion? %s, YCbCr 4:2:0 allowed? %s, YCbCr 4:4:4->4:2:0 conversion? %s\n",
5915	connector->base.base.id, connector->base.name,
5916	str_yes_no(intel_dp->dfp.rgb_to_ycbcr),
5917	str_yes_no(connector->base.ycbcr_420_allowed),
5918	str_yes_no(intel_dp->dfp.ycbcr_444_to_420));
5919	}
5920
5921	static void
5922	intel_dp_set_edid(struct intel_dp *intel_dp)
5923	{
5924	struct intel_display *display = to_intel_display(intel_dp);
5925	struct intel_connector *connector = intel_dp->attached_connector;
5926	const struct drm_edid *drm_edid;
5927	bool vrr_capable;
5928
5929	intel_dp_unset_edid(intel_dp);
5930	drm_edid = intel_dp_get_edid(intel_dp);
5931	connector->detect_edid = drm_edid;
5932
5933	/* Below we depend on display info having been updated */
5934	drm_edid_connector_update(connector: &connector->base, edid: drm_edid);
5935
5936	vrr_capable = intel_vrr_is_capable(connector);
5937	drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] VRR capable: %s\n",
5938	connector->base.base.id, connector->base.name, str_yes_no(vrr_capable));
5939	drm_connector_set_vrr_capable_property(connector: &connector->base, capable: vrr_capable);
5940
5941	intel_dp_update_dfp(intel_dp, drm_edid);
5942	intel_dp_update_420(intel_dp);
5943
5944	drm_dp_cec_attach(aux: &intel_dp->aux,
5945	source_physical_address: connector->base.display_info.source_physical_address);
5946	}
5947
5948	static void
5949	intel_dp_unset_edid(struct intel_dp *intel_dp)
5950	{
5951	struct intel_connector *connector = intel_dp->attached_connector;
5952
5953	drm_dp_cec_unset_edid(aux: &intel_dp->aux);
5954	drm_edid_free(drm_edid: connector->detect_edid);
5955	connector->detect_edid = NULL;
5956
5957	intel_dp->dfp.max_bpc = 0;
5958	intel_dp->dfp.max_dotclock = 0;
5959	intel_dp->dfp.min_tmds_clock = 0;
5960	intel_dp->dfp.max_tmds_clock = 0;
5961
5962	intel_dp->dfp.pcon_max_frl_bw = 0;
5963
5964	intel_dp->dfp.ycbcr_444_to_420 = false;
5965	connector->base.ycbcr_420_allowed = false;
5966
5967	drm_connector_set_vrr_capable_property(connector: &connector->base,
5968	capable: false);
5969	}
5970
5971	static void
5972	intel_dp_detect_sdp_caps(struct intel_dp *intel_dp)
5973	{
5974	struct intel_display *display = to_intel_display(intel_dp);
5975
5976	intel_dp->as_sdp_supported = HAS_AS_SDP(display) &&
5977	drm_dp_as_sdp_supported(aux: &intel_dp->aux, dpcd: intel_dp->dpcd);
5978	}
5979
5980	static bool intel_dp_needs_dpcd_probe(struct intel_dp *intel_dp, bool force_on_external)
5981	{
5982	struct intel_connector *connector = intel_dp->attached_connector;
5983
5984	if (intel_dp_is_edp(intel_dp))
5985	return false;
5986
5987	if (force_on_external)
5988	return true;
5989
5990	if (intel_dp->is_mst)
5991	return false;
5992
5993	return drm_edid_has_quirk(connector: &connector->base, quirk: DRM_EDID_QUIRK_DP_DPCD_PROBE);
5994	}
5995
5996	void intel_dp_dpcd_set_probe(struct intel_dp *intel_dp, bool force_on_external)
5997	{
5998	drm_dp_dpcd_set_probe(aux: &intel_dp->aux,
5999	enable: intel_dp_needs_dpcd_probe(intel_dp, force_on_external));
6000	}
6001
6002	static int
6003	intel_dp_detect(struct drm_connector *_connector,
6004	struct drm_modeset_acquire_ctx *ctx,
6005	bool force)
6006	{
6007	struct intel_display *display = to_intel_display(_connector->dev);
6008	struct intel_connector *connector = to_intel_connector(_connector);
6009	struct intel_dp *intel_dp = intel_attached_dp(connector);
6010	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
6011	struct intel_encoder *encoder = &dig_port->base;
6012	enum drm_connector_status status;
6013	int ret;
6014
6015	drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n",
6016	connector->base.base.id, connector->base.name);
6017	drm_WARN_ON(display->drm,
6018	!drm_modeset_is_locked(&display->drm->mode_config.connection_mutex));
6019
6020	if (!intel_display_device_enabled(display))
6021	return connector_status_disconnected;
6022
6023	if (!intel_display_driver_check_access(display))
6024	return connector->base.status;
6025
6026	intel_dp_flush_connector_commits(connector);
6027
6028	intel_pps_vdd_on(intel_dp);
6029
6030	/* Can't disconnect eDP */
6031	if (intel_dp_is_edp(intel_dp))
6032	status = edp_detect(intel_dp);
6033	else if (intel_digital_port_connected(encoder))
6034	status = intel_dp_detect_dpcd(intel_dp);
6035	else
6036	status = connector_status_disconnected;
6037
6038	if (status != connector_status_disconnected &&
6039	!intel_dp_mst_verify_dpcd_state(intel_dp))
6040	/*
6041	* This requires retrying detection for instance to re-enable
6042	* the MST mode that got reset via a long HPD pulse. The retry
6043	* will happen either via the hotplug handler's retry logic,
6044	* ensured by setting the connector here to SST/disconnected,
6045	* or via a userspace connector probing in response to the
6046	* hotplug uevent sent when removing the MST connectors.
6047	*/
6048	status = connector_status_disconnected;
6049
6050	if (status == connector_status_disconnected) {
6051	intel_dp_test_reset(intel_dp);
6052	memset(connector->dp.dsc_dpcd, 0, sizeof(connector->dp.dsc_dpcd));
6053	intel_dp->psr.sink_panel_replay_support = false;
6054	intel_dp->psr.sink_panel_replay_su_support = false;
6055	intel_dp->psr.sink_panel_replay_dsc_support =
6056	INTEL_DP_PANEL_REPLAY_DSC_NOT_SUPPORTED;
6057
6058	intel_dp_mst_disconnect(intel_dp);
6059
6060	intel_dp_tunnel_disconnect(intel_dp);
6061
6062	goto out_unset_edid;
6063	}
6064
6065	intel_dp_init_source_oui(intel_dp);
6066
6067	ret = intel_dp_tunnel_detect(intel_dp, ctx);
6068	if (ret == -EDEADLK) {
6069	status = ret;
6070
6071	goto out_vdd_off;
6072	}
6073
6074	if (ret == 1)
6075	connector->base.epoch_counter++;
6076
6077	if (!intel_dp_is_edp(intel_dp))
6078	intel_psr_init_dpcd(intel_dp);
6079
6080	intel_dp_detect_dsc_caps(intel_dp, connector);
6081
6082	intel_dp_detect_sdp_caps(intel_dp);
6083
6084	if (intel_dp->reset_link_params) {
6085	intel_dp_reset_link_params(intel_dp);
6086	intel_dp->reset_link_params = false;
6087	}
6088
6089	intel_dp_mst_configure(intel_dp);
6090
6091	intel_dp_print_rates(intel_dp);
6092
6093	if (intel_dp->is_mst) {
6094	/*
6095	* If we are in MST mode then this connector
6096	* won't appear connected or have anything
6097	* with EDID on it
6098	*/
6099	status = connector_status_disconnected;
6100	goto out_unset_edid;
6101	}
6102
6103	/*
6104	* Some external monitors do not signal loss of link synchronization
6105	* with an IRQ_HPD, so force a link status check.
6106	*
6107	* TODO: this probably became redundant, so remove it: the link state
6108	* is rechecked/recovered now after modesets, where the loss of
6109	* synchronization tends to occur.
6110	*/
6111	if (!intel_dp_is_edp(intel_dp))
6112	intel_dp_check_link_state(intel_dp);
6113
6114	/*
6115	* Clearing NACK and defer counts to get their exact values
6116	* while reading EDID which are required by Compliance tests
6117	* 4.2.2.4 and 4.2.2.5
6118	*/
6119	intel_dp->aux.i2c_nack_count = 0;
6120	intel_dp->aux.i2c_defer_count = 0;
6121
6122	intel_dp_set_edid(intel_dp);
6123	if (intel_dp_is_edp(intel_dp) || connector->detect_edid)
6124	status = connector_status_connected;
6125
6126	intel_dp_check_device_service_irq(intel_dp);
6127
6128	out_unset_edid:
6129	if (status != connector_status_connected && !intel_dp->is_mst)
6130	intel_dp_unset_edid(intel_dp);
6131
6132	intel_dp_dpcd_set_probe(intel_dp, force_on_external: false);
6133
6134	if (!intel_dp_is_edp(intel_dp))
6135	drm_dp_set_subconnector_property(connector: &connector->base,
6136	status,
6137	dpcd: intel_dp->dpcd,
6138	port_cap: intel_dp->downstream_ports);
6139	out_vdd_off:
6140	intel_pps_vdd_off(intel_dp);
6141
6142	return status;
6143	}
6144
6145	static void
6146	intel_dp_force(struct drm_connector *_connector)
6147	{
6148	struct intel_connector *connector = to_intel_connector(_connector);
6149	struct intel_display *display = to_intel_display(connector);
6150	struct intel_dp *intel_dp = intel_attached_dp(connector);
6151
6152	drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n",
6153	connector->base.base.id, connector->base.name);
6154
6155	if (!intel_display_driver_check_access(display))
6156	return;
6157
6158	intel_dp_unset_edid(intel_dp);
6159
6160	if (connector->base.status != connector_status_connected)
6161	return;
6162
6163	intel_dp_set_edid(intel_dp);
6164
6165	intel_dp_dpcd_set_probe(intel_dp, force_on_external: false);
6166	}
6167
6168	static int intel_dp_get_modes(struct drm_connector *_connector)
6169	{
6170	struct intel_display *display = to_intel_display(_connector->dev);
6171	struct intel_connector *connector = to_intel_connector(_connector);
6172	struct intel_dp *intel_dp = intel_attached_dp(connector);
6173	int num_modes;
6174
6175	/* drm_edid_connector_update() done in ->detect() or ->force() */
6176	num_modes = drm_edid_connector_add_modes(connector: &connector->base);
6177
6178	/* Also add fixed mode, which may or may not be present in EDID */
6179	if (intel_dp_is_edp(intel_dp))
6180	num_modes += intel_panel_get_modes(connector);
6181
6182	if (num_modes)
6183	return num_modes;
6184
6185	if (!connector->detect_edid) {
6186	struct drm_display_mode *mode;
6187
6188	mode = drm_dp_downstream_mode(dev: display->drm,
6189	dpcd: intel_dp->dpcd,
6190	port_cap: intel_dp->downstream_ports);
6191	if (mode) {
6192	drm_mode_probed_add(connector: &connector->base, mode);
6193	num_modes++;
6194	}
6195	}
6196
6197	return num_modes;
6198	}
6199
6200	static int
6201	intel_dp_connector_register(struct drm_connector *_connector)
6202	{
6203	struct intel_connector *connector = to_intel_connector(_connector);
6204	struct intel_display *display = to_intel_display(connector);
6205	struct intel_dp *intel_dp = intel_attached_dp(connector);
6206	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
6207	int ret;
6208
6209	ret = intel_connector_register(connector: &connector->base);
6210	if (ret)
6211	return ret;
6212
6213	drm_dbg_kms(display->drm, "registering %s bus for %s\n",
6214	intel_dp->aux.name, connector->base.kdev->kobj.name);
6215
6216	intel_dp->aux.dev = connector->base.kdev;
6217	ret = drm_dp_aux_register(aux: &intel_dp->aux);
6218	if (!ret)
6219	drm_dp_cec_register_connector(aux: &intel_dp->aux, connector: &connector->base);
6220
6221	if (!intel_bios_encoder_is_lspcon(devdata: dig_port->base.devdata))
6222	return ret;
6223
6224	/*
6225	* ToDo: Clean this up to handle lspcon init and resume more
6226	* efficiently and streamlined.
6227	*/
6228	if (intel_lspcon_init(dig_port)) {
6229	if (intel_lspcon_detect_hdr_capability(dig_port))
6230	drm_connector_attach_hdr_output_metadata_property(connector: &connector->base);
6231	}
6232
6233	return ret;
6234	}
6235
6236	static void
6237	intel_dp_connector_unregister(struct drm_connector *_connector)
6238	{
6239	struct intel_connector *connector = to_intel_connector(_connector);
6240	struct intel_dp *intel_dp = intel_attached_dp(connector);
6241
6242	drm_dp_cec_unregister_connector(aux: &intel_dp->aux);
6243	drm_dp_aux_unregister(aux: &intel_dp->aux);
6244	intel_connector_unregister(connector: &connector->base);
6245	}
6246
6247	void intel_dp_connector_sync_state(struct intel_connector *connector,
6248	const struct intel_crtc_state *crtc_state)
6249	{
6250	struct intel_display *display = to_intel_display(connector);
6251
6252	if (crtc_state && crtc_state->dsc.compression_enable) {
6253	drm_WARN_ON(display->drm,
6254	!connector->dp.dsc_decompression_aux);
6255	connector->dp.dsc_decompression_enabled = true;
6256	} else {
6257	connector->dp.dsc_decompression_enabled = false;
6258	}
6259	}
6260
6261	void intel_dp_encoder_flush_work(struct drm_encoder *_encoder)
6262	{
6263	struct intel_encoder *encoder = to_intel_encoder(_encoder);
6264	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
6265	struct intel_dp *intel_dp = &dig_port->dp;
6266
6267	intel_encoder_link_check_flush_work(encoder);
6268
6269	intel_dp_mst_encoder_cleanup(dig_port);
6270
6271	intel_dp_tunnel_destroy(intel_dp);
6272
6273	intel_pps_vdd_off_sync(intel_dp);
6274
6275	/*
6276	* Ensure power off delay is respected on module remove, so that we can
6277	* reduce delays at driver probe. See pps_init_timestamps().
6278	*/
6279	intel_pps_wait_power_cycle(intel_dp);
6280
6281	intel_dp_aux_fini(intel_dp);
6282	}
6283
6284	void intel_dp_encoder_suspend(struct intel_encoder *encoder)
6285	{
6286	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
6287
6288	intel_pps_vdd_off_sync(intel_dp);
6289
6290	intel_dp_tunnel_suspend(intel_dp);
6291	}
6292
6293	void intel_dp_encoder_shutdown(struct intel_encoder *encoder)
6294	{
6295	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
6296
6297	intel_pps_wait_power_cycle(intel_dp);
6298	}
6299
6300	static int intel_modeset_tile_group(struct intel_atomic_state *state,
6301	int tile_group_id)
6302	{
6303	struct intel_display *display = to_intel_display(state);
6304	struct drm_connector_list_iter conn_iter;
6305	struct intel_connector *connector;
6306	int ret = 0;
6307
6308	drm_connector_list_iter_begin(dev: display->drm, iter: &conn_iter);
6309	for_each_intel_connector_iter(connector, &conn_iter) {
6310	struct drm_connector_state *conn_state;
6311	struct intel_crtc_state *crtc_state;
6312	struct intel_crtc *crtc;
6313
6314	if (!connector->base.has_tile ||
6315	connector->base.tile_group->id != tile_group_id)
6316	continue;
6317
6318	conn_state = drm_atomic_get_connector_state(state: &state->base,
6319	connector: &connector->base);
6320	if (IS_ERR(ptr: conn_state)) {
6321	ret = PTR_ERR(ptr: conn_state);
6322	break;
6323	}
6324
6325	crtc = to_intel_crtc(conn_state->crtc);
6326
6327	if (!crtc)
6328	continue;
6329
6330	crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
6331	crtc_state->uapi.mode_changed = true;
6332
6333	ret = drm_atomic_add_affected_planes(state: &state->base, crtc: &crtc->base);
6334	if (ret)
6335	break;
6336	}
6337	drm_connector_list_iter_end(iter: &conn_iter);
6338
6339	return ret;
6340	}
6341
6342	static int intel_modeset_affected_transcoders(struct intel_atomic_state *state, u8 transcoders)
6343	{
6344	struct intel_display *display = to_intel_display(state);
6345	struct intel_crtc *crtc;
6346
6347	if (transcoders == 0)
6348	return 0;
6349
6350	for_each_intel_crtc(display->drm, crtc) {
6351	struct intel_crtc_state *crtc_state;
6352	int ret;
6353
6354	crtc_state = intel_atomic_get_crtc_state(state: &state->base, crtc);
6355	if (IS_ERR(ptr: crtc_state))
6356	return PTR_ERR(ptr: crtc_state);
6357
6358	if (!crtc_state->hw.enable)
6359	continue;
6360
6361	if (!(transcoders & BIT(crtc_state->cpu_transcoder)))
6362	continue;
6363
6364	crtc_state->uapi.mode_changed = true;
6365
6366	ret = drm_atomic_add_affected_connectors(state: &state->base, crtc: &crtc->base);
6367	if (ret)
6368	return ret;
6369
6370	ret = drm_atomic_add_affected_planes(state: &state->base, crtc: &crtc->base);
6371	if (ret)
6372	return ret;
6373
6374	transcoders &= ~BIT(crtc_state->cpu_transcoder);
6375	}
6376
6377	drm_WARN_ON(display->drm, transcoders != 0);
6378
6379	return 0;
6380	}
6381
6382	static int intel_modeset_synced_crtcs(struct intel_atomic_state *state,
6383	struct drm_connector *_connector)
6384	{
6385	struct intel_connector *connector = to_intel_connector(_connector);
6386	const struct drm_connector_state *old_conn_state =
6387	drm_atomic_get_old_connector_state(state: &state->base, connector: &connector->base);
6388	const struct intel_crtc_state *old_crtc_state;
6389	struct intel_crtc *crtc;
6390	u8 transcoders;
6391
6392	crtc = to_intel_crtc(old_conn_state->crtc);
6393	if (!crtc)
6394	return 0;
6395
6396	old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
6397
6398	if (!old_crtc_state->hw.active)
6399	return 0;
6400
6401	transcoders = old_crtc_state->sync_mode_slaves_mask;
6402	if (old_crtc_state->master_transcoder != INVALID_TRANSCODER)
6403	transcoders |= BIT(old_crtc_state->master_transcoder);
6404
6405	return intel_modeset_affected_transcoders(state,
6406	transcoders);
6407	}
6408
6409	static int intel_dp_connector_atomic_check(struct drm_connector *_connector,
6410	struct drm_atomic_state *_state)
6411	{
6412	struct intel_connector *connector = to_intel_connector(_connector);
6413	struct intel_display *display = to_intel_display(connector);
6414	struct intel_atomic_state *state = to_intel_atomic_state(_state);
6415	struct drm_connector_state *conn_state =
6416	drm_atomic_get_new_connector_state(state: _state, connector: &connector->base);
6417	struct intel_dp *intel_dp = enc_to_intel_dp(encoder: connector->encoder);
6418	int ret;
6419
6420	ret = intel_digital_connector_atomic_check(conn: &connector->base, state: &state->base);
6421	if (ret)
6422	return ret;
6423
6424	if (intel_dp_mst_source_support(intel_dp)) {
6425	ret = drm_dp_mst_root_conn_atomic_check(new_conn_state: conn_state, mgr: &intel_dp->mst.mgr);
6426	if (ret)
6427	return ret;
6428	}
6429
6430	if (!intel_connector_needs_modeset(state, connector: &connector->base))
6431	return 0;
6432
6433	ret = intel_dp_tunnel_atomic_check_state(state,
6434	intel_dp,
6435	connector);
6436	if (ret)
6437	return ret;
6438
6439	/*
6440	* We don't enable port sync on BDW due to missing w/as and
6441	* due to not having adjusted the modeset sequence appropriately.
6442	*/
6443	if (DISPLAY_VER(display) < 9)
6444	return 0;
6445
6446	if (connector->base.has_tile) {
6447	ret = intel_modeset_tile_group(state, tile_group_id: connector->base.tile_group->id);
6448	if (ret)
6449	return ret;
6450	}
6451
6452	return intel_modeset_synced_crtcs(state, connector: &connector->base);
6453	}
6454
6455	static void intel_dp_oob_hotplug_event(struct drm_connector *_connector,
6456	enum drm_connector_status hpd_state)
6457	{
6458	struct intel_connector *connector = to_intel_connector(_connector);
6459	struct intel_display *display = to_intel_display(connector);
6460	struct intel_encoder *encoder = intel_attached_encoder(connector);
6461	bool hpd_high = hpd_state == connector_status_connected;
6462	unsigned int hpd_pin = encoder->hpd_pin;
6463	bool need_work = false;
6464
6465	spin_lock_irq(lock: &display->irq.lock);
6466	if (hpd_high != test_bit(hpd_pin, &display->hotplug.oob_hotplug_last_state)) {
6467	display->hotplug.event_bits |= BIT(hpd_pin);
6468
6469	__assign_bit(hpd_pin,
6470	&display->hotplug.oob_hotplug_last_state,
6471	hpd_high);
6472	need_work = true;
6473	}
6474	spin_unlock_irq(lock: &display->irq.lock);
6475
6476	if (need_work)
6477	intel_hpd_schedule_detection(display);
6478	}
6479
6480	static const struct drm_connector_funcs intel_dp_connector_funcs = {
6481	.force = intel_dp_force,
6482	.fill_modes = drm_helper_probe_single_connector_modes,
6483	.atomic_get_property = intel_digital_connector_atomic_get_property,
6484	.atomic_set_property = intel_digital_connector_atomic_set_property,
6485	.late_register = intel_dp_connector_register,
6486	.early_unregister = intel_dp_connector_unregister,
6487	.destroy = intel_connector_destroy,
6488	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
6489	.atomic_duplicate_state = intel_digital_connector_duplicate_state,
6490	.oob_hotplug_event = intel_dp_oob_hotplug_event,
6491	};
6492
6493	static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
6494	.detect_ctx = intel_dp_detect,
6495	.get_modes = intel_dp_get_modes,
6496	.mode_valid = intel_dp_mode_valid,
6497	.atomic_check = intel_dp_connector_atomic_check,
6498	};
6499
6500	enum irqreturn
6501	intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd)
6502	{
6503	struct intel_display *display = to_intel_display(dig_port);
6504	struct intel_dp *intel_dp = &dig_port->dp;
6505	u8 dpcd[DP_RECEIVER_CAP_SIZE];
6506
6507	if (dig_port->base.type == INTEL_OUTPUT_EDP &&
6508	(long_hpd ||
6509	intel_display_rpm_suspended(display) ||
6510	!intel_pps_have_panel_power_or_vdd(intel_dp))) {
6511	/*
6512	* vdd off can generate a long/short pulse on eDP which
6513	* would require vdd on to handle it, and thus we
6514	* would end up in an endless cycle of
6515	* "vdd off -> long/short hpd -> vdd on -> detect -> vdd off -> ..."
6516	*/
6517	drm_dbg_kms(display->drm,
6518	"ignoring %s hpd on eDP [ENCODER:%d:%s]\n",
6519	long_hpd ? "long" : "short",
6520	dig_port->base.base.base.id,
6521	dig_port->base.base.name);
6522	return IRQ_HANDLED;
6523	}
6524
6525	drm_dbg_kms(display->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n",
6526	dig_port->base.base.base.id,
6527	dig_port->base.base.name,
6528	long_hpd ? "long" : "short");
6529
6530	/*
6531	* TBT DP tunnels require the GFX driver to read out the DPRX caps in
6532	* response to long HPD pulses. The DP hotplug handler does that,
6533	* however the hotplug handler may be blocked by another
6534	* connector's/encoder's hotplug handler. Since the TBT CM may not
6535	* complete the DP tunnel BW request for the latter connector/encoder
6536	* waiting for this encoder's DPRX read, perform a dummy read here.
6537	*/
6538	if (long_hpd) {
6539	intel_dp_dpcd_set_probe(intel_dp, force_on_external: true);
6540
6541	intel_dp_read_dprx_caps(intel_dp, dpcd);
6542
6543	intel_dp->reset_link_params = true;
6544	intel_dp_invalidate_source_oui(intel_dp);
6545
6546	return IRQ_NONE;
6547	}
6548
6549	if (intel_dp->is_mst) {
6550	if (!intel_dp_check_mst_status(intel_dp))
6551	return IRQ_NONE;
6552	} else if (!intel_dp_short_pulse(intel_dp)) {
6553	return IRQ_NONE;
6554	}
6555
6556	return IRQ_HANDLED;
6557	}
6558
6559	static bool _intel_dp_is_port_edp(struct intel_display *display,
6560	const struct intel_bios_encoder_data *devdata,
6561	enum port port)
6562	{
6563	/*
6564	* eDP not supported on g4x. so bail out early just
6565	* for a bit extra safety in case the VBT is bonkers.
6566	*/
6567	if (DISPLAY_VER(display) < 5)
6568	return false;
6569
6570	if (DISPLAY_VER(display) < 9 && port == PORT_A)
6571	return true;
6572
6573	return devdata && intel_bios_encoder_supports_edp(devdata);
6574	}
6575
6576	bool intel_dp_is_port_edp(struct intel_display *display, enum port port)
6577	{
6578	const struct intel_bios_encoder_data *devdata =
6579	intel_bios_encoder_data_lookup(display, port);
6580
6581	return _intel_dp_is_port_edp(display, devdata, port);
6582	}
6583
6584	bool
6585	intel_dp_has_gamut_metadata_dip(struct intel_encoder *encoder)
6586	{
6587	struct intel_display *display = to_intel_display(encoder);
6588	enum port port = encoder->port;
6589
6590	if (intel_bios_encoder_is_lspcon(devdata: encoder->devdata))
6591	return false;
6592
6593	if (DISPLAY_VER(display) >= 11)
6594	return true;
6595
6596	if (port == PORT_A)
6597	return false;
6598
6599	if (display->platform.haswell || display->platform.broadwell ||
6600	DISPLAY_VER(display) >= 9)
6601	return true;
6602
6603	return false;
6604	}
6605
6606	static void
6607	intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *_connector)
6608	{
6609	struct intel_connector *connector = to_intel_connector(_connector);
6610	struct intel_display *display = to_intel_display(intel_dp);
6611	enum port port = dp_to_dig_port(intel_dp)->base.port;
6612
6613	if (!intel_dp_is_edp(intel_dp))
6614	drm_connector_attach_dp_subconnector_property(connector: &connector->base);
6615
6616	if (!display->platform.g4x && port != PORT_A)
6617	intel_attach_force_audio_property(connector: &connector->base);
6618
6619	intel_attach_broadcast_rgb_property(connector: &connector->base);
6620	if (HAS_GMCH(display))
6621	drm_connector_attach_max_bpc_property(connector: &connector->base, min: 6, max: 10);
6622	else if (DISPLAY_VER(display) >= 5)
6623	drm_connector_attach_max_bpc_property(connector: &connector->base, min: 6, max: 12);
6624
6625	/* Register HDMI colorspace for case of lspcon */
6626	if (intel_bios_encoder_is_lspcon(devdata: dp_to_dig_port(intel_dp)->base.devdata)) {
6627	drm_connector_attach_content_type_property(dev: &connector->base);
6628	intel_attach_hdmi_colorspace_property(connector: &connector->base);
6629	} else {
6630	intel_attach_dp_colorspace_property(connector: &connector->base);
6631	}
6632
6633	if (intel_dp_has_gamut_metadata_dip(encoder: &dp_to_dig_port(intel_dp)->base))
6634	drm_connector_attach_hdr_output_metadata_property(connector: &connector->base);
6635
6636	if (HAS_VRR(display))
6637	drm_connector_attach_vrr_capable_property(connector: &connector->base);
6638	}
6639
6640	static void
6641	intel_edp_add_properties(struct intel_dp *intel_dp)
6642	{
6643	struct intel_display *display = to_intel_display(intel_dp);
6644	struct intel_connector *connector = intel_dp->attached_connector;
6645	const struct drm_display_mode *fixed_mode =
6646	intel_panel_preferred_fixed_mode(connector);
6647
6648	intel_attach_scaling_mode_property(connector: &connector->base);
6649
6650	drm_connector_set_panel_orientation_with_quirk(connector: &connector->base,
6651	panel_orientation: display->vbt.orientation,
6652	width: fixed_mode->hdisplay,
6653	height: fixed_mode->vdisplay);
6654	}
6655
6656	static void intel_edp_backlight_setup(struct intel_dp *intel_dp,
6657	struct intel_connector *connector)
6658	{
6659	struct intel_display *display = to_intel_display(intel_dp);
6660	enum pipe pipe = INVALID_PIPE;
6661
6662	if (display->platform.valleyview || display->platform.cherryview)
6663	pipe = vlv_pps_backlight_initial_pipe(intel_dp);
6664
6665	intel_backlight_setup(connector, pipe);
6666	}
6667
6668	static bool intel_edp_init_connector(struct intel_dp *intel_dp,
6669	struct intel_connector *connector)
6670	{
6671	struct intel_display *display = to_intel_display(intel_dp);
6672	struct drm_display_mode *fixed_mode;
6673	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
6674	bool has_dpcd;
6675	const struct drm_edid *drm_edid;
6676
6677	if (!intel_dp_is_edp(intel_dp))
6678	return true;
6679
6680	/*
6681	* On IBX/CPT we may get here with LVDS already registered. Since the
6682	* driver uses the only internal power sequencer available for both
6683	* eDP and LVDS bail out early in this case to prevent interfering
6684	* with an already powered-on LVDS power sequencer.
6685	*/
6686	if (intel_get_lvds_encoder(display)) {
6687	drm_WARN_ON(display->drm,
6688	!(HAS_PCH_IBX(display) || HAS_PCH_CPT(display)));
6689	drm_info(display->drm,
6690	"LVDS was detected, not registering eDP\n");
6691
6692	return false;
6693	}
6694
6695	intel_bios_init_panel_early(display, panel: &connector->panel,
6696	devdata: encoder->devdata);
6697
6698	if (!intel_pps_init(intel_dp)) {
6699	drm_info(display->drm,
6700	"[ENCODER:%d:%s] unusable PPS, disabling eDP\n",
6701	encoder->base.base.id, encoder->base.name);
6702	/*
6703	* The BIOS may have still enabled VDD on the PPS even
6704	* though it's unusable. Make sure we turn it back off
6705	* and to release the power domain references/etc.
6706	*/
6707	goto out_vdd_off;
6708	}
6709
6710	/*
6711	* Enable HPD sense for live status check.
6712	* intel_hpd_irq_setup() will turn it off again
6713	* if it's no longer needed later.
6714	*
6715	* The DPCD probe below will make sure VDD is on.
6716	*/
6717	intel_hpd_enable_detection(encoder);
6718
6719	intel_alpm_init(intel_dp);
6720
6721	/* Cache DPCD and EDID for edp. */
6722	has_dpcd = intel_edp_init_dpcd(intel_dp, connector);
6723
6724	if (!has_dpcd) {
6725	/* if this fails, presume the device is a ghost */
6726	drm_info(display->drm,
6727	"[ENCODER:%d:%s] failed to retrieve link info, disabling eDP\n",
6728	encoder->base.base.id, encoder->base.name);
6729	goto out_vdd_off;
6730	}
6731
6732	/*
6733	* VBT and straps are liars. Also check HPD as that seems
6734	* to be the most reliable piece of information available.
6735	*
6736	* ... expect on devices that forgot to hook HPD up for eDP
6737	* (eg. Acer Chromebook C710), so we'll check it only if multiple
6738	* ports are attempting to use the same AUX CH, according to VBT.
6739	*/
6740	if (intel_bios_dp_has_shared_aux_ch(devdata: encoder->devdata)) {
6741	/*
6742	* If this fails, presume the DPCD answer came
6743	* from some other port using the same AUX CH.
6744	*
6745	* FIXME maybe cleaner to check this before the
6746	* DPCD read? Would need sort out the VDD handling...
6747	*/
6748	if (!intel_digital_port_connected(encoder)) {
6749	drm_info(display->drm,
6750	"[ENCODER:%d:%s] HPD is down, disabling eDP\n",
6751	encoder->base.base.id, encoder->base.name);
6752	goto out_vdd_off;
6753	}
6754
6755	/*
6756	* Unfortunately even the HPD based detection fails on
6757	* eg. Asus B360M-A (CFL+CNP), so as a last resort fall
6758	* back to checking for a VGA branch device. Only do this
6759	* on known affected platforms to minimize false positives.
6760	*/
6761	if (DISPLAY_VER(display) == 9 && drm_dp_is_branch(dpcd: intel_dp->dpcd) &&
6762	(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) ==
6763	DP_DWN_STRM_PORT_TYPE_ANALOG) {
6764	drm_info(display->drm,
6765	"[ENCODER:%d:%s] VGA converter detected, disabling eDP\n",
6766	encoder->base.base.id, encoder->base.name);
6767	goto out_vdd_off;
6768	}
6769	}
6770
6771	mutex_lock(&display->drm->mode_config.mutex);
6772	drm_edid = drm_edid_read_ddc(connector: &connector->base, adapter: connector->base.ddc);
6773	if (!drm_edid) {
6774	/* Fallback to EDID from ACPI OpRegion, if any */
6775	drm_edid = intel_opregion_get_edid(connector);
6776	if (drm_edid)
6777	drm_dbg_kms(display->drm,
6778	"[CONNECTOR:%d:%s] Using OpRegion EDID\n",
6779	connector->base.base.id, connector->base.name);
6780	}
6781	if (drm_edid) {
6782	if (drm_edid_connector_update(connector: &connector->base, edid: drm_edid) ||
6783	!drm_edid_connector_add_modes(connector: &connector->base)) {
6784	drm_edid_connector_update(connector: &connector->base, NULL);
6785	drm_edid_free(drm_edid);
6786	drm_edid = ERR_PTR(error: -EINVAL);
6787	}
6788	} else {
6789	drm_edid = ERR_PTR(error: -ENOENT);
6790	}
6791
6792	intel_bios_init_panel_late(display, panel: &connector->panel, devdata: encoder->devdata,
6793	drm_edid: IS_ERR(ptr: drm_edid) ? NULL : drm_edid);
6794
6795	intel_panel_add_edid_fixed_modes(connector, use_alt_fixed_modes: true);
6796
6797	/* MSO requires information from the EDID */
6798	intel_edp_mso_init(intel_dp);
6799
6800	/* multiply the mode clock and horizontal timings for MSO */
6801	list_for_each_entry(fixed_mode, &connector->panel.fixed_modes, head)
6802	intel_edp_mso_mode_fixup(connector, mode: fixed_mode);
6803
6804	/* fallback to VBT if available for eDP */
6805	if (!intel_panel_preferred_fixed_mode(connector))
6806	intel_panel_add_vbt_lfp_fixed_mode(connector);
6807
6808	mutex_unlock(lock: &display->drm->mode_config.mutex);
6809
6810	if (!intel_panel_preferred_fixed_mode(connector)) {
6811	drm_info(display->drm,
6812	"[ENCODER:%d:%s] failed to find fixed mode for the panel, disabling eDP\n",
6813	encoder->base.base.id, encoder->base.name);
6814	goto out_vdd_off;
6815	}
6816
6817	intel_panel_init(connector, fixed_edid: drm_edid);
6818
6819	intel_edp_backlight_setup(intel_dp, connector);
6820
6821	intel_edp_add_properties(intel_dp);
6822
6823	intel_pps_init_late(intel_dp);
6824
6825	return true;
6826
6827	out_vdd_off:
6828	intel_pps_vdd_off_sync(intel_dp);
6829	intel_bios_fini_panel(panel: &connector->panel);
6830
6831	return false;
6832	}
6833
6834	bool
6835	intel_dp_init_connector(struct intel_digital_port *dig_port,
6836	struct intel_connector *connector)
6837	{
6838	struct intel_display *display = to_intel_display(dig_port);
6839	struct intel_dp *intel_dp = &dig_port->dp;
6840	struct intel_encoder *encoder = &dig_port->base;
6841	struct drm_device *dev = encoder->base.dev;
6842	enum port port = encoder->port;
6843	int type;
6844
6845	if (drm_WARN(dev, dig_port->max_lanes < 1,
6846	"Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n",
6847	dig_port->max_lanes, encoder->base.base.id,
6848	encoder->base.name))
6849	return false;
6850
6851	intel_dp->reset_link_params = true;
6852
6853	/* Preserve the current hw state. */
6854	intel_dp->DP = intel_de_read(display, reg: intel_dp->output_reg);
6855	intel_dp->attached_connector = connector;
6856
6857	if (_intel_dp_is_port_edp(display, devdata: encoder->devdata, port)) {
6858	/*
6859	* Currently we don't support eDP on TypeC ports for DISPLAY_VER < 30,
6860	* although in theory it could work on TypeC legacy ports.
6861	*/
6862	drm_WARN_ON(dev, intel_encoder_is_tc(encoder) &&
6863	DISPLAY_VER(display) < 30);
6864	type = DRM_MODE_CONNECTOR_eDP;
6865	encoder->type = INTEL_OUTPUT_EDP;
6866
6867	/* eDP only on port B and/or C on vlv/chv */
6868	if (drm_WARN_ON(dev, (display->platform.valleyview ||
6869	display->platform.cherryview) &&
6870	port != PORT_B && port != PORT_C))
6871	return false;
6872	} else {
6873	type = DRM_MODE_CONNECTOR_DisplayPort;
6874	}
6875
6876	intel_dp_set_default_sink_rates(intel_dp);
6877	intel_dp_set_default_max_sink_lane_count(intel_dp);
6878
6879	if (display->platform.valleyview || display->platform.cherryview)
6880	vlv_pps_pipe_init(intel_dp);
6881
6882	intel_dp_aux_init(intel_dp);
6883	connector->dp.dsc_decompression_aux = &intel_dp->aux;
6884
6885	drm_dbg_kms(display->drm,
6886	"Adding %s connector on [ENCODER:%d:%s]\n",
6887	type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
6888	encoder->base.base.id, encoder->base.name);
6889
6890	drm_connector_init_with_ddc(dev, connector: &connector->base, funcs: &intel_dp_connector_funcs,
6891	connector_type: type, ddc: &intel_dp->aux.ddc);
6892	drm_connector_helper_add(connector: &connector->base, funcs: &intel_dp_connector_helper_funcs);
6893
6894	if (!HAS_GMCH(display) && DISPLAY_VER(display) < 12)
6895	connector->base.interlace_allowed = true;
6896
6897	if (type != DRM_MODE_CONNECTOR_eDP)
6898	connector->polled = DRM_CONNECTOR_POLL_HPD;
6899	connector->base.polled = connector->polled;
6900
6901	intel_connector_attach_encoder(connector, encoder);
6902
6903	if (HAS_DDI(display))
6904	connector->get_hw_state = intel_ddi_connector_get_hw_state;
6905	else
6906	connector->get_hw_state = intel_connector_get_hw_state;
6907	connector->sync_state = intel_dp_connector_sync_state;
6908
6909	if (!intel_edp_init_connector(intel_dp, connector)) {
6910	intel_dp_aux_fini(intel_dp);
6911	goto fail;
6912	}
6913
6914	intel_dp_set_source_rates(intel_dp);
6915	intel_dp_set_common_rates(intel_dp);
6916	intel_dp_reset_link_params(intel_dp);
6917
6918	/* init MST on ports that can support it */
6919	intel_dp_mst_encoder_init(dig_port, conn_id: connector->base.base.id);
6920
6921	intel_dp_add_properties(intel_dp, connector: &connector->base);
6922
6923	if (is_hdcp_supported(display, port) && !intel_dp_is_edp(intel_dp)) {
6924	int ret = intel_dp_hdcp_init(dig_port, intel_connector: connector);
6925	if (ret)
6926	drm_dbg_kms(display->drm,
6927	"HDCP init failed, skipping.\n");
6928	}
6929
6930	intel_dp->frl.is_trained = false;
6931	intel_dp->frl.trained_rate_gbps = 0;
6932
6933	intel_psr_init(intel_dp);
6934
6935	return true;
6936
6937	fail:
6938	intel_display_power_flush_work(display);
6939	drm_connector_cleanup(connector: &connector->base);
6940
6941	return false;
6942	}
6943
6944	void intel_dp_mst_suspend(struct intel_display *display)
6945	{
6946	struct intel_encoder *encoder;
6947
6948	if (!HAS_DISPLAY(display))
6949	return;
6950
6951	for_each_intel_encoder(display->drm, encoder) {
6952	struct intel_dp *intel_dp;
6953
6954	if (encoder->type != INTEL_OUTPUT_DDI)
6955	continue;
6956
6957	intel_dp = enc_to_intel_dp(encoder);
6958
6959	if (!intel_dp_mst_source_support(intel_dp))
6960	continue;
6961
6962	if (intel_dp->is_mst)
6963	drm_dp_mst_topology_mgr_suspend(mgr: &intel_dp->mst.mgr);
6964	}
6965	}
6966
6967	void intel_dp_mst_resume(struct intel_display *display)
6968	{
6969	struct intel_encoder *encoder;
6970
6971	if (!HAS_DISPLAY(display))
6972	return;
6973
6974	for_each_intel_encoder(display->drm, encoder) {
6975	struct intel_dp *intel_dp;
6976	int ret;
6977
6978	if (encoder->type != INTEL_OUTPUT_DDI)
6979	continue;
6980
6981	intel_dp = enc_to_intel_dp(encoder);
6982
6983	if (!intel_dp_mst_source_support(intel_dp))
6984	continue;
6985
6986	ret = drm_dp_mst_topology_mgr_resume(mgr: &intel_dp->mst.mgr, sync: true);
6987	if (ret) {
6988	intel_dp->is_mst = false;
6989	drm_dp_mst_topology_mgr_set_mst(mgr: &intel_dp->mst.mgr, mst_state: false);
6990	}
6991	}
6992	}
6993
6994	static
6995	int intel_dp_sdp_compute_config_late(struct intel_crtc_state *crtc_state)
6996	{
6997	struct intel_display *display = to_intel_display(crtc_state);
6998	int guardband = intel_crtc_vblank_length(crtc_state);
6999	int min_sdp_guardband = intel_dp_sdp_min_guardband(crtc_state, assume_all_enabled: false);
7000
7001	if (guardband < min_sdp_guardband) {
7002	drm_dbg_kms(display->drm, "guardband %d < min sdp guardband %d\n",
7003	guardband, min_sdp_guardband);
7004	return -EINVAL;
7005	}
7006
7007	return 0;
7008	}
7009
7010	int intel_dp_compute_config_late(struct intel_encoder *encoder,
7011	struct intel_crtc_state *crtc_state,
7012	struct drm_connector_state *conn_state)
7013	{
7014	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
7015	int ret;
7016
7017	intel_psr_compute_config_late(intel_dp, crtc_state);
7018
7019	ret = intel_dp_sdp_compute_config_late(crtc_state);
7020	if (ret)
7021	return ret;
7022
7023	return 0;
7024	}
7025
7026	static
7027	int intel_dp_get_lines_for_sdp(const struct intel_crtc_state *crtc_state, u32 type)
7028	{
7029	switch (type) {
7030	case DP_SDP_VSC_EXT_VESA:
7031	case DP_SDP_VSC_EXT_CEA:
7032	return 10;
7033	case HDMI_PACKET_TYPE_GAMUT_METADATA:
7034	return 8;
7035	case DP_SDP_PPS:
7036	return 7;
7037	case DP_SDP_ADAPTIVE_SYNC:
7038	return crtc_state->vrr.vsync_start + 1;
7039	default:
7040	break;
7041	}
7042
7043	return 0;
7044	}
7045
7046	int intel_dp_sdp_min_guardband(const struct intel_crtc_state *crtc_state,
7047	bool assume_all_enabled)
7048	{
7049	struct intel_display *display = to_intel_display(crtc_state);
7050	int sdp_guardband = 0;
7051
7052	if (assume_all_enabled ||
7053	crtc_state->infoframes.enable &
7054	intel_hdmi_infoframe_enable(type: HDMI_PACKET_TYPE_GAMUT_METADATA))
7055	sdp_guardband = max(sdp_guardband,
7056	intel_dp_get_lines_for_sdp(crtc_state,
7057	HDMI_PACKET_TYPE_GAMUT_METADATA));
7058
7059	if (assume_all_enabled ||
7060	crtc_state->dsc.compression_enable)
7061	sdp_guardband = max(sdp_guardband,
7062	intel_dp_get_lines_for_sdp(crtc_state, DP_SDP_PPS));
7063
7064	if ((assume_all_enabled && HAS_AS_SDP(display)) ||
7065	crtc_state->infoframes.enable & intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC))
7066	sdp_guardband = max(sdp_guardband,
7067	intel_dp_get_lines_for_sdp(crtc_state, DP_SDP_ADAPTIVE_SYNC));
7068
7069	return sdp_guardband;
7070	}
7071