| 1 | /* SPDX-License-Identifier: MIT */ |
| 2 | /* |
| 3 | * Copyright © 2019 Intel Corporation |
| 4 | */ |
| 5 | |
| 6 | #ifndef __INTEL_DP_H__ |
| 7 | #define __INTEL_DP_H__ |
| 8 | |
| 9 | #include <linux/types.h> |
| 10 | |
| 11 | enum intel_output_format; |
| 12 | enum pipe; |
| 13 | enum port; |
| 14 | struct drm_connector_state; |
| 15 | struct drm_dp_desc; |
| 16 | struct drm_dp_vsc_sdp; |
| 17 | struct drm_encoder; |
| 18 | struct drm_modeset_acquire_ctx; |
| 19 | struct intel_atomic_state; |
| 20 | struct intel_connector; |
| 21 | struct intel_crtc_state; |
| 22 | struct intel_digital_port; |
| 23 | struct intel_display; |
| 24 | struct intel_dp; |
| 25 | struct intel_encoder; |
| 26 | |
| 27 | struct link_config_limits { |
| 28 | int min_rate, max_rate; |
| 29 | int min_lane_count, max_lane_count; |
| 30 | struct { |
| 31 | /* Uncompressed DSC input or link output bpp in 1 bpp units */ |
| 32 | int min_bpp, max_bpp; |
| 33 | } pipe; |
| 34 | struct { |
| 35 | /* Compressed or uncompressed link output bpp in 1/16 bpp units */ |
| 36 | int min_bpp_x16, max_bpp_x16; |
| 37 | } link; |
| 38 | }; |
| 39 | |
| 40 | void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp); |
| 41 | bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state, |
| 42 | const struct drm_connector_state *conn_state); |
| 43 | int intel_dp_min_bpp(enum intel_output_format output_format); |
| 44 | void intel_dp_init_modeset_retry_work(struct intel_connector *connector); |
| 45 | void |
| 46 | intel_dp_queue_modeset_retry_for_link(struct intel_atomic_state *state, |
| 47 | struct intel_encoder *encoder, |
| 48 | const struct intel_crtc_state *crtc_state); |
| 49 | bool intel_dp_init_connector(struct intel_digital_port *dig_port, |
| 50 | struct intel_connector *intel_connector); |
| 51 | void intel_dp_connector_sync_state(struct intel_connector *connector, |
| 52 | const struct intel_crtc_state *crtc_state); |
| 53 | void intel_dp_set_link_params(struct intel_dp *intel_dp, |
| 54 | int link_rate, int lane_count); |
| 55 | int intel_dp_get_active_pipes(struct intel_dp *intel_dp, |
| 56 | struct drm_modeset_acquire_ctx *ctx, |
| 57 | u8 *pipe_mask); |
| 58 | void intel_dp_flush_connector_commits(struct intel_connector *connector); |
| 59 | void intel_dp_link_check(struct intel_encoder *encoder); |
| 60 | void intel_dp_check_link_state(struct intel_dp *intel_dp); |
| 61 | void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode); |
| 62 | void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp, |
| 63 | const struct intel_crtc_state *crtc_state); |
| 64 | void intel_dp_sink_enable_decompression(struct intel_atomic_state *state, |
| 65 | struct intel_connector *connector, |
| 66 | const struct intel_crtc_state *new_crtc_state); |
| 67 | void intel_dp_sink_disable_decompression(struct intel_atomic_state *state, |
| 68 | struct intel_connector *connector, |
| 69 | const struct intel_crtc_state *old_crtc_state); |
| 70 | void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder); |
| 71 | void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder); |
| 72 | void intel_dp_encoder_flush_work(struct drm_encoder *encoder); |
| 73 | int intel_dp_compute_config(struct intel_encoder *encoder, |
| 74 | struct intel_crtc_state *pipe_config, |
| 75 | struct drm_connector_state *conn_state); |
| 76 | bool intel_dp_needs_8b10b_fec(const struct intel_crtc_state *crtc_state, |
| 77 | bool dsc_enabled_on_crtc); |
| 78 | int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, |
| 79 | struct intel_crtc_state *pipe_config, |
| 80 | struct drm_connector_state *conn_state, |
| 81 | const struct link_config_limits *limits, |
| 82 | int timeslots); |
| 83 | void intel_dp_audio_compute_config(struct intel_encoder *encoder, |
| 84 | struct intel_crtc_state *pipe_config, |
| 85 | struct drm_connector_state *conn_state); |
| 86 | bool intel_dp_has_hdmi_sink(struct intel_dp *intel_dp); |
| 87 | bool intel_dp_is_edp(struct intel_dp *intel_dp); |
| 88 | bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state); |
| 89 | bool intel_dp_has_dsc(const struct intel_connector *connector); |
| 90 | int intel_dp_link_symbol_size(int rate); |
| 91 | int intel_dp_link_symbol_clock(int rate); |
| 92 | bool intel_dp_is_port_edp(struct intel_display *display, enum port port); |
| 93 | enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *dig_port, |
| 94 | bool long_hpd); |
| 95 | void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state, |
| 96 | const struct drm_connector_state *conn_state); |
| 97 | void intel_edp_backlight_off(const struct drm_connector_state *conn_state); |
| 98 | void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp); |
| 99 | void intel_dp_mst_suspend(struct intel_display *display); |
| 100 | void intel_dp_mst_resume(struct intel_display *display); |
| 101 | int intel_dp_max_source_lane_count(struct intel_digital_port *dig_port); |
| 102 | int intel_dp_max_link_rate(struct intel_dp *intel_dp); |
| 103 | int intel_dp_max_lane_count(struct intel_dp *intel_dp); |
| 104 | int intel_dp_config_required_rate(const struct intel_crtc_state *crtc_state); |
| 105 | int intel_dp_rate_select(struct intel_dp *intel_dp, int rate); |
| 106 | int intel_dp_max_common_rate(struct intel_dp *intel_dp); |
| 107 | int intel_dp_max_common_lane_count(struct intel_dp *intel_dp); |
| 108 | int intel_dp_common_rate(struct intel_dp *intel_dp, int index); |
| 109 | int intel_dp_rate_index(const int *rates, int len, int rate); |
| 110 | int intel_dp_link_config_index(struct intel_dp *intel_dp, int link_rate, int lane_count); |
| 111 | void intel_dp_link_config_get(struct intel_dp *intel_dp, int idx, int *link_rate, int *lane_count); |
| 112 | void intel_dp_update_sink_caps(struct intel_dp *intel_dp); |
| 113 | void intel_dp_reset_link_params(struct intel_dp *intel_dp); |
| 114 | |
| 115 | void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, |
| 116 | u8 *link_bw, u8 *rate_select); |
| 117 | bool intel_dp_source_supports_tps3(struct intel_display *display); |
| 118 | bool intel_dp_source_supports_tps4(struct intel_display *display); |
| 119 | |
| 120 | int intel_dp_link_required(int pixel_clock, int bpp); |
| 121 | int intel_dp_effective_data_rate(int pixel_clock, int bpp_x16, |
| 122 | int bw_overhead); |
| 123 | int intel_dp_max_link_data_rate(struct intel_dp *intel_dp, |
| 124 | int max_dprx_rate, int max_dprx_lanes); |
| 125 | bool intel_dp_joiner_needs_dsc(struct intel_display *display, |
| 126 | int num_joined_pipes); |
| 127 | bool intel_dp_has_joiner(struct intel_dp *intel_dp); |
| 128 | bool intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state, |
| 129 | const struct drm_connector_state *conn_state); |
| 130 | void intel_dp_set_infoframes(struct intel_encoder *encoder, bool enable, |
| 131 | const struct intel_crtc_state *crtc_state, |
| 132 | const struct drm_connector_state *conn_state); |
| 133 | void intel_read_dp_sdp(struct intel_encoder *encoder, |
| 134 | struct intel_crtc_state *crtc_state, |
| 135 | unsigned int type); |
| 136 | void intel_digital_port_lock(struct intel_encoder *encoder); |
| 137 | void intel_digital_port_unlock(struct intel_encoder *encoder); |
| 138 | bool intel_digital_port_connected(struct intel_encoder *encoder); |
| 139 | bool intel_digital_port_connected_locked(struct intel_encoder *encoder); |
| 140 | int intel_dp_dsc_compute_max_bpp(const struct intel_connector *connector, |
| 141 | u8 dsc_max_bpc); |
| 142 | u16 intel_dp_dsc_get_max_compressed_bpp(struct intel_display *display, |
| 143 | u32 link_clock, u32 lane_count, |
| 144 | u32 mode_clock, u32 mode_hdisplay, |
| 145 | int num_joined_pipes, |
| 146 | enum intel_output_format output_format, |
| 147 | u32 pipe_bpp, |
| 148 | u32 timeslots); |
| 149 | int intel_dp_dsc_sink_min_compressed_bpp(const struct intel_crtc_state *pipe_config); |
| 150 | int intel_dp_dsc_sink_max_compressed_bpp(const struct intel_connector *connector, |
| 151 | const struct intel_crtc_state *pipe_config, |
| 152 | int bpc); |
| 153 | bool intel_dp_dsc_valid_compressed_bpp(struct intel_dp *intel_dp, int bpp_x16); |
| 154 | u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector, |
| 155 | int mode_clock, int mode_hdisplay, |
| 156 | int num_joined_pipes); |
| 157 | int intel_dp_num_joined_pipes(struct intel_dp *intel_dp, |
| 158 | struct intel_connector *connector, |
| 159 | int hdisplay, int clock); |
| 160 | |
| 161 | static inline unsigned int intel_dp_unused_lane_mask(int lane_count) |
| 162 | { |
| 163 | return ~((1 << lane_count) - 1) & 0xf; |
| 164 | } |
| 165 | |
| 166 | bool intel_dp_supports_fec(struct intel_dp *intel_dp, |
| 167 | const struct intel_connector *connector, |
| 168 | const struct intel_crtc_state *pipe_config); |
| 169 | u32 intel_dp_mode_to_fec_clock(u32 mode_clock); |
| 170 | int intel_dp_bw_fec_overhead(bool fec_enabled); |
| 171 | |
| 172 | bool intel_dp_supports_fec(struct intel_dp *intel_dp, |
| 173 | const struct intel_connector *connector, |
| 174 | const struct intel_crtc_state *pipe_config); |
| 175 | |
| 176 | bool intel_dp_supports_dsc(struct intel_dp *intel_dp, |
| 177 | const struct intel_connector *connector, |
| 178 | const struct intel_crtc_state *crtc_state); |
| 179 | |
| 180 | void intel_ddi_update_pipe(struct intel_atomic_state *state, |
| 181 | struct intel_encoder *encoder, |
| 182 | const struct intel_crtc_state *crtc_state, |
| 183 | const struct drm_connector_state *conn_state); |
| 184 | |
| 185 | bool intel_dp_initial_fastset_check(struct intel_encoder *encoder, |
| 186 | struct intel_crtc_state *crtc_state); |
| 187 | void intel_dp_sync_state(struct intel_encoder *encoder, |
| 188 | const struct intel_crtc_state *crtc_state); |
| 189 | |
| 190 | void intel_dp_check_frl_training(struct intel_dp *intel_dp); |
| 191 | void intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp, |
| 192 | const struct intel_crtc_state *crtc_state); |
| 193 | |
| 194 | void intel_dp_invalidate_source_oui(struct intel_dp *intel_dp); |
| 195 | void intel_dp_wait_source_oui(struct intel_dp *intel_dp); |
| 196 | int intel_dp_output_bpp(enum intel_output_format output_format, int bpp); |
| 197 | |
| 198 | bool intel_dp_compute_config_limits(struct intel_dp *intel_dp, |
| 199 | struct drm_connector_state *conn_state, |
| 200 | struct intel_crtc_state *crtc_state, |
| 201 | bool respect_downstream_limits, |
| 202 | bool dsc, |
| 203 | struct link_config_limits *limits); |
| 204 | |
| 205 | void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, |
| 206 | const struct drm_dp_desc *desc, bool is_branch, |
| 207 | struct intel_connector *connector); |
| 208 | bool intel_dp_has_gamut_metadata_dip(struct intel_encoder *encoder); |
| 209 | |
| 210 | bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate, |
| 211 | u8 lane_count); |
| 212 | bool intel_dp_has_connector(struct intel_dp *intel_dp, |
| 213 | const struct drm_connector_state *conn_state); |
| 214 | int intel_dp_dsc_max_src_input_bpc(struct intel_display *display); |
| 215 | int intel_dp_dsc_min_src_input_bpc(void); |
| 216 | int intel_dp_dsc_min_src_compressed_bpp(void); |
| 217 | int intel_dp_compute_min_hblank(struct intel_crtc_state *crtc_state, |
| 218 | const struct drm_connector_state *conn_state); |
| 219 | |
| 220 | int intel_dp_dsc_bpp_step_x16(const struct intel_connector *connector); |
| 221 | void intel_dp_dpcd_set_probe(struct intel_dp *intel_dp, bool force_on_external); |
| 222 | bool intel_dp_in_hdr_mode(const struct drm_connector_state *conn_state); |
| 223 | int intel_dp_compute_config_late(struct intel_encoder *encoder, |
| 224 | struct intel_crtc_state *crtc_state, |
| 225 | struct drm_connector_state *conn_state); |
| 226 | int intel_dp_sdp_min_guardband(const struct intel_crtc_state *crtc_state, |
| 227 | bool assume_all_enabled); |
| 228 | |
| 229 | #endif /* __INTEL_DP_H__ */ |
| 230 | |