1	/*
2	* Copyright © 2006-2007 Intel Corporation
3	*
4	* Permission is hereby granted, free of charge, to any person obtaining a
5	* copy of this software and associated documentation files (the "Software"),
6	* to deal in the Software without restriction, including without limitation
7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8	* and/or sell copies of the Software, and to permit persons to whom the
9	* Software is furnished to do so, subject to the following conditions:
10	*
11	* The above copyright notice and this permission notice (including the next
12	* paragraph) shall be included in all copies or substantial portions of the
13	* Software.
14	*
15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21	* DEALINGS IN THE SOFTWARE.
22	*
23	* Authors:
24	* Eric Anholt <eric@anholt.net>
25	*/
26
27	#include <linux/dma-resv.h>
28	#include <linux/i2c.h>
29	#include <linux/input.h>
30	#include <linux/kernel.h>
31	#include <linux/module.h>
32	#include <linux/slab.h>
33	#include <linux/string_helpers.h>
34
35	#include <drm/display/drm_dp_helper.h>
36	#include <drm/display/drm_dp_tunnel.h>
37	#include <drm/drm_atomic.h>
38	#include <drm/drm_atomic_helper.h>
39	#include <drm/drm_atomic_uapi.h>
40	#include <drm/drm_damage_helper.h>
41	#include <drm/drm_edid.h>
42	#include <drm/drm_fixed.h>
43	#include <drm/drm_fourcc.h>
44	#include <drm/drm_print.h>
45	#include <drm/drm_probe_helper.h>
46	#include <drm/drm_rect.h>
47	#include <drm/drm_vblank.h>
48
49	#include "g4x_dp.h"
50	#include "g4x_hdmi.h"
51	#include "hsw_ips.h"
52	#include "i915_config.h"
53	#include "i915_drv.h"
54	#include "i915_reg.h"
55	#include "i9xx_plane.h"
56	#include "i9xx_plane_regs.h"
57	#include "i9xx_wm.h"
58	#include "intel_alpm.h"
59	#include "intel_atomic.h"
60	#include "intel_audio.h"
61	#include "intel_bo.h"
62	#include "intel_bw.h"
63	#include "intel_casf.h"
64	#include "intel_cdclk.h"
65	#include "intel_clock_gating.h"
66	#include "intel_color.h"
67	#include "intel_crt.h"
68	#include "intel_crtc.h"
69	#include "intel_crtc_state_dump.h"
70	#include "intel_cursor.h"
71	#include "intel_cursor_regs.h"
72	#include "intel_cx0_phy.h"
73	#include "intel_ddi.h"
74	#include "intel_de.h"
75	#include "intel_display_driver.h"
76	#include "intel_display_power.h"
77	#include "intel_display_regs.h"
78	#include "intel_display_rpm.h"
79	#include "intel_display_types.h"
80	#include "intel_display_utils.h"
81	#include "intel_display_wa.h"
82	#include "intel_dmc.h"
83	#include "intel_dp.h"
84	#include "intel_dp_link_training.h"
85	#include "intel_dp_mst.h"
86	#include "intel_dp_tunnel.h"
87	#include "intel_dpll.h"
88	#include "intel_dpll_mgr.h"
89	#include "intel_dpt.h"
90	#include "intel_dpt_common.h"
91	#include "intel_drrs.h"
92	#include "intel_dsb.h"
93	#include "intel_dsi.h"
94	#include "intel_dvo.h"
95	#include "intel_fb.h"
96	#include "intel_fbc.h"
97	#include "intel_fdi.h"
98	#include "intel_fifo_underrun.h"
99	#include "intel_flipq.h"
100	#include "intel_frontbuffer.h"
101	#include "intel_hdmi.h"
102	#include "intel_hotplug.h"
103	#include "intel_link_bw.h"
104	#include "intel_lt_phy.h"
105	#include "intel_lvds.h"
106	#include "intel_lvds_regs.h"
107	#include "intel_modeset_setup.h"
108	#include "intel_modeset_verify.h"
109	#include "intel_overlay.h"
110	#include "intel_panel.h"
111	#include "intel_pch_display.h"
112	#include "intel_pch_refclk.h"
113	#include "intel_pfit.h"
114	#include "intel_pipe_crc.h"
115	#include "intel_plane.h"
116	#include "intel_plane_initial.h"
117	#include "intel_pmdemand.h"
118	#include "intel_pps.h"
119	#include "intel_psr.h"
120	#include "intel_psr_regs.h"
121	#include "intel_sdvo.h"
122	#include "intel_snps_phy.h"
123	#include "intel_tc.h"
124	#include "intel_tdf.h"
125	#include "intel_tv.h"
126	#include "intel_vblank.h"
127	#include "intel_vdsc.h"
128	#include "intel_vdsc_regs.h"
129	#include "intel_vga.h"
130	#include "intel_vrr.h"
131	#include "intel_wm.h"
132	#include "skl_scaler.h"
133	#include "skl_universal_plane.h"
134	#include "skl_watermark.h"
135	#include "vlv_dsi.h"
136	#include "vlv_dsi_pll.h"
137	#include "vlv_dsi_regs.h"
138
139	static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state);
140	static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
141	static void hsw_set_transconf(const struct intel_crtc_state *crtc_state);
142	static void bdw_set_pipe_misc(struct intel_dsb *dsb,
143	const struct intel_crtc_state *crtc_state);
144
145	static bool is_hdr_mode(const struct intel_crtc_state *crtc_state)
146	{
147	return (crtc_state->active_planes &
148	~(icl_hdr_plane_mask() | BIT(PLANE_CURSOR))) == 0;
149	}
150
151	/* WA Display #0827: Gen9:all */
152	static void
153	skl_wa_827(struct intel_display *display, enum pipe pipe, bool enable)
154	{
155	intel_de_rmw(display, CLKGATE_DIS_PSL(pipe),
156	DUPS1_GATING_DIS | DUPS2_GATING_DIS,
157	set: enable ? DUPS1_GATING_DIS | DUPS2_GATING_DIS : 0);
158	}
159
160	/* Wa_2006604312:icl,ehl */
161	static void
162	icl_wa_scalerclkgating(struct intel_display *display, enum pipe pipe,
163	bool enable)
164	{
165	intel_de_rmw(display, CLKGATE_DIS_PSL(pipe),
166	DPFR_GATING_DIS,
167	set: enable ? DPFR_GATING_DIS : 0);
168	}
169
170	/* Wa_1604331009:icl,jsl,ehl */
171	static void
172	icl_wa_cursorclkgating(struct intel_display *display, enum pipe pipe,
173	bool enable)
174	{
175	intel_de_rmw(display, CLKGATE_DIS_PSL(pipe),
176	CURSOR_GATING_DIS,
177	set: enable ? CURSOR_GATING_DIS : 0);
178	}
179
180	static bool
181	is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state)
182	{
183	return crtc_state->master_transcoder != INVALID_TRANSCODER;
184	}
185
186	bool
187	is_trans_port_sync_master(const struct intel_crtc_state *crtc_state)
188	{
189	return crtc_state->sync_mode_slaves_mask != 0;
190	}
191
192	bool
193	is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state)
194	{
195	return is_trans_port_sync_master(crtc_state) ||
196	is_trans_port_sync_slave(crtc_state);
197	}
198
199	static enum pipe joiner_primary_pipe(const struct intel_crtc_state *crtc_state)
200	{
201	return ffs(crtc_state->joiner_pipes) - 1;
202	}
203
204	/*
205	* The following helper functions, despite being named for bigjoiner,
206	* are applicable to both bigjoiner and uncompressed joiner configurations.
207	*/
208	static bool is_bigjoiner(const struct intel_crtc_state *crtc_state)
209	{
210	return hweight8(crtc_state->joiner_pipes) >= 2;
211	}
212
213	static u8 bigjoiner_primary_pipes(const struct intel_crtc_state *crtc_state)
214	{
215	if (!is_bigjoiner(crtc_state))
216	return 0;
217
218	return crtc_state->joiner_pipes & (0b01010101 << joiner_primary_pipe(crtc_state));
219	}
220
221	static unsigned int bigjoiner_secondary_pipes(const struct intel_crtc_state *crtc_state)
222	{
223	if (!is_bigjoiner(crtc_state))
224	return 0;
225
226	return crtc_state->joiner_pipes & (0b10101010 << joiner_primary_pipe(crtc_state));
227	}
228
229	bool intel_crtc_is_bigjoiner_primary(const struct intel_crtc_state *crtc_state)
230	{
231	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
232
233	if (!is_bigjoiner(crtc_state))
234	return false;
235
236	return BIT(crtc->pipe) & bigjoiner_primary_pipes(crtc_state);
237	}
238
239	bool intel_crtc_is_bigjoiner_secondary(const struct intel_crtc_state *crtc_state)
240	{
241	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
242
243	if (!is_bigjoiner(crtc_state))
244	return false;
245
246	return BIT(crtc->pipe) & bigjoiner_secondary_pipes(crtc_state);
247	}
248
249	u8 _intel_modeset_primary_pipes(const struct intel_crtc_state *crtc_state)
250	{
251	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
252
253	if (!is_bigjoiner(crtc_state))
254	return BIT(crtc->pipe);
255
256	return bigjoiner_primary_pipes(crtc_state);
257	}
258
259	u8 _intel_modeset_secondary_pipes(const struct intel_crtc_state *crtc_state)
260	{
261	return bigjoiner_secondary_pipes(crtc_state);
262	}
263
264	bool intel_crtc_is_ultrajoiner(const struct intel_crtc_state *crtc_state)
265	{
266	return intel_crtc_num_joined_pipes(crtc_state) >= 4;
267	}
268
269	static u8 ultrajoiner_primary_pipes(const struct intel_crtc_state *crtc_state)
270	{
271	if (!intel_crtc_is_ultrajoiner(crtc_state))
272	return 0;
273
274	return crtc_state->joiner_pipes & (0b00010001 << joiner_primary_pipe(crtc_state));
275	}
276
277	bool intel_crtc_is_ultrajoiner_primary(const struct intel_crtc_state *crtc_state)
278	{
279	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
280
281	return intel_crtc_is_ultrajoiner(crtc_state) &&
282	BIT(crtc->pipe) & ultrajoiner_primary_pipes(crtc_state);
283	}
284
285	/*
286	* The ultrajoiner enable bit doesn't seem to follow primary/secondary logic or
287	* any other logic, so lets just add helper function to
288	* at least hide this hassle..
289	*/
290	static u8 ultrajoiner_enable_pipes(const struct intel_crtc_state *crtc_state)
291	{
292	if (!intel_crtc_is_ultrajoiner(crtc_state))
293	return 0;
294
295	return crtc_state->joiner_pipes & (0b01110111 << joiner_primary_pipe(crtc_state));
296	}
297
298	bool intel_crtc_ultrajoiner_enable_needed(const struct intel_crtc_state *crtc_state)
299	{
300	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
301
302	return intel_crtc_is_ultrajoiner(crtc_state) &&
303	BIT(crtc->pipe) & ultrajoiner_enable_pipes(crtc_state);
304	}
305
306	u8 intel_crtc_joiner_secondary_pipes(const struct intel_crtc_state *crtc_state)
307	{
308	if (crtc_state->joiner_pipes)
309	return crtc_state->joiner_pipes & ~BIT(joiner_primary_pipe(crtc_state));
310	else
311	return 0;
312	}
313
314	bool intel_crtc_is_joiner_secondary(const struct intel_crtc_state *crtc_state)
315	{
316	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
317
318	return crtc_state->joiner_pipes &&
319	crtc->pipe != joiner_primary_pipe(crtc_state);
320	}
321
322	bool intel_crtc_is_joiner_primary(const struct intel_crtc_state *crtc_state)
323	{
324	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
325
326	return crtc_state->joiner_pipes &&
327	crtc->pipe == joiner_primary_pipe(crtc_state);
328	}
329
330	int intel_crtc_num_joined_pipes(const struct intel_crtc_state *crtc_state)
331	{
332	return hweight8(intel_crtc_joined_pipe_mask(crtc_state));
333	}
334
335	u8 intel_crtc_joined_pipe_mask(const struct intel_crtc_state *crtc_state)
336	{
337	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
338
339	return BIT(crtc->pipe) | crtc_state->joiner_pipes;
340	}
341
342	struct intel_crtc *intel_primary_crtc(const struct intel_crtc_state *crtc_state)
343	{
344	struct intel_display *display = to_intel_display(crtc_state);
345
346	if (intel_crtc_is_joiner_secondary(crtc_state))
347	return intel_crtc_for_pipe(display, pipe: joiner_primary_pipe(crtc_state));
348	else
349	return to_intel_crtc(crtc_state->uapi.crtc);
350	}
351
352	static void
353	intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
354	{
355	struct intel_display *display = to_intel_display(old_crtc_state);
356	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
357
358	if (DISPLAY_VER(display) >= 4) {
359	enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
360
361	/* Wait for the Pipe State to go off */
362	if (intel_de_wait_for_clear_ms(display, TRANSCONF(display, cpu_transcoder),
363	TRANSCONF_STATE_ENABLE, timeout_ms: 100))
364	drm_WARN(display->drm, 1, "pipe_off wait timed out\n");
365	} else {
366	intel_wait_for_pipe_scanline_stopped(crtc);
367	}
368	}
369
370	void assert_transcoder(struct intel_display *display,
371	enum transcoder cpu_transcoder, bool state)
372	{
373	bool cur_state;
374	enum intel_display_power_domain power_domain;
375	intel_wakeref_t wakeref;
376
377	/* we keep both pipes enabled on 830 */
378	if (display->platform.i830)
379	state = true;
380
381	power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
382	wakeref = intel_display_power_get_if_enabled(display, domain: power_domain);
383	if (wakeref) {
384	u32 val = intel_de_read(display,
385	TRANSCONF(display, cpu_transcoder));
386	cur_state = !!(val & TRANSCONF_ENABLE);
387
388	intel_display_power_put(display, domain: power_domain, wakeref);
389	} else {
390	cur_state = false;
391	}
392
393	INTEL_DISPLAY_STATE_WARN(display, cur_state != state,
394	"transcoder %s assertion failure (expected %s, current %s)\n",
395	transcoder_name(cpu_transcoder), str_on_off(state),
396	str_on_off(cur_state));
397	}
398
399	static void assert_plane(struct intel_plane *plane, bool state)
400	{
401	struct intel_display *display = to_intel_display(plane->base.dev);
402	enum pipe pipe;
403	bool cur_state;
404
405	cur_state = plane->get_hw_state(plane, &pipe);
406
407	INTEL_DISPLAY_STATE_WARN(display, cur_state != state,
408	"%s assertion failure (expected %s, current %s)\n",
409	plane->base.name, str_on_off(state),
410	str_on_off(cur_state));
411	}
412
413	#define assert_plane_enabled(p) assert_plane(p, true)
414	#define assert_plane_disabled(p) assert_plane(p, false)
415
416	static void assert_planes_disabled(struct intel_crtc *crtc)
417	{
418	struct intel_display *display = to_intel_display(crtc);
419	struct intel_plane *plane;
420
421	for_each_intel_plane_on_crtc(display->drm, crtc, plane)
422	assert_plane_disabled(plane);
423	}
424
425	void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state)
426	{
427	struct intel_display *display = to_intel_display(new_crtc_state);
428	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
429	enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
430	enum pipe pipe = crtc->pipe;
431	u32 val;
432
433	drm_dbg_kms(display->drm, "enabling pipe %c\n", pipe_name(pipe));
434
435	assert_planes_disabled(crtc);
436
437	/*
438	* A pipe without a PLL won't actually be able to drive bits from
439	* a plane. On ILK+ the pipe PLLs are integrated, so we don't
440	* need the check.
441	*/
442	if (HAS_GMCH(display)) {
443	if (intel_crtc_has_type(crtc_state: new_crtc_state, type: INTEL_OUTPUT_DSI))
444	assert_dsi_pll_enabled(display);
445	else
446	assert_pll_enabled(display, pipe);
447	} else {
448	if (new_crtc_state->has_pch_encoder) {
449	/* if driving the PCH, we need FDI enabled */
450	assert_fdi_rx_pll_enabled(display,
451	pipe: intel_crtc_pch_transcoder(crtc));
452	assert_fdi_tx_pll_enabled(display,
453	pipe: (enum pipe) cpu_transcoder);
454	}
455	/* FIXME: assert CPU port conditions for SNB+ */
456	}
457
458	/* Wa_22012358565:adl-p */
459	if (DISPLAY_VER(display) == 13)
460	intel_de_rmw(display, PIPE_ARB_CTL(display, pipe),
461	clear: 0, PIPE_ARB_USE_PROG_SLOTS);
462
463	if (DISPLAY_VER(display) >= 14) {
464	u32 clear = DP_DSC_INSERT_SF_AT_EOL_WA;
465	u32 set = 0;
466
467	if (DISPLAY_VER(display) == 14)
468	set |= DP_FEC_BS_JITTER_WA;
469
470	intel_de_rmw(display, CHICKEN_TRANS(display, cpu_transcoder),
471	clear, set);
472	}
473
474	val = intel_de_read(display, TRANSCONF(display, cpu_transcoder));
475	if (val & TRANSCONF_ENABLE) {
476	/* we keep both pipes enabled on 830 */
477	drm_WARN_ON(display->drm, !display->platform.i830);
478	return;
479	}
480
481	/* Wa_1409098942:adlp+ */
482	if (DISPLAY_VER(display) >= 13 &&
483	new_crtc_state->dsc.compression_enable) {
484	val &= ~TRANSCONF_PIXEL_COUNT_SCALING_MASK;
485	val |= REG_FIELD_PREP(TRANSCONF_PIXEL_COUNT_SCALING_MASK,
486	TRANSCONF_PIXEL_COUNT_SCALING_X4);
487	}
488
489	intel_de_write(display, TRANSCONF(display, cpu_transcoder),
490	val: val | TRANSCONF_ENABLE);
491	intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder));
492
493	/*
494	* Until the pipe starts PIPEDSL reads will return a stale value,
495	* which causes an apparent vblank timestamp jump when PIPEDSL
496	* resets to its proper value. That also messes up the frame count
497	* when it's derived from the timestamps. So let's wait for the
498	* pipe to start properly before we call drm_crtc_vblank_on()
499	*/
500	if (intel_crtc_max_vblank_count(crtc_state: new_crtc_state) == 0)
501	intel_wait_for_pipe_scanline_moving(crtc);
502	}
503
504	void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state)
505	{
506	struct intel_display *display = to_intel_display(old_crtc_state);
507	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
508	enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
509	enum pipe pipe = crtc->pipe;
510	u32 val;
511
512	drm_dbg_kms(display->drm, "disabling pipe %c\n", pipe_name(pipe));
513
514	/*
515	* Make sure planes won't keep trying to pump pixels to us,
516	* or we might hang the display.
517	*/
518	assert_planes_disabled(crtc);
519
520	val = intel_de_read(display, TRANSCONF(display, cpu_transcoder));
521	if ((val & TRANSCONF_ENABLE) == 0)
522	return;
523
524	/*
525	* Double wide has implications for planes
526	* so best keep it disabled when not needed.
527	*/
528	if (old_crtc_state->double_wide)
529	val &= ~TRANSCONF_DOUBLE_WIDE;
530
531	/* Don't disable pipe or pipe PLLs if needed */
532	if (!display->platform.i830)
533	val &= ~TRANSCONF_ENABLE;
534
535	/* Wa_1409098942:adlp+ */
536	if (DISPLAY_VER(display) >= 13 &&
537	old_crtc_state->dsc.compression_enable)
538	val &= ~TRANSCONF_PIXEL_COUNT_SCALING_MASK;
539
540	intel_de_write(display, TRANSCONF(display, cpu_transcoder), val);
541
542	if (DISPLAY_VER(display) >= 12)
543	intel_de_rmw(display, CHICKEN_TRANS(display, cpu_transcoder),
544	FECSTALL_DIS_DPTSTREAM_DPTTG, set: 0);
545
546	if ((val & TRANSCONF_ENABLE) == 0)
547	intel_wait_for_pipe_off(old_crtc_state);
548	}
549
550	u32 intel_plane_fb_max_stride(struct intel_display *display,
551	const struct drm_format_info *info,
552	u64 modifier)
553	{
554	struct intel_crtc *crtc;
555	struct intel_plane *plane;
556
557	/*
558	* We assume the primary plane for pipe A has
559	* the highest stride limits of them all,
560	* if in case pipe A is disabled, use the first pipe from pipe_mask.
561	*/
562	crtc = intel_first_crtc(display);
563	if (!crtc)
564	return 0;
565
566	plane = to_intel_plane(crtc->base.primary);
567
568	return plane->max_stride(plane, info, modifier,
569	DRM_MODE_ROTATE_0);
570	}
571
572	u32 intel_dumb_fb_max_stride(struct drm_device *drm,
573	u32 pixel_format, u64 modifier)
574	{
575	struct intel_display *display = to_intel_display(drm);
576
577	if (!HAS_DISPLAY(display))
578	return 0;
579
580	return intel_plane_fb_max_stride(display,
581	info: drm_get_format_info(dev: drm, pixel_format, modifier),
582	modifier);
583	}
584
585	void intel_set_plane_visible(struct intel_crtc_state *crtc_state,
586	struct intel_plane_state *plane_state,
587	bool visible)
588	{
589	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
590
591	plane_state->uapi.visible = visible;
592
593	if (visible)
594	crtc_state->uapi.plane_mask |= drm_plane_mask(plane: &plane->base);
595	else
596	crtc_state->uapi.plane_mask &= ~drm_plane_mask(plane: &plane->base);
597	}
598
599	void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state)
600	{
601	struct intel_display *display = to_intel_display(crtc_state);
602	struct drm_plane *plane;
603
604	/*
605	* Active_planes aliases if multiple "primary" or cursor planes
606	* have been used on the same (or wrong) pipe. plane_mask uses
607	* unique ids, hence we can use that to reconstruct active_planes.
608	*/
609	crtc_state->enabled_planes = 0;
610	crtc_state->active_planes = 0;
611
612	drm_for_each_plane_mask(plane, display->drm,
613	crtc_state->uapi.plane_mask) {
614	crtc_state->enabled_planes |= BIT(to_intel_plane(plane)->id);
615	crtc_state->active_planes |= BIT(to_intel_plane(plane)->id);
616	}
617	}
618
619	void intel_plane_disable_noatomic(struct intel_crtc *crtc,
620	struct intel_plane *plane)
621	{
622	struct intel_display *display = to_intel_display(crtc);
623	struct intel_crtc_state *crtc_state =
624	to_intel_crtc_state(crtc->base.state);
625	struct intel_plane_state *plane_state =
626	to_intel_plane_state(plane->base.state);
627
628	drm_dbg_kms(display->drm,
629	"Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n",
630	plane->base.base.id, plane->base.name,
631	crtc->base.base.id, crtc->base.name);
632
633	intel_plane_set_invisible(crtc_state, plane_state);
634	intel_set_plane_visible(crtc_state, plane_state, visible: false);
635	intel_plane_fixup_bitmasks(crtc_state);
636
637	skl_wm_plane_disable_noatomic(crtc, plane);
638
639	if ((crtc_state->active_planes & ~BIT(PLANE_CURSOR)) == 0 &&
640	hsw_ips_disable(crtc_state)) {
641	crtc_state->ips_enabled = false;
642	intel_plane_initial_vblank_wait(crtc);
643	}
644
645	/*
646	* Vblank time updates from the shadow to live plane control register
647	* are blocked if the memory self-refresh mode is active at that
648	* moment. So to make sure the plane gets truly disabled, disable
649	* first the self-refresh mode. The self-refresh enable bit in turn
650	* will be checked/applied by the HW only at the next frame start
651	* event which is after the vblank start event, so we need to have a
652	* wait-for-vblank between disabling the plane and the pipe.
653	*/
654	if (HAS_GMCH(display) &&
655	intel_set_memory_cxsr(display, enable: false))
656	intel_plane_initial_vblank_wait(crtc);
657
658	/*
659	* Gen2 reports pipe underruns whenever all planes are disabled.
660	* So disable underrun reporting before all the planes get disabled.
661	*/
662	if (DISPLAY_VER(display) == 2 && !crtc_state->active_planes)
663	intel_set_cpu_fifo_underrun_reporting(display, pipe: crtc->pipe, enable: false);
664
665	intel_plane_disable_arm(NULL, plane, crtc_state);
666	intel_plane_initial_vblank_wait(crtc);
667	}
668
669	unsigned int
670	intel_plane_fence_y_offset(const struct intel_plane_state *plane_state)
671	{
672	int x = 0, y = 0;
673
674	intel_plane_adjust_aligned_offset(x: &x, y: &y, plane_state, color_plane: 0,
675	old_offset: plane_state->view.color_plane[0].offset, new_offset: 0);
676
677	return y;
678	}
679
680	static void icl_set_pipe_chicken(const struct intel_crtc_state *crtc_state)
681	{
682	struct intel_display *display = to_intel_display(crtc_state);
683	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
684	enum pipe pipe = crtc->pipe;
685	u32 tmp;
686
687	tmp = intel_de_read(display, PIPE_CHICKEN(pipe));
688
689	/*
690	* Display WA #1153: icl
691	* enable hardware to bypass the alpha math
692	* and rounding for per-pixel values 00 and 0xff
693	*/
694	tmp |= PER_PIXEL_ALPHA_BYPASS_EN;
695	/*
696	* Display WA # 1605353570: icl
697	* Set the pixel rounding bit to 1 for allowing
698	* passthrough of Frame buffer pixels unmodified
699	* across pipe
700	*/
701	tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU;
702
703	/*
704	* Underrun recovery must always be disabled on display 13+.
705	* DG2 chicken bit meaning is inverted compared to other platforms.
706	*/
707	if (display->platform.dg2)
708	tmp &= ~UNDERRUN_RECOVERY_ENABLE_DG2;
709	else if ((DISPLAY_VER(display) >= 13) && (DISPLAY_VER(display) < 30))
710	tmp |= UNDERRUN_RECOVERY_DISABLE_ADLP;
711
712	/* Wa_14010547955:dg2 */
713	if (display->platform.dg2)
714	tmp |= DG2_RENDER_CCSTAG_4_3_EN;
715
716	intel_de_write(display, PIPE_CHICKEN(pipe), val: tmp);
717	}
718
719	bool intel_has_pending_fb_unpin(struct intel_display *display)
720	{
721	struct drm_crtc *crtc;
722	bool cleanup_done;
723
724	drm_for_each_crtc(crtc, display->drm) {
725	struct drm_crtc_commit *commit;
726	spin_lock(lock: &crtc->commit_lock);
727	commit = list_first_entry_or_null(&crtc->commit_list,
728	struct drm_crtc_commit, commit_entry);
729	cleanup_done = commit ?
730	try_wait_for_completion(x: &commit->cleanup_done) : true;
731	spin_unlock(lock: &crtc->commit_lock);
732
733	if (cleanup_done)
734	continue;
735
736	intel_crtc_wait_for_next_vblank(to_intel_crtc(crtc));
737
738	return true;
739	}
740
741	return false;
742	}
743
744	/*
745	* Finds the encoder associated with the given CRTC. This can only be
746	* used when we know that the CRTC isn't feeding multiple encoders!
747	*/
748	struct intel_encoder *
749	intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
750	const struct intel_crtc_state *crtc_state)
751	{
752	const struct drm_connector_state *connector_state;
753	const struct drm_connector *connector;
754	struct intel_encoder *encoder = NULL;
755	struct intel_crtc *primary_crtc;
756	int num_encoders = 0;
757	int i;
758
759	primary_crtc = intel_primary_crtc(crtc_state);
760
761	for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
762	if (connector_state->crtc != &primary_crtc->base)
763	continue;
764
765	encoder = to_intel_encoder(connector_state->best_encoder);
766	num_encoders++;
767	}
768
769	drm_WARN(state->base.dev, num_encoders != 1,
770	"%d encoders for pipe %c\n",
771	num_encoders, pipe_name(primary_crtc->pipe));
772
773	return encoder;
774	}
775
776	static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc)
777	{
778	if (crtc->overlay)
779	(void) intel_overlay_switch_off(overlay: crtc->overlay);
780
781	/* Let userspace switch the overlay on again. In most cases userspace
782	* has to recompute where to put it anyway.
783	*/
784	}
785
786	static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state)
787	{
788	struct intel_display *display = to_intel_display(crtc_state);
789
790	if (!crtc_state->nv12_planes)
791	return false;
792
793	/* WA Display #0827: Gen9:all */
794	if (DISPLAY_VER(display) == 9)
795	return true;
796
797	return false;
798	}
799
800	static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state)
801	{
802	struct intel_display *display = to_intel_display(crtc_state);
803
804	/* Wa_2006604312:icl,ehl */
805	if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(display) == 11)
806	return true;
807
808	return false;
809	}
810
811	static bool needs_cursorclk_wa(const struct intel_crtc_state *crtc_state)
812	{
813	struct intel_display *display = to_intel_display(crtc_state);
814
815	/* Wa_1604331009:icl,jsl,ehl */
816	if (is_hdr_mode(crtc_state) &&
817	crtc_state->active_planes & BIT(PLANE_CURSOR) &&
818	DISPLAY_VER(display) == 11)
819	return true;
820
821	return false;
822	}
823
824	static void intel_async_flip_vtd_wa(struct intel_display *display,
825	enum pipe pipe, bool enable)
826	{
827	if (DISPLAY_VER(display) == 9) {
828	/*
829	* "Plane N stretch max must be programmed to 11b (x1)
830	* when Async flips are enabled on that plane."
831	*/
832	intel_de_rmw(display, CHICKEN_PIPESL_1(pipe),
833	SKL_PLANE1_STRETCH_MAX_MASK,
834	set: enable ? SKL_PLANE1_STRETCH_MAX_X1 : SKL_PLANE1_STRETCH_MAX_X8);
835	} else {
836	/* Also needed on HSW/BDW albeit undocumented */
837	intel_de_rmw(display, CHICKEN_PIPESL_1(pipe),
838	HSW_PRI_STRETCH_MAX_MASK,
839	set: enable ? HSW_PRI_STRETCH_MAX_X1 : HSW_PRI_STRETCH_MAX_X8);
840	}
841	}
842
843	static bool needs_async_flip_vtd_wa(const struct intel_crtc_state *crtc_state)
844	{
845	struct intel_display *display = to_intel_display(crtc_state);
846
847	return crtc_state->uapi.async_flip && intel_display_vtd_active(display) &&
848	(DISPLAY_VER(display) == 9 || display->platform.broadwell ||
849	display->platform.haswell);
850	}
851
852	static void intel_encoders_audio_enable(struct intel_atomic_state *state,
853	struct intel_crtc *crtc)
854	{
855	const struct intel_crtc_state *crtc_state =
856	intel_atomic_get_new_crtc_state(state, crtc);
857	const struct drm_connector_state *conn_state;
858	struct drm_connector *conn;
859	int i;
860
861	for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
862	struct intel_encoder *encoder =
863	to_intel_encoder(conn_state->best_encoder);
864
865	if (conn_state->crtc != &crtc->base)
866	continue;
867
868	if (encoder->audio_enable)
869	encoder->audio_enable(encoder, crtc_state, conn_state);
870	}
871	}
872
873	static void intel_encoders_audio_disable(struct intel_atomic_state *state,
874	struct intel_crtc *crtc)
875	{
876	const struct intel_crtc_state *old_crtc_state =
877	intel_atomic_get_old_crtc_state(state, crtc);
878	const struct drm_connector_state *old_conn_state;
879	struct drm_connector *conn;
880	int i;
881
882	for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
883	struct intel_encoder *encoder =
884	to_intel_encoder(old_conn_state->best_encoder);
885
886	if (old_conn_state->crtc != &crtc->base)
887	continue;
888
889	if (encoder->audio_disable)
890	encoder->audio_disable(encoder, old_crtc_state, old_conn_state);
891	}
892	}
893
894	#define is_enabling(feature, old_crtc_state, new_crtc_state) \
895	((!(old_crtc_state)->feature || intel_crtc_needs_modeset(new_crtc_state)) && \
896	(new_crtc_state)->feature)
897	#define is_disabling(feature, old_crtc_state, new_crtc_state) \
898	((old_crtc_state)->feature && \
899	(!(new_crtc_state)->feature || intel_crtc_needs_modeset(new_crtc_state)))
900
901	static bool planes_enabling(const struct intel_crtc_state *old_crtc_state,
902	const struct intel_crtc_state *new_crtc_state)
903	{
904	if (!new_crtc_state->hw.active)
905	return false;
906
907	return is_enabling(active_planes, old_crtc_state, new_crtc_state);
908	}
909
910	static bool planes_disabling(const struct intel_crtc_state *old_crtc_state,
911	const struct intel_crtc_state *new_crtc_state)
912	{
913	if (!old_crtc_state->hw.active)
914	return false;
915
916	return is_disabling(active_planes, old_crtc_state, new_crtc_state);
917	}
918
919	static bool vrr_params_changed(const struct intel_crtc_state *old_crtc_state,
920	const struct intel_crtc_state *new_crtc_state)
921	{
922	return old_crtc_state->vrr.flipline != new_crtc_state->vrr.flipline ||
923	old_crtc_state->vrr.vmin != new_crtc_state->vrr.vmin ||
924	old_crtc_state->vrr.vmax != new_crtc_state->vrr.vmax ||
925	old_crtc_state->vrr.guardband != new_crtc_state->vrr.guardband ||
926	old_crtc_state->vrr.pipeline_full != new_crtc_state->vrr.pipeline_full ||
927	old_crtc_state->vrr.vsync_start != new_crtc_state->vrr.vsync_start ||
928	old_crtc_state->vrr.vsync_end != new_crtc_state->vrr.vsync_end;
929	}
930
931	static bool cmrr_params_changed(const struct intel_crtc_state *old_crtc_state,
932	const struct intel_crtc_state *new_crtc_state)
933	{
934	return old_crtc_state->cmrr.cmrr_m != new_crtc_state->cmrr.cmrr_m ||
935	old_crtc_state->cmrr.cmrr_n != new_crtc_state->cmrr.cmrr_n;
936	}
937
938	static bool intel_crtc_vrr_enabling(struct intel_atomic_state *state,
939	struct intel_crtc *crtc)
940	{
941	const struct intel_crtc_state *old_crtc_state =
942	intel_atomic_get_old_crtc_state(state, crtc);
943	const struct intel_crtc_state *new_crtc_state =
944	intel_atomic_get_new_crtc_state(state, crtc);
945
946	if (!new_crtc_state->hw.active)
947	return false;
948
949	return is_enabling(vrr.enable, old_crtc_state, new_crtc_state) ||
950	(new_crtc_state->vrr.enable &&
951	(new_crtc_state->update_m_n || new_crtc_state->update_lrr ||
952	vrr_params_changed(old_crtc_state, new_crtc_state)));
953	}
954
955	bool intel_crtc_vrr_disabling(struct intel_atomic_state *state,
956	struct intel_crtc *crtc)
957	{
958	const struct intel_crtc_state *old_crtc_state =
959	intel_atomic_get_old_crtc_state(state, crtc);
960	const struct intel_crtc_state *new_crtc_state =
961	intel_atomic_get_new_crtc_state(state, crtc);
962
963	if (!old_crtc_state->hw.active)
964	return false;
965
966	return is_disabling(vrr.enable, old_crtc_state, new_crtc_state) ||
967	(old_crtc_state->vrr.enable &&
968	(new_crtc_state->update_m_n || new_crtc_state->update_lrr ||
969	vrr_params_changed(old_crtc_state, new_crtc_state)));
970	}
971
972	static bool audio_enabling(const struct intel_crtc_state *old_crtc_state,
973	const struct intel_crtc_state *new_crtc_state)
974	{
975	if (!new_crtc_state->hw.active)
976	return false;
977
978	return is_enabling(has_audio, old_crtc_state, new_crtc_state) ||
979	(new_crtc_state->has_audio &&
980	memcmp(p: old_crtc_state->eld, q: new_crtc_state->eld, MAX_ELD_BYTES) != 0);
981	}
982
983	static bool audio_disabling(const struct intel_crtc_state *old_crtc_state,
984	const struct intel_crtc_state *new_crtc_state)
985	{
986	if (!old_crtc_state->hw.active)
987	return false;
988
989	return is_disabling(has_audio, old_crtc_state, new_crtc_state) ||
990	(old_crtc_state->has_audio &&
991	memcmp(p: old_crtc_state->eld, q: new_crtc_state->eld, MAX_ELD_BYTES) != 0);
992	}
993
994	static bool intel_casf_enabling(const struct intel_crtc_state *new_crtc_state,
995	const struct intel_crtc_state *old_crtc_state)
996	{
997	if (!new_crtc_state->hw.active)
998	return false;
999
1000	return is_enabling(hw.casf_params.casf_enable, old_crtc_state, new_crtc_state);
1001	}
1002
1003	static bool intel_casf_disabling(const struct intel_crtc_state *old_crtc_state,
1004	const struct intel_crtc_state *new_crtc_state)
1005	{
1006	if (!new_crtc_state->hw.active)
1007	return false;
1008
1009	return is_disabling(hw.casf_params.casf_enable, old_crtc_state, new_crtc_state);
1010	}
1011
1012	#undef is_disabling
1013	#undef is_enabling
1014
1015	static void intel_post_plane_update(struct intel_atomic_state *state,
1016	struct intel_crtc *crtc)
1017	{
1018	struct intel_display *display = to_intel_display(state);
1019	const struct intel_crtc_state *old_crtc_state =
1020	intel_atomic_get_old_crtc_state(state, crtc);
1021	const struct intel_crtc_state *new_crtc_state =
1022	intel_atomic_get_new_crtc_state(state, crtc);
1023	enum pipe pipe = crtc->pipe;
1024
1025	intel_frontbuffer_flip(display, frontbuffer_bits: new_crtc_state->fb_bits);
1026
1027	if (new_crtc_state->update_wm_post && new_crtc_state->hw.active)
1028	intel_update_watermarks(display);
1029
1030	intel_fbc_post_update(state, crtc);
1031
1032	if (needs_async_flip_vtd_wa(crtc_state: old_crtc_state) &&
1033	!needs_async_flip_vtd_wa(crtc_state: new_crtc_state))
1034	intel_async_flip_vtd_wa(display, pipe, enable: false);
1035
1036	if (needs_nv12_wa(crtc_state: old_crtc_state) &&
1037	!needs_nv12_wa(crtc_state: new_crtc_state))
1038	skl_wa_827(display, pipe, enable: false);
1039
1040	if (needs_scalerclk_wa(crtc_state: old_crtc_state) &&
1041	!needs_scalerclk_wa(crtc_state: new_crtc_state))
1042	icl_wa_scalerclkgating(display, pipe, enable: false);
1043
1044	if (needs_cursorclk_wa(crtc_state: old_crtc_state) &&
1045	!needs_cursorclk_wa(crtc_state: new_crtc_state))
1046	icl_wa_cursorclkgating(display, pipe, enable: false);
1047
1048	if (intel_crtc_needs_color_update(crtc_state: new_crtc_state))
1049	intel_color_post_update(crtc_state: new_crtc_state);
1050
1051	if (audio_enabling(old_crtc_state, new_crtc_state))
1052	intel_encoders_audio_enable(state, crtc);
1053
1054	if (intel_display_wa(display, 14011503117)) {
1055	if (old_crtc_state->pch_pfit.enabled != new_crtc_state->pch_pfit.enabled)
1056	adl_scaler_ecc_unmask(crtc_state: new_crtc_state);
1057	}
1058
1059	intel_alpm_post_plane_update(state, crtc);
1060
1061	intel_psr_post_plane_update(state, crtc);
1062	}
1063
1064	static void intel_post_plane_update_after_readout(struct intel_atomic_state *state,
1065	struct intel_crtc *crtc)
1066	{
1067	const struct intel_crtc_state *new_crtc_state =
1068	intel_atomic_get_new_crtc_state(state, crtc);
1069
1070	/* Must be done after gamma readout due to HSW split gamma vs. IPS w/a */
1071	hsw_ips_post_update(state, crtc);
1072
1073	/*
1074	* Activate DRRS after state readout to avoid
1075	* dp_m_n vs. dp_m2_n2 confusion on BDW+.
1076	*/
1077	intel_drrs_activate(crtc_state: new_crtc_state);
1078	}
1079
1080	static void intel_crtc_enable_flip_done(struct intel_atomic_state *state,
1081	struct intel_crtc *crtc)
1082	{
1083	const struct intel_crtc_state *crtc_state =
1084	intel_atomic_get_new_crtc_state(state, crtc);
1085	u8 update_planes = crtc_state->update_planes;
1086	const struct intel_plane_state __maybe_unused *plane_state;
1087	struct intel_plane *plane;
1088	int i;
1089
1090	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1091	if (plane->pipe == crtc->pipe &&
1092	update_planes & BIT(plane->id))
1093	plane->enable_flip_done(plane);
1094	}
1095	}
1096
1097	static void intel_crtc_disable_flip_done(struct intel_atomic_state *state,
1098	struct intel_crtc *crtc)
1099	{
1100	const struct intel_crtc_state *crtc_state =
1101	intel_atomic_get_new_crtc_state(state, crtc);
1102	u8 update_planes = crtc_state->update_planes;
1103	const struct intel_plane_state __maybe_unused *plane_state;
1104	struct intel_plane *plane;
1105	int i;
1106
1107	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
1108	if (plane->pipe == crtc->pipe &&
1109	update_planes & BIT(plane->id))
1110	plane->disable_flip_done(plane);
1111	}
1112	}
1113
1114	static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state,
1115	struct intel_crtc *crtc)
1116	{
1117	const struct intel_crtc_state *old_crtc_state =
1118	intel_atomic_get_old_crtc_state(state, crtc);
1119	const struct intel_crtc_state *new_crtc_state =
1120	intel_atomic_get_new_crtc_state(state, crtc);
1121	u8 disable_async_flip_planes = old_crtc_state->async_flip_planes &
1122	~new_crtc_state->async_flip_planes;
1123	const struct intel_plane_state *old_plane_state;
1124	struct intel_plane *plane;
1125	bool need_vbl_wait = false;
1126	int i;
1127
1128	for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
1129	if (plane->need_async_flip_toggle_wa &&
1130	plane->pipe == crtc->pipe &&
1131	disable_async_flip_planes & BIT(plane->id)) {
1132	/*
1133	* Apart from the async flip bit we want to
1134	* preserve the old state for the plane.
1135	*/
1136	intel_plane_async_flip(NULL, plane,
1137	crtc_state: old_crtc_state, plane_state: old_plane_state, async_flip: false);
1138	need_vbl_wait = true;
1139	}
1140	}
1141
1142	if (need_vbl_wait)
1143	intel_crtc_wait_for_next_vblank(crtc);
1144	}
1145
1146	static void intel_pre_plane_update(struct intel_atomic_state *state,
1147	struct intel_crtc *crtc)
1148	{
1149	struct intel_display *display = to_intel_display(state);
1150	const struct intel_crtc_state *old_crtc_state =
1151	intel_atomic_get_old_crtc_state(state, crtc);
1152	const struct intel_crtc_state *new_crtc_state =
1153	intel_atomic_get_new_crtc_state(state, crtc);
1154	enum pipe pipe = crtc->pipe;
1155
1156	intel_alpm_pre_plane_update(state, crtc);
1157	intel_psr_pre_plane_update(state, crtc);
1158
1159	if (intel_crtc_vrr_disabling(state, crtc)) {
1160	intel_vrr_disable(old_crtc_state);
1161	intel_crtc_update_active_timings(crtc_state: old_crtc_state, vrr_enable: false);
1162	}
1163
1164	if (audio_disabling(old_crtc_state, new_crtc_state))
1165	intel_encoders_audio_disable(state, crtc);
1166
1167	if (intel_casf_disabling(old_crtc_state, new_crtc_state))
1168	intel_casf_disable(crtc_state: new_crtc_state);
1169
1170	intel_drrs_deactivate(crtc_state: old_crtc_state);
1171
1172	if (hsw_ips_pre_update(state, crtc))
1173	intel_crtc_wait_for_next_vblank(crtc);
1174
1175	if (intel_fbc_pre_update(state, crtc))
1176	intel_crtc_wait_for_next_vblank(crtc);
1177
1178	if (!needs_async_flip_vtd_wa(crtc_state: old_crtc_state) &&
1179	needs_async_flip_vtd_wa(crtc_state: new_crtc_state))
1180	intel_async_flip_vtd_wa(display, pipe, enable: true);
1181
1182	/* Display WA 827 */
1183	if (!needs_nv12_wa(crtc_state: old_crtc_state) &&
1184	needs_nv12_wa(crtc_state: new_crtc_state))
1185	skl_wa_827(display, pipe, enable: true);
1186
1187	/* Wa_2006604312:icl,ehl */
1188	if (!needs_scalerclk_wa(crtc_state: old_crtc_state) &&
1189	needs_scalerclk_wa(crtc_state: new_crtc_state))
1190	icl_wa_scalerclkgating(display, pipe, enable: true);
1191
1192	/* Wa_1604331009:icl,jsl,ehl */
1193	if (!needs_cursorclk_wa(crtc_state: old_crtc_state) &&
1194	needs_cursorclk_wa(crtc_state: new_crtc_state))
1195	icl_wa_cursorclkgating(display, pipe, enable: true);
1196
1197	/*
1198	* Vblank time updates from the shadow to live plane control register
1199	* are blocked if the memory self-refresh mode is active at that
1200	* moment. So to make sure the plane gets truly disabled, disable
1201	* first the self-refresh mode. The self-refresh enable bit in turn
1202	* will be checked/applied by the HW only at the next frame start
1203	* event which is after the vblank start event, so we need to have a
1204	* wait-for-vblank between disabling the plane and the pipe.
1205	*/
1206	if (HAS_GMCH(display) && old_crtc_state->hw.active &&
1207	new_crtc_state->disable_cxsr && intel_set_memory_cxsr(display, enable: false))
1208	intel_crtc_wait_for_next_vblank(crtc);
1209
1210	/*
1211	* IVB workaround: must disable low power watermarks for at least
1212	* one frame before enabling scaling. LP watermarks can be re-enabled
1213	* when scaling is disabled.
1214	*
1215	* WaCxSRDisabledForSpriteScaling:ivb
1216	*/
1217	if (!HAS_GMCH(display) && old_crtc_state->hw.active &&
1218	new_crtc_state->disable_cxsr && ilk_disable_cxsr(display))
1219	intel_crtc_wait_for_next_vblank(crtc);
1220
1221	/*
1222	* If we're doing a modeset we don't need to do any
1223	* pre-vblank watermark programming here.
1224	*/
1225	if (!intel_crtc_needs_modeset(crtc_state: new_crtc_state)) {
1226	/*
1227	* For platforms that support atomic watermarks, program the
1228	* 'intermediate' watermarks immediately. On pre-gen9 platforms, these
1229	* will be the intermediate values that are safe for both pre- and
1230	* post- vblank; when vblank happens, the 'active' values will be set
1231	* to the final 'target' values and we'll do this again to get the
1232	* optimal watermarks. For gen9+ platforms, the values we program here
1233	* will be the final target values which will get automatically latched
1234	* at vblank time; no further programming will be necessary.
1235	*
1236	* If a platform hasn't been transitioned to atomic watermarks yet,
1237	* we'll continue to update watermarks the old way, if flags tell
1238	* us to.
1239	*/
1240	if (!intel_initial_watermarks(state, crtc))
1241	if (new_crtc_state->update_wm_pre)
1242	intel_update_watermarks(display);
1243	}
1244
1245	/*
1246	* Gen2 reports pipe underruns whenever all planes are disabled.
1247	* So disable underrun reporting before all the planes get disabled.
1248	*
1249	* We do this after .initial_watermarks() so that we have a
1250	* chance of catching underruns with the intermediate watermarks
1251	* vs. the old plane configuration.
1252	*/
1253	if (DISPLAY_VER(display) == 2 && planes_disabling(old_crtc_state, new_crtc_state))
1254	intel_set_cpu_fifo_underrun_reporting(display, pipe, enable: false);
1255
1256	/*
1257	* WA for platforms where async address update enable bit
1258	* is double buffered and only latched at start of vblank.
1259	*/
1260	if (old_crtc_state->async_flip_planes & ~new_crtc_state->async_flip_planes)
1261	intel_crtc_async_flip_disable_wa(state, crtc);
1262	}
1263
1264	static void intel_crtc_disable_planes(struct intel_atomic_state *state,
1265	struct intel_crtc *crtc)
1266	{
1267	struct intel_display *display = to_intel_display(state);
1268	const struct intel_crtc_state *new_crtc_state =
1269	intel_atomic_get_new_crtc_state(state, crtc);
1270	unsigned int update_mask = new_crtc_state->update_planes;
1271	const struct intel_plane_state *old_plane_state;
1272	struct intel_plane *plane;
1273	unsigned fb_bits = 0;
1274	int i;
1275
1276	intel_crtc_dpms_overlay_disable(crtc);
1277
1278	for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
1279	if (crtc->pipe != plane->pipe ||
1280	!(update_mask & BIT(plane->id)))
1281	continue;
1282
1283	intel_plane_disable_arm(NULL, plane, crtc_state: new_crtc_state);
1284
1285	if (old_plane_state->uapi.visible)
1286	fb_bits |= plane->frontbuffer_bit;
1287	}
1288
1289	intel_frontbuffer_flip(display, frontbuffer_bits: fb_bits);
1290	}
1291
1292	static void intel_encoders_update_prepare(struct intel_atomic_state *state)
1293	{
1294	struct intel_display *display = to_intel_display(state);
1295	struct intel_crtc_state *new_crtc_state, *old_crtc_state;
1296	struct intel_crtc *crtc;
1297	int i;
1298
1299	/*
1300	* Make sure the DPLL state is up-to-date for fastset TypeC ports after non-blocking commits.
1301	* TODO: Update the DPLL state for all cases in the encoder->update_prepare() hook.
1302	*/
1303	if (display->dpll.mgr) {
1304	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
1305	if (intel_crtc_needs_modeset(crtc_state: new_crtc_state))
1306	continue;
1307
1308	new_crtc_state->intel_dpll = old_crtc_state->intel_dpll;
1309	new_crtc_state->dpll_hw_state = old_crtc_state->dpll_hw_state;
1310	}
1311	}
1312	}
1313
1314	static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state,
1315	struct intel_crtc *crtc)
1316	{
1317	const struct intel_crtc_state *crtc_state =
1318	intel_atomic_get_new_crtc_state(state, crtc);
1319	const struct drm_connector_state *conn_state;
1320	struct drm_connector *conn;
1321	int i;
1322
1323	for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
1324	struct intel_encoder *encoder =
1325	to_intel_encoder(conn_state->best_encoder);
1326
1327	if (conn_state->crtc != &crtc->base)
1328	continue;
1329
1330	if (encoder->pre_pll_enable)
1331	encoder->pre_pll_enable(state, encoder,
1332	crtc_state, conn_state);
1333	}
1334	}
1335
1336	static void intel_encoders_pre_enable(struct intel_atomic_state *state,
1337	struct intel_crtc *crtc)
1338	{
1339	const struct intel_crtc_state *crtc_state =
1340	intel_atomic_get_new_crtc_state(state, crtc);
1341	const struct drm_connector_state *conn_state;
1342	struct drm_connector *conn;
1343	int i;
1344
1345	for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
1346	struct intel_encoder *encoder =
1347	to_intel_encoder(conn_state->best_encoder);
1348
1349	if (conn_state->crtc != &crtc->base)
1350	continue;
1351
1352	if (encoder->pre_enable)
1353	encoder->pre_enable(state, encoder,
1354	crtc_state, conn_state);
1355	}
1356	}
1357
1358	static void intel_encoders_enable(struct intel_atomic_state *state,
1359	struct intel_crtc *crtc)
1360	{
1361	const struct intel_crtc_state *crtc_state =
1362	intel_atomic_get_new_crtc_state(state, crtc);
1363	const struct drm_connector_state *conn_state;
1364	struct drm_connector *conn;
1365	int i;
1366
1367	for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
1368	struct intel_encoder *encoder =
1369	to_intel_encoder(conn_state->best_encoder);
1370
1371	if (conn_state->crtc != &crtc->base)
1372	continue;
1373
1374	if (encoder->enable)
1375	encoder->enable(state, encoder,
1376	crtc_state, conn_state);
1377	intel_opregion_notify_encoder(encoder, enable: true);
1378	}
1379	}
1380
1381	static void intel_encoders_disable(struct intel_atomic_state *state,
1382	struct intel_crtc *crtc)
1383	{
1384	const struct intel_crtc_state *old_crtc_state =
1385	intel_atomic_get_old_crtc_state(state, crtc);
1386	const struct drm_connector_state *old_conn_state;
1387	struct drm_connector *conn;
1388	int i;
1389
1390	for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
1391	struct intel_encoder *encoder =
1392	to_intel_encoder(old_conn_state->best_encoder);
1393
1394	if (old_conn_state->crtc != &crtc->base)
1395	continue;
1396
1397	intel_opregion_notify_encoder(encoder, enable: false);
1398	if (encoder->disable)
1399	encoder->disable(state, encoder,
1400	old_crtc_state, old_conn_state);
1401	}
1402	}
1403
1404	static void intel_encoders_post_disable(struct intel_atomic_state *state,
1405	struct intel_crtc *crtc)
1406	{
1407	const struct intel_crtc_state *old_crtc_state =
1408	intel_atomic_get_old_crtc_state(state, crtc);
1409	const struct drm_connector_state *old_conn_state;
1410	struct drm_connector *conn;
1411	int i;
1412
1413	for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
1414	struct intel_encoder *encoder =
1415	to_intel_encoder(old_conn_state->best_encoder);
1416
1417	if (old_conn_state->crtc != &crtc->base)
1418	continue;
1419
1420	if (encoder->post_disable)
1421	encoder->post_disable(state, encoder,
1422	old_crtc_state, old_conn_state);
1423	}
1424	}
1425
1426	static void intel_encoders_post_pll_disable(struct intel_atomic_state *state,
1427	struct intel_crtc *crtc)
1428	{
1429	const struct intel_crtc_state *old_crtc_state =
1430	intel_atomic_get_old_crtc_state(state, crtc);
1431	const struct drm_connector_state *old_conn_state;
1432	struct drm_connector *conn;
1433	int i;
1434
1435	for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
1436	struct intel_encoder *encoder =
1437	to_intel_encoder(old_conn_state->best_encoder);
1438
1439	if (old_conn_state->crtc != &crtc->base)
1440	continue;
1441
1442	if (encoder->post_pll_disable)
1443	encoder->post_pll_disable(state, encoder,
1444	old_crtc_state, old_conn_state);
1445	}
1446	}
1447
1448	static void intel_encoders_update_pipe(struct intel_atomic_state *state,
1449	struct intel_crtc *crtc)
1450	{
1451	const struct intel_crtc_state *crtc_state =
1452	intel_atomic_get_new_crtc_state(state, crtc);
1453	const struct drm_connector_state *conn_state;
1454	struct drm_connector *conn;
1455	int i;
1456
1457	for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
1458	struct intel_encoder *encoder =
1459	to_intel_encoder(conn_state->best_encoder);
1460
1461	if (conn_state->crtc != &crtc->base)
1462	continue;
1463
1464	if (encoder->update_pipe)
1465	encoder->update_pipe(state, encoder,
1466	crtc_state, conn_state);
1467	}
1468	}
1469
1470	static void ilk_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state)
1471	{
1472	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1473	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1474
1475	if (crtc_state->has_pch_encoder) {
1476	intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1477	m_n: &crtc_state->fdi_m_n);
1478	} else if (intel_crtc_has_dp_encoder(crtc_state)) {
1479	intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1480	m_n: &crtc_state->dp_m_n);
1481	intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
1482	m_n: &crtc_state->dp_m2_n2);
1483	}
1484
1485	intel_set_transcoder_timings(crtc_state);
1486
1487	ilk_set_pipeconf(crtc_state);
1488	}
1489
1490	static void ilk_crtc_enable(struct intel_atomic_state *state,
1491	struct intel_crtc *crtc)
1492	{
1493	struct intel_display *display = to_intel_display(crtc);
1494	const struct intel_crtc_state *new_crtc_state =
1495	intel_atomic_get_new_crtc_state(state, crtc);
1496	enum pipe pipe = crtc->pipe;
1497
1498	if (drm_WARN_ON(display->drm, crtc->active))
1499	return;
1500
1501	/*
1502	* Sometimes spurious CPU pipe underruns happen during FDI
1503	* training, at least with VGA+HDMI cloning. Suppress them.
1504	*
1505	* On ILK we get an occasional spurious CPU pipe underruns
1506	* between eDP port A enable and vdd enable. Also PCH port
1507	* enable seems to result in the occasional CPU pipe underrun.
1508	*
1509	* Spurious PCH underruns also occur during PCH enabling.
1510	*/
1511	intel_set_cpu_fifo_underrun_reporting(display, pipe, enable: false);
1512	intel_set_pch_fifo_underrun_reporting(display, pch_transcoder: pipe, enable: false);
1513
1514	ilk_configure_cpu_transcoder(crtc_state: new_crtc_state);
1515
1516	intel_set_pipe_src_size(crtc_state: new_crtc_state);
1517
1518	crtc->active = true;
1519
1520	intel_encoders_pre_enable(state, crtc);
1521
1522	if (new_crtc_state->has_pch_encoder) {
1523	ilk_pch_pre_enable(state, crtc);
1524	} else {
1525	assert_fdi_tx_disabled(display, pipe);
1526	assert_fdi_rx_disabled(display, pipe);
1527	}
1528
1529	ilk_pfit_enable(crtc_state: new_crtc_state);
1530
1531	/*
1532	* On ILK+ LUT must be loaded before the pipe is running but with
1533	* clocks enabled
1534	*/
1535	intel_color_modeset(crtc_state: new_crtc_state);
1536
1537	intel_initial_watermarks(state, crtc);
1538	intel_enable_transcoder(new_crtc_state);
1539
1540	if (new_crtc_state->has_pch_encoder)
1541	ilk_pch_enable(state, crtc);
1542
1543	intel_crtc_vblank_on(crtc_state: new_crtc_state);
1544
1545	intel_encoders_enable(state, crtc);
1546
1547	if (HAS_PCH_CPT(display))
1548	intel_wait_for_pipe_scanline_moving(crtc);
1549
1550	/*
1551	* Must wait for vblank to avoid spurious PCH FIFO underruns.
1552	* And a second vblank wait is needed at least on ILK with
1553	* some interlaced HDMI modes. Let's do the double wait always
1554	* in case there are more corner cases we don't know about.
1555	*/
1556	if (new_crtc_state->has_pch_encoder) {
1557	intel_crtc_wait_for_next_vblank(crtc);
1558	intel_crtc_wait_for_next_vblank(crtc);
1559	}
1560	intel_set_cpu_fifo_underrun_reporting(display, pipe, enable: true);
1561	intel_set_pch_fifo_underrun_reporting(display, pch_transcoder: pipe, enable: true);
1562	}
1563
1564	/* Display WA #1180: WaDisableScalarClockGating: glk */
1565	static bool glk_need_scaler_clock_gating_wa(const struct intel_crtc_state *crtc_state)
1566	{
1567	struct intel_display *display = to_intel_display(crtc_state);
1568
1569	return DISPLAY_VER(display) == 10 && crtc_state->pch_pfit.enabled;
1570	}
1571
1572	static void glk_pipe_scaler_clock_gating_wa(struct intel_crtc *crtc, bool enable)
1573	{
1574	struct intel_display *display = to_intel_display(crtc);
1575	u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS;
1576
1577	intel_de_rmw(display, CLKGATE_DIS_PSL(crtc->pipe),
1578	clear: mask, set: enable ? mask : 0);
1579	}
1580
1581	static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state)
1582	{
1583	struct intel_display *display = to_intel_display(crtc_state);
1584	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1585
1586	intel_de_write(display, WM_LINETIME(crtc->pipe),
1587	HSW_LINETIME(crtc_state->linetime) |
1588	HSW_IPS_LINETIME(crtc_state->ips_linetime));
1589	}
1590
1591	static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
1592	{
1593	struct intel_display *display = to_intel_display(crtc_state);
1594
1595	intel_de_rmw(display, CHICKEN_TRANS(display, crtc_state->cpu_transcoder),
1596	HSW_FRAME_START_DELAY_MASK,
1597	HSW_FRAME_START_DELAY(crtc_state->framestart_delay - 1));
1598	}
1599
1600	static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state)
1601	{
1602	struct intel_display *display = to_intel_display(crtc_state);
1603	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1604	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1605
1606	if (crtc_state->has_pch_encoder) {
1607	intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1608	m_n: &crtc_state->fdi_m_n);
1609	} else if (intel_crtc_has_dp_encoder(crtc_state)) {
1610	intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1611	m_n: &crtc_state->dp_m_n);
1612	intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
1613	m_n: &crtc_state->dp_m2_n2);
1614	}
1615
1616	intel_set_transcoder_timings(crtc_state);
1617	intel_vrr_set_transcoder_timings(crtc_state);
1618
1619	if (cpu_transcoder != TRANSCODER_EDP)
1620	intel_de_write(display, TRANS_MULT(display, cpu_transcoder),
1621	val: crtc_state->pixel_multiplier - 1);
1622
1623	hsw_set_frame_start_delay(crtc_state);
1624
1625	hsw_set_transconf(crtc_state);
1626	}
1627
1628	static void hsw_crtc_enable(struct intel_atomic_state *state,
1629	struct intel_crtc *crtc)
1630	{
1631	struct intel_display *display = to_intel_display(state);
1632	const struct intel_crtc_state *new_crtc_state =
1633	intel_atomic_get_new_crtc_state(state, crtc);
1634	enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
1635	struct intel_crtc *pipe_crtc;
1636	int i;
1637
1638	if (drm_WARN_ON(display->drm, crtc->active))
1639	return;
1640	for_each_pipe_crtc_modeset_enable(display, pipe_crtc, new_crtc_state, i) {
1641	const struct intel_crtc_state *new_pipe_crtc_state =
1642	intel_atomic_get_new_crtc_state(state, crtc: pipe_crtc);
1643
1644	intel_dmc_enable_pipe(crtc_state: new_pipe_crtc_state);
1645	}
1646
1647	intel_encoders_pre_pll_enable(state, crtc);
1648
1649	if (new_crtc_state->intel_dpll)
1650	intel_dpll_enable(crtc_state: new_crtc_state);
1651
1652	intel_encoders_pre_enable(state, crtc);
1653
1654	for_each_pipe_crtc_modeset_enable(display, pipe_crtc, new_crtc_state, i) {
1655	const struct intel_crtc_state *pipe_crtc_state =
1656	intel_atomic_get_new_crtc_state(state, crtc: pipe_crtc);
1657
1658	intel_dsc_enable(crtc_state: pipe_crtc_state);
1659
1660	if (HAS_UNCOMPRESSED_JOINER(display))
1661	intel_uncompressed_joiner_enable(crtc_state: pipe_crtc_state);
1662
1663	intel_set_pipe_src_size(crtc_state: pipe_crtc_state);
1664
1665	if (DISPLAY_VER(display) >= 9 || display->platform.broadwell)
1666	bdw_set_pipe_misc(NULL, crtc_state: pipe_crtc_state);
1667	}
1668
1669	if (!transcoder_is_dsi(transcoder: cpu_transcoder))
1670	hsw_configure_cpu_transcoder(crtc_state: new_crtc_state);
1671
1672	for_each_pipe_crtc_modeset_enable(display, pipe_crtc, new_crtc_state, i) {
1673	const struct intel_crtc_state *pipe_crtc_state =
1674	intel_atomic_get_new_crtc_state(state, crtc: pipe_crtc);
1675
1676	pipe_crtc->active = true;
1677
1678	if (glk_need_scaler_clock_gating_wa(crtc_state: pipe_crtc_state))
1679	glk_pipe_scaler_clock_gating_wa(crtc: pipe_crtc, enable: true);
1680
1681	if (DISPLAY_VER(display) >= 9)
1682	skl_pfit_enable(crtc_state: pipe_crtc_state);
1683	else
1684	ilk_pfit_enable(crtc_state: pipe_crtc_state);
1685
1686	/*
1687	* On ILK+ LUT must be loaded before the pipe is running but with
1688	* clocks enabled
1689	*/
1690	intel_color_modeset(crtc_state: pipe_crtc_state);
1691
1692	hsw_set_linetime_wm(crtc_state: pipe_crtc_state);
1693
1694	if (DISPLAY_VER(display) >= 11)
1695	icl_set_pipe_chicken(crtc_state: pipe_crtc_state);
1696
1697	intel_initial_watermarks(state, crtc: pipe_crtc);
1698	}
1699
1700	intel_encoders_enable(state, crtc);
1701
1702	for_each_pipe_crtc_modeset_enable(display, pipe_crtc, new_crtc_state, i) {
1703	const struct intel_crtc_state *pipe_crtc_state =
1704	intel_atomic_get_new_crtc_state(state, crtc: pipe_crtc);
1705	enum pipe hsw_workaround_pipe;
1706
1707	if (glk_need_scaler_clock_gating_wa(crtc_state: pipe_crtc_state)) {
1708	intel_crtc_wait_for_next_vblank(crtc: pipe_crtc);
1709	glk_pipe_scaler_clock_gating_wa(crtc: pipe_crtc, enable: false);
1710	}
1711
1712	/*
1713	* If we change the relative order between pipe/planes
1714	* enabling, we need to change the workaround.
1715	*/
1716	hsw_workaround_pipe = pipe_crtc_state->hsw_workaround_pipe;
1717	if (display->platform.haswell && hsw_workaround_pipe != INVALID_PIPE) {
1718	struct intel_crtc *wa_crtc =
1719	intel_crtc_for_pipe(display, pipe: hsw_workaround_pipe);
1720
1721	intel_crtc_wait_for_next_vblank(crtc: wa_crtc);
1722	intel_crtc_wait_for_next_vblank(crtc: wa_crtc);
1723	}
1724	}
1725	}
1726
1727	static void ilk_crtc_disable(struct intel_atomic_state *state,
1728	struct intel_crtc *crtc)
1729	{
1730	struct intel_display *display = to_intel_display(crtc);
1731	const struct intel_crtc_state *old_crtc_state =
1732	intel_atomic_get_old_crtc_state(state, crtc);
1733	enum pipe pipe = crtc->pipe;
1734
1735	/*
1736	* Sometimes spurious CPU pipe underruns happen when the
1737	* pipe is already disabled, but FDI RX/TX is still enabled.
1738	* Happens at least with VGA+HDMI cloning. Suppress them.
1739	*/
1740	intel_set_cpu_fifo_underrun_reporting(display, pipe, enable: false);
1741	intel_set_pch_fifo_underrun_reporting(display, pch_transcoder: pipe, enable: false);
1742
1743	intel_encoders_disable(state, crtc);
1744
1745	intel_crtc_vblank_off(crtc_state: old_crtc_state);
1746
1747	intel_disable_transcoder(old_crtc_state);
1748
1749	ilk_pfit_disable(old_crtc_state);
1750
1751	if (old_crtc_state->has_pch_encoder)
1752	ilk_pch_disable(state, crtc);
1753
1754	intel_encoders_post_disable(state, crtc);
1755
1756	if (old_crtc_state->has_pch_encoder)
1757	ilk_pch_post_disable(state, crtc);
1758
1759	intel_set_cpu_fifo_underrun_reporting(display, pipe, enable: true);
1760	intel_set_pch_fifo_underrun_reporting(display, pch_transcoder: pipe, enable: true);
1761	}
1762
1763	static void hsw_crtc_disable(struct intel_atomic_state *state,
1764	struct intel_crtc *crtc)
1765	{
1766	struct intel_display *display = to_intel_display(state);
1767	const struct intel_crtc_state *old_crtc_state =
1768	intel_atomic_get_old_crtc_state(state, crtc);
1769	struct intel_crtc *pipe_crtc;
1770	int i;
1771
1772	/*
1773	* FIXME collapse everything to one hook.
1774	* Need care with mst->ddi interactions.
1775	*/
1776	intel_encoders_disable(state, crtc);
1777	intel_encoders_post_disable(state, crtc);
1778
1779	intel_dpll_disable(crtc_state: old_crtc_state);
1780
1781	intel_encoders_post_pll_disable(state, crtc);
1782
1783	for_each_pipe_crtc_modeset_disable(display, pipe_crtc, old_crtc_state, i) {
1784	const struct intel_crtc_state *old_pipe_crtc_state =
1785	intel_atomic_get_old_crtc_state(state, crtc: pipe_crtc);
1786
1787	intel_dmc_disable_pipe(crtc_state: old_pipe_crtc_state);
1788	}
1789	}
1790
1791	/* Prefer intel_encoder_is_combo() */
1792	bool intel_phy_is_combo(struct intel_display *display, enum phy phy)
1793	{
1794	if (phy == PHY_NONE)
1795	return false;
1796	else if (display->platform.alderlake_s)
1797	return phy <= PHY_E;
1798	else if (display->platform.dg1 || display->platform.rocketlake)
1799	return phy <= PHY_D;
1800	else if (display->platform.jasperlake || display->platform.elkhartlake)
1801	return phy <= PHY_C;
1802	else if (display->platform.alderlake_p || IS_DISPLAY_VER(display, 11, 12))
1803	return phy <= PHY_B;
1804	else
1805	/*
1806	* DG2 outputs labelled as "combo PHY" in the bspec use
1807	* SNPS PHYs with completely different programming,
1808	* hence we always return false here.
1809	*/
1810	return false;
1811	}
1812
1813	/* Prefer intel_encoder_is_tc() */
1814	bool intel_phy_is_tc(struct intel_display *display, enum phy phy)
1815	{
1816	/*
1817	* Discrete GPU phy's are not attached to FIA's to support TC
1818	* subsystem Legacy or non-legacy, and only support native DP/HDMI
1819	*/
1820	if (display->platform.dgfx)
1821	return false;
1822
1823	if (DISPLAY_VER(display) >= 13)
1824	return phy >= PHY_F && phy <= PHY_I;
1825	else if (display->platform.tigerlake)
1826	return phy >= PHY_D && phy <= PHY_I;
1827	else if (display->platform.icelake)
1828	return phy >= PHY_C && phy <= PHY_F;
1829
1830	return false;
1831	}
1832
1833	/* Prefer intel_encoder_is_snps() */
1834	bool intel_phy_is_snps(struct intel_display *display, enum phy phy)
1835	{
1836	/*
1837	* For DG2, and for DG2 only, all four "combo" ports and the TC1 port
1838	* (PHY E) use Synopsis PHYs. See intel_phy_is_tc().
1839	*/
1840	return display->platform.dg2 && phy > PHY_NONE && phy <= PHY_E;
1841	}
1842
1843	/* Prefer intel_encoder_to_phy() */
1844	enum phy intel_port_to_phy(struct intel_display *display, enum port port)
1845	{
1846	if (DISPLAY_VER(display) >= 13 && port >= PORT_D_XELPD)
1847	return PHY_D + port - PORT_D_XELPD;
1848	else if (DISPLAY_VER(display) >= 13 && port >= PORT_TC1)
1849	return PHY_F + port - PORT_TC1;
1850	else if (display->platform.alderlake_s && port >= PORT_TC1)
1851	return PHY_B + port - PORT_TC1;
1852	else if ((display->platform.dg1 || display->platform.rocketlake) && port >= PORT_TC1)
1853	return PHY_C + port - PORT_TC1;
1854	else if ((display->platform.jasperlake || display->platform.elkhartlake) &&
1855	port == PORT_D)
1856	return PHY_A;
1857
1858	return PHY_A + port - PORT_A;
1859	}
1860
1861	/* Prefer intel_encoder_to_tc() */
1862	enum tc_port intel_port_to_tc(struct intel_display *display, enum port port)
1863	{
1864	if (!intel_phy_is_tc(display, phy: intel_port_to_phy(display, port)))
1865	return TC_PORT_NONE;
1866
1867	if (DISPLAY_VER(display) >= 12)
1868	return TC_PORT_1 + port - PORT_TC1;
1869	else
1870	return TC_PORT_1 + port - PORT_C;
1871	}
1872
1873	enum phy intel_encoder_to_phy(struct intel_encoder *encoder)
1874	{
1875	struct intel_display *display = to_intel_display(encoder);
1876
1877	return intel_port_to_phy(display, port: encoder->port);
1878	}
1879
1880	bool intel_encoder_is_combo(struct intel_encoder *encoder)
1881	{
1882	struct intel_display *display = to_intel_display(encoder);
1883
1884	return intel_phy_is_combo(display, phy: intel_encoder_to_phy(encoder));
1885	}
1886
1887	bool intel_encoder_is_snps(struct intel_encoder *encoder)
1888	{
1889	struct intel_display *display = to_intel_display(encoder);
1890
1891	return intel_phy_is_snps(display, phy: intel_encoder_to_phy(encoder));
1892	}
1893
1894	bool intel_encoder_is_tc(struct intel_encoder *encoder)
1895	{
1896	struct intel_display *display = to_intel_display(encoder);
1897
1898	return intel_phy_is_tc(display, phy: intel_encoder_to_phy(encoder));
1899	}
1900
1901	enum tc_port intel_encoder_to_tc(struct intel_encoder *encoder)
1902	{
1903	struct intel_display *display = to_intel_display(encoder);
1904
1905	return intel_port_to_tc(display, port: encoder->port);
1906	}
1907
1908	enum intel_display_power_domain
1909	intel_aux_power_domain(struct intel_digital_port *dig_port)
1910	{
1911	struct intel_display *display = to_intel_display(dig_port);
1912
1913	if (intel_tc_port_in_tbt_alt_mode(dig_port))
1914	return intel_display_power_tbt_aux_domain(display, aux_ch: dig_port->aux_ch);
1915
1916	return intel_display_power_legacy_aux_domain(display, aux_ch: dig_port->aux_ch);
1917	}
1918
1919	static void get_crtc_power_domains(struct intel_crtc_state *crtc_state,
1920	struct intel_power_domain_mask *mask)
1921	{
1922	struct intel_display *display = to_intel_display(crtc_state);
1923	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1924	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1925	struct drm_encoder *encoder;
1926	enum pipe pipe = crtc->pipe;
1927
1928	bitmap_zero(dst: mask->bits, nbits: POWER_DOMAIN_NUM);
1929
1930	if (!crtc_state->hw.active)
1931	return;
1932
1933	set_bit(POWER_DOMAIN_PIPE(pipe), addr: mask->bits);
1934	set_bit(POWER_DOMAIN_TRANSCODER(cpu_transcoder), addr: mask->bits);
1935	if (crtc_state->pch_pfit.enabled ||
1936	crtc_state->pch_pfit.force_thru)
1937	set_bit(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe), addr: mask->bits);
1938
1939	drm_for_each_encoder_mask(encoder, display->drm,
1940	crtc_state->uapi.encoder_mask) {
1941	struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
1942
1943	set_bit(nr: intel_encoder->power_domain, addr: mask->bits);
1944	}
1945
1946	if (HAS_DDI(display) && crtc_state->has_audio)
1947	set_bit(nr: POWER_DOMAIN_AUDIO_MMIO, addr: mask->bits);
1948
1949	if (crtc_state->intel_dpll)
1950	set_bit(nr: POWER_DOMAIN_DISPLAY_CORE, addr: mask->bits);
1951
1952	if (crtc_state->dsc.compression_enable)
1953	set_bit(nr: intel_dsc_power_domain(crtc, cpu_transcoder), addr: mask->bits);
1954	}
1955
1956	void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state,
1957	struct intel_power_domain_mask *old_domains)
1958	{
1959	struct intel_display *display = to_intel_display(crtc_state);
1960	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1961	enum intel_display_power_domain domain;
1962	struct intel_power_domain_mask domains, new_domains;
1963
1964	get_crtc_power_domains(crtc_state, mask: &domains);
1965
1966	bitmap_andnot(dst: new_domains.bits,
1967	src1: domains.bits,
1968	src2: crtc->enabled_power_domains.mask.bits,
1969	nbits: POWER_DOMAIN_NUM);
1970	bitmap_andnot(dst: old_domains->bits,
1971	src1: crtc->enabled_power_domains.mask.bits,
1972	src2: domains.bits,
1973	nbits: POWER_DOMAIN_NUM);
1974
1975	for_each_power_domain(domain, &new_domains)
1976	intel_display_power_get_in_set(display,
1977	power_domain_set: &crtc->enabled_power_domains,
1978	domain);
1979	}
1980
1981	void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc,
1982	struct intel_power_domain_mask *domains)
1983	{
1984	struct intel_display *display = to_intel_display(crtc);
1985
1986	intel_display_power_put_mask_in_set(display,
1987	power_domain_set: &crtc->enabled_power_domains,
1988	mask: domains);
1989	}
1990
1991	static void i9xx_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state)
1992	{
1993	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1994	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1995
1996	if (intel_crtc_has_dp_encoder(crtc_state)) {
1997	intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1998	m_n: &crtc_state->dp_m_n);
1999	intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
2000	m_n: &crtc_state->dp_m2_n2);
2001	}
2002
2003	intel_set_transcoder_timings(crtc_state);
2004
2005	i9xx_set_pipeconf(crtc_state);
2006	}
2007
2008	static void valleyview_crtc_enable(struct intel_atomic_state *state,
2009	struct intel_crtc *crtc)
2010	{
2011	struct intel_display *display = to_intel_display(crtc);
2012	const struct intel_crtc_state *new_crtc_state =
2013	intel_atomic_get_new_crtc_state(state, crtc);
2014	enum pipe pipe = crtc->pipe;
2015
2016	if (drm_WARN_ON(display->drm, crtc->active))
2017	return;
2018
2019	i9xx_configure_cpu_transcoder(crtc_state: new_crtc_state);
2020
2021	intel_set_pipe_src_size(crtc_state: new_crtc_state);
2022
2023	intel_de_write(display, VLV_PIPE_MSA_MISC(display, pipe), val: 0);
2024
2025	if (display->platform.cherryview && pipe == PIPE_B) {
2026	intel_de_write(display, CHV_BLEND(display, pipe),
2027	CHV_BLEND_LEGACY);
2028	intel_de_write(display, CHV_CANVAS(display, pipe), val: 0);
2029	}
2030
2031	crtc->active = true;
2032
2033	intel_set_cpu_fifo_underrun_reporting(display, pipe, enable: true);
2034
2035	intel_encoders_pre_pll_enable(state, crtc);
2036
2037	if (display->platform.cherryview)
2038	chv_enable_pll(crtc_state: new_crtc_state);
2039	else
2040	vlv_enable_pll(crtc_state: new_crtc_state);
2041
2042	intel_encoders_pre_enable(state, crtc);
2043
2044	i9xx_pfit_enable(crtc_state: new_crtc_state);
2045
2046	intel_color_modeset(crtc_state: new_crtc_state);
2047
2048	intel_initial_watermarks(state, crtc);
2049	intel_enable_transcoder(new_crtc_state);
2050
2051	intel_crtc_vblank_on(crtc_state: new_crtc_state);
2052
2053	intel_encoders_enable(state, crtc);
2054	}
2055
2056	static void i9xx_crtc_enable(struct intel_atomic_state *state,
2057	struct intel_crtc *crtc)
2058	{
2059	struct intel_display *display = to_intel_display(crtc);
2060	const struct intel_crtc_state *new_crtc_state =
2061	intel_atomic_get_new_crtc_state(state, crtc);
2062	enum pipe pipe = crtc->pipe;
2063
2064	if (drm_WARN_ON(display->drm, crtc->active))
2065	return;
2066
2067	i9xx_configure_cpu_transcoder(crtc_state: new_crtc_state);
2068
2069	intel_set_pipe_src_size(crtc_state: new_crtc_state);
2070
2071	crtc->active = true;
2072
2073	if (DISPLAY_VER(display) != 2)
2074	intel_set_cpu_fifo_underrun_reporting(display, pipe, enable: true);
2075
2076	intel_encoders_pre_enable(state, crtc);
2077
2078	i9xx_enable_pll(crtc_state: new_crtc_state);
2079
2080	i9xx_pfit_enable(crtc_state: new_crtc_state);
2081
2082	intel_color_modeset(crtc_state: new_crtc_state);
2083
2084	if (!intel_initial_watermarks(state, crtc))
2085	intel_update_watermarks(display);
2086	intel_enable_transcoder(new_crtc_state);
2087
2088	intel_crtc_vblank_on(crtc_state: new_crtc_state);
2089
2090	intel_encoders_enable(state, crtc);
2091
2092	/* prevents spurious underruns */
2093	if (DISPLAY_VER(display) == 2)
2094	intel_crtc_wait_for_next_vblank(crtc);
2095	}
2096
2097	static void i9xx_crtc_disable(struct intel_atomic_state *state,
2098	struct intel_crtc *crtc)
2099	{
2100	struct intel_display *display = to_intel_display(state);
2101	struct intel_crtc_state *old_crtc_state =
2102	intel_atomic_get_old_crtc_state(state, crtc);
2103	enum pipe pipe = crtc->pipe;
2104
2105	/*
2106	* On gen2 planes are double buffered but the pipe isn't, so we must
2107	* wait for planes to fully turn off before disabling the pipe.
2108	*/
2109	if (DISPLAY_VER(display) == 2)
2110	intel_crtc_wait_for_next_vblank(crtc);
2111
2112	intel_encoders_disable(state, crtc);
2113
2114	intel_crtc_vblank_off(crtc_state: old_crtc_state);
2115
2116	intel_disable_transcoder(old_crtc_state);
2117
2118	i9xx_pfit_disable(old_crtc_state);
2119
2120	intel_encoders_post_disable(state, crtc);
2121
2122	if (!intel_crtc_has_type(crtc_state: old_crtc_state, type: INTEL_OUTPUT_DSI)) {
2123	if (display->platform.cherryview)
2124	chv_disable_pll(display, pipe);
2125	else if (display->platform.valleyview)
2126	vlv_disable_pll(display, pipe);
2127	else
2128	i9xx_disable_pll(crtc_state: old_crtc_state);
2129	}
2130
2131	intel_encoders_post_pll_disable(state, crtc);
2132
2133	if (DISPLAY_VER(display) != 2)
2134	intel_set_cpu_fifo_underrun_reporting(display, pipe, enable: false);
2135
2136	if (!display->funcs.wm->initial_watermarks)
2137	intel_update_watermarks(display);
2138
2139	/* clock the pipe down to 640x480@60 to potentially save power */
2140	if (display->platform.i830)
2141	i830_enable_pipe(display, pipe);
2142	}
2143
2144	void intel_encoder_destroy(struct drm_encoder *encoder)
2145	{
2146	struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
2147
2148	drm_encoder_cleanup(encoder);
2149	kfree(objp: intel_encoder);
2150	}
2151
2152	static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
2153	{
2154	struct intel_display *display = to_intel_display(crtc);
2155
2156	/* GDG double wide on either pipe, otherwise pipe A only */
2157	return HAS_DOUBLE_WIDE(display) &&
2158	(crtc->pipe == PIPE_A || display->platform.i915g);
2159	}
2160
2161	static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
2162	{
2163	u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock;
2164	struct drm_rect src;
2165
2166	/*
2167	* We only use IF-ID interlacing. If we ever use
2168	* PF-ID we'll need to adjust the pixel_rate here.
2169	*/
2170
2171	if (!crtc_state->pch_pfit.enabled)
2172	return pixel_rate;
2173
2174	drm_rect_init(r: &src, x: 0, y: 0,
2175	width: drm_rect_width(r: &crtc_state->pipe_src) << 16,
2176	height: drm_rect_height(r: &crtc_state->pipe_src) << 16);
2177
2178	return intel_adjusted_rate(src: &src, dst: &crtc_state->pch_pfit.dst,
2179	rate: pixel_rate);
2180	}
2181
2182	static void intel_mode_from_crtc_timings(struct drm_display_mode *mode,
2183	const struct drm_display_mode *timings)
2184	{
2185	mode->hdisplay = timings->crtc_hdisplay;
2186	mode->htotal = timings->crtc_htotal;
2187	mode->hsync_start = timings->crtc_hsync_start;
2188	mode->hsync_end = timings->crtc_hsync_end;
2189
2190	mode->vdisplay = timings->crtc_vdisplay;
2191	mode->vtotal = timings->crtc_vtotal;
2192	mode->vsync_start = timings->crtc_vsync_start;
2193	mode->vsync_end = timings->crtc_vsync_end;
2194
2195	mode->flags = timings->flags;
2196	mode->type = DRM_MODE_TYPE_DRIVER;
2197
2198	mode->clock = timings->crtc_clock;
2199
2200	drm_mode_set_name(mode);
2201	}
2202
2203	static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
2204	{
2205	struct intel_display *display = to_intel_display(crtc_state);
2206
2207	if (HAS_GMCH(display))
2208	/* FIXME calculate proper pipe pixel rate for GMCH pfit */
2209	crtc_state->pixel_rate =
2210	crtc_state->hw.pipe_mode.crtc_clock;
2211	else
2212	crtc_state->pixel_rate =
2213	ilk_pipe_pixel_rate(crtc_state);
2214	}
2215
2216	static void intel_joiner_adjust_timings(const struct intel_crtc_state *crtc_state,
2217	struct drm_display_mode *mode)
2218	{
2219	int num_pipes = intel_crtc_num_joined_pipes(crtc_state);
2220
2221	if (num_pipes == 1)
2222	return;
2223
2224	mode->crtc_clock /= num_pipes;
2225	mode->crtc_hdisplay /= num_pipes;
2226	mode->crtc_hblank_start /= num_pipes;
2227	mode->crtc_hblank_end /= num_pipes;
2228	mode->crtc_hsync_start /= num_pipes;
2229	mode->crtc_hsync_end /= num_pipes;
2230	mode->crtc_htotal /= num_pipes;
2231	}
2232
2233	static void intel_splitter_adjust_timings(const struct intel_crtc_state *crtc_state,
2234	struct drm_display_mode *mode)
2235	{
2236	int overlap = crtc_state->splitter.pixel_overlap;
2237	int n = crtc_state->splitter.link_count;
2238
2239	if (!crtc_state->splitter.enable)
2240	return;
2241
2242	/*
2243	* eDP MSO uses segment timings from EDID for transcoder
2244	* timings, but full mode for everything else.
2245	*
2246	* h_full = (h_segment - pixel_overlap) * link_count
2247	*/
2248	mode->crtc_hdisplay = (mode->crtc_hdisplay - overlap) * n;
2249	mode->crtc_hblank_start = (mode->crtc_hblank_start - overlap) * n;
2250	mode->crtc_hblank_end = (mode->crtc_hblank_end - overlap) * n;
2251	mode->crtc_hsync_start = (mode->crtc_hsync_start - overlap) * n;
2252	mode->crtc_hsync_end = (mode->crtc_hsync_end - overlap) * n;
2253	mode->crtc_htotal = (mode->crtc_htotal - overlap) * n;
2254	mode->crtc_clock *= n;
2255	}
2256
2257	static void intel_crtc_readout_derived_state(struct intel_crtc_state *crtc_state)
2258	{
2259	struct drm_display_mode *mode = &crtc_state->hw.mode;
2260	struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
2261	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2262
2263	/*
2264	* Start with the adjusted_mode crtc timings, which
2265	* have been filled with the transcoder timings.
2266	*/
2267	drm_mode_copy(dst: pipe_mode, src: adjusted_mode);
2268
2269	/* Expand MSO per-segment transcoder timings to full */
2270	intel_splitter_adjust_timings(crtc_state, mode: pipe_mode);
2271
2272	/*
2273	* We want the full numbers in adjusted_mode normal timings,
2274	* adjusted_mode crtc timings are left with the raw transcoder
2275	* timings.
2276	*/
2277	intel_mode_from_crtc_timings(mode: adjusted_mode, timings: pipe_mode);
2278
2279	/* Populate the "user" mode with full numbers */
2280	drm_mode_copy(dst: mode, src: pipe_mode);
2281	intel_mode_from_crtc_timings(mode, timings: mode);
2282	mode->hdisplay = drm_rect_width(r: &crtc_state->pipe_src) *
2283	intel_crtc_num_joined_pipes(crtc_state);
2284	mode->vdisplay = drm_rect_height(r: &crtc_state->pipe_src);
2285
2286	/* Derive per-pipe timings in case joiner is used */
2287	intel_joiner_adjust_timings(crtc_state, mode: pipe_mode);
2288	intel_mode_from_crtc_timings(mode: pipe_mode, timings: pipe_mode);
2289
2290	intel_crtc_compute_pixel_rate(crtc_state);
2291	}
2292
2293	void intel_encoder_get_config(struct intel_encoder *encoder,
2294	struct intel_crtc_state *crtc_state)
2295	{
2296	encoder->get_config(encoder, crtc_state);
2297
2298	intel_crtc_readout_derived_state(crtc_state);
2299	}
2300
2301	static void intel_joiner_compute_pipe_src(struct intel_crtc_state *crtc_state)
2302	{
2303	int num_pipes = intel_crtc_num_joined_pipes(crtc_state);
2304	int width, height;
2305
2306	if (num_pipes == 1)
2307	return;
2308
2309	width = drm_rect_width(r: &crtc_state->pipe_src);
2310	height = drm_rect_height(r: &crtc_state->pipe_src);
2311
2312	drm_rect_init(r: &crtc_state->pipe_src, x: 0, y: 0,
2313	width: width / num_pipes, height);
2314	}
2315
2316	static int intel_crtc_compute_pipe_src(struct intel_crtc_state *crtc_state)
2317	{
2318	struct intel_display *display = to_intel_display(crtc_state);
2319	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2320
2321	intel_joiner_compute_pipe_src(crtc_state);
2322
2323	/*
2324	* Pipe horizontal size must be even in:
2325	* - DVO ganged mode
2326	* - LVDS dual channel mode
2327	* - Double wide pipe
2328	*/
2329	if (drm_rect_width(r: &crtc_state->pipe_src) & 1) {
2330	if (crtc_state->double_wide) {
2331	drm_dbg_kms(display->drm,
2332	"[CRTC:%d:%s] Odd pipe source width not supported with double wide pipe\n",
2333	crtc->base.base.id, crtc->base.name);
2334	return -EINVAL;
2335	}
2336
2337	if (intel_crtc_has_type(crtc_state, type: INTEL_OUTPUT_LVDS) &&
2338	intel_is_dual_link_lvds(display)) {
2339	drm_dbg_kms(display->drm,
2340	"[CRTC:%d:%s] Odd pipe source width not supported with dual link LVDS\n",
2341	crtc->base.base.id, crtc->base.name);
2342	return -EINVAL;
2343	}
2344	}
2345
2346	return 0;
2347	}
2348
2349	static int intel_crtc_compute_pipe_mode(struct intel_crtc_state *crtc_state)
2350	{
2351	struct intel_display *display = to_intel_display(crtc_state);
2352	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2353	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2354	struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
2355	int clock_limit = display->cdclk.max_dotclk_freq;
2356
2357	/*
2358	* Start with the adjusted_mode crtc timings, which
2359	* have been filled with the transcoder timings.
2360	*/
2361	drm_mode_copy(dst: pipe_mode, src: adjusted_mode);
2362
2363	/* Expand MSO per-segment transcoder timings to full */
2364	intel_splitter_adjust_timings(crtc_state, mode: pipe_mode);
2365
2366	/* Derive per-pipe timings in case joiner is used */
2367	intel_joiner_adjust_timings(crtc_state, mode: pipe_mode);
2368	intel_mode_from_crtc_timings(mode: pipe_mode, timings: pipe_mode);
2369
2370	if (DISPLAY_VER(display) < 4) {
2371	clock_limit = display->cdclk.max_cdclk_freq * 9 / 10;
2372
2373	/*
2374	* Enable double wide mode when the dot clock
2375	* is > 90% of the (display) core speed.
2376	*/
2377	if (intel_crtc_supports_double_wide(crtc) &&
2378	pipe_mode->crtc_clock > clock_limit) {
2379	clock_limit = display->cdclk.max_dotclk_freq;
2380	crtc_state->double_wide = true;
2381	}
2382	}
2383
2384	if (pipe_mode->crtc_clock > clock_limit) {
2385	drm_dbg_kms(display->drm,
2386	"[CRTC:%d:%s] requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
2387	crtc->base.base.id, crtc->base.name,
2388	pipe_mode->crtc_clock, clock_limit,
2389	str_yes_no(crtc_state->double_wide));
2390	return -EINVAL;
2391	}
2392
2393	return 0;
2394	}
2395
2396	static int intel_crtc_set_context_latency(struct intel_crtc_state *crtc_state)
2397	{
2398	struct intel_display *display = to_intel_display(crtc_state);
2399	int set_context_latency = 0;
2400
2401	if (!HAS_DSB(display))
2402	return 0;
2403
2404	set_context_latency = max(set_context_latency,
2405	intel_psr_min_set_context_latency(crtc_state));
2406
2407	return set_context_latency;
2408	}
2409
2410	static int intel_crtc_compute_set_context_latency(struct intel_atomic_state *state,
2411	struct intel_crtc *crtc)
2412	{
2413	struct intel_display *display = to_intel_display(state);
2414	struct intel_crtc_state *crtc_state =
2415	intel_atomic_get_new_crtc_state(state, crtc);
2416	struct drm_display_mode *adjusted_mode =
2417	&crtc_state->hw.adjusted_mode;
2418	int set_context_latency, max_vblank_delay;
2419
2420	set_context_latency = intel_crtc_set_context_latency(crtc_state);
2421
2422	max_vblank_delay = adjusted_mode->crtc_vblank_end - adjusted_mode->crtc_vblank_start - 1;
2423
2424	if (set_context_latency > max_vblank_delay) {
2425	drm_dbg_kms(display->drm, "[CRTC:%d:%s] set context latency (%d) exceeds max (%d)\n",
2426	crtc->base.base.id, crtc->base.name,
2427	set_context_latency,
2428	max_vblank_delay);
2429	return -EINVAL;
2430	}
2431
2432	crtc_state->set_context_latency = set_context_latency;
2433	adjusted_mode->crtc_vblank_start += set_context_latency;
2434
2435	return 0;
2436	}
2437
2438	static int intel_crtc_compute_config(struct intel_atomic_state *state,
2439	struct intel_crtc *crtc)
2440	{
2441	struct intel_crtc_state *crtc_state =
2442	intel_atomic_get_new_crtc_state(state, crtc);
2443	int ret;
2444
2445	ret = intel_dpll_crtc_compute_clock(state, crtc);
2446	if (ret)
2447	return ret;
2448
2449	ret = intel_crtc_compute_set_context_latency(state, crtc);
2450	if (ret)
2451	return ret;
2452
2453	ret = intel_crtc_compute_pipe_src(crtc_state);
2454	if (ret)
2455	return ret;
2456
2457	ret = intel_crtc_compute_pipe_mode(crtc_state);
2458	if (ret)
2459	return ret;
2460
2461	intel_crtc_compute_pixel_rate(crtc_state);
2462
2463	if (crtc_state->has_pch_encoder)
2464	return ilk_fdi_compute_config(intel_crtc: crtc, pipe_config: crtc_state);
2465
2466	intel_vrr_compute_guardband(crtc_state);
2467
2468	return 0;
2469	}
2470
2471	static void
2472	intel_reduce_m_n_ratio(u32 *num, u32 *den)
2473	{
2474	while (*num > DATA_LINK_M_N_MASK ||
2475	*den > DATA_LINK_M_N_MASK) {
2476	*num >>= 1;
2477	*den >>= 1;
2478	}
2479	}
2480
2481	static void compute_m_n(u32 *ret_m, u32 *ret_n,
2482	u32 m, u32 n, u32 constant_n)
2483	{
2484	if (constant_n)
2485	*ret_n = constant_n;
2486	else
2487	*ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
2488
2489	*ret_m = div_u64(dividend: mul_u32_u32(a: m, b: *ret_n), divisor: n);
2490	intel_reduce_m_n_ratio(num: ret_m, den: ret_n);
2491	}
2492
2493	void
2494	intel_link_compute_m_n(u16 bits_per_pixel_x16, int nlanes,
2495	int pixel_clock, int link_clock,
2496	int bw_overhead,
2497	struct intel_link_m_n *m_n)
2498	{
2499	u32 link_symbol_clock = intel_dp_link_symbol_clock(rate: link_clock);
2500	u32 data_m = intel_dp_effective_data_rate(pixel_clock, bpp_x16: bits_per_pixel_x16,
2501	bw_overhead);
2502	u32 data_n = drm_dp_max_dprx_data_rate(max_link_rate: link_clock, max_lanes: nlanes);
2503
2504	/*
2505	* Windows/BIOS uses fixed M/N values always. Follow suit.
2506	*
2507	* Also several DP dongles in particular seem to be fussy
2508	* about too large link M/N values. Presumably the 20bit
2509	* value used by Windows/BIOS is acceptable to everyone.
2510	*/
2511	m_n->tu = 64;
2512	compute_m_n(ret_m: &m_n->data_m, ret_n: &m_n->data_n,
2513	m: data_m, n: data_n,
2514	constant_n: 0x8000000);
2515
2516	compute_m_n(ret_m: &m_n->link_m, ret_n: &m_n->link_n,
2517	m: pixel_clock, n: link_symbol_clock,
2518	constant_n: 0x80000);
2519	}
2520
2521	void intel_panel_sanitize_ssc(struct intel_display *display)
2522	{
2523	/*
2524	* There may be no VBT; and if the BIOS enabled SSC we can
2525	* just keep using it to avoid unnecessary flicker. Whereas if the
2526	* BIOS isn't using it, don't assume it will work even if the VBT
2527	* indicates as much.
2528	*/
2529	if (HAS_PCH_IBX(display) || HAS_PCH_CPT(display)) {
2530	bool bios_lvds_use_ssc = intel_de_read(display,
2531	PCH_DREF_CONTROL) &
2532	DREF_SSC1_ENABLE;
2533
2534	if (display->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
2535	drm_dbg_kms(display->drm,
2536	"SSC %s by BIOS, overriding VBT which says %s\n",
2537	str_enabled_disabled(bios_lvds_use_ssc),
2538	str_enabled_disabled(display->vbt.lvds_use_ssc));
2539	display->vbt.lvds_use_ssc = bios_lvds_use_ssc;
2540	}
2541	}
2542	}
2543
2544	void intel_zero_m_n(struct intel_link_m_n *m_n)
2545	{
2546	/* corresponds to 0 register value */
2547	memset(m_n, 0, sizeof(*m_n));
2548	m_n->tu = 1;
2549	}
2550
2551	void intel_set_m_n(struct intel_display *display,
2552	const struct intel_link_m_n *m_n,
2553	i915_reg_t data_m_reg, i915_reg_t data_n_reg,
2554	i915_reg_t link_m_reg, i915_reg_t link_n_reg)
2555	{
2556	intel_de_write(display, reg: data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m);
2557	intel_de_write(display, reg: data_n_reg, val: m_n->data_n);
2558	intel_de_write(display, reg: link_m_reg, val: m_n->link_m);
2559	/*
2560	* On BDW+ writing LINK_N arms the double buffered update
2561	* of all the M/N registers, so it must be written last.
2562	*/
2563	intel_de_write(display, reg: link_n_reg, val: m_n->link_n);
2564	}
2565
2566	bool intel_cpu_transcoder_has_m2_n2(struct intel_display *display,
2567	enum transcoder transcoder)
2568	{
2569	if (display->platform.haswell)
2570	return transcoder == TRANSCODER_EDP;
2571
2572	return IS_DISPLAY_VER(display, 5, 7) || display->platform.cherryview;
2573	}
2574
2575	void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
2576	enum transcoder transcoder,
2577	const struct intel_link_m_n *m_n)
2578	{
2579	struct intel_display *display = to_intel_display(crtc);
2580	enum pipe pipe = crtc->pipe;
2581
2582	if (DISPLAY_VER(display) >= 5)
2583	intel_set_m_n(display, m_n,
2584	PIPE_DATA_M1(display, transcoder),
2585	PIPE_DATA_N1(display, transcoder),
2586	PIPE_LINK_M1(display, transcoder),
2587	PIPE_LINK_N1(display, transcoder));
2588	else
2589	intel_set_m_n(display, m_n,
2590	PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),
2591	PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe));
2592	}
2593
2594	void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc,
2595	enum transcoder transcoder,
2596	const struct intel_link_m_n *m_n)
2597	{
2598	struct intel_display *display = to_intel_display(crtc);
2599
2600	if (!intel_cpu_transcoder_has_m2_n2(display, transcoder))
2601	return;
2602
2603	intel_set_m_n(display, m_n,
2604	PIPE_DATA_M2(display, transcoder),
2605	PIPE_DATA_N2(display, transcoder),
2606	PIPE_LINK_M2(display, transcoder),
2607	PIPE_LINK_N2(display, transcoder));
2608	}
2609
2610	static bool
2611	transcoder_has_vrr(const struct intel_crtc_state *crtc_state)
2612	{
2613	struct intel_display *display = to_intel_display(crtc_state);
2614	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2615
2616	return HAS_VRR(display) && !transcoder_is_dsi(transcoder: cpu_transcoder);
2617	}
2618
2619	static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
2620	{
2621	struct intel_display *display = to_intel_display(crtc_state);
2622	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2623	enum pipe pipe = crtc->pipe;
2624	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2625	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2626	u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end;
2627	int vsyncshift = 0;
2628
2629	drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder));
2630
2631	/* We need to be careful not to changed the adjusted mode, for otherwise
2632	* the hw state checker will get angry at the mismatch. */
2633	crtc_vdisplay = adjusted_mode->crtc_vdisplay;
2634	crtc_vtotal = adjusted_mode->crtc_vtotal;
2635	crtc_vblank_start = adjusted_mode->crtc_vblank_start;
2636	crtc_vblank_end = adjusted_mode->crtc_vblank_end;
2637
2638	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
2639	/* the chip adds 2 halflines automatically */
2640	crtc_vtotal -= 1;
2641	crtc_vblank_end -= 1;
2642
2643	if (intel_crtc_has_type(crtc_state, type: INTEL_OUTPUT_SDVO))
2644	vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
2645	else
2646	vsyncshift = adjusted_mode->crtc_hsync_start -
2647	adjusted_mode->crtc_htotal / 2;
2648	if (vsyncshift < 0)
2649	vsyncshift += adjusted_mode->crtc_htotal;
2650	}
2651
2652	/*
2653	* VBLANK_START no longer works on ADL+, instead we must use
2654	* TRANS_SET_CONTEXT_LATENCY to configure the pipe vblank start.
2655	*/
2656	if (DISPLAY_VER(display) >= 13) {
2657	intel_de_write(display,
2658	TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder),
2659	val: crtc_state->set_context_latency);
2660
2661	/*
2662	* VBLANK_START not used by hw, just clear it
2663	* to make it stand out in register dumps.
2664	*/
2665	crtc_vblank_start = 1;
2666	} else if (DISPLAY_VER(display) == 12) {
2667	/* VBLANK_START - VACTIVE defines SCL on TGL */
2668	crtc_vblank_start = crtc_vdisplay + crtc_state->set_context_latency;
2669	}
2670
2671	if (DISPLAY_VER(display) >= 4 && DISPLAY_VER(display) < 35)
2672	intel_de_write(display,
2673	TRANS_VSYNCSHIFT(display, cpu_transcoder),
2674	val: vsyncshift);
2675
2676	intel_de_write(display, TRANS_HTOTAL(display, cpu_transcoder),
2677	HACTIVE(adjusted_mode->crtc_hdisplay - 1) |
2678	HTOTAL(adjusted_mode->crtc_htotal - 1));
2679	intel_de_write(display, TRANS_HBLANK(display, cpu_transcoder),
2680	HBLANK_START(adjusted_mode->crtc_hblank_start - 1) |
2681	HBLANK_END(adjusted_mode->crtc_hblank_end - 1));
2682	intel_de_write(display, TRANS_HSYNC(display, cpu_transcoder),
2683	HSYNC_START(adjusted_mode->crtc_hsync_start - 1) |
2684	HSYNC_END(adjusted_mode->crtc_hsync_end - 1));
2685
2686	/*
2687	* For platforms that always use VRR Timing Generator, the VTOTAL.Vtotal
2688	* bits are not required. Since the support for these bits is going to
2689	* be deprecated in upcoming platforms, avoid writing these bits for the
2690	* platforms that do not use legacy Timing Generator.
2691	*/
2692	if (intel_vrr_always_use_vrr_tg(display))
2693	crtc_vtotal = 1;
2694
2695	intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder),
2696	VACTIVE(crtc_vdisplay - 1) |
2697	VTOTAL(crtc_vtotal - 1));
2698	intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder),
2699	VBLANK_START(crtc_vblank_start - 1) |
2700	VBLANK_END(crtc_vblank_end - 1));
2701	intel_de_write(display, TRANS_VSYNC(display, cpu_transcoder),
2702	VSYNC_START(adjusted_mode->crtc_vsync_start - 1) |
2703	VSYNC_END(adjusted_mode->crtc_vsync_end - 1));
2704
2705	/* Workaround: when the EDP input selection is B, the VTOTAL_B must be
2706	* programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
2707	* documented on the DDI_FUNC_CTL register description, EDP Input Select
2708	* bits. */
2709	if (display->platform.haswell && cpu_transcoder == TRANSCODER_EDP &&
2710	(pipe == PIPE_B || pipe == PIPE_C))
2711	intel_de_write(display, TRANS_VTOTAL(display, pipe),
2712	VACTIVE(crtc_vdisplay - 1) |
2713	VTOTAL(crtc_vtotal - 1));
2714
2715	if (DISPLAY_VER(display) >= 30) {
2716	/*
2717	* Address issues for resolutions with high refresh rate that
2718	* have small Hblank, specifically where Hblank is smaller than
2719	* one MTP. Simulations indicate this will address the
2720	* jitter issues that currently causes BS to be immediately
2721	* followed by BE which DPRX devices are unable to handle.
2722	* https://groups.vesa.org/wg/DP/document/20494
2723	*/
2724	intel_de_write(display, DP_MIN_HBLANK_CTL(cpu_transcoder),
2725	val: crtc_state->min_hblank);
2726	}
2727	}
2728
2729	static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc_state)
2730	{
2731	struct intel_display *display = to_intel_display(crtc_state);
2732	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2733	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2734	u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end;
2735
2736	drm_WARN_ON(display->drm, transcoder_is_dsi(cpu_transcoder));
2737
2738	crtc_vdisplay = adjusted_mode->crtc_vdisplay;
2739	crtc_vtotal = adjusted_mode->crtc_vtotal;
2740	crtc_vblank_start = adjusted_mode->crtc_vblank_start;
2741	crtc_vblank_end = adjusted_mode->crtc_vblank_end;
2742
2743	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
2744	/* the chip adds 2 halflines automatically */
2745	crtc_vtotal -= 1;
2746	crtc_vblank_end -= 1;
2747	}
2748
2749	if (DISPLAY_VER(display) >= 13) {
2750	intel_de_write(display,
2751	TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder),
2752	val: crtc_state->set_context_latency);
2753
2754	/*
2755	* VBLANK_START not used by hw, just clear it
2756	* to make it stand out in register dumps.
2757	*/
2758	crtc_vblank_start = 1;
2759	} else if (DISPLAY_VER(display) == 12) {
2760	/* VBLANK_START - VACTIVE defines SCL on TGL */
2761	crtc_vblank_start = crtc_vdisplay + crtc_state->set_context_latency;
2762	}
2763
2764	/*
2765	* The hardware actually ignores TRANS_VBLANK.VBLANK_END in DP mode.
2766	* But let's write it anyway to keep the state checker happy.
2767	*/
2768	intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder),
2769	VBLANK_START(crtc_vblank_start - 1) |
2770	VBLANK_END(crtc_vblank_end - 1));
2771	/*
2772	* For platforms that always use VRR Timing Generator, the VTOTAL.Vtotal
2773	* bits are not required. Since the support for these bits is going to
2774	* be deprecated in upcoming platforms, avoid writing these bits for the
2775	* platforms that do not use legacy Timing Generator.
2776	*/
2777	if (intel_vrr_always_use_vrr_tg(display))
2778	crtc_vtotal = 1;
2779
2780	/*
2781	* The double buffer latch point for TRANS_VTOTAL
2782	* is the transcoder's undelayed vblank.
2783	*/
2784	intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder),
2785	VACTIVE(crtc_vdisplay - 1) |
2786	VTOTAL(crtc_vtotal - 1));
2787
2788	intel_vrr_set_fixed_rr_timings(crtc_state);
2789	intel_vrr_transcoder_enable(crtc_state);
2790	}
2791
2792	static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
2793	{
2794	struct intel_display *display = to_intel_display(crtc_state);
2795	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2796	int width = drm_rect_width(r: &crtc_state->pipe_src);
2797	int height = drm_rect_height(r: &crtc_state->pipe_src);
2798	enum pipe pipe = crtc->pipe;
2799
2800	/* pipesrc controls the size that is scaled from, which should
2801	* always be the user's requested size.
2802	*/
2803	intel_de_write(display, PIPESRC(display, pipe),
2804	PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1));
2805	}
2806
2807	static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
2808	{
2809	struct intel_display *display = to_intel_display(crtc_state);
2810	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2811
2812	if (DISPLAY_VER(display) == 2 || DISPLAY_VER(display) >= 35)
2813	return false;
2814
2815	if (DISPLAY_VER(display) >= 9 ||
2816	display->platform.broadwell || display->platform.haswell)
2817	return intel_de_read(display,
2818	TRANSCONF(display, cpu_transcoder)) & TRANSCONF_INTERLACE_MASK_HSW;
2819	else
2820	return intel_de_read(display,
2821	TRANSCONF(display, cpu_transcoder)) & TRANSCONF_INTERLACE_MASK;
2822	}
2823
2824	static void intel_get_transcoder_timings(struct intel_crtc *crtc,
2825	struct intel_crtc_state *pipe_config)
2826	{
2827	struct intel_display *display = to_intel_display(crtc);
2828	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
2829	struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2830	u32 tmp;
2831
2832	tmp = intel_de_read(display, TRANS_HTOTAL(display, cpu_transcoder));
2833	adjusted_mode->crtc_hdisplay = REG_FIELD_GET(HACTIVE_MASK, tmp) + 1;
2834	adjusted_mode->crtc_htotal = REG_FIELD_GET(HTOTAL_MASK, tmp) + 1;
2835
2836	if (!transcoder_is_dsi(transcoder: cpu_transcoder)) {
2837	tmp = intel_de_read(display,
2838	TRANS_HBLANK(display, cpu_transcoder));
2839	adjusted_mode->crtc_hblank_start = REG_FIELD_GET(HBLANK_START_MASK, tmp) + 1;
2840	adjusted_mode->crtc_hblank_end = REG_FIELD_GET(HBLANK_END_MASK, tmp) + 1;
2841	}
2842
2843	tmp = intel_de_read(display, TRANS_HSYNC(display, cpu_transcoder));
2844	adjusted_mode->crtc_hsync_start = REG_FIELD_GET(HSYNC_START_MASK, tmp) + 1;
2845	adjusted_mode->crtc_hsync_end = REG_FIELD_GET(HSYNC_END_MASK, tmp) + 1;
2846
2847	tmp = intel_de_read(display, TRANS_VTOTAL(display, cpu_transcoder));
2848	adjusted_mode->crtc_vdisplay = REG_FIELD_GET(VACTIVE_MASK, tmp) + 1;
2849	adjusted_mode->crtc_vtotal = REG_FIELD_GET(VTOTAL_MASK, tmp) + 1;
2850
2851	/* FIXME TGL+ DSI transcoders have this! */
2852	if (!transcoder_is_dsi(transcoder: cpu_transcoder)) {
2853	tmp = intel_de_read(display,
2854	TRANS_VBLANK(display, cpu_transcoder));
2855	adjusted_mode->crtc_vblank_start = REG_FIELD_GET(VBLANK_START_MASK, tmp) + 1;
2856	adjusted_mode->crtc_vblank_end = REG_FIELD_GET(VBLANK_END_MASK, tmp) + 1;
2857	}
2858	tmp = intel_de_read(display, TRANS_VSYNC(display, cpu_transcoder));
2859	adjusted_mode->crtc_vsync_start = REG_FIELD_GET(VSYNC_START_MASK, tmp) + 1;
2860	adjusted_mode->crtc_vsync_end = REG_FIELD_GET(VSYNC_END_MASK, tmp) + 1;
2861
2862	if (intel_pipe_is_interlaced(crtc_state: pipe_config)) {
2863	adjusted_mode->flags |= DRM_MODE_FLAG_INTERLACE;
2864	adjusted_mode->crtc_vtotal += 1;
2865	adjusted_mode->crtc_vblank_end += 1;
2866	}
2867
2868	if (DISPLAY_VER(display) >= 13 && !transcoder_is_dsi(transcoder: cpu_transcoder)) {
2869	pipe_config->set_context_latency =
2870	intel_de_read(display,
2871	TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder));
2872	adjusted_mode->crtc_vblank_start =
2873	adjusted_mode->crtc_vdisplay +
2874	pipe_config->set_context_latency;
2875	} else if (DISPLAY_VER(display) == 12) {
2876	/*
2877	* TGL doesn't have a dedicated register for SCL.
2878	* Instead, the hardware derives SCL from the difference between
2879	* TRANS_VBLANK.vblank_start and TRANS_VTOTAL.vactive.
2880	* To reflect the HW behaviour, readout the value for SCL as
2881	* Vblank start - Vactive.
2882	*/
2883	pipe_config->set_context_latency =
2884	adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay;
2885	}
2886
2887	if (DISPLAY_VER(display) >= 30)
2888	pipe_config->min_hblank = intel_de_read(display,
2889	DP_MIN_HBLANK_CTL(cpu_transcoder));
2890	}
2891
2892	static void intel_joiner_adjust_pipe_src(struct intel_crtc_state *crtc_state)
2893	{
2894	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2895	int num_pipes = intel_crtc_num_joined_pipes(crtc_state);
2896	enum pipe primary_pipe, pipe = crtc->pipe;
2897	int width;
2898
2899	if (num_pipes == 1)
2900	return;
2901
2902	primary_pipe = joiner_primary_pipe(crtc_state);
2903	width = drm_rect_width(r: &crtc_state->pipe_src);
2904
2905	drm_rect_translate_to(r: &crtc_state->pipe_src,
2906	x: (pipe - primary_pipe) * width, y: 0);
2907	}
2908
2909	static void intel_get_pipe_src_size(struct intel_crtc *crtc,
2910	struct intel_crtc_state *pipe_config)
2911	{
2912	struct intel_display *display = to_intel_display(crtc);
2913	u32 tmp;
2914
2915	tmp = intel_de_read(display, PIPESRC(display, crtc->pipe));
2916
2917	drm_rect_init(r: &pipe_config->pipe_src, x: 0, y: 0,
2918	REG_FIELD_GET(PIPESRC_WIDTH_MASK, tmp) + 1,
2919	REG_FIELD_GET(PIPESRC_HEIGHT_MASK, tmp) + 1);
2920
2921	intel_joiner_adjust_pipe_src(crtc_state: pipe_config);
2922	}
2923
2924	void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
2925	{
2926	struct intel_display *display = to_intel_display(crtc_state);
2927	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2928	u32 val = 0;
2929
2930	/*
2931	* - We keep both pipes enabled on 830
2932	* - During modeset the pipe is still disabled and must remain so
2933	* - During fastset the pipe is already enabled and must remain so
2934	*/
2935	if (display->platform.i830 || !intel_crtc_needs_modeset(crtc_state))
2936	val |= TRANSCONF_ENABLE;
2937
2938	if (crtc_state->double_wide)
2939	val |= TRANSCONF_DOUBLE_WIDE;
2940
2941	/* only g4x and later have fancy bpc/dither controls */
2942	if (display->platform.g4x || display->platform.valleyview ||
2943	display->platform.cherryview) {
2944	/* Bspec claims that we can't use dithering for 30bpp pipes. */
2945	if (crtc_state->dither && crtc_state->pipe_bpp != 30)
2946	val |= TRANSCONF_DITHER_EN |
2947	TRANSCONF_DITHER_TYPE_SP;
2948
2949	switch (crtc_state->pipe_bpp) {
2950	default:
2951	/* Case prevented by intel_choose_pipe_bpp_dither. */
2952	MISSING_CASE(crtc_state->pipe_bpp);
2953	fallthrough;
2954	case 18:
2955	val |= TRANSCONF_BPC_6;
2956	break;
2957	case 24:
2958	val |= TRANSCONF_BPC_8;
2959	break;
2960	case 30:
2961	val |= TRANSCONF_BPC_10;
2962	break;
2963	}
2964	}
2965
2966	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
2967	if (DISPLAY_VER(display) < 4 ||
2968	intel_crtc_has_type(crtc_state, type: INTEL_OUTPUT_SDVO))
2969	val |= TRANSCONF_INTERLACE_W_FIELD_INDICATION;
2970	else
2971	val |= TRANSCONF_INTERLACE_W_SYNC_SHIFT;
2972	} else {
2973	val |= TRANSCONF_INTERLACE_PROGRESSIVE;
2974	}
2975
2976	if ((display->platform.valleyview || display->platform.cherryview) &&
2977	crtc_state->limited_color_range)
2978	val |= TRANSCONF_COLOR_RANGE_SELECT;
2979
2980	val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode);
2981
2982	if (crtc_state->wgc_enable)
2983	val |= TRANSCONF_WGC_ENABLE;
2984
2985	val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
2986
2987	intel_de_write(display, TRANSCONF(display, cpu_transcoder), val);
2988	intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder));
2989	}
2990
2991	static enum intel_output_format
2992	bdw_get_pipe_misc_output_format(struct intel_crtc *crtc)
2993	{
2994	struct intel_display *display = to_intel_display(crtc);
2995	u32 tmp;
2996
2997	tmp = intel_de_read(display, PIPE_MISC(crtc->pipe));
2998
2999	if (tmp & PIPE_MISC_YUV420_ENABLE) {
3000	/*
3001	* We support 4:2:0 in full blend mode only.
3002	* For xe3_lpd+ this is implied in YUV420 Enable bit.
3003	* Ensure the same for prior platforms in YUV420 Mode bit.
3004	*/
3005	if (DISPLAY_VER(display) < 30)
3006	drm_WARN_ON(display->drm,
3007	(tmp & PIPE_MISC_YUV420_MODE_FULL_BLEND) == 0);
3008
3009	return INTEL_OUTPUT_FORMAT_YCBCR420;
3010	} else if (tmp & PIPE_MISC_OUTPUT_COLORSPACE_YUV) {
3011	return INTEL_OUTPUT_FORMAT_YCBCR444;
3012	} else {
3013	return INTEL_OUTPUT_FORMAT_RGB;
3014	}
3015	}
3016
3017	static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
3018	struct intel_crtc_state *pipe_config)
3019	{
3020	struct intel_display *display = to_intel_display(crtc);
3021	enum intel_display_power_domain power_domain;
3022	enum transcoder cpu_transcoder = (enum transcoder)crtc->pipe;
3023	intel_wakeref_t wakeref;
3024	bool ret = false;
3025	u32 tmp;
3026
3027	power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
3028	wakeref = intel_display_power_get_if_enabled(display, domain: power_domain);
3029	if (!wakeref)
3030	return false;
3031
3032	tmp = intel_de_read(display, TRANSCONF(display, cpu_transcoder));
3033	if (!(tmp & TRANSCONF_ENABLE))
3034	goto out;
3035
3036	pipe_config->cpu_transcoder = cpu_transcoder;
3037
3038	pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
3039	pipe_config->sink_format = pipe_config->output_format;
3040
3041	if (display->platform.g4x || display->platform.valleyview ||
3042	display->platform.cherryview) {
3043	switch (tmp & TRANSCONF_BPC_MASK) {
3044	case TRANSCONF_BPC_6:
3045	pipe_config->pipe_bpp = 18;
3046	break;
3047	case TRANSCONF_BPC_8:
3048	pipe_config->pipe_bpp = 24;
3049	break;
3050	case TRANSCONF_BPC_10:
3051	pipe_config->pipe_bpp = 30;
3052	break;
3053	default:
3054	MISSING_CASE(tmp);
3055	break;
3056	}
3057	}
3058
3059	if ((display->platform.valleyview || display->platform.cherryview) &&
3060	(tmp & TRANSCONF_COLOR_RANGE_SELECT))
3061	pipe_config->limited_color_range = true;
3062
3063	pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_I9XX, tmp);
3064
3065	pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1;
3066
3067	if ((display->platform.valleyview || display->platform.cherryview) &&
3068	(tmp & TRANSCONF_WGC_ENABLE))
3069	pipe_config->wgc_enable = true;
3070
3071	intel_color_get_config(crtc_state: pipe_config);
3072
3073	if (HAS_DOUBLE_WIDE(display))
3074	pipe_config->double_wide = tmp & TRANSCONF_DOUBLE_WIDE;
3075
3076	intel_get_transcoder_timings(crtc, pipe_config);
3077	intel_get_pipe_src_size(crtc, pipe_config);
3078
3079	i9xx_pfit_get_config(crtc_state: pipe_config);
3080
3081	i9xx_dpll_get_hw_state(crtc, dpll_hw_state: &pipe_config->dpll_hw_state);
3082
3083	if (DISPLAY_VER(display) >= 4) {
3084	tmp = pipe_config->dpll_hw_state.i9xx.dpll_md;
3085	pipe_config->pixel_multiplier =
3086	((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
3087	>> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
3088	} else if (display->platform.i945g || display->platform.i945gm ||
3089	display->platform.g33 || display->platform.pineview) {
3090	tmp = pipe_config->dpll_hw_state.i9xx.dpll;
3091	pipe_config->pixel_multiplier =
3092	((tmp & SDVO_MULTIPLIER_MASK)
3093	>> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
3094	} else {
3095	/* Note that on i915G/GM the pixel multiplier is in the sdvo
3096	* port and will be fixed up in the encoder->get_config
3097	* function. */
3098	pipe_config->pixel_multiplier = 1;
3099	}
3100
3101	if (display->platform.cherryview)
3102	chv_crtc_clock_get(crtc_state: pipe_config);
3103	else if (display->platform.valleyview)
3104	vlv_crtc_clock_get(crtc_state: pipe_config);
3105	else
3106	i9xx_crtc_clock_get(crtc_state: pipe_config);
3107
3108	/*
3109	* Normally the dotclock is filled in by the encoder .get_config()
3110	* but in case the pipe is enabled w/o any ports we need a sane
3111	* default.
3112	*/
3113	pipe_config->hw.adjusted_mode.crtc_clock =
3114	pipe_config->port_clock / pipe_config->pixel_multiplier;
3115
3116	ret = true;
3117
3118	out:
3119	intel_display_power_put(display, domain: power_domain, wakeref);
3120
3121	return ret;
3122	}
3123
3124	void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)
3125	{
3126	struct intel_display *display = to_intel_display(crtc_state);
3127	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
3128	u32 val = 0;
3129
3130	/*
3131	* - During modeset the pipe is still disabled and must remain so
3132	* - During fastset the pipe is already enabled and must remain so
3133	*/
3134	if (!intel_crtc_needs_modeset(crtc_state))
3135	val |= TRANSCONF_ENABLE;
3136
3137	switch (crtc_state->pipe_bpp) {
3138	default:
3139	/* Case prevented by intel_choose_pipe_bpp_dither. */
3140	MISSING_CASE(crtc_state->pipe_bpp);
3141	fallthrough;
3142	case 18:
3143	val |= TRANSCONF_BPC_6;
3144	break;
3145	case 24:
3146	val |= TRANSCONF_BPC_8;
3147	break;
3148	case 30:
3149	val |= TRANSCONF_BPC_10;
3150	break;
3151	case 36:
3152	val |= TRANSCONF_BPC_12;
3153	break;
3154	}
3155
3156	if (crtc_state->dither)
3157	val |= TRANSCONF_DITHER_EN | TRANSCONF_DITHER_TYPE_SP;
3158
3159	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3160	val |= TRANSCONF_INTERLACE_IF_ID_ILK;
3161	else
3162	val |= TRANSCONF_INTERLACE_PF_PD_ILK;
3163
3164	/*
3165	* This would end up with an odd purple hue over
3166	* the entire display. Make sure we don't do it.
3167	*/
3168	drm_WARN_ON(display->drm, crtc_state->limited_color_range &&
3169	crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
3170
3171	if (crtc_state->limited_color_range &&
3172	!intel_crtc_has_type(crtc_state, type: INTEL_OUTPUT_SDVO))
3173	val |= TRANSCONF_COLOR_RANGE_SELECT;
3174
3175	if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
3176	val |= TRANSCONF_OUTPUT_COLORSPACE_YUV709;
3177
3178	val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode);
3179
3180	val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
3181	val |= TRANSCONF_MSA_TIMING_DELAY(crtc_state->msa_timing_delay);
3182
3183	intel_de_write(display, TRANSCONF(display, cpu_transcoder), val);
3184	intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder));
3185	}
3186
3187	static void hsw_set_transconf(const struct intel_crtc_state *crtc_state)
3188	{
3189	struct intel_display *display = to_intel_display(crtc_state);
3190	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
3191	u32 val = 0;
3192
3193	/*
3194	* - During modeset the pipe is still disabled and must remain so
3195	* - During fastset the pipe is already enabled and must remain so
3196	*/
3197	if (!intel_crtc_needs_modeset(crtc_state))
3198	val |= TRANSCONF_ENABLE;
3199
3200	if (display->platform.haswell && crtc_state->dither)
3201	val |= TRANSCONF_DITHER_EN | TRANSCONF_DITHER_TYPE_SP;
3202
3203	if (DISPLAY_VER(display) < 35) {
3204	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3205	val |= TRANSCONF_INTERLACE_IF_ID_ILK;
3206	else
3207	val |= TRANSCONF_INTERLACE_PF_PD_ILK;
3208	}
3209
3210	if (display->platform.haswell &&
3211	crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
3212	val |= TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW;
3213
3214	intel_de_write(display, TRANSCONF(display, cpu_transcoder), val);
3215	intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder));
3216	}
3217
3218	static void bdw_set_pipe_misc(struct intel_dsb *dsb,
3219	const struct intel_crtc_state *crtc_state)
3220	{
3221	struct intel_display *display = to_intel_display(crtc_state);
3222	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3223	u32 val = 0;
3224
3225	switch (crtc_state->pipe_bpp) {
3226	case 18:
3227	val |= PIPE_MISC_BPC_6;
3228	break;
3229	case 24:
3230	val |= PIPE_MISC_BPC_8;
3231	break;
3232	case 30:
3233	val |= PIPE_MISC_BPC_10;
3234	break;
3235	case 36:
3236	/* Port output 12BPC defined for ADLP+ */
3237	if (DISPLAY_VER(display) >= 13)
3238	val |= PIPE_MISC_BPC_12_ADLP;
3239	break;
3240	default:
3241	MISSING_CASE(crtc_state->pipe_bpp);
3242	break;
3243	}
3244
3245	if (crtc_state->dither)
3246	val |= PIPE_MISC_DITHER_ENABLE | PIPE_MISC_DITHER_TYPE_SP;
3247
3248	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
3249	crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
3250	val |= PIPE_MISC_OUTPUT_COLORSPACE_YUV;
3251
3252	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
3253	val |= DISPLAY_VER(display) >= 30 ? PIPE_MISC_YUV420_ENABLE :
3254	PIPE_MISC_YUV420_ENABLE | PIPE_MISC_YUV420_MODE_FULL_BLEND;
3255
3256	if (DISPLAY_VER(display) >= 11 && is_hdr_mode(crtc_state))
3257	val |= PIPE_MISC_HDR_MODE_PRECISION;
3258
3259	if (DISPLAY_VER(display) >= 12)
3260	val |= PIPE_MISC_PIXEL_ROUNDING_TRUNC;
3261
3262	/* allow PSR with sprite enabled */
3263	if (display->platform.broadwell)
3264	val |= PIPE_MISC_PSR_MASK_SPRITE_ENABLE;
3265
3266	intel_de_write_dsb(display, dsb, PIPE_MISC(crtc->pipe), val);
3267	}
3268
3269	int bdw_get_pipe_misc_bpp(struct intel_crtc *crtc)
3270	{
3271	struct intel_display *display = to_intel_display(crtc);
3272	u32 tmp;
3273
3274	tmp = intel_de_read(display, PIPE_MISC(crtc->pipe));
3275
3276	switch (tmp & PIPE_MISC_BPC_MASK) {
3277	case PIPE_MISC_BPC_6:
3278	return 18;
3279	case PIPE_MISC_BPC_8:
3280	return 24;
3281	case PIPE_MISC_BPC_10:
3282	return 30;
3283	/*
3284	* PORT OUTPUT 12 BPC defined for ADLP+.
3285	*
3286	* TODO:
3287	* For previous platforms with DSI interface, bits 5:7
3288	* are used for storing pipe_bpp irrespective of dithering.
3289	* Since the value of 12 BPC is not defined for these bits
3290	* on older platforms, need to find a workaround for 12 BPC
3291	* MIPI DSI HW readout.
3292	*/
3293	case PIPE_MISC_BPC_12_ADLP:
3294	if (DISPLAY_VER(display) >= 13)
3295	return 36;
3296	fallthrough;
3297	default:
3298	MISSING_CASE(tmp);
3299	return 0;
3300	}
3301	}
3302
3303	int ilk_get_lanes_required(int target_clock, int link_bw, int bpp)
3304	{
3305	/*
3306	* Account for spread spectrum to avoid
3307	* oversubscribing the link. Max center spread
3308	* is 2.5%; use 5% for safety's sake.
3309	*/
3310	u32 bps = target_clock * bpp * 21 / 20;
3311	return DIV_ROUND_UP(bps, link_bw * 8);
3312	}
3313
3314	void intel_get_m_n(struct intel_display *display,
3315	struct intel_link_m_n *m_n,
3316	i915_reg_t data_m_reg, i915_reg_t data_n_reg,
3317	i915_reg_t link_m_reg, i915_reg_t link_n_reg)
3318	{
3319	m_n->link_m = intel_de_read(display, reg: link_m_reg) & DATA_LINK_M_N_MASK;
3320	m_n->link_n = intel_de_read(display, reg: link_n_reg) & DATA_LINK_M_N_MASK;
3321	m_n->data_m = intel_de_read(display, reg: data_m_reg) & DATA_LINK_M_N_MASK;
3322	m_n->data_n = intel_de_read(display, reg: data_n_reg) & DATA_LINK_M_N_MASK;
3323	m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(display, data_m_reg)) + 1;
3324	}
3325
3326	void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc,
3327	enum transcoder transcoder,
3328	struct intel_link_m_n *m_n)
3329	{
3330	struct intel_display *display = to_intel_display(crtc);
3331	enum pipe pipe = crtc->pipe;
3332
3333	if (DISPLAY_VER(display) >= 5)
3334	intel_get_m_n(display, m_n,
3335	PIPE_DATA_M1(display, transcoder),
3336	PIPE_DATA_N1(display, transcoder),
3337	PIPE_LINK_M1(display, transcoder),
3338	PIPE_LINK_N1(display, transcoder));
3339	else
3340	intel_get_m_n(display, m_n,
3341	PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),
3342	PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe));
3343	}
3344
3345	void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
3346	enum transcoder transcoder,
3347	struct intel_link_m_n *m_n)
3348	{
3349	struct intel_display *display = to_intel_display(crtc);
3350
3351	if (!intel_cpu_transcoder_has_m2_n2(display, transcoder))
3352	return;
3353
3354	intel_get_m_n(display, m_n,
3355	PIPE_DATA_M2(display, transcoder),
3356	PIPE_DATA_N2(display, transcoder),
3357	PIPE_LINK_M2(display, transcoder),
3358	PIPE_LINK_N2(display, transcoder));
3359	}
3360
3361	static bool ilk_get_pipe_config(struct intel_crtc *crtc,
3362	struct intel_crtc_state *pipe_config)
3363	{
3364	struct intel_display *display = to_intel_display(crtc);
3365	enum intel_display_power_domain power_domain;
3366	enum transcoder cpu_transcoder = (enum transcoder)crtc->pipe;
3367	intel_wakeref_t wakeref;
3368	bool ret = false;
3369	u32 tmp;
3370
3371	power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
3372	wakeref = intel_display_power_get_if_enabled(display, domain: power_domain);
3373	if (!wakeref)
3374	return false;
3375
3376	tmp = intel_de_read(display, TRANSCONF(display, cpu_transcoder));
3377	if (!(tmp & TRANSCONF_ENABLE))
3378	goto out;
3379
3380	pipe_config->cpu_transcoder = cpu_transcoder;
3381
3382	switch (tmp & TRANSCONF_BPC_MASK) {
3383	case TRANSCONF_BPC_6:
3384	pipe_config->pipe_bpp = 18;
3385	break;
3386	case TRANSCONF_BPC_8:
3387	pipe_config->pipe_bpp = 24;
3388	break;
3389	case TRANSCONF_BPC_10:
3390	pipe_config->pipe_bpp = 30;
3391	break;
3392	case TRANSCONF_BPC_12:
3393	pipe_config->pipe_bpp = 36;
3394	break;
3395	default:
3396	break;
3397	}
3398
3399	if (tmp & TRANSCONF_COLOR_RANGE_SELECT)
3400	pipe_config->limited_color_range = true;
3401
3402	switch (tmp & TRANSCONF_OUTPUT_COLORSPACE_MASK) {
3403	case TRANSCONF_OUTPUT_COLORSPACE_YUV601:
3404	case TRANSCONF_OUTPUT_COLORSPACE_YUV709:
3405	pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
3406	break;
3407	default:
3408	pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
3409	break;
3410	}
3411
3412	pipe_config->sink_format = pipe_config->output_format;
3413
3414	pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_ILK, tmp);
3415
3416	pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1;
3417
3418	pipe_config->msa_timing_delay = REG_FIELD_GET(TRANSCONF_MSA_TIMING_DELAY_MASK, tmp);
3419
3420	intel_color_get_config(crtc_state: pipe_config);
3421
3422	pipe_config->pixel_multiplier = 1;
3423
3424	ilk_pch_get_config(crtc_state: pipe_config);
3425
3426	intel_get_transcoder_timings(crtc, pipe_config);
3427	intel_get_pipe_src_size(crtc, pipe_config);
3428
3429	ilk_pfit_get_config(crtc_state: pipe_config);
3430
3431	ret = true;
3432
3433	out:
3434	intel_display_power_put(display, domain: power_domain, wakeref);
3435
3436	return ret;
3437	}
3438
3439	static u8 joiner_pipes(struct intel_display *display)
3440	{
3441	u8 pipes;
3442
3443	if (DISPLAY_VER(display) >= 12)
3444	pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D);
3445	else if (DISPLAY_VER(display) >= 11)
3446	pipes = BIT(PIPE_B) | BIT(PIPE_C);
3447	else
3448	pipes = 0;
3449
3450	return pipes & DISPLAY_RUNTIME_INFO(display)->pipe_mask;
3451	}
3452
3453	static bool transcoder_ddi_func_is_enabled(struct intel_display *display,
3454	enum transcoder cpu_transcoder)
3455	{
3456	enum intel_display_power_domain power_domain;
3457	intel_wakeref_t wakeref;
3458	u32 tmp = 0;
3459
3460	power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
3461
3462	with_intel_display_power_if_enabled(display, power_domain, wakeref)
3463	tmp = intel_de_read(display,
3464	TRANS_DDI_FUNC_CTL(display, cpu_transcoder));
3465
3466	return tmp & TRANS_DDI_FUNC_ENABLE;
3467	}
3468
3469	static void enabled_uncompressed_joiner_pipes(struct intel_display *display,
3470	u8 *primary_pipes, u8 *secondary_pipes)
3471	{
3472	struct intel_crtc *crtc;
3473
3474	*primary_pipes = 0;
3475	*secondary_pipes = 0;
3476
3477	if (!HAS_UNCOMPRESSED_JOINER(display))
3478	return;
3479
3480	for_each_intel_crtc_in_pipe_mask(display->drm, crtc,
3481	joiner_pipes(display)) {
3482	enum intel_display_power_domain power_domain;
3483	enum pipe pipe = crtc->pipe;
3484	intel_wakeref_t wakeref;
3485
3486	power_domain = POWER_DOMAIN_PIPE(pipe);
3487	with_intel_display_power_if_enabled(display, power_domain, wakeref) {
3488	u32 tmp = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe));
3489
3490	if (tmp & UNCOMPRESSED_JOINER_PRIMARY)
3491	*primary_pipes |= BIT(pipe);
3492	if (tmp & UNCOMPRESSED_JOINER_SECONDARY)
3493	*secondary_pipes |= BIT(pipe);
3494	}
3495	}
3496	}
3497
3498	static void enabled_bigjoiner_pipes(struct intel_display *display,
3499	u8 *primary_pipes, u8 *secondary_pipes)
3500	{
3501	struct intel_crtc *crtc;
3502
3503	*primary_pipes = 0;
3504	*secondary_pipes = 0;
3505
3506	if (!HAS_BIGJOINER(display))
3507	return;
3508
3509	for_each_intel_crtc_in_pipe_mask(display->drm, crtc,
3510	joiner_pipes(display)) {
3511	enum intel_display_power_domain power_domain;
3512	enum pipe pipe = crtc->pipe;
3513	intel_wakeref_t wakeref;
3514
3515	power_domain = intel_dsc_power_domain(crtc, cpu_transcoder: (enum transcoder)pipe);
3516	with_intel_display_power_if_enabled(display, power_domain, wakeref) {
3517	u32 tmp = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe));
3518
3519	if (!(tmp & BIG_JOINER_ENABLE))
3520	continue;
3521
3522	if (tmp & PRIMARY_BIG_JOINER_ENABLE)
3523	*primary_pipes |= BIT(pipe);
3524	else
3525	*secondary_pipes |= BIT(pipe);
3526	}
3527	}
3528	}
3529
3530	static u8 expected_secondary_pipes(u8 primary_pipes, int num_pipes)
3531	{
3532	u8 secondary_pipes = 0;
3533
3534	for (int i = 1; i < num_pipes; i++)
3535	secondary_pipes |= primary_pipes << i;
3536
3537	return secondary_pipes;
3538	}
3539
3540	static u8 expected_uncompressed_joiner_secondary_pipes(u8 uncompjoiner_primary_pipes)
3541	{
3542	return expected_secondary_pipes(primary_pipes: uncompjoiner_primary_pipes, num_pipes: 2);
3543	}
3544
3545	static u8 expected_bigjoiner_secondary_pipes(u8 bigjoiner_primary_pipes)
3546	{
3547	return expected_secondary_pipes(primary_pipes: bigjoiner_primary_pipes, num_pipes: 2);
3548	}
3549
3550	static u8 get_joiner_primary_pipe(enum pipe pipe, u8 primary_pipes)
3551	{
3552	primary_pipes &= GENMASK(pipe, 0);
3553
3554	return primary_pipes ? BIT(fls(primary_pipes) - 1) : 0;
3555	}
3556
3557	static u8 expected_ultrajoiner_secondary_pipes(u8 ultrajoiner_primary_pipes)
3558	{
3559	return expected_secondary_pipes(primary_pipes: ultrajoiner_primary_pipes, num_pipes: 4);
3560	}
3561
3562	static u8 fixup_ultrajoiner_secondary_pipes(u8 ultrajoiner_primary_pipes,
3563	u8 ultrajoiner_secondary_pipes)
3564	{
3565	return ultrajoiner_secondary_pipes | ultrajoiner_primary_pipes << 3;
3566	}
3567
3568	static void enabled_ultrajoiner_pipes(struct intel_display *display,
3569	u8 *primary_pipes, u8 *secondary_pipes)
3570	{
3571	struct intel_crtc *crtc;
3572
3573	*primary_pipes = 0;
3574	*secondary_pipes = 0;
3575
3576	if (!HAS_ULTRAJOINER(display))
3577	return;
3578
3579	for_each_intel_crtc_in_pipe_mask(display->drm, crtc,
3580	joiner_pipes(display)) {
3581	enum intel_display_power_domain power_domain;
3582	enum pipe pipe = crtc->pipe;
3583	intel_wakeref_t wakeref;
3584
3585	power_domain = intel_dsc_power_domain(crtc, cpu_transcoder: (enum transcoder)pipe);
3586	with_intel_display_power_if_enabled(display, power_domain, wakeref) {
3587	u32 tmp = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe));
3588
3589	if (!(tmp & ULTRA_JOINER_ENABLE))
3590	continue;
3591
3592	if (tmp & PRIMARY_ULTRA_JOINER_ENABLE)
3593	*primary_pipes |= BIT(pipe);
3594	else
3595	*secondary_pipes |= BIT(pipe);
3596	}
3597	}
3598	}
3599
3600	static void enabled_joiner_pipes(struct intel_display *display,
3601	enum pipe pipe,
3602	u8 *primary_pipe, u8 *secondary_pipes)
3603	{
3604	u8 primary_ultrajoiner_pipes;
3605	u8 primary_uncompressed_joiner_pipes, primary_bigjoiner_pipes;
3606	u8 secondary_ultrajoiner_pipes;
3607	u8 secondary_uncompressed_joiner_pipes, secondary_bigjoiner_pipes;
3608	u8 ultrajoiner_pipes;
3609	u8 uncompressed_joiner_pipes, bigjoiner_pipes;
3610
3611	enabled_ultrajoiner_pipes(display, primary_pipes: &primary_ultrajoiner_pipes,
3612	secondary_pipes: &secondary_ultrajoiner_pipes);
3613	/*
3614	* For some strange reason the last pipe in the set of four
3615	* shouldn't have ultrajoiner enable bit set in hardware.
3616	* Set the bit anyway to make life easier.
3617	*/
3618	drm_WARN_ON(display->drm,
3619	expected_secondary_pipes(primary_ultrajoiner_pipes, 3) !=
3620	secondary_ultrajoiner_pipes);
3621	secondary_ultrajoiner_pipes =
3622	fixup_ultrajoiner_secondary_pipes(ultrajoiner_primary_pipes: primary_ultrajoiner_pipes,
3623	ultrajoiner_secondary_pipes: secondary_ultrajoiner_pipes);
3624
3625	drm_WARN_ON(display->drm, (primary_ultrajoiner_pipes & secondary_ultrajoiner_pipes) != 0);
3626
3627	enabled_uncompressed_joiner_pipes(display, primary_pipes: &primary_uncompressed_joiner_pipes,
3628	secondary_pipes: &secondary_uncompressed_joiner_pipes);
3629
3630	drm_WARN_ON(display->drm,
3631	(primary_uncompressed_joiner_pipes & secondary_uncompressed_joiner_pipes) != 0);
3632
3633	enabled_bigjoiner_pipes(display, primary_pipes: &primary_bigjoiner_pipes,
3634	secondary_pipes: &secondary_bigjoiner_pipes);
3635
3636	drm_WARN_ON(display->drm,
3637	(primary_bigjoiner_pipes & secondary_bigjoiner_pipes) != 0);
3638
3639	ultrajoiner_pipes = primary_ultrajoiner_pipes | secondary_ultrajoiner_pipes;
3640	uncompressed_joiner_pipes = primary_uncompressed_joiner_pipes |
3641	secondary_uncompressed_joiner_pipes;
3642	bigjoiner_pipes = primary_bigjoiner_pipes | secondary_bigjoiner_pipes;
3643
3644	drm_WARN(display->drm, (ultrajoiner_pipes & bigjoiner_pipes) != ultrajoiner_pipes,
3645	"Ultrajoiner pipes(%#x) should be bigjoiner pipes(%#x)\n",
3646	ultrajoiner_pipes, bigjoiner_pipes);
3647
3648	drm_WARN(display->drm, secondary_ultrajoiner_pipes !=
3649	expected_ultrajoiner_secondary_pipes(primary_ultrajoiner_pipes),
3650	"Wrong secondary ultrajoiner pipes(expected %#x, current %#x)\n",
3651	expected_ultrajoiner_secondary_pipes(primary_ultrajoiner_pipes),
3652	secondary_ultrajoiner_pipes);
3653
3654	drm_WARN(display->drm, (uncompressed_joiner_pipes & bigjoiner_pipes) != 0,
3655	"Uncompressed joiner pipes(%#x) and bigjoiner pipes(%#x) can't intersect\n",
3656	uncompressed_joiner_pipes, bigjoiner_pipes);
3657
3658	drm_WARN(display->drm, secondary_bigjoiner_pipes !=
3659	expected_bigjoiner_secondary_pipes(primary_bigjoiner_pipes),
3660	"Wrong secondary bigjoiner pipes(expected %#x, current %#x)\n",
3661	expected_bigjoiner_secondary_pipes(primary_bigjoiner_pipes),
3662	secondary_bigjoiner_pipes);
3663
3664	drm_WARN(display->drm, secondary_uncompressed_joiner_pipes !=
3665	expected_uncompressed_joiner_secondary_pipes(primary_uncompressed_joiner_pipes),
3666	"Wrong secondary uncompressed joiner pipes(expected %#x, current %#x)\n",
3667	expected_uncompressed_joiner_secondary_pipes(primary_uncompressed_joiner_pipes),
3668	secondary_uncompressed_joiner_pipes);
3669
3670	*primary_pipe = 0;
3671	*secondary_pipes = 0;
3672
3673	if (ultrajoiner_pipes & BIT(pipe)) {
3674	*primary_pipe = get_joiner_primary_pipe(pipe, primary_pipes: primary_ultrajoiner_pipes);
3675	*secondary_pipes = secondary_ultrajoiner_pipes &
3676	expected_ultrajoiner_secondary_pipes(ultrajoiner_primary_pipes: *primary_pipe);
3677
3678	drm_WARN(display->drm,
3679	expected_ultrajoiner_secondary_pipes(*primary_pipe) !=
3680	*secondary_pipes,
3681	"Wrong ultrajoiner secondary pipes for primary_pipe %#x (expected %#x, current %#x)\n",
3682	*primary_pipe,
3683	expected_ultrajoiner_secondary_pipes(*primary_pipe),
3684	*secondary_pipes);
3685	return;
3686	}
3687
3688	if (uncompressed_joiner_pipes & BIT(pipe)) {
3689	*primary_pipe = get_joiner_primary_pipe(pipe, primary_pipes: primary_uncompressed_joiner_pipes);
3690	*secondary_pipes = secondary_uncompressed_joiner_pipes &
3691	expected_uncompressed_joiner_secondary_pipes(uncompjoiner_primary_pipes: *primary_pipe);
3692
3693	drm_WARN(display->drm,
3694	expected_uncompressed_joiner_secondary_pipes(*primary_pipe) !=
3695	*secondary_pipes,
3696	"Wrong uncompressed joiner secondary pipes for primary_pipe %#x (expected %#x, current %#x)\n",
3697	*primary_pipe,
3698	expected_uncompressed_joiner_secondary_pipes(*primary_pipe),
3699	*secondary_pipes);
3700	return;
3701	}
3702
3703	if (bigjoiner_pipes & BIT(pipe)) {
3704	*primary_pipe = get_joiner_primary_pipe(pipe, primary_pipes: primary_bigjoiner_pipes);
3705	*secondary_pipes = secondary_bigjoiner_pipes &
3706	expected_bigjoiner_secondary_pipes(bigjoiner_primary_pipes: *primary_pipe);
3707
3708	drm_WARN(display->drm,
3709	expected_bigjoiner_secondary_pipes(*primary_pipe) !=
3710	*secondary_pipes,
3711	"Wrong bigjoiner secondary pipes for primary_pipe %#x (expected %#x, current %#x)\n",
3712	*primary_pipe,
3713	expected_bigjoiner_secondary_pipes(*primary_pipe),
3714	*secondary_pipes);
3715	return;
3716	}
3717	}
3718
3719	static u8 hsw_panel_transcoders(struct intel_display *display)
3720	{
3721	u8 panel_transcoder_mask = BIT(TRANSCODER_EDP);
3722
3723	if (DISPLAY_VER(display) >= 11)
3724	panel_transcoder_mask |= BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1);
3725
3726	return panel_transcoder_mask;
3727	}
3728
3729	static u8 hsw_enabled_transcoders(struct intel_crtc *crtc)
3730	{
3731	struct intel_display *display = to_intel_display(crtc);
3732	u8 panel_transcoder_mask = hsw_panel_transcoders(display);
3733	enum transcoder cpu_transcoder;
3734	u8 primary_pipe, secondary_pipes;
3735	u8 enabled_transcoders = 0;
3736
3737	/*
3738	* XXX: Do intel_display_power_get_if_enabled before reading this (for
3739	* consistency and less surprising code; it's in always on power).
3740	*/
3741	for_each_cpu_transcoder_masked(display, cpu_transcoder,
3742	panel_transcoder_mask) {
3743	enum intel_display_power_domain power_domain;
3744	intel_wakeref_t wakeref;
3745	enum pipe trans_pipe;
3746	u32 tmp = 0;
3747
3748	power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
3749	with_intel_display_power_if_enabled(display, power_domain, wakeref)
3750	tmp = intel_de_read(display,
3751	TRANS_DDI_FUNC_CTL(display, cpu_transcoder));
3752
3753	if (!(tmp & TRANS_DDI_FUNC_ENABLE))
3754	continue;
3755
3756	switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
3757	default:
3758	drm_WARN(display->drm, 1,
3759	"unknown pipe linked to transcoder %s\n",
3760	transcoder_name(cpu_transcoder));
3761	fallthrough;
3762	case TRANS_DDI_EDP_INPUT_A_ONOFF:
3763	case TRANS_DDI_EDP_INPUT_A_ON:
3764	trans_pipe = PIPE_A;
3765	break;
3766	case TRANS_DDI_EDP_INPUT_B_ONOFF:
3767	trans_pipe = PIPE_B;
3768	break;
3769	case TRANS_DDI_EDP_INPUT_C_ONOFF:
3770	trans_pipe = PIPE_C;
3771	break;
3772	case TRANS_DDI_EDP_INPUT_D_ONOFF:
3773	trans_pipe = PIPE_D;
3774	break;
3775	}
3776
3777	if (trans_pipe == crtc->pipe)
3778	enabled_transcoders |= BIT(cpu_transcoder);
3779	}
3780
3781	/* single pipe or joiner primary */
3782	cpu_transcoder = (enum transcoder) crtc->pipe;
3783	if (transcoder_ddi_func_is_enabled(display, cpu_transcoder))
3784	enabled_transcoders |= BIT(cpu_transcoder);
3785
3786	/* joiner secondary -> consider the primary pipe's transcoder as well */
3787	enabled_joiner_pipes(display, pipe: crtc->pipe, primary_pipe: &primary_pipe, secondary_pipes: &secondary_pipes);
3788	if (secondary_pipes & BIT(crtc->pipe)) {
3789	cpu_transcoder = (enum transcoder)ffs(primary_pipe) - 1;
3790	if (transcoder_ddi_func_is_enabled(display, cpu_transcoder))
3791	enabled_transcoders |= BIT(cpu_transcoder);
3792	}
3793
3794	return enabled_transcoders;
3795	}
3796
3797	static bool has_edp_transcoders(u8 enabled_transcoders)
3798	{
3799	return enabled_transcoders & BIT(TRANSCODER_EDP);
3800	}
3801
3802	static bool has_dsi_transcoders(u8 enabled_transcoders)
3803	{
3804	return enabled_transcoders & (BIT(TRANSCODER_DSI_0) |
3805	BIT(TRANSCODER_DSI_1));
3806	}
3807
3808	static bool has_pipe_transcoders(u8 enabled_transcoders)
3809	{
3810	return enabled_transcoders & ~(BIT(TRANSCODER_EDP) |
3811	BIT(TRANSCODER_DSI_0) |
3812	BIT(TRANSCODER_DSI_1));
3813	}
3814
3815	static void assert_enabled_transcoders(struct intel_display *display,
3816	u8 enabled_transcoders)
3817	{
3818	/* Only one type of transcoder please */
3819	drm_WARN_ON(display->drm,
3820	has_edp_transcoders(enabled_transcoders) +
3821	has_dsi_transcoders(enabled_transcoders) +
3822	has_pipe_transcoders(enabled_transcoders) > 1);
3823
3824	/* Only DSI transcoders can be ganged */
3825	drm_WARN_ON(display->drm,
3826	!has_dsi_transcoders(enabled_transcoders) &&
3827	!is_power_of_2(enabled_transcoders));
3828	}
3829
3830	static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
3831	struct intel_crtc_state *pipe_config,
3832	struct intel_display_power_domain_set *power_domain_set)
3833	{
3834	struct intel_display *display = to_intel_display(crtc);
3835	unsigned long enabled_transcoders;
3836	u32 tmp;
3837
3838	enabled_transcoders = hsw_enabled_transcoders(crtc);
3839	if (!enabled_transcoders)
3840	return false;
3841
3842	assert_enabled_transcoders(display, enabled_transcoders);
3843
3844	/*
3845	* With the exception of DSI we should only ever have
3846	* a single enabled transcoder. With DSI let's just
3847	* pick the first one.
3848	*/
3849	pipe_config->cpu_transcoder = ffs(enabled_transcoders) - 1;
3850
3851	if (!intel_display_power_get_in_set_if_enabled(display, power_domain_set,
3852	POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
3853	return false;
3854
3855	if (hsw_panel_transcoders(display) & BIT(pipe_config->cpu_transcoder)) {
3856	tmp = intel_de_read(display,
3857	TRANS_DDI_FUNC_CTL(display, pipe_config->cpu_transcoder));
3858
3859	if ((tmp & TRANS_DDI_EDP_INPUT_MASK) == TRANS_DDI_EDP_INPUT_A_ONOFF)
3860	pipe_config->pch_pfit.force_thru = true;
3861	}
3862
3863	tmp = intel_de_read(display,
3864	TRANSCONF(display, pipe_config->cpu_transcoder));
3865
3866	return tmp & TRANSCONF_ENABLE;
3867	}
3868
3869	static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
3870	struct intel_crtc_state *pipe_config,
3871	struct intel_display_power_domain_set *power_domain_set)
3872	{
3873	struct intel_display *display = to_intel_display(crtc);
3874	enum transcoder cpu_transcoder;
3875	enum port port;
3876	u32 tmp;
3877
3878	for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
3879	if (port == PORT_A)
3880	cpu_transcoder = TRANSCODER_DSI_A;
3881	else
3882	cpu_transcoder = TRANSCODER_DSI_C;
3883
3884	if (!intel_display_power_get_in_set_if_enabled(display, power_domain_set,
3885	POWER_DOMAIN_TRANSCODER(cpu_transcoder)))
3886	continue;
3887
3888	/*
3889	* The PLL needs to be enabled with a valid divider
3890	* configuration, otherwise accessing DSI registers will hang
3891	* the machine. See BSpec North Display Engine
3892	* registers/MIPI[BXT]. We can break out here early, since we
3893	* need the same DSI PLL to be enabled for both DSI ports.
3894	*/
3895	if (!bxt_dsi_pll_is_enabled(display))
3896	break;
3897
3898	/* XXX: this works for video mode only */
3899	tmp = intel_de_read(display, BXT_MIPI_PORT_CTRL(port));
3900	if (!(tmp & DPI_ENABLE))
3901	continue;
3902
3903	tmp = intel_de_read(display, MIPI_CTRL(display, port));
3904	if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
3905	continue;
3906
3907	pipe_config->cpu_transcoder = cpu_transcoder;
3908	break;
3909	}
3910
3911	return transcoder_is_dsi(transcoder: pipe_config->cpu_transcoder);
3912	}
3913
3914	static void intel_joiner_get_config(struct intel_crtc_state *crtc_state)
3915	{
3916	struct intel_display *display = to_intel_display(crtc_state);
3917	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3918	u8 primary_pipe, secondary_pipes;
3919	enum pipe pipe = crtc->pipe;
3920
3921	enabled_joiner_pipes(display, pipe, primary_pipe: &primary_pipe, secondary_pipes: &secondary_pipes);
3922
3923	if (((primary_pipe | secondary_pipes) & BIT(pipe)) == 0)
3924	return;
3925
3926	crtc_state->joiner_pipes = primary_pipe | secondary_pipes;
3927	}
3928
3929	static bool hsw_get_pipe_config(struct intel_crtc *crtc,
3930	struct intel_crtc_state *pipe_config)
3931	{
3932	struct intel_display *display = to_intel_display(crtc);
3933	bool active;
3934	u32 tmp;
3935
3936	if (!intel_display_power_get_in_set_if_enabled(display, power_domain_set: &crtc->hw_readout_power_domains,
3937	POWER_DOMAIN_PIPE(crtc->pipe)))
3938	return false;
3939
3940	active = hsw_get_transcoder_state(crtc, pipe_config, power_domain_set: &crtc->hw_readout_power_domains);
3941
3942	if ((display->platform.geminilake || display->platform.broxton) &&
3943	bxt_get_dsi_transcoder_state(crtc, pipe_config, power_domain_set: &crtc->hw_readout_power_domains)) {
3944	drm_WARN_ON(display->drm, active);
3945	active = true;
3946	}
3947
3948	if (!active)
3949	goto out;
3950
3951	intel_joiner_get_config(crtc_state: pipe_config);
3952	intel_dsc_get_config(crtc_state: pipe_config);
3953
3954	/* intel_vrr_get_config() depends on .framestart_delay */
3955	if (!transcoder_is_dsi(transcoder: pipe_config->cpu_transcoder)) {
3956	tmp = intel_de_read(display, CHICKEN_TRANS(display, pipe_config->cpu_transcoder));
3957
3958	pipe_config->framestart_delay = REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1;
3959	} else {
3960	/* no idea if this is correct */
3961	pipe_config->framestart_delay = 1;
3962	}
3963
3964	/*
3965	* intel_vrr_get_config() depends on TRANS_SET_CONTEXT_LATENCY
3966	* readout done by intel_get_transcoder_timings().
3967	*/
3968	if (!transcoder_is_dsi(transcoder: pipe_config->cpu_transcoder) ||
3969	DISPLAY_VER(display) >= 11)
3970	intel_get_transcoder_timings(crtc, pipe_config);
3971
3972	if (transcoder_has_vrr(crtc_state: pipe_config))
3973	intel_vrr_get_config(crtc_state: pipe_config);
3974
3975	intel_get_pipe_src_size(crtc, pipe_config);
3976
3977	if (display->platform.haswell) {
3978	u32 tmp = intel_de_read(display,
3979	TRANSCONF(display, pipe_config->cpu_transcoder));
3980
3981	if (tmp & TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW)
3982	pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
3983	else
3984	pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
3985	} else {
3986	pipe_config->output_format =
3987	bdw_get_pipe_misc_output_format(crtc);
3988	}
3989
3990	pipe_config->sink_format = pipe_config->output_format;
3991
3992	intel_color_get_config(crtc_state: pipe_config);
3993
3994	tmp = intel_de_read(display, WM_LINETIME(crtc->pipe));
3995	pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp);
3996	if (display->platform.broadwell || display->platform.haswell)
3997	pipe_config->ips_linetime =
3998	REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp);
3999
4000	if (intel_display_power_get_in_set_if_enabled(display, power_domain_set: &crtc->hw_readout_power_domains,
4001	POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe))) {
4002	if (DISPLAY_VER(display) >= 9)
4003	skl_scaler_get_config(crtc_state: pipe_config);
4004	else
4005	ilk_pfit_get_config(crtc_state: pipe_config);
4006	}
4007
4008	hsw_ips_get_config(crtc_state: pipe_config);
4009
4010	if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
4011	!transcoder_is_dsi(transcoder: pipe_config->cpu_transcoder)) {
4012	pipe_config->pixel_multiplier =
4013	intel_de_read(display,
4014	TRANS_MULT(display, pipe_config->cpu_transcoder)) + 1;
4015	} else {
4016	pipe_config->pixel_multiplier = 1;
4017	}
4018
4019	out:
4020	intel_display_power_put_all_in_set(display, power_domain_set: &crtc->hw_readout_power_domains);
4021
4022	return active;
4023	}
4024
4025	bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state)
4026	{
4027	struct intel_display *display = to_intel_display(crtc_state);
4028	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4029
4030	if (!display->funcs.display->get_pipe_config(crtc, crtc_state))
4031	return false;
4032
4033	crtc_state->hw.active = true;
4034
4035	intel_crtc_readout_derived_state(crtc_state);
4036
4037	return true;
4038	}
4039
4040	int intel_dotclock_calculate(int link_freq,
4041	const struct intel_link_m_n *m_n)
4042	{
4043	/*
4044	* The calculation for the data clock -> pixel clock is:
4045	* pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
4046	* But we want to avoid losing precision if possible, so:
4047	* pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
4048	*
4049	* and for link freq (10kbs units) -> pixel clock it is:
4050	* link_symbol_clock = link_freq * 10 / link_symbol_size
4051	* pixel_clock = (m * link_symbol_clock) / n
4052	* or for more precision:
4053	* pixel_clock = (m * link_freq * 10) / (n * link_symbol_size)
4054	*/
4055
4056	if (!m_n->link_n)
4057	return 0;
4058
4059	return DIV_ROUND_UP_ULL(mul_u32_u32(m_n->link_m, link_freq * 10),
4060	m_n->link_n * intel_dp_link_symbol_size(link_freq));
4061	}
4062
4063	int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config)
4064	{
4065	int dotclock;
4066
4067	if (intel_crtc_has_dp_encoder(crtc_state: pipe_config))
4068	dotclock = intel_dotclock_calculate(link_freq: pipe_config->port_clock,
4069	m_n: &pipe_config->dp_m_n);
4070	else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24)
4071	dotclock = DIV_ROUND_CLOSEST(pipe_config->port_clock * 24,
4072	pipe_config->pipe_bpp);
4073	else
4074	dotclock = pipe_config->port_clock;
4075
4076	if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
4077	!intel_crtc_has_dp_encoder(crtc_state: pipe_config))
4078	dotclock *= 2;
4079
4080	if (pipe_config->pixel_multiplier)
4081	dotclock /= pipe_config->pixel_multiplier;
4082
4083	return dotclock;
4084	}
4085
4086	/* Returns the currently programmed mode of the given encoder. */
4087	struct drm_display_mode *
4088	intel_encoder_current_mode(struct intel_encoder *encoder)
4089	{
4090	struct intel_display *display = to_intel_display(encoder);
4091	struct intel_crtc_state *crtc_state;
4092	struct drm_display_mode *mode;
4093	struct intel_crtc *crtc;
4094	enum pipe pipe;
4095
4096	if (!encoder->get_hw_state(encoder, &pipe))
4097	return NULL;
4098
4099	crtc = intel_crtc_for_pipe(display, pipe);
4100
4101	mode = kzalloc(sizeof(*mode), GFP_KERNEL);
4102	if (!mode)
4103	return NULL;
4104
4105	crtc_state = intel_crtc_state_alloc(crtc);
4106	if (!crtc_state) {
4107	kfree(objp: mode);
4108	return NULL;
4109	}
4110
4111	if (!intel_crtc_get_pipe_config(crtc_state)) {
4112	intel_crtc_destroy_state(crtc: &crtc->base, state: &crtc_state->uapi);
4113	kfree(objp: mode);
4114	return NULL;
4115	}
4116
4117	intel_encoder_get_config(encoder, crtc_state);
4118
4119	intel_mode_from_crtc_timings(mode, timings: &crtc_state->hw.adjusted_mode);
4120
4121	intel_crtc_destroy_state(crtc: &crtc->base, state: &crtc_state->uapi);
4122
4123	return mode;
4124	}
4125
4126	static bool encoders_cloneable(const struct intel_encoder *a,
4127	const struct intel_encoder *b)
4128	{
4129	/* masks could be asymmetric, so check both ways */
4130	return a == b || (a->cloneable & BIT(b->type) &&
4131	b->cloneable & BIT(a->type));
4132	}
4133
4134	static bool check_single_encoder_cloning(struct intel_atomic_state *state,
4135	struct intel_crtc *crtc,
4136	struct intel_encoder *encoder)
4137	{
4138	struct intel_encoder *source_encoder;
4139	struct drm_connector *connector;
4140	struct drm_connector_state *connector_state;
4141	int i;
4142
4143	for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
4144	if (connector_state->crtc != &crtc->base)
4145	continue;
4146
4147	source_encoder =
4148	to_intel_encoder(connector_state->best_encoder);
4149	if (!encoders_cloneable(a: encoder, b: source_encoder))
4150	return false;
4151	}
4152
4153	return true;
4154	}
4155
4156	static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state)
4157	{
4158	const struct drm_display_mode *pipe_mode =
4159	&crtc_state->hw.pipe_mode;
4160	int linetime_wm;
4161
4162	if (!crtc_state->hw.enable)
4163	return 0;
4164
4165	linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8,
4166	pipe_mode->crtc_clock);
4167
4168	return min(linetime_wm, 0x1ff);
4169	}
4170
4171	static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state,
4172	const struct intel_cdclk_state *cdclk_state)
4173	{
4174	const struct drm_display_mode *pipe_mode =
4175	&crtc_state->hw.pipe_mode;
4176	int linetime_wm;
4177
4178	if (!crtc_state->hw.enable)
4179	return 0;
4180
4181	linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8,
4182	intel_cdclk_logical(cdclk_state));
4183
4184	return min(linetime_wm, 0x1ff);
4185	}
4186
4187	static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state)
4188	{
4189	struct intel_display *display = to_intel_display(crtc_state);
4190	const struct drm_display_mode *pipe_mode =
4191	&crtc_state->hw.pipe_mode;
4192	int linetime_wm;
4193
4194	if (!crtc_state->hw.enable)
4195	return 0;
4196
4197	linetime_wm = DIV_ROUND_UP(pipe_mode->crtc_htotal * 1000 * 8,
4198	crtc_state->pixel_rate);
4199
4200	/* Display WA #1135: BXT:ALL GLK:ALL */
4201	if ((display->platform.geminilake || display->platform.broxton) &&
4202	skl_watermark_ipc_enabled(display))
4203	linetime_wm /= 2;
4204
4205	return min(linetime_wm, 0x1ff);
4206	}
4207
4208	static int hsw_compute_linetime_wm(struct intel_atomic_state *state,
4209	struct intel_crtc *crtc)
4210	{
4211	struct intel_display *display = to_intel_display(state);
4212	struct intel_crtc_state *crtc_state =
4213	intel_atomic_get_new_crtc_state(state, crtc);
4214	const struct intel_cdclk_state *cdclk_state;
4215
4216	if (DISPLAY_VER(display) >= 9)
4217	crtc_state->linetime = skl_linetime_wm(crtc_state);
4218	else
4219	crtc_state->linetime = hsw_linetime_wm(crtc_state);
4220
4221	if (!hsw_crtc_supports_ips(crtc))
4222	return 0;
4223
4224	cdclk_state = intel_atomic_get_cdclk_state(state);
4225	if (IS_ERR(ptr: cdclk_state))
4226	return PTR_ERR(ptr: cdclk_state);
4227
4228	crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state,
4229	cdclk_state);
4230
4231	return 0;
4232	}
4233
4234	static int intel_crtc_atomic_check(struct intel_atomic_state *state,
4235	struct intel_crtc *crtc)
4236	{
4237	struct intel_display *display = to_intel_display(crtc);
4238	struct intel_crtc_state *crtc_state =
4239	intel_atomic_get_new_crtc_state(state, crtc);
4240	int ret;
4241
4242	if (DISPLAY_VER(display) < 5 && !display->platform.g4x &&
4243	intel_crtc_needs_modeset(crtc_state) &&
4244	!crtc_state->hw.active)
4245	crtc_state->update_wm_post = true;
4246
4247	if (intel_crtc_needs_modeset(crtc_state)) {
4248	ret = intel_dpll_crtc_get_dpll(state, crtc);
4249	if (ret)
4250	return ret;
4251	}
4252
4253	ret = intel_color_check(state, crtc);
4254	if (ret)
4255	return ret;
4256
4257	ret = intel_wm_compute(state, crtc);
4258	if (ret) {
4259	drm_dbg_kms(display->drm,
4260	"[CRTC:%d:%s] watermarks are invalid\n",
4261	crtc->base.base.id, crtc->base.name);
4262	return ret;
4263	}
4264
4265	ret = intel_casf_compute_config(crtc_state);
4266	if (ret)
4267	return ret;
4268
4269	if (DISPLAY_VER(display) >= 9) {
4270	if (intel_crtc_needs_modeset(crtc_state) ||
4271	intel_crtc_needs_fastset(crtc_state) ||
4272	intel_casf_needs_scaler(crtc_state)) {
4273	ret = skl_update_scaler_crtc(crtc_state);
4274	if (ret)
4275	return ret;
4276	}
4277
4278	ret = intel_atomic_setup_scalers(state, crtc);
4279	if (ret)
4280	return ret;
4281	}
4282
4283	if (HAS_IPS(display)) {
4284	ret = hsw_ips_compute_config(state, crtc);
4285	if (ret)
4286	return ret;
4287	}
4288
4289	if (DISPLAY_VER(display) >= 9 ||
4290	display->platform.broadwell || display->platform.haswell) {
4291	ret = hsw_compute_linetime_wm(state, crtc);
4292	if (ret)
4293	return ret;
4294
4295	}
4296
4297	ret = intel_psr2_sel_fetch_update(state, crtc);
4298	if (ret)
4299	return ret;
4300
4301	return 0;
4302	}
4303
4304	static int
4305	compute_sink_pipe_bpp(const struct drm_connector_state *conn_state,
4306	struct intel_crtc_state *crtc_state)
4307	{
4308	struct intel_display *display = to_intel_display(crtc_state);
4309	struct drm_connector *connector = conn_state->connector;
4310	const struct drm_display_info *info = &connector->display_info;
4311	int bpp;
4312
4313	switch (conn_state->max_bpc) {
4314	case 6 ... 7:
4315	bpp = 6 * 3;
4316	break;
4317	case 8 ... 9:
4318	bpp = 8 * 3;
4319	break;
4320	case 10 ... 11:
4321	bpp = 10 * 3;
4322	break;
4323	case 12 ... 16:
4324	bpp = 12 * 3;
4325	break;
4326	default:
4327	MISSING_CASE(conn_state->max_bpc);
4328	return -EINVAL;
4329	}
4330
4331	if (bpp < crtc_state->pipe_bpp) {
4332	drm_dbg_kms(display->drm,
4333	"[CONNECTOR:%d:%s] Limiting display bpp to %d "
4334	"(EDID bpp %d, max requested bpp %d, max platform bpp %d)\n",
4335	connector->base.id, connector->name,
4336	bpp, 3 * info->bpc,
4337	3 * conn_state->max_requested_bpc,
4338	crtc_state->pipe_bpp);
4339
4340	crtc_state->pipe_bpp = bpp;
4341	}
4342
4343	return 0;
4344	}
4345
4346	int intel_display_min_pipe_bpp(void)
4347	{
4348	return 6 * 3;
4349	}
4350
4351	int intel_display_max_pipe_bpp(struct intel_display *display)
4352	{
4353	if (display->platform.g4x || display->platform.valleyview ||
4354	display->platform.cherryview)
4355	return 10*3;
4356	else if (DISPLAY_VER(display) >= 5)
4357	return 12*3;
4358	else
4359	return 8*3;
4360	}
4361
4362	static int
4363	compute_baseline_pipe_bpp(struct intel_atomic_state *state,
4364	struct intel_crtc *crtc)
4365	{
4366	struct intel_display *display = to_intel_display(crtc);
4367	struct intel_crtc_state *crtc_state =
4368	intel_atomic_get_new_crtc_state(state, crtc);
4369	struct drm_connector *connector;
4370	struct drm_connector_state *connector_state;
4371	int i;
4372
4373	crtc_state->pipe_bpp = intel_display_max_pipe_bpp(display);
4374
4375	/* Clamp display bpp to connector max bpp */
4376	for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
4377	int ret;
4378
4379	if (connector_state->crtc != &crtc->base)
4380	continue;
4381
4382	ret = compute_sink_pipe_bpp(conn_state: connector_state, crtc_state);
4383	if (ret)
4384	return ret;
4385	}
4386
4387	return 0;
4388	}
4389
4390	static bool check_digital_port_conflicts(struct intel_atomic_state *state)
4391	{
4392	struct intel_display *display = to_intel_display(state);
4393	struct drm_connector *connector;
4394	struct drm_connector_list_iter conn_iter;
4395	unsigned int used_ports = 0;
4396	unsigned int used_mst_ports = 0;
4397	bool ret = true;
4398
4399	/*
4400	* We're going to peek into connector->state,
4401	* hence connection_mutex must be held.
4402	*/
4403	drm_modeset_lock_assert_held(lock: &display->drm->mode_config.connection_mutex);
4404
4405	/*
4406	* Walk the connector list instead of the encoder
4407	* list to detect the problem on ddi platforms
4408	* where there's just one encoder per digital port.
4409	*/
4410	drm_connector_list_iter_begin(dev: display->drm, iter: &conn_iter);
4411	drm_for_each_connector_iter(connector, &conn_iter) {
4412	struct drm_connector_state *connector_state;
4413	struct intel_encoder *encoder;
4414
4415	connector_state =
4416	drm_atomic_get_new_connector_state(state: &state->base,
4417	connector);
4418	if (!connector_state)
4419	connector_state = connector->state;
4420
4421	if (!connector_state->best_encoder)
4422	continue;
4423
4424	encoder = to_intel_encoder(connector_state->best_encoder);
4425
4426	drm_WARN_ON(display->drm, !connector_state->crtc);
4427
4428	switch (encoder->type) {
4429	case INTEL_OUTPUT_DDI:
4430	if (drm_WARN_ON(display->drm, !HAS_DDI(display)))
4431	break;
4432	fallthrough;
4433	case INTEL_OUTPUT_DP:
4434	case INTEL_OUTPUT_HDMI:
4435	case INTEL_OUTPUT_EDP:
4436	/* the same port mustn't appear more than once */
4437	if (used_ports & BIT(encoder->port))
4438	ret = false;
4439
4440	used_ports |= BIT(encoder->port);
4441	break;
4442	case INTEL_OUTPUT_DP_MST:
4443	used_mst_ports |=
4444	1 << encoder->port;
4445	break;
4446	default:
4447	break;
4448	}
4449	}
4450	drm_connector_list_iter_end(iter: &conn_iter);
4451
4452	/* can't mix MST and SST/HDMI on the same port */
4453	if (used_ports & used_mst_ports)
4454	return false;
4455
4456	return ret;
4457	}
4458
4459	static void
4460	intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_atomic_state *state,
4461	struct intel_crtc *crtc)
4462	{
4463	struct intel_crtc_state *crtc_state =
4464	intel_atomic_get_new_crtc_state(state, crtc);
4465
4466	WARN_ON(intel_crtc_is_joiner_secondary(crtc_state));
4467
4468	drm_property_replace_blob(blob: &crtc_state->hw.degamma_lut,
4469	new_blob: crtc_state->uapi.degamma_lut);
4470	drm_property_replace_blob(blob: &crtc_state->hw.gamma_lut,
4471	new_blob: crtc_state->uapi.gamma_lut);
4472	drm_property_replace_blob(blob: &crtc_state->hw.ctm,
4473	new_blob: crtc_state->uapi.ctm);
4474	}
4475
4476	static void
4477	intel_crtc_copy_uapi_to_hw_state_modeset(struct intel_atomic_state *state,
4478	struct intel_crtc *crtc)
4479	{
4480	struct intel_crtc_state *crtc_state =
4481	intel_atomic_get_new_crtc_state(state, crtc);
4482
4483	WARN_ON(intel_crtc_is_joiner_secondary(crtc_state));
4484
4485	crtc_state->hw.enable = crtc_state->uapi.enable;
4486	crtc_state->hw.active = crtc_state->uapi.active;
4487	drm_mode_copy(dst: &crtc_state->hw.mode,
4488	src: &crtc_state->uapi.mode);
4489	drm_mode_copy(dst: &crtc_state->hw.adjusted_mode,
4490	src: &crtc_state->uapi.adjusted_mode);
4491	crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter;
4492
4493	intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc);
4494	}
4495
4496	static void
4497	copy_joiner_crtc_state_nomodeset(struct intel_atomic_state *state,
4498	struct intel_crtc *secondary_crtc)
4499	{
4500	struct intel_crtc_state *secondary_crtc_state =
4501	intel_atomic_get_new_crtc_state(state, crtc: secondary_crtc);
4502	struct intel_crtc *primary_crtc = intel_primary_crtc(crtc_state: secondary_crtc_state);
4503	const struct intel_crtc_state *primary_crtc_state =
4504	intel_atomic_get_new_crtc_state(state, crtc: primary_crtc);
4505
4506	drm_property_replace_blob(blob: &secondary_crtc_state->hw.degamma_lut,
4507	new_blob: primary_crtc_state->hw.degamma_lut);
4508	drm_property_replace_blob(blob: &secondary_crtc_state->hw.gamma_lut,
4509	new_blob: primary_crtc_state->hw.gamma_lut);
4510	drm_property_replace_blob(blob: &secondary_crtc_state->hw.ctm,
4511	new_blob: primary_crtc_state->hw.ctm);
4512
4513	secondary_crtc_state->uapi.color_mgmt_changed = primary_crtc_state->uapi.color_mgmt_changed;
4514	}
4515
4516	static int
4517	copy_joiner_crtc_state_modeset(struct intel_atomic_state *state,
4518	struct intel_crtc *secondary_crtc)
4519	{
4520	struct intel_crtc_state *secondary_crtc_state =
4521	intel_atomic_get_new_crtc_state(state, crtc: secondary_crtc);
4522	struct intel_crtc *primary_crtc = intel_primary_crtc(crtc_state: secondary_crtc_state);
4523	const struct intel_crtc_state *primary_crtc_state =
4524	intel_atomic_get_new_crtc_state(state, crtc: primary_crtc);
4525	struct intel_crtc_state *saved_state;
4526
4527	WARN_ON(primary_crtc_state->joiner_pipes !=
4528	secondary_crtc_state->joiner_pipes);
4529
4530	saved_state = kmemdup(primary_crtc_state, sizeof(*saved_state), GFP_KERNEL);
4531	if (!saved_state)
4532	return -ENOMEM;
4533
4534	/* preserve some things from the slave's original crtc state */
4535	saved_state->uapi = secondary_crtc_state->uapi;
4536	saved_state->scaler_state = secondary_crtc_state->scaler_state;
4537	saved_state->intel_dpll = secondary_crtc_state->intel_dpll;
4538	saved_state->crc_enabled = secondary_crtc_state->crc_enabled;
4539
4540	intel_crtc_free_hw_state(crtc_state: secondary_crtc_state);
4541	if (secondary_crtc_state->dp_tunnel_ref.tunnel)
4542	drm_dp_tunnel_ref_put(tunnel_ref: &secondary_crtc_state->dp_tunnel_ref);
4543	memcpy(secondary_crtc_state, saved_state, sizeof(*secondary_crtc_state));
4544	kfree(objp: saved_state);
4545
4546	/* Re-init hw state */
4547	memset(&secondary_crtc_state->hw, 0, sizeof(secondary_crtc_state->hw));
4548	secondary_crtc_state->hw.enable = primary_crtc_state->hw.enable;
4549	secondary_crtc_state->hw.active = primary_crtc_state->hw.active;
4550	drm_mode_copy(dst: &secondary_crtc_state->hw.mode,
4551	src: &primary_crtc_state->hw.mode);
4552	drm_mode_copy(dst: &secondary_crtc_state->hw.pipe_mode,
4553	src: &primary_crtc_state->hw.pipe_mode);
4554	drm_mode_copy(dst: &secondary_crtc_state->hw.adjusted_mode,
4555	src: &primary_crtc_state->hw.adjusted_mode);
4556	secondary_crtc_state->hw.scaling_filter = primary_crtc_state->hw.scaling_filter;
4557
4558	if (primary_crtc_state->dp_tunnel_ref.tunnel)
4559	drm_dp_tunnel_ref_get(tunnel: primary_crtc_state->dp_tunnel_ref.tunnel,
4560	tunnel_ref: &secondary_crtc_state->dp_tunnel_ref);
4561
4562	copy_joiner_crtc_state_nomodeset(state, secondary_crtc);
4563
4564	secondary_crtc_state->uapi.mode_changed = primary_crtc_state->uapi.mode_changed;
4565	secondary_crtc_state->uapi.connectors_changed = primary_crtc_state->uapi.connectors_changed;
4566	secondary_crtc_state->uapi.active_changed = primary_crtc_state->uapi.active_changed;
4567
4568	WARN_ON(primary_crtc_state->joiner_pipes !=
4569	secondary_crtc_state->joiner_pipes);
4570
4571	return 0;
4572	}
4573
4574	static int
4575	intel_crtc_prepare_cleared_state(struct intel_atomic_state *state,
4576	struct intel_crtc *crtc)
4577	{
4578	struct intel_display *display = to_intel_display(state);
4579	struct intel_crtc_state *crtc_state =
4580	intel_atomic_get_new_crtc_state(state, crtc);
4581	struct intel_crtc_state *saved_state;
4582
4583	saved_state = intel_crtc_state_alloc(crtc);
4584	if (!saved_state)
4585	return -ENOMEM;
4586
4587	/* free the old crtc_state->hw members */
4588	intel_crtc_free_hw_state(crtc_state);
4589
4590	intel_dp_tunnel_atomic_clear_stream_bw(state, crtc_state);
4591
4592	/* FIXME: before the switch to atomic started, a new pipe_config was
4593	* kzalloc'd. Code that depends on any field being zero should be
4594	* fixed, so that the crtc_state can be safely duplicated. For now,
4595	* only fields that are know to not cause problems are preserved. */
4596
4597	saved_state->uapi = crtc_state->uapi;
4598	saved_state->inherited = crtc_state->inherited;
4599	saved_state->scaler_state = crtc_state->scaler_state;
4600	saved_state->intel_dpll = crtc_state->intel_dpll;
4601	saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
4602	memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls,
4603	sizeof(saved_state->icl_port_dplls));
4604	saved_state->crc_enabled = crtc_state->crc_enabled;
4605	if (display->platform.g4x ||
4606	display->platform.valleyview || display->platform.cherryview)
4607	saved_state->wm = crtc_state->wm;
4608
4609	memcpy(crtc_state, saved_state, sizeof(*crtc_state));
4610	kfree(objp: saved_state);
4611
4612	intel_crtc_copy_uapi_to_hw_state_modeset(state, crtc);
4613
4614	return 0;
4615	}
4616
4617	static int
4618	intel_modeset_pipe_config(struct intel_atomic_state *state,
4619	struct intel_crtc *crtc,
4620	const struct intel_link_bw_limits *limits)
4621	{
4622	struct intel_display *display = to_intel_display(crtc);
4623	struct intel_crtc_state *crtc_state =
4624	intel_atomic_get_new_crtc_state(state, crtc);
4625	struct drm_connector *connector;
4626	struct drm_connector_state *connector_state;
4627	int pipe_src_w, pipe_src_h;
4628	int base_bpp, ret, i;
4629
4630	crtc_state->cpu_transcoder = (enum transcoder) crtc->pipe;
4631
4632	crtc_state->framestart_delay = 1;
4633
4634	/*
4635	* Sanitize sync polarity flags based on requested ones. If neither
4636	* positive or negative polarity is requested, treat this as meaning
4637	* negative polarity.
4638	*/
4639	if (!(crtc_state->hw.adjusted_mode.flags &
4640	(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
4641	crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
4642
4643	if (!(crtc_state->hw.adjusted_mode.flags &
4644	(DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
4645	crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
4646
4647	ret = compute_baseline_pipe_bpp(state, crtc);
4648	if (ret)
4649	return ret;
4650
4651	crtc_state->dsc.compression_enabled_on_link = limits->link_dsc_pipes & BIT(crtc->pipe);
4652	crtc_state->max_link_bpp_x16 = limits->max_bpp_x16[crtc->pipe];
4653
4654	if (crtc_state->pipe_bpp > fxp_q4_to_int(val_q4: crtc_state->max_link_bpp_x16)) {
4655	drm_dbg_kms(display->drm,
4656	"[CRTC:%d:%s] Link bpp limited to " FXP_Q4_FMT "\n",
4657	crtc->base.base.id, crtc->base.name,
4658	FXP_Q4_ARGS(crtc_state->max_link_bpp_x16));
4659	crtc_state->bw_constrained = true;
4660	}
4661
4662	base_bpp = crtc_state->pipe_bpp;
4663
4664	/*
4665	* Determine the real pipe dimensions. Note that stereo modes can
4666	* increase the actual pipe size due to the frame doubling and
4667	* insertion of additional space for blanks between the frame. This
4668	* is stored in the crtc timings. We use the requested mode to do this
4669	* computation to clearly distinguish it from the adjusted mode, which
4670	* can be changed by the connectors in the below retry loop.
4671	*/
4672	drm_mode_get_hv_timing(mode: &crtc_state->hw.mode,
4673	hdisplay: &pipe_src_w, vdisplay: &pipe_src_h);
4674	drm_rect_init(r: &crtc_state->pipe_src, x: 0, y: 0,
4675	width: pipe_src_w, height: pipe_src_h);
4676
4677	for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
4678	struct intel_encoder *encoder =
4679	to_intel_encoder(connector_state->best_encoder);
4680
4681	if (connector_state->crtc != &crtc->base)
4682	continue;
4683
4684	if (!check_single_encoder_cloning(state, crtc, encoder)) {
4685	drm_dbg_kms(display->drm,
4686	"[ENCODER:%d:%s] rejecting invalid cloning configuration\n",
4687	encoder->base.base.id, encoder->base.name);
4688	return -EINVAL;
4689	}
4690
4691	/*
4692	* Determine output_types before calling the .compute_config()
4693	* hooks so that the hooks can use this information safely.
4694	*/
4695	if (encoder->compute_output_type)
4696	crtc_state->output_types |=
4697	BIT(encoder->compute_output_type(encoder, crtc_state,
4698	connector_state));
4699	else
4700	crtc_state->output_types |= BIT(encoder->type);
4701	}
4702
4703	/* Ensure the port clock defaults are reset when retrying. */
4704	crtc_state->port_clock = 0;
4705	crtc_state->pixel_multiplier = 1;
4706
4707	/* Fill in default crtc timings, allow encoders to overwrite them. */
4708	drm_mode_set_crtcinfo(p: &crtc_state->hw.adjusted_mode,
4709	CRTC_STEREO_DOUBLE);
4710
4711	/* Pass our mode to the connectors and the CRTC to give them a chance to
4712	* adjust it according to limitations or connector properties, and also
4713	* a chance to reject the mode entirely.
4714	*/
4715	for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
4716	struct intel_encoder *encoder =
4717	to_intel_encoder(connector_state->best_encoder);
4718
4719	if (connector_state->crtc != &crtc->base)
4720	continue;
4721
4722	ret = encoder->compute_config(encoder, crtc_state,
4723	connector_state);
4724	if (ret == -EDEADLK)
4725	return ret;
4726	if (ret < 0) {
4727	drm_dbg_kms(display->drm, "[ENCODER:%d:%s] config failure: %d\n",
4728	encoder->base.base.id, encoder->base.name, ret);
4729	return ret;
4730	}
4731	}
4732
4733	/* Set default port clock if not overwritten by the encoder. Needs to be
4734	* done afterwards in case the encoder adjusts the mode. */
4735	if (!crtc_state->port_clock)
4736	crtc_state->port_clock = crtc_state->hw.adjusted_mode.crtc_clock
4737	* crtc_state->pixel_multiplier;
4738
4739	ret = intel_crtc_compute_config(state, crtc);
4740	if (ret == -EDEADLK)
4741	return ret;
4742	if (ret < 0) {
4743	drm_dbg_kms(display->drm, "[CRTC:%d:%s] config failure: %d\n",
4744	crtc->base.base.id, crtc->base.name, ret);
4745	return ret;
4746	}
4747
4748	/* Dithering seems to not pass-through bits correctly when it should, so
4749	* only enable it on 6bpc panels and when its not a compliance
4750	* test requesting 6bpc video pattern.
4751	*/
4752	crtc_state->dither = (crtc_state->pipe_bpp == 6*3) &&
4753	!crtc_state->dither_force_disable;
4754	drm_dbg_kms(display->drm,
4755	"[CRTC:%d:%s] hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
4756	crtc->base.base.id, crtc->base.name,
4757	base_bpp, crtc_state->pipe_bpp, crtc_state->dither);
4758
4759	return 0;
4760	}
4761
4762	static int
4763	intel_modeset_pipe_config_late(struct intel_atomic_state *state,
4764	struct intel_crtc *crtc)
4765	{
4766	struct intel_crtc_state *crtc_state =
4767	intel_atomic_get_new_crtc_state(state, crtc);
4768	struct drm_connector_state *conn_state;
4769	struct drm_connector *connector;
4770	int i;
4771
4772	for_each_new_connector_in_state(&state->base, connector,
4773	conn_state, i) {
4774	struct intel_encoder *encoder =
4775	to_intel_encoder(conn_state->best_encoder);
4776	int ret;
4777
4778	if (conn_state->crtc != &crtc->base ||
4779	!encoder->compute_config_late)
4780	continue;
4781
4782	ret = encoder->compute_config_late(encoder, crtc_state,
4783	conn_state);
4784	if (ret)
4785	return ret;
4786	}
4787
4788	return 0;
4789	}
4790
4791	bool intel_fuzzy_clock_check(int clock1, int clock2)
4792	{
4793	int diff;
4794
4795	if (clock1 == clock2)
4796	return true;
4797
4798	if (!clock1 || !clock2)
4799	return false;
4800
4801	diff = abs(clock1 - clock2);
4802
4803	if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
4804	return true;
4805
4806	return false;
4807	}
4808
4809	static bool
4810	intel_compare_link_m_n(const struct intel_link_m_n *m_n,
4811	const struct intel_link_m_n *m2_n2)
4812	{
4813	return m_n->tu == m2_n2->tu &&
4814	m_n->data_m == m2_n2->data_m &&
4815	m_n->data_n == m2_n2->data_n &&
4816	m_n->link_m == m2_n2->link_m &&
4817	m_n->link_n == m2_n2->link_n;
4818	}
4819
4820	static bool
4821	intel_compare_infoframe(const union hdmi_infoframe *a,
4822	const union hdmi_infoframe *b)
4823	{
4824	return memcmp(p: a, q: b, size: sizeof(*a)) == 0;
4825	}
4826
4827	static bool
4828	intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a,
4829	const struct drm_dp_vsc_sdp *b)
4830	{
4831	return a->pixelformat == b->pixelformat &&
4832	a->colorimetry == b->colorimetry &&
4833	a->bpc == b->bpc &&
4834	a->dynamic_range == b->dynamic_range &&
4835	a->content_type == b->content_type;
4836	}
4837
4838	static bool
4839	intel_compare_dp_as_sdp(const struct drm_dp_as_sdp *a,
4840	const struct drm_dp_as_sdp *b)
4841	{
4842	return a->vtotal == b->vtotal &&
4843	a->target_rr == b->target_rr &&
4844	a->duration_incr_ms == b->duration_incr_ms &&
4845	a->duration_decr_ms == b->duration_decr_ms &&
4846	a->mode == b->mode;
4847	}
4848
4849	static bool
4850	intel_compare_buffer(const u8 *a, const u8 *b, size_t len)
4851	{
4852	return memcmp(p: a, q: b, size: len) == 0;
4853	}
4854
4855	static void __printf(5, 6)
4856	pipe_config_mismatch(struct drm_printer *p, bool fastset,
4857	const struct intel_crtc *crtc,
4858	const char *name, const char *format, ...)
4859	{
4860	struct va_format vaf;
4861	va_list args;
4862
4863	va_start(args, format);
4864	vaf.fmt = format;
4865	vaf.va = &args;
4866
4867	if (fastset)
4868	drm_printf(p, f: "[CRTC:%d:%s] fastset requirement not met in %s %pV\n",
4869	crtc->base.base.id, crtc->base.name, name, &vaf);
4870	else
4871	drm_printf(p, f: "[CRTC:%d:%s] mismatch in %s %pV\n",
4872	crtc->base.base.id, crtc->base.name, name, &vaf);
4873
4874	va_end(args);
4875	}
4876
4877	static void
4878	pipe_config_infoframe_mismatch(struct drm_printer *p, bool fastset,
4879	const struct intel_crtc *crtc,
4880	const char *name,
4881	const union hdmi_infoframe *a,
4882	const union hdmi_infoframe *b)
4883	{
4884	struct intel_display *display = to_intel_display(crtc);
4885	const char *loglevel;
4886
4887	if (fastset) {
4888	if (!drm_debug_enabled(DRM_UT_KMS))
4889	return;
4890
4891	loglevel = KERN_DEBUG;
4892	} else {
4893	loglevel = KERN_ERR;
4894	}
4895
4896	pipe_config_mismatch(p, fastset, crtc, name, format: "infoframe");
4897
4898	drm_printf(p, f: "expected:\n");
4899	hdmi_infoframe_log(level: loglevel, dev: display->drm->dev, frame: a);
4900	drm_printf(p, f: "found:\n");
4901	hdmi_infoframe_log(level: loglevel, dev: display->drm->dev, frame: b);
4902	}
4903
4904	static void
4905	pipe_config_dp_vsc_sdp_mismatch(struct drm_printer *p, bool fastset,
4906	const struct intel_crtc *crtc,
4907	const char *name,
4908	const struct drm_dp_vsc_sdp *a,
4909	const struct drm_dp_vsc_sdp *b)
4910	{
4911	pipe_config_mismatch(p, fastset, crtc, name, format: "dp vsc sdp");
4912
4913	drm_printf(p, f: "expected:\n");
4914	drm_dp_vsc_sdp_log(p, vsc: a);
4915	drm_printf(p, f: "found:\n");
4916	drm_dp_vsc_sdp_log(p, vsc: b);
4917	}
4918
4919	static void
4920	pipe_config_dp_as_sdp_mismatch(struct drm_printer *p, bool fastset,
4921	const struct intel_crtc *crtc,
4922	const char *name,
4923	const struct drm_dp_as_sdp *a,
4924	const struct drm_dp_as_sdp *b)
4925	{
4926	pipe_config_mismatch(p, fastset, crtc, name, format: "dp as sdp");
4927
4928	drm_printf(p, f: "expected:\n");
4929	drm_dp_as_sdp_log(p, as_sdp: a);
4930	drm_printf(p, f: "found:\n");
4931	drm_dp_as_sdp_log(p, as_sdp: b);
4932	}
4933
4934	/* Returns the length up to and including the last differing byte */
4935	static size_t
4936	memcmp_diff_len(const u8 *a, const u8 *b, size_t len)
4937	{
4938	int i;
4939
4940	for (i = len - 1; i >= 0; i--) {
4941	if (a[i] != b[i])
4942	return i + 1;
4943	}
4944
4945	return 0;
4946	}
4947
4948	static void
4949	pipe_config_buffer_mismatch(struct drm_printer *p, bool fastset,
4950	const struct intel_crtc *crtc,
4951	const char *name,
4952	const u8 *a, const u8 *b, size_t len)
4953	{
4954	pipe_config_mismatch(p, fastset, crtc, name, format: "buffer");
4955
4956	/* only dump up to the last difference */
4957	len = memcmp_diff_len(a, b, len);
4958
4959	drm_print_hex_dump(p, prefix: "expected: ", buf: a, len);
4960	drm_print_hex_dump(p, prefix: "found: ", buf: b, len);
4961	}
4962
4963	static void
4964	pipe_config_pll_mismatch(struct drm_printer *p, bool fastset,
4965	const struct intel_crtc *crtc,
4966	const char *name,
4967	const struct intel_dpll_hw_state *a,
4968	const struct intel_dpll_hw_state *b)
4969	{
4970	struct intel_display *display = to_intel_display(crtc);
4971
4972	pipe_config_mismatch(p, fastset, crtc, name, format: " "); /* stupid -Werror=format-zero-length */
4973
4974	drm_printf(p, f: "expected:\n");
4975	intel_dpll_dump_hw_state(display, p, dpll_hw_state: a);
4976	drm_printf(p, f: "found:\n");
4977	intel_dpll_dump_hw_state(display, p, dpll_hw_state: b);
4978	}
4979
4980	static void
4981	pipe_config_cx0pll_mismatch(struct drm_printer *p, bool fastset,
4982	const struct intel_crtc *crtc,
4983	const char *name,
4984	const struct intel_cx0pll_state *a,
4985	const struct intel_cx0pll_state *b)
4986	{
4987	struct intel_display *display = to_intel_display(crtc);
4988	char *chipname = a->use_c10 ? "C10" : "C20";
4989
4990	pipe_config_mismatch(p, fastset, crtc, name, format: chipname);
4991
4992	drm_printf(p, f: "expected:\n");
4993	intel_cx0pll_dump_hw_state(display, hw_state: a);
4994	drm_printf(p, f: "found:\n");
4995	intel_cx0pll_dump_hw_state(display, hw_state: b);
4996	}
4997
4998	static bool allow_vblank_delay_fastset(const struct intel_crtc_state *old_crtc_state)
4999	{
5000	struct intel_display *display = to_intel_display(old_crtc_state);
5001
5002	/*
5003	* Allow fastboot to fix up vblank delay (handled via LRR
5004	* codepaths), a bit dodgy as the registers aren't
5005	* double buffered but seems to be working more or less...
5006	*
5007	* Also allow this when the VRR timing generator is always on,
5008	* and optimized guardband is used. In such cases,
5009	* vblank delay may vary even without inherited state, but it's
5010	* still safe as VRR guardband is still same.
5011	*/
5012	return HAS_LRR(display) &&
5013	(old_crtc_state->inherited || intel_vrr_always_use_vrr_tg(display)) &&
5014	!intel_crtc_has_type(crtc_state: old_crtc_state, type: INTEL_OUTPUT_DSI);
5015	}
5016
5017	static void
5018	pipe_config_lt_phy_pll_mismatch(struct drm_printer *p, bool fastset,
5019	const struct intel_crtc *crtc,
5020	const char *name,
5021	const struct intel_lt_phy_pll_state *a,
5022	const struct intel_lt_phy_pll_state *b)
5023	{
5024	struct intel_display *display = to_intel_display(crtc);
5025	char *chipname = "LTPHY";
5026
5027	pipe_config_mismatch(p, fastset, crtc, name, format: chipname);
5028
5029	drm_printf(p, f: "expected:\n");
5030	intel_lt_phy_dump_hw_state(display, hw_state: a);
5031	drm_printf(p, f: "found:\n");
5032	intel_lt_phy_dump_hw_state(display, hw_state: b);
5033	}
5034
5035	bool
5036	intel_pipe_config_compare(const struct intel_crtc_state *current_config,
5037	const struct intel_crtc_state *pipe_config,
5038	bool fastset)
5039	{
5040	struct intel_display *display = to_intel_display(current_config);
5041	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
5042	struct drm_printer p;
5043	u32 exclude_infoframes = 0;
5044	bool ret = true;
5045
5046	if (fastset)
5047	p = drm_dbg_printer(drm: display->drm, category: DRM_UT_KMS, NULL);
5048	else
5049	p = drm_err_printer(drm: display->drm, NULL);
5050
5051	#define PIPE_CONF_CHECK_X(name) do { \
5052	if (current_config->name != pipe_config->name) { \
5053	BUILD_BUG_ON_MSG(__same_type(current_config->name, bool), \
5054	__stringify(name) " is bool"); \
5055	pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
5056	"(expected 0x%08x, found 0x%08x)", \
5057	current_config->name, \
5058	pipe_config->name); \
5059	ret = false; \
5060	} \
5061	} while (0)
5062
5063	#define PIPE_CONF_CHECK_X_WITH_MASK(name, mask) do { \
5064	if ((current_config->name & (mask)) != (pipe_config->name & (mask))) { \
5065	BUILD_BUG_ON_MSG(__same_type(current_config->name, bool), \
5066	__stringify(name) " is bool"); \
5067	pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
5068	"(expected 0x%08x, found 0x%08x)", \
5069	current_config->name & (mask), \
5070	pipe_config->name & (mask)); \
5071	ret = false; \
5072	} \
5073	} while (0)
5074
5075	#define PIPE_CONF_CHECK_I(name) do { \
5076	if (current_config->name != pipe_config->name) { \
5077	BUILD_BUG_ON_MSG(__same_type(current_config->name, bool), \
5078	__stringify(name) " is bool"); \
5079	pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
5080	"(expected %i, found %i)", \
5081	current_config->name, \
5082	pipe_config->name); \
5083	ret = false; \
5084	} \
5085	} while (0)
5086
5087	#define PIPE_CONF_CHECK_LLI(name) do { \
5088	if (current_config->name != pipe_config->name) { \
5089	pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
5090	"(expected %lli, found %lli)", \
5091	current_config->name, \
5092	pipe_config->name); \
5093	ret = false; \
5094	} \
5095	} while (0)
5096
5097	#define PIPE_CONF_CHECK_BOOL(name) do { \
5098	if (current_config->name != pipe_config->name) { \
5099	BUILD_BUG_ON_MSG(!__same_type(current_config->name, bool), \
5100	__stringify(name) " is not bool"); \
5101	pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
5102	"(expected %s, found %s)", \
5103	str_yes_no(current_config->name), \
5104	str_yes_no(pipe_config->name)); \
5105	ret = false; \
5106	} \
5107	} while (0)
5108
5109	#define PIPE_CONF_CHECK_P(name) do { \
5110	if (current_config->name != pipe_config->name) { \
5111	pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
5112	"(expected %p, found %p)", \
5113	current_config->name, \
5114	pipe_config->name); \
5115	ret = false; \
5116	} \
5117	} while (0)
5118
5119	#define PIPE_CONF_CHECK_M_N(name) do { \
5120	if (!intel_compare_link_m_n(&current_config->name, \
5121	&pipe_config->name)) { \
5122	pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
5123	"(expected tu %i data %i/%i link %i/%i, " \
5124	"found tu %i, data %i/%i link %i/%i)", \
5125	current_config->name.tu, \
5126	current_config->name.data_m, \
5127	current_config->name.data_n, \
5128	current_config->name.link_m, \
5129	current_config->name.link_n, \
5130	pipe_config->name.tu, \
5131	pipe_config->name.data_m, \
5132	pipe_config->name.data_n, \
5133	pipe_config->name.link_m, \
5134	pipe_config->name.link_n); \
5135	ret = false; \
5136	} \
5137	} while (0)
5138
5139	#define PIPE_CONF_CHECK_PLL(name) do { \
5140	if (!intel_dpll_compare_hw_state(display, &current_config->name, \
5141	&pipe_config->name)) { \
5142	pipe_config_pll_mismatch(&p, fastset, crtc, __stringify(name), \
5143	&current_config->name, \
5144	&pipe_config->name); \
5145	ret = false; \
5146	} \
5147	} while (0)
5148
5149	#define PIPE_CONF_CHECK_PLL_CX0(name) do { \
5150	if (!intel_cx0pll_compare_hw_state(&current_config->name, \
5151	&pipe_config->name)) { \
5152	pipe_config_cx0pll_mismatch(&p, fastset, crtc, __stringify(name), \
5153	&current_config->name, \
5154	&pipe_config->name); \
5155	ret = false; \
5156	} \
5157	} while (0)
5158
5159	#define PIPE_CONF_CHECK_PLL_LT(name) do { \
5160	if (!intel_lt_phy_pll_compare_hw_state(&current_config->name, \
5161	&pipe_config->name)) { \
5162	pipe_config_lt_phy_pll_mismatch(&p, fastset, crtc, __stringify(name), \
5163	&current_config->name, \
5164	&pipe_config->name); \
5165	ret = false; \
5166	} \
5167	} while (0)
5168
5169	#define PIPE_CONF_CHECK_TIMINGS(name) do { \
5170	PIPE_CONF_CHECK_I(name.crtc_hdisplay); \
5171	PIPE_CONF_CHECK_I(name.crtc_htotal); \
5172	PIPE_CONF_CHECK_I(name.crtc_hblank_start); \
5173	PIPE_CONF_CHECK_I(name.crtc_hblank_end); \
5174	PIPE_CONF_CHECK_I(name.crtc_hsync_start); \
5175	PIPE_CONF_CHECK_I(name.crtc_hsync_end); \
5176	PIPE_CONF_CHECK_I(name.crtc_vdisplay); \
5177	if (!fastset || !allow_vblank_delay_fastset(current_config)) \
5178	PIPE_CONF_CHECK_I(name.crtc_vblank_start); \
5179	PIPE_CONF_CHECK_I(name.crtc_vsync_start); \
5180	PIPE_CONF_CHECK_I(name.crtc_vsync_end); \
5181	if (!fastset || !pipe_config->update_lrr) { \
5182	PIPE_CONF_CHECK_I(name.crtc_vtotal); \
5183	PIPE_CONF_CHECK_I(name.crtc_vblank_end); \
5184	} \
5185	} while (0)
5186
5187	#define PIPE_CONF_CHECK_RECT(name) do { \
5188	PIPE_CONF_CHECK_I(name.x1); \
5189	PIPE_CONF_CHECK_I(name.x2); \
5190	PIPE_CONF_CHECK_I(name.y1); \
5191	PIPE_CONF_CHECK_I(name.y2); \
5192	} while (0)
5193
5194	#define PIPE_CONF_CHECK_FLAGS(name, mask) do { \
5195	if ((current_config->name ^ pipe_config->name) & (mask)) { \
5196	pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
5197	"(%x) (expected %i, found %i)", \
5198	(mask), \
5199	current_config->name & (mask), \
5200	pipe_config->name & (mask)); \
5201	ret = false; \
5202	} \
5203	} while (0)
5204
5205	#define PIPE_CONF_CHECK_INFOFRAME(name) do { \
5206	if (!intel_compare_infoframe(&current_config->infoframes.name, \
5207	&pipe_config->infoframes.name)) { \
5208	pipe_config_infoframe_mismatch(&p, fastset, crtc, __stringify(name), \
5209	&current_config->infoframes.name, \
5210	&pipe_config->infoframes.name); \
5211	ret = false; \
5212	} \
5213	} while (0)
5214
5215	#define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \
5216	if (!intel_compare_dp_vsc_sdp(&current_config->infoframes.name, \
5217	&pipe_config->infoframes.name)) { \
5218	pipe_config_dp_vsc_sdp_mismatch(&p, fastset, crtc, __stringify(name), \
5219	&current_config->infoframes.name, \
5220	&pipe_config->infoframes.name); \
5221	ret = false; \
5222	} \
5223	} while (0)
5224
5225	#define PIPE_CONF_CHECK_DP_AS_SDP(name) do { \
5226	if (!intel_compare_dp_as_sdp(&current_config->infoframes.name, \
5227	&pipe_config->infoframes.name)) { \
5228	pipe_config_dp_as_sdp_mismatch(&p, fastset, crtc, __stringify(name), \
5229	&current_config->infoframes.name, \
5230	&pipe_config->infoframes.name); \
5231	ret = false; \
5232	} \
5233	} while (0)
5234
5235	#define PIPE_CONF_CHECK_BUFFER(name, len) do { \
5236	BUILD_BUG_ON(sizeof(current_config->name) != (len)); \
5237	BUILD_BUG_ON(sizeof(pipe_config->name) != (len)); \
5238	if (!intel_compare_buffer(current_config->name, pipe_config->name, (len))) { \
5239	pipe_config_buffer_mismatch(&p, fastset, crtc, __stringify(name), \
5240	current_config->name, \
5241	pipe_config->name, \
5242	(len)); \
5243	ret = false; \
5244	} \
5245	} while (0)
5246
5247	#define PIPE_CONF_CHECK_COLOR_LUT(lut, is_pre_csc_lut) do { \
5248	if (current_config->gamma_mode == pipe_config->gamma_mode && \
5249	!intel_color_lut_equal(current_config, \
5250	current_config->lut, pipe_config->lut, \
5251	is_pre_csc_lut)) { \
5252	pipe_config_mismatch(&p, fastset, crtc, __stringify(lut), \
5253	"hw_state doesn't match sw_state"); \
5254	ret = false; \
5255	} \
5256	} while (0)
5257
5258	#define PIPE_CONF_CHECK_CSC(name) do { \
5259	PIPE_CONF_CHECK_X(name.preoff[0]); \
5260	PIPE_CONF_CHECK_X(name.preoff[1]); \
5261	PIPE_CONF_CHECK_X(name.preoff[2]); \
5262	PIPE_CONF_CHECK_X(name.coeff[0]); \
5263	PIPE_CONF_CHECK_X(name.coeff[1]); \
5264	PIPE_CONF_CHECK_X(name.coeff[2]); \
5265	PIPE_CONF_CHECK_X(name.coeff[3]); \
5266	PIPE_CONF_CHECK_X(name.coeff[4]); \
5267	PIPE_CONF_CHECK_X(name.coeff[5]); \
5268	PIPE_CONF_CHECK_X(name.coeff[6]); \
5269	PIPE_CONF_CHECK_X(name.coeff[7]); \
5270	PIPE_CONF_CHECK_X(name.coeff[8]); \
5271	PIPE_CONF_CHECK_X(name.postoff[0]); \
5272	PIPE_CONF_CHECK_X(name.postoff[1]); \
5273	PIPE_CONF_CHECK_X(name.postoff[2]); \
5274	} while (0)
5275
5276	#define PIPE_CONF_QUIRK(quirk) \
5277	((current_config->quirks | pipe_config->quirks) & (quirk))
5278
5279	PIPE_CONF_CHECK_BOOL(hw.enable);
5280	PIPE_CONF_CHECK_BOOL(hw.active);
5281
5282	PIPE_CONF_CHECK_I(cpu_transcoder);
5283	PIPE_CONF_CHECK_I(mst_master_transcoder);
5284
5285	PIPE_CONF_CHECK_BOOL(has_pch_encoder);
5286	PIPE_CONF_CHECK_I(fdi_lanes);
5287	PIPE_CONF_CHECK_M_N(fdi_m_n);
5288
5289	PIPE_CONF_CHECK_I(lane_count);
5290	PIPE_CONF_CHECK_X(lane_lat_optim_mask);
5291
5292	PIPE_CONF_CHECK_I(min_hblank);
5293
5294	if (HAS_DOUBLE_BUFFERED_M_N(display)) {
5295	if (!fastset || !pipe_config->update_m_n)
5296	PIPE_CONF_CHECK_M_N(dp_m_n);
5297	} else {
5298	PIPE_CONF_CHECK_M_N(dp_m_n);
5299	PIPE_CONF_CHECK_M_N(dp_m2_n2);
5300	}
5301
5302	PIPE_CONF_CHECK_X(output_types);
5303
5304	PIPE_CONF_CHECK_I(framestart_delay);
5305	PIPE_CONF_CHECK_I(msa_timing_delay);
5306
5307	PIPE_CONF_CHECK_TIMINGS(hw.pipe_mode);
5308	PIPE_CONF_CHECK_TIMINGS(hw.adjusted_mode);
5309
5310	PIPE_CONF_CHECK_I(pixel_multiplier);
5311
5312	PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5313	DRM_MODE_FLAG_INTERLACE);
5314
5315	if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
5316	PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5317	DRM_MODE_FLAG_PHSYNC);
5318	PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5319	DRM_MODE_FLAG_NHSYNC);
5320	PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5321	DRM_MODE_FLAG_PVSYNC);
5322	PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5323	DRM_MODE_FLAG_NVSYNC);
5324	}
5325
5326	PIPE_CONF_CHECK_I(output_format);
5327	PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
5328	if ((DISPLAY_VER(display) < 8 && !display->platform.haswell) ||
5329	display->platform.valleyview || display->platform.cherryview)
5330	PIPE_CONF_CHECK_BOOL(limited_color_range);
5331
5332	PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
5333	PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
5334	PIPE_CONF_CHECK_BOOL(has_infoframe);
5335	PIPE_CONF_CHECK_BOOL(enhanced_framing);
5336	PIPE_CONF_CHECK_BOOL(fec_enable);
5337
5338	if (!fastset) {
5339	PIPE_CONF_CHECK_BOOL(has_audio);
5340	PIPE_CONF_CHECK_BUFFER(eld, MAX_ELD_BYTES);
5341	}
5342
5343	PIPE_CONF_CHECK_X(gmch_pfit.control);
5344	/* pfit ratios are autocomputed by the hw on gen4+ */
5345	if (DISPLAY_VER(display) < 4)
5346	PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
5347	PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
5348
5349	/*
5350	* Changing the EDP transcoder input mux
5351	* (A_ONOFF vs. A_ON) requires a full modeset.
5352	*/
5353	PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru);
5354
5355	if (!fastset) {
5356	PIPE_CONF_CHECK_RECT(pipe_src);
5357
5358	PIPE_CONF_CHECK_BOOL(pch_pfit.enabled);
5359	PIPE_CONF_CHECK_RECT(pch_pfit.dst);
5360
5361	PIPE_CONF_CHECK_I(scaler_state.scaler_id);
5362	PIPE_CONF_CHECK_I(pixel_rate);
5363	PIPE_CONF_CHECK_BOOL(hw.casf_params.casf_enable);
5364	PIPE_CONF_CHECK_I(hw.casf_params.win_size);
5365	PIPE_CONF_CHECK_I(hw.casf_params.strength);
5366
5367	PIPE_CONF_CHECK_X(gamma_mode);
5368	if (display->platform.cherryview)
5369	PIPE_CONF_CHECK_X(cgm_mode);
5370	else
5371	PIPE_CONF_CHECK_X(csc_mode);
5372	PIPE_CONF_CHECK_BOOL(gamma_enable);
5373	PIPE_CONF_CHECK_BOOL(csc_enable);
5374	PIPE_CONF_CHECK_BOOL(wgc_enable);
5375
5376	PIPE_CONF_CHECK_I(linetime);
5377	PIPE_CONF_CHECK_I(ips_linetime);
5378
5379	PIPE_CONF_CHECK_COLOR_LUT(pre_csc_lut, true);
5380	PIPE_CONF_CHECK_COLOR_LUT(post_csc_lut, false);
5381
5382	PIPE_CONF_CHECK_CSC(csc);
5383	PIPE_CONF_CHECK_CSC(output_csc);
5384	}
5385
5386	PIPE_CONF_CHECK_BOOL(double_wide);
5387
5388	if (display->dpll.mgr)
5389	PIPE_CONF_CHECK_P(intel_dpll);
5390
5391	/* FIXME convert everything over the dpll_mgr */
5392	if (display->dpll.mgr || HAS_GMCH(display))
5393	PIPE_CONF_CHECK_PLL(dpll_hw_state);
5394
5395	/* FIXME convert MTL+ platforms over to dpll_mgr */
5396	if (HAS_LT_PHY(display))
5397	PIPE_CONF_CHECK_PLL_LT(dpll_hw_state.ltpll);
5398	else if (DISPLAY_VER(display) >= 14)
5399	PIPE_CONF_CHECK_PLL_CX0(dpll_hw_state.cx0pll);
5400
5401	PIPE_CONF_CHECK_X(dsi_pll.ctrl);
5402	PIPE_CONF_CHECK_X(dsi_pll.div);
5403
5404	if (display->platform.g4x || DISPLAY_VER(display) >= 5)
5405	PIPE_CONF_CHECK_I(pipe_bpp);
5406
5407	if (!fastset || !pipe_config->update_m_n) {
5408	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_clock);
5409	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_clock);
5410	}
5411	PIPE_CONF_CHECK_I(port_clock);
5412
5413	PIPE_CONF_CHECK_I(min_voltage_level);
5414
5415	if (current_config->has_psr || pipe_config->has_psr)
5416	exclude_infoframes |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
5417
5418	if (current_config->vrr.enable || pipe_config->vrr.enable)
5419	exclude_infoframes |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC);
5420
5421	PIPE_CONF_CHECK_X_WITH_MASK(infoframes.enable, ~exclude_infoframes);
5422	PIPE_CONF_CHECK_X(infoframes.gcp);
5423	PIPE_CONF_CHECK_INFOFRAME(avi);
5424	PIPE_CONF_CHECK_INFOFRAME(spd);
5425	PIPE_CONF_CHECK_INFOFRAME(hdmi);
5426	if (!fastset) {
5427	PIPE_CONF_CHECK_INFOFRAME(drm);
5428	PIPE_CONF_CHECK_DP_AS_SDP(as_sdp);
5429	}
5430	PIPE_CONF_CHECK_DP_VSC_SDP(vsc);
5431
5432	PIPE_CONF_CHECK_X(sync_mode_slaves_mask);
5433	PIPE_CONF_CHECK_I(master_transcoder);
5434	PIPE_CONF_CHECK_X(joiner_pipes);
5435
5436	PIPE_CONF_CHECK_BOOL(dsc.config.block_pred_enable);
5437	PIPE_CONF_CHECK_BOOL(dsc.config.convert_rgb);
5438	PIPE_CONF_CHECK_BOOL(dsc.config.simple_422);
5439	PIPE_CONF_CHECK_BOOL(dsc.config.native_422);
5440	PIPE_CONF_CHECK_BOOL(dsc.config.native_420);
5441	PIPE_CONF_CHECK_BOOL(dsc.config.vbr_enable);
5442	PIPE_CONF_CHECK_I(dsc.config.line_buf_depth);
5443	PIPE_CONF_CHECK_I(dsc.config.bits_per_component);
5444	PIPE_CONF_CHECK_I(dsc.config.pic_width);
5445	PIPE_CONF_CHECK_I(dsc.config.pic_height);
5446	PIPE_CONF_CHECK_I(dsc.config.slice_width);
5447	PIPE_CONF_CHECK_I(dsc.config.slice_height);
5448	PIPE_CONF_CHECK_I(dsc.config.initial_dec_delay);
5449	PIPE_CONF_CHECK_I(dsc.config.initial_xmit_delay);
5450	PIPE_CONF_CHECK_I(dsc.config.scale_decrement_interval);
5451	PIPE_CONF_CHECK_I(dsc.config.scale_increment_interval);
5452	PIPE_CONF_CHECK_I(dsc.config.initial_scale_value);
5453	PIPE_CONF_CHECK_I(dsc.config.first_line_bpg_offset);
5454	PIPE_CONF_CHECK_I(dsc.config.flatness_min_qp);
5455	PIPE_CONF_CHECK_I(dsc.config.flatness_max_qp);
5456	PIPE_CONF_CHECK_I(dsc.config.slice_bpg_offset);
5457	PIPE_CONF_CHECK_I(dsc.config.nfl_bpg_offset);
5458	PIPE_CONF_CHECK_I(dsc.config.initial_offset);
5459	PIPE_CONF_CHECK_I(dsc.config.final_offset);
5460	PIPE_CONF_CHECK_I(dsc.config.rc_model_size);
5461	PIPE_CONF_CHECK_I(dsc.config.rc_quant_incr_limit0);
5462	PIPE_CONF_CHECK_I(dsc.config.rc_quant_incr_limit1);
5463	PIPE_CONF_CHECK_I(dsc.config.slice_chunk_size);
5464	PIPE_CONF_CHECK_I(dsc.config.second_line_bpg_offset);
5465	PIPE_CONF_CHECK_I(dsc.config.nsl_bpg_offset);
5466
5467	PIPE_CONF_CHECK_BOOL(dsc.compression_enable);
5468	PIPE_CONF_CHECK_I(dsc.num_streams);
5469	PIPE_CONF_CHECK_I(dsc.compressed_bpp_x16);
5470
5471	PIPE_CONF_CHECK_BOOL(splitter.enable);
5472	PIPE_CONF_CHECK_I(splitter.link_count);
5473	PIPE_CONF_CHECK_I(splitter.pixel_overlap);
5474
5475	if (!fastset) {
5476	PIPE_CONF_CHECK_BOOL(vrr.enable);
5477	PIPE_CONF_CHECK_I(vrr.vmin);
5478	PIPE_CONF_CHECK_I(vrr.vmax);
5479	PIPE_CONF_CHECK_I(vrr.flipline);
5480	PIPE_CONF_CHECK_I(vrr.vsync_start);
5481	PIPE_CONF_CHECK_I(vrr.vsync_end);
5482	PIPE_CONF_CHECK_LLI(cmrr.cmrr_m);
5483	PIPE_CONF_CHECK_LLI(cmrr.cmrr_n);
5484	PIPE_CONF_CHECK_BOOL(cmrr.enable);
5485	}
5486
5487	if (!fastset || intel_vrr_always_use_vrr_tg(display)) {
5488	PIPE_CONF_CHECK_I(vrr.pipeline_full);
5489	PIPE_CONF_CHECK_I(vrr.guardband);
5490	}
5491
5492	PIPE_CONF_CHECK_I(set_context_latency);
5493
5494	#undef PIPE_CONF_CHECK_X
5495	#undef PIPE_CONF_CHECK_I
5496	#undef PIPE_CONF_CHECK_LLI
5497	#undef PIPE_CONF_CHECK_BOOL
5498	#undef PIPE_CONF_CHECK_P
5499	#undef PIPE_CONF_CHECK_FLAGS
5500	#undef PIPE_CONF_CHECK_COLOR_LUT
5501	#undef PIPE_CONF_CHECK_TIMINGS
5502	#undef PIPE_CONF_CHECK_RECT
5503	#undef PIPE_CONF_QUIRK
5504
5505	return ret;
5506	}
5507
5508	static void
5509	intel_verify_planes(struct intel_atomic_state *state)
5510	{
5511	struct intel_plane *plane;
5512	const struct intel_plane_state *plane_state;
5513	int i;
5514
5515	for_each_new_intel_plane_in_state(state, plane,
5516	plane_state, i)
5517	assert_plane(plane, state: plane_state->is_y_plane ||
5518	plane_state->uapi.visible);
5519	}
5520
5521	static int intel_modeset_pipe(struct intel_atomic_state *state,
5522	struct intel_crtc_state *crtc_state,
5523	const char *reason)
5524	{
5525	struct intel_display *display = to_intel_display(state);
5526	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5527	int ret;
5528
5529	drm_dbg_kms(display->drm, "[CRTC:%d:%s] Full modeset due to %s\n",
5530	crtc->base.base.id, crtc->base.name, reason);
5531
5532	ret = drm_atomic_add_affected_connectors(state: &state->base,
5533	crtc: &crtc->base);
5534	if (ret)
5535	return ret;
5536
5537	ret = intel_dp_tunnel_atomic_add_state_for_crtc(state, crtc);
5538	if (ret)
5539	return ret;
5540
5541	ret = intel_dp_mst_add_topology_state_for_crtc(state, crtc);
5542	if (ret)
5543	return ret;
5544
5545	ret = intel_plane_add_affected(state, crtc);
5546	if (ret)
5547	return ret;
5548
5549	crtc_state->uapi.mode_changed = true;
5550
5551	return 0;
5552	}
5553
5554	/**
5555	* intel_modeset_pipes_in_mask_early - force a full modeset on a set of pipes
5556	* @state: intel atomic state
5557	* @reason: the reason for the full modeset
5558	* @mask: mask of pipes to modeset
5559	*
5560	* Add pipes in @mask to @state and force a full modeset on the enabled ones
5561	* due to the description in @reason.
5562	* This function can be called only before new plane states are computed.
5563	*
5564	* Returns 0 in case of success, negative error code otherwise.
5565	*/
5566	int intel_modeset_pipes_in_mask_early(struct intel_atomic_state *state,
5567	const char *reason, u8 mask)
5568	{
5569	struct intel_display *display = to_intel_display(state);
5570	struct intel_crtc *crtc;
5571
5572	for_each_intel_crtc_in_pipe_mask(display->drm, crtc, mask) {
5573	struct intel_crtc_state *crtc_state;
5574	int ret;
5575
5576	crtc_state = intel_atomic_get_crtc_state(state: &state->base, crtc);
5577	if (IS_ERR(ptr: crtc_state))
5578	return PTR_ERR(ptr: crtc_state);
5579
5580	if (!crtc_state->hw.enable ||
5581	intel_crtc_needs_modeset(crtc_state))
5582	continue;
5583
5584	ret = intel_modeset_pipe(state, crtc_state, reason);
5585	if (ret)
5586	return ret;
5587	}
5588
5589	return 0;
5590	}
5591
5592	static void
5593	intel_crtc_flag_modeset(struct intel_crtc_state *crtc_state)
5594	{
5595	crtc_state->uapi.mode_changed = true;
5596
5597	crtc_state->update_pipe = false;
5598	crtc_state->update_m_n = false;
5599	crtc_state->update_lrr = false;
5600	}
5601
5602	/**
5603	* intel_modeset_all_pipes_late - force a full modeset on all pipes
5604	* @state: intel atomic state
5605	* @reason: the reason for the full modeset
5606	*
5607	* Add all pipes to @state and force a full modeset on the active ones due to
5608	* the description in @reason.
5609	* This function can be called only after new plane states are computed already.
5610	*
5611	* Returns 0 in case of success, negative error code otherwise.
5612	*/
5613	int intel_modeset_all_pipes_late(struct intel_atomic_state *state,
5614	const char *reason)
5615	{
5616	struct intel_display *display = to_intel_display(state);
5617	struct intel_crtc *crtc;
5618
5619	for_each_intel_crtc(display->drm, crtc) {
5620	struct intel_crtc_state *crtc_state;
5621	int ret;
5622
5623	crtc_state = intel_atomic_get_crtc_state(state: &state->base, crtc);
5624	if (IS_ERR(ptr: crtc_state))
5625	return PTR_ERR(ptr: crtc_state);
5626
5627	if (!crtc_state->hw.active ||
5628	intel_crtc_needs_modeset(crtc_state))
5629	continue;
5630
5631	ret = intel_modeset_pipe(state, crtc_state, reason);
5632	if (ret)
5633	return ret;
5634
5635	intel_crtc_flag_modeset(crtc_state);
5636
5637	crtc_state->update_planes |= crtc_state->active_planes;
5638	crtc_state->async_flip_planes = 0;
5639	crtc_state->do_async_flip = false;
5640	}
5641
5642	return 0;
5643	}
5644
5645	int intel_modeset_commit_pipes(struct intel_display *display,
5646	u8 pipe_mask,
5647	struct drm_modeset_acquire_ctx *ctx)
5648	{
5649	struct drm_atomic_state *state;
5650	struct intel_crtc *crtc;
5651	int ret;
5652
5653	state = drm_atomic_state_alloc(dev: display->drm);
5654	if (!state)
5655	return -ENOMEM;
5656
5657	state->acquire_ctx = ctx;
5658	to_intel_atomic_state(state)->internal = true;
5659
5660	for_each_intel_crtc_in_pipe_mask(display->drm, crtc, pipe_mask) {
5661	struct intel_crtc_state *crtc_state =
5662	intel_atomic_get_crtc_state(state, crtc);
5663
5664	if (IS_ERR(ptr: crtc_state)) {
5665	ret = PTR_ERR(ptr: crtc_state);
5666	goto out;
5667	}
5668
5669	crtc_state->uapi.connectors_changed = true;
5670	}
5671
5672	ret = drm_atomic_commit(state);
5673	out:
5674	drm_atomic_state_put(state);
5675
5676	return ret;
5677	}
5678
5679	/*
5680	* This implements the workaround described in the "notes" section of the mode
5681	* set sequence documentation. When going from no pipes or single pipe to
5682	* multiple pipes, and planes are enabled after the pipe, we need to wait at
5683	* least 2 vblanks on the first pipe before enabling planes on the second pipe.
5684	*/
5685	static int hsw_mode_set_planes_workaround(struct intel_atomic_state *state)
5686	{
5687	struct intel_crtc_state *crtc_state;
5688	struct intel_crtc *crtc;
5689	struct intel_crtc_state *first_crtc_state = NULL;
5690	struct intel_crtc_state *other_crtc_state = NULL;
5691	enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
5692	int i;
5693
5694	/* look at all crtc's that are going to be enabled in during modeset */
5695	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
5696	if (!crtc_state->hw.active ||
5697	!intel_crtc_needs_modeset(crtc_state))
5698	continue;
5699
5700	if (first_crtc_state) {
5701	other_crtc_state = crtc_state;
5702	break;
5703	} else {
5704	first_crtc_state = crtc_state;
5705	first_pipe = crtc->pipe;
5706	}
5707	}
5708
5709	/* No workaround needed? */
5710	if (!first_crtc_state)
5711	return 0;
5712
5713	/* w/a possibly needed, check how many crtc's are already enabled. */
5714	for_each_intel_crtc(state->base.dev, crtc) {
5715	crtc_state = intel_atomic_get_crtc_state(state: &state->base, crtc);
5716	if (IS_ERR(ptr: crtc_state))
5717	return PTR_ERR(ptr: crtc_state);
5718
5719	crtc_state->hsw_workaround_pipe = INVALID_PIPE;
5720
5721	if (!crtc_state->hw.active ||
5722	intel_crtc_needs_modeset(crtc_state))
5723	continue;
5724
5725	/* 2 or more enabled crtcs means no need for w/a */
5726	if (enabled_pipe != INVALID_PIPE)
5727	return 0;
5728
5729	enabled_pipe = crtc->pipe;
5730	}
5731
5732	if (enabled_pipe != INVALID_PIPE)
5733	first_crtc_state->hsw_workaround_pipe = enabled_pipe;
5734	else if (other_crtc_state)
5735	other_crtc_state->hsw_workaround_pipe = first_pipe;
5736
5737	return 0;
5738	}
5739
5740	u8 intel_calc_enabled_pipes(struct intel_atomic_state *state,
5741	u8 enabled_pipes)
5742	{
5743	const struct intel_crtc_state *crtc_state;
5744	struct intel_crtc *crtc;
5745	int i;
5746
5747	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
5748	if (crtc_state->hw.enable)
5749	enabled_pipes |= BIT(crtc->pipe);
5750	else
5751	enabled_pipes &= ~BIT(crtc->pipe);
5752	}
5753
5754	return enabled_pipes;
5755	}
5756
5757	u8 intel_calc_active_pipes(struct intel_atomic_state *state,
5758	u8 active_pipes)
5759	{
5760	const struct intel_crtc_state *crtc_state;
5761	struct intel_crtc *crtc;
5762	int i;
5763
5764	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
5765	if (crtc_state->hw.active)
5766	active_pipes |= BIT(crtc->pipe);
5767	else
5768	active_pipes &= ~BIT(crtc->pipe);
5769	}
5770
5771	return active_pipes;
5772	}
5773
5774	static int intel_modeset_checks(struct intel_atomic_state *state)
5775	{
5776	struct intel_display *display = to_intel_display(state);
5777
5778	state->modeset = true;
5779
5780	if (display->platform.haswell)
5781	return hsw_mode_set_planes_workaround(state);
5782
5783	return 0;
5784	}
5785
5786	static bool lrr_params_changed(const struct intel_crtc_state *old_crtc_state,
5787	const struct intel_crtc_state *new_crtc_state)
5788	{
5789	const struct drm_display_mode *old_adjusted_mode = &old_crtc_state->hw.adjusted_mode;
5790	const struct drm_display_mode *new_adjusted_mode = &new_crtc_state->hw.adjusted_mode;
5791
5792	return old_adjusted_mode->crtc_vblank_start != new_adjusted_mode->crtc_vblank_start ||
5793	old_adjusted_mode->crtc_vblank_end != new_adjusted_mode->crtc_vblank_end ||
5794	old_adjusted_mode->crtc_vtotal != new_adjusted_mode->crtc_vtotal ||
5795	old_crtc_state->set_context_latency != new_crtc_state->set_context_latency;
5796	}
5797
5798	static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state,
5799	struct intel_crtc_state *new_crtc_state)
5800	{
5801	struct intel_display *display = to_intel_display(new_crtc_state);
5802	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
5803
5804	/* only allow LRR when the timings stay within the VRR range */
5805	if (old_crtc_state->vrr.in_range != new_crtc_state->vrr.in_range)
5806	new_crtc_state->update_lrr = false;
5807
5808	if (!intel_pipe_config_compare(current_config: old_crtc_state, pipe_config: new_crtc_state, fastset: true)) {
5809	drm_dbg_kms(display->drm, "[CRTC:%d:%s] fastset requirement not met, forcing full modeset\n",
5810	crtc->base.base.id, crtc->base.name);
5811	} else {
5812	if (allow_vblank_delay_fastset(old_crtc_state))
5813	new_crtc_state->update_lrr = true;
5814	new_crtc_state->uapi.mode_changed = false;
5815	}
5816
5817	if (intel_compare_link_m_n(m_n: &old_crtc_state->dp_m_n,
5818	m2_n2: &new_crtc_state->dp_m_n))
5819	new_crtc_state->update_m_n = false;
5820
5821	if (!lrr_params_changed(old_crtc_state, new_crtc_state))
5822	new_crtc_state->update_lrr = false;
5823
5824	if (intel_crtc_needs_modeset(crtc_state: new_crtc_state))
5825	intel_crtc_flag_modeset(crtc_state: new_crtc_state);
5826	else
5827	new_crtc_state->update_pipe = true;
5828	}
5829
5830	static int intel_atomic_check_crtcs(struct intel_atomic_state *state)
5831	{
5832	struct intel_display *display = to_intel_display(state);
5833	struct intel_crtc_state __maybe_unused *crtc_state;
5834	struct intel_crtc *crtc;
5835	int i;
5836
5837	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
5838	int ret;
5839
5840	ret = intel_crtc_atomic_check(state, crtc);
5841	if (ret) {
5842	drm_dbg_atomic(display->drm,
5843	"[CRTC:%d:%s] atomic driver check failed\n",
5844	crtc->base.base.id, crtc->base.name);
5845	return ret;
5846	}
5847	}
5848
5849	return 0;
5850	}
5851
5852	static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state,
5853	u8 transcoders)
5854	{
5855	const struct intel_crtc_state *new_crtc_state;
5856	struct intel_crtc *crtc;
5857	int i;
5858
5859	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
5860	if (new_crtc_state->hw.enable &&
5861	transcoders & BIT(new_crtc_state->cpu_transcoder) &&
5862	intel_crtc_needs_modeset(crtc_state: new_crtc_state))
5863	return true;
5864	}
5865
5866	return false;
5867	}
5868
5869	static bool intel_pipes_need_modeset(struct intel_atomic_state *state,
5870	u8 pipes)
5871	{
5872	const struct intel_crtc_state *new_crtc_state;
5873	struct intel_crtc *crtc;
5874	int i;
5875
5876	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
5877	if (new_crtc_state->hw.enable &&
5878	pipes & BIT(crtc->pipe) &&
5879	intel_crtc_needs_modeset(crtc_state: new_crtc_state))
5880	return true;
5881	}
5882
5883	return false;
5884	}
5885
5886	static int intel_atomic_check_joiner(struct intel_atomic_state *state,
5887	struct intel_crtc *primary_crtc)
5888	{
5889	struct intel_display *display = to_intel_display(state);
5890	struct intel_crtc_state *primary_crtc_state =
5891	intel_atomic_get_new_crtc_state(state, crtc: primary_crtc);
5892	struct intel_crtc *secondary_crtc;
5893
5894	if (!primary_crtc_state->joiner_pipes)
5895	return 0;
5896
5897	/* sanity check */
5898	if (drm_WARN_ON(display->drm,
5899	primary_crtc->pipe != joiner_primary_pipe(primary_crtc_state)))
5900	return -EINVAL;
5901
5902	if (primary_crtc_state->joiner_pipes & ~joiner_pipes(display)) {
5903	drm_dbg_kms(display->drm,
5904	"[CRTC:%d:%s] Cannot act as joiner primary "
5905	"(need 0x%x as pipes, only 0x%x possible)\n",
5906	primary_crtc->base.base.id, primary_crtc->base.name,
5907	primary_crtc_state->joiner_pipes, joiner_pipes(display));
5908	return -EINVAL;
5909	}
5910
5911	for_each_intel_crtc_in_pipe_mask(display->drm, secondary_crtc,
5912	intel_crtc_joiner_secondary_pipes(primary_crtc_state)) {
5913	struct intel_crtc_state *secondary_crtc_state;
5914	int ret;
5915
5916	secondary_crtc_state = intel_atomic_get_crtc_state(state: &state->base, crtc: secondary_crtc);
5917	if (IS_ERR(ptr: secondary_crtc_state))
5918	return PTR_ERR(ptr: secondary_crtc_state);
5919
5920	/* primary being enabled, secondary was already configured? */
5921	if (secondary_crtc_state->uapi.enable) {
5922	drm_dbg_kms(display->drm,
5923	"[CRTC:%d:%s] secondary is enabled as normal CRTC, but "
5924	"[CRTC:%d:%s] claiming this CRTC for joiner.\n",
5925	secondary_crtc->base.base.id, secondary_crtc->base.name,
5926	primary_crtc->base.base.id, primary_crtc->base.name);
5927	return -EINVAL;
5928	}
5929
5930	/*
5931	* The state copy logic assumes the primary crtc gets processed
5932	* before the secondary crtc during the main compute_config loop.
5933	* This works because the crtcs are created in pipe order,
5934	* and the hardware requires primary pipe < secondary pipe as well.
5935	* Should that change we need to rethink the logic.
5936	*/
5937	if (WARN_ON(drm_crtc_index(&primary_crtc->base) >
5938	drm_crtc_index(&secondary_crtc->base)))
5939	return -EINVAL;
5940
5941	drm_dbg_kms(display->drm,
5942	"[CRTC:%d:%s] Used as secondary for joiner primary [CRTC:%d:%s]\n",
5943	secondary_crtc->base.base.id, secondary_crtc->base.name,
5944	primary_crtc->base.base.id, primary_crtc->base.name);
5945
5946	secondary_crtc_state->joiner_pipes =
5947	primary_crtc_state->joiner_pipes;
5948
5949	ret = copy_joiner_crtc_state_modeset(state, secondary_crtc);
5950	if (ret)
5951	return ret;
5952	}
5953
5954	return 0;
5955	}
5956
5957	static void kill_joiner_secondaries(struct intel_atomic_state *state,
5958	struct intel_crtc *primary_crtc)
5959	{
5960	struct intel_display *display = to_intel_display(state);
5961	struct intel_crtc_state *primary_crtc_state =
5962	intel_atomic_get_new_crtc_state(state, crtc: primary_crtc);
5963	struct intel_crtc *secondary_crtc;
5964
5965	for_each_intel_crtc_in_pipe_mask(display->drm, secondary_crtc,
5966	intel_crtc_joiner_secondary_pipes(primary_crtc_state)) {
5967	struct intel_crtc_state *secondary_crtc_state =
5968	intel_atomic_get_new_crtc_state(state, crtc: secondary_crtc);
5969
5970	secondary_crtc_state->joiner_pipes = 0;
5971
5972	intel_crtc_copy_uapi_to_hw_state_modeset(state, crtc: secondary_crtc);
5973	}
5974
5975	primary_crtc_state->joiner_pipes = 0;
5976	}
5977
5978	/**
5979	* DOC: asynchronous flip implementation
5980	*
5981	* Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC
5982	* flag. Currently async flip is only supported via the drmModePageFlip IOCTL.
5983	* Correspondingly, support is currently added for primary plane only.
5984	*
5985	* Async flip can only change the plane surface address, so anything else
5986	* changing is rejected from the intel_async_flip_check_hw() function.
5987	* Once this check is cleared, flip done interrupt is enabled using
5988	* the intel_crtc_enable_flip_done() function.
5989	*
5990	* As soon as the surface address register is written, flip done interrupt is
5991	* generated and the requested events are sent to the userspace in the interrupt
5992	* handler itself. The timestamp and sequence sent during the flip done event
5993	* correspond to the last vblank and have no relation to the actual time when
5994	* the flip done event was sent.
5995	*/
5996	static int intel_async_flip_check_uapi(struct intel_atomic_state *state,
5997	struct intel_crtc *crtc)
5998	{
5999	struct intel_display *display = to_intel_display(state);
6000	const struct intel_crtc_state *new_crtc_state =
6001	intel_atomic_get_new_crtc_state(state, crtc);
6002	const struct intel_plane_state *old_plane_state;
6003	struct intel_plane_state *new_plane_state;
6004	struct intel_plane *plane;
6005	int i;
6006
6007	if (!new_crtc_state->uapi.async_flip)
6008	return 0;
6009
6010	if (!new_crtc_state->uapi.active) {
6011	drm_dbg_kms(display->drm,
6012	"[CRTC:%d:%s] not active\n",
6013	crtc->base.base.id, crtc->base.name);
6014	return -EINVAL;
6015	}
6016
6017	if (intel_crtc_needs_modeset(crtc_state: new_crtc_state)) {
6018	drm_dbg_kms(display->drm,
6019	"[CRTC:%d:%s] modeset required\n",
6020	crtc->base.base.id, crtc->base.name);
6021	return -EINVAL;
6022	}
6023
6024	/*
6025	* FIXME: joiner+async flip is busted currently.
6026	* Remove this check once the issues are fixed.
6027	*/
6028	if (new_crtc_state->joiner_pipes) {
6029	drm_dbg_kms(display->drm,
6030	"[CRTC:%d:%s] async flip disallowed with joiner\n",
6031	crtc->base.base.id, crtc->base.name);
6032	return -EINVAL;
6033	}
6034
6035	/* FIXME: selective fetch should be disabled for async flips */
6036	if (new_crtc_state->enable_psr2_sel_fetch) {
6037	drm_dbg_kms(display->drm,
6038	"[CRTC:%d:%s] async flip disallowed with PSR2 selective fetch\n",
6039	crtc->base.base.id, crtc->base.name);
6040	return -EINVAL;
6041	}
6042
6043	for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
6044	new_plane_state, i) {
6045	if (plane->pipe != crtc->pipe)
6046	continue;
6047
6048	/*
6049	* TODO: Async flip is only supported through the page flip IOCTL
6050	* as of now. So support currently added for primary plane only.
6051	* Support for other planes on platforms on which supports
6052	* this(vlv/chv and icl+) should be added when async flip is
6053	* enabled in the atomic IOCTL path.
6054	*/
6055	if (!plane->async_flip) {
6056	drm_dbg_kms(display->drm,
6057	"[PLANE:%d:%s] async flip not supported\n",
6058	plane->base.base.id, plane->base.name);
6059	return -EINVAL;
6060	}
6061
6062	if (!old_plane_state->uapi.fb || !new_plane_state->uapi.fb) {
6063	drm_dbg_kms(display->drm,
6064	"[PLANE:%d:%s] no old or new framebuffer\n",
6065	plane->base.base.id, plane->base.name);
6066	return -EINVAL;
6067	}
6068	}
6069
6070	return 0;
6071	}
6072
6073	static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct intel_crtc *crtc)
6074	{
6075	struct intel_display *display = to_intel_display(state);
6076	const struct intel_crtc_state *old_crtc_state, *new_crtc_state;
6077	const struct intel_plane_state *new_plane_state, *old_plane_state;
6078	struct intel_plane *plane;
6079	int i;
6080
6081	old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
6082	new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
6083
6084	if (!new_crtc_state->uapi.async_flip)
6085	return 0;
6086
6087	if (!new_crtc_state->hw.active) {
6088	drm_dbg_kms(display->drm,
6089	"[CRTC:%d:%s] not active\n",
6090	crtc->base.base.id, crtc->base.name);
6091	return -EINVAL;
6092	}
6093
6094	if (intel_crtc_needs_modeset(crtc_state: new_crtc_state)) {
6095	drm_dbg_kms(display->drm,
6096	"[CRTC:%d:%s] modeset required\n",
6097	crtc->base.base.id, crtc->base.name);
6098	return -EINVAL;
6099	}
6100
6101	if (old_crtc_state->active_planes != new_crtc_state->active_planes) {
6102	drm_dbg_kms(display->drm,
6103	"[CRTC:%d:%s] Active planes cannot be in async flip\n",
6104	crtc->base.base.id, crtc->base.name);
6105	return -EINVAL;
6106	}
6107
6108	for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
6109	new_plane_state, i) {
6110	if (plane->pipe != crtc->pipe)
6111	continue;
6112
6113	/*
6114	* Only async flip capable planes should be in the state
6115	* if we're really about to ask the hardware to perform
6116	* an async flip. We should never get this far otherwise.
6117	*/
6118	if (drm_WARN_ON(display->drm,
6119	new_crtc_state->do_async_flip && !plane->async_flip))
6120	return -EINVAL;
6121
6122	/*
6123	* Only check async flip capable planes other planes
6124	* may be involved in the initial commit due to
6125	* the wm0/ddb optimization.
6126	*
6127	* TODO maybe should track which planes actually
6128	* were requested to do the async flip...
6129	*/
6130	if (!plane->async_flip)
6131	continue;
6132
6133	if (!intel_plane_can_async_flip(plane, format: new_plane_state->hw.fb->format->format,
6134	modifier: new_plane_state->hw.fb->modifier)) {
6135	drm_dbg_kms(display->drm,
6136	"[PLANE:%d:%s] pixel format %p4cc / modifier 0x%llx does not support async flip\n",
6137	plane->base.base.id, plane->base.name,
6138	&new_plane_state->hw.fb->format->format,
6139	new_plane_state->hw.fb->modifier);
6140	return -EINVAL;
6141	}
6142
6143	/*
6144	* We turn the first async flip request into a sync flip
6145	* so that we can reconfigure the plane (eg. change modifier).
6146	*/
6147	if (!new_crtc_state->do_async_flip)
6148	continue;
6149
6150	if (old_plane_state->view.color_plane[0].mapping_stride !=
6151	new_plane_state->view.color_plane[0].mapping_stride) {
6152	drm_dbg_kms(display->drm,
6153	"[PLANE:%d:%s] Stride cannot be changed in async flip\n",
6154	plane->base.base.id, plane->base.name);
6155	return -EINVAL;
6156	}
6157
6158	if (old_plane_state->hw.fb->modifier !=
6159	new_plane_state->hw.fb->modifier) {
6160	drm_dbg_kms(display->drm,
6161	"[PLANE:%d:%s] Modifier cannot be changed in async flip\n",
6162	plane->base.base.id, plane->base.name);
6163	return -EINVAL;
6164	}
6165
6166	if (old_plane_state->hw.fb->format !=
6167	new_plane_state->hw.fb->format) {
6168	drm_dbg_kms(display->drm,
6169	"[PLANE:%d:%s] Pixel format cannot be changed in async flip\n",
6170	plane->base.base.id, plane->base.name);
6171	return -EINVAL;
6172	}
6173
6174	if (old_plane_state->hw.rotation !=
6175	new_plane_state->hw.rotation) {
6176	drm_dbg_kms(display->drm,
6177	"[PLANE:%d:%s] Rotation cannot be changed in async flip\n",
6178	plane->base.base.id, plane->base.name);
6179	return -EINVAL;
6180	}
6181
6182	if (skl_plane_aux_dist(plane_state: old_plane_state, color_plane: 0) !=
6183	skl_plane_aux_dist(plane_state: new_plane_state, color_plane: 0)) {
6184	drm_dbg_kms(display->drm,
6185	"[PLANE:%d:%s] AUX_DIST cannot be changed in async flip\n",
6186	plane->base.base.id, plane->base.name);
6187	return -EINVAL;
6188	}
6189
6190	if (!drm_rect_equals(r1: &old_plane_state->uapi.src, r2: &new_plane_state->uapi.src) ||
6191	!drm_rect_equals(r1: &old_plane_state->uapi.dst, r2: &new_plane_state->uapi.dst)) {
6192	drm_dbg_kms(display->drm,
6193	"[PLANE:%d:%s] Size/co-ordinates cannot be changed in async flip\n",
6194	plane->base.base.id, plane->base.name);
6195	return -EINVAL;
6196	}
6197
6198	if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) {
6199	drm_dbg_kms(display->drm,
6200	"[PLANES:%d:%s] Alpha value cannot be changed in async flip\n",
6201	plane->base.base.id, plane->base.name);
6202	return -EINVAL;
6203	}
6204
6205	if (old_plane_state->hw.pixel_blend_mode !=
6206	new_plane_state->hw.pixel_blend_mode) {
6207	drm_dbg_kms(display->drm,
6208	"[PLANE:%d:%s] Pixel blend mode cannot be changed in async flip\n",
6209	plane->base.base.id, plane->base.name);
6210	return -EINVAL;
6211	}
6212
6213	if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) {
6214	drm_dbg_kms(display->drm,
6215	"[PLANE:%d:%s] Color encoding cannot be changed in async flip\n",
6216	plane->base.base.id, plane->base.name);
6217	return -EINVAL;
6218	}
6219
6220	if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) {
6221	drm_dbg_kms(display->drm,
6222	"[PLANE:%d:%s] Color range cannot be changed in async flip\n",
6223	plane->base.base.id, plane->base.name);
6224	return -EINVAL;
6225	}
6226
6227	/* plane decryption is allow to change only in synchronous flips */
6228	if (old_plane_state->decrypt != new_plane_state->decrypt) {
6229	drm_dbg_kms(display->drm,
6230	"[PLANE:%d:%s] Decryption cannot be changed in async flip\n",
6231	plane->base.base.id, plane->base.name);
6232	return -EINVAL;
6233	}
6234	}
6235
6236	return 0;
6237	}
6238
6239	static int intel_joiner_add_affected_crtcs(struct intel_atomic_state *state)
6240	{
6241	struct intel_display *display = to_intel_display(state);
6242	const struct intel_plane_state *plane_state;
6243	struct intel_crtc_state *crtc_state;
6244	struct intel_plane *plane;
6245	struct intel_crtc *crtc;
6246	u8 affected_pipes = 0;
6247	u8 modeset_pipes = 0;
6248	int i;
6249
6250	/*
6251	* Any plane which is in use by the joiner needs its crtc.
6252	* Pull those in first as this will not have happened yet
6253	* if the plane remains disabled according to uapi.
6254	*/
6255	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
6256	crtc = to_intel_crtc(plane_state->hw.crtc);
6257	if (!crtc)
6258	continue;
6259
6260	crtc_state = intel_atomic_get_crtc_state(state: &state->base, crtc);
6261	if (IS_ERR(ptr: crtc_state))
6262	return PTR_ERR(ptr: crtc_state);
6263	}
6264
6265	/* Now pull in all joined crtcs */
6266	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
6267	affected_pipes |= crtc_state->joiner_pipes;
6268	if (intel_crtc_needs_modeset(crtc_state))
6269	modeset_pipes |= crtc_state->joiner_pipes;
6270	}
6271
6272	for_each_intel_crtc_in_pipe_mask(display->drm, crtc, affected_pipes) {
6273	crtc_state = intel_atomic_get_crtc_state(state: &state->base, crtc);
6274	if (IS_ERR(ptr: crtc_state))
6275	return PTR_ERR(ptr: crtc_state);
6276	}
6277
6278	for_each_intel_crtc_in_pipe_mask(display->drm, crtc, modeset_pipes) {
6279	int ret;
6280
6281	crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
6282
6283	crtc_state->uapi.mode_changed = true;
6284
6285	ret = drm_atomic_add_affected_connectors(state: &state->base, crtc: &crtc->base);
6286	if (ret)
6287	return ret;
6288
6289	ret = intel_plane_add_affected(state, crtc);
6290	if (ret)
6291	return ret;
6292	}
6293
6294	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
6295	/* Kill old joiner link, we may re-establish afterwards */
6296	if (intel_crtc_needs_modeset(crtc_state) &&
6297	intel_crtc_is_joiner_primary(crtc_state))
6298	kill_joiner_secondaries(state, primary_crtc: crtc);
6299	}
6300
6301	return 0;
6302	}
6303
6304	static int intel_atomic_check_config(struct intel_atomic_state *state,
6305	struct intel_link_bw_limits *limits,
6306	enum pipe *failed_pipe)
6307	{
6308	struct intel_display *display = to_intel_display(state);
6309	struct intel_crtc_state *new_crtc_state;
6310	struct intel_crtc *crtc;
6311	int ret;
6312	int i;
6313
6314	*failed_pipe = INVALID_PIPE;
6315
6316	ret = intel_joiner_add_affected_crtcs(state);
6317	if (ret)
6318	return ret;
6319
6320	ret = intel_fdi_add_affected_crtcs(state);
6321	if (ret)
6322	return ret;
6323
6324	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6325	if (!intel_crtc_needs_modeset(crtc_state: new_crtc_state)) {
6326	if (intel_crtc_is_joiner_secondary(crtc_state: new_crtc_state))
6327	copy_joiner_crtc_state_nomodeset(state, secondary_crtc: crtc);
6328	else
6329	intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc);
6330	continue;
6331	}
6332
6333	if (drm_WARN_ON(display->drm, intel_crtc_is_joiner_secondary(new_crtc_state)))
6334	continue;
6335
6336	ret = intel_crtc_prepare_cleared_state(state, crtc);
6337	if (ret)
6338	goto fail;
6339
6340	if (!new_crtc_state->hw.enable)
6341	continue;
6342
6343	ret = intel_modeset_pipe_config(state, crtc, limits);
6344	if (ret)
6345	goto fail;
6346	}
6347
6348	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6349	if (!intel_crtc_needs_modeset(crtc_state: new_crtc_state))
6350	continue;
6351
6352	if (drm_WARN_ON(display->drm, intel_crtc_is_joiner_secondary(new_crtc_state)))
6353	continue;
6354
6355	if (!new_crtc_state->hw.enable)
6356	continue;
6357
6358	ret = intel_modeset_pipe_config_late(state, crtc);
6359	if (ret)
6360	goto fail;
6361	}
6362
6363	fail:
6364	if (ret)
6365	*failed_pipe = crtc->pipe;
6366
6367	return ret;
6368	}
6369
6370	static int intel_atomic_check_config_and_link(struct intel_atomic_state *state)
6371	{
6372	struct intel_link_bw_limits new_limits;
6373	struct intel_link_bw_limits old_limits;
6374	int ret;
6375
6376	intel_link_bw_init_limits(state, limits: &new_limits);
6377	old_limits = new_limits;
6378
6379	while (true) {
6380	enum pipe failed_pipe;
6381
6382	ret = intel_atomic_check_config(state, limits: &new_limits,
6383	failed_pipe: &failed_pipe);
6384	if (ret) {
6385	/*
6386	* The bpp limit for a pipe is below the minimum it supports, set the
6387	* limit to the minimum and recalculate the config.
6388	*/
6389	if (ret == -EINVAL &&
6390	intel_link_bw_set_bpp_limit_for_pipe(state,
6391	old_limits: &old_limits,
6392	new_limits: &new_limits,
6393	pipe: failed_pipe))
6394	continue;
6395
6396	break;
6397	}
6398
6399	old_limits = new_limits;
6400
6401	ret = intel_link_bw_atomic_check(state, new_limits: &new_limits);
6402	if (ret != -EAGAIN)
6403	break;
6404	}
6405
6406	return ret;
6407	}
6408	/**
6409	* intel_atomic_check - validate state object
6410	* @dev: drm device
6411	* @_state: state to validate
6412	*/
6413	int intel_atomic_check(struct drm_device *dev,
6414	struct drm_atomic_state *_state)
6415	{
6416	struct intel_display *display = to_intel_display(dev);
6417	struct intel_atomic_state *state = to_intel_atomic_state(_state);
6418	struct intel_crtc_state *old_crtc_state, *new_crtc_state;
6419	struct intel_crtc *crtc;
6420	int ret, i;
6421
6422	if (!intel_display_driver_check_access(display))
6423	return -ENODEV;
6424
6425	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6426	new_crtc_state, i) {
6427	/*
6428	* crtc's state no longer considered to be inherited
6429	* after the first userspace/client initiated commit.
6430	*/
6431	if (!state->internal)
6432	new_crtc_state->inherited = false;
6433
6434	if (new_crtc_state->inherited != old_crtc_state->inherited)
6435	new_crtc_state->uapi.mode_changed = true;
6436
6437	if (new_crtc_state->uapi.scaling_filter !=
6438	old_crtc_state->uapi.scaling_filter)
6439	new_crtc_state->uapi.mode_changed = true;
6440	}
6441
6442	intel_vrr_check_modeset(state);
6443
6444	ret = drm_atomic_helper_check_modeset(dev, state: &state->base);
6445	if (ret)
6446	goto fail;
6447
6448	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6449	ret = intel_async_flip_check_uapi(state, crtc);
6450	if (ret)
6451	return ret;
6452	}
6453
6454	ret = intel_atomic_check_config_and_link(state);
6455	if (ret)
6456	goto fail;
6457
6458	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6459	if (!intel_crtc_needs_modeset(crtc_state: new_crtc_state))
6460	continue;
6461
6462	if (intel_crtc_is_joiner_secondary(crtc_state: new_crtc_state)) {
6463	drm_WARN_ON(display->drm, new_crtc_state->uapi.enable);
6464	continue;
6465	}
6466
6467	ret = intel_atomic_check_joiner(state, primary_crtc: crtc);
6468	if (ret)
6469	goto fail;
6470	}
6471
6472	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6473	new_crtc_state, i) {
6474	if (!intel_crtc_needs_modeset(crtc_state: new_crtc_state))
6475	continue;
6476
6477	intel_joiner_adjust_pipe_src(crtc_state: new_crtc_state);
6478
6479	intel_crtc_check_fastset(old_crtc_state, new_crtc_state);
6480	}
6481
6482	/**
6483	* Check if fastset is allowed by external dependencies like other
6484	* pipes and transcoders.
6485	*
6486	* Right now it only forces a fullmodeset when the MST master
6487	* transcoder did not changed but the pipe of the master transcoder
6488	* needs a fullmodeset so all slaves also needs to do a fullmodeset or
6489	* in case of port synced crtcs, if one of the synced crtcs
6490	* needs a full modeset, all other synced crtcs should be
6491	* forced a full modeset.
6492	*/
6493	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6494	if (!new_crtc_state->hw.enable || intel_crtc_needs_modeset(crtc_state: new_crtc_state))
6495	continue;
6496
6497	if (intel_dp_mst_crtc_needs_modeset(state, crtc))
6498	intel_crtc_flag_modeset(crtc_state: new_crtc_state);
6499
6500	if (intel_dp_mst_is_slave_trans(crtc_state: new_crtc_state)) {
6501	enum transcoder master = new_crtc_state->mst_master_transcoder;
6502
6503	if (intel_cpu_transcoders_need_modeset(state, BIT(master)))
6504	intel_crtc_flag_modeset(crtc_state: new_crtc_state);
6505	}
6506
6507	if (is_trans_port_sync_mode(crtc_state: new_crtc_state)) {
6508	u8 trans = new_crtc_state->sync_mode_slaves_mask;
6509
6510	if (new_crtc_state->master_transcoder != INVALID_TRANSCODER)
6511	trans |= BIT(new_crtc_state->master_transcoder);
6512
6513	if (intel_cpu_transcoders_need_modeset(state, transcoders: trans))
6514	intel_crtc_flag_modeset(crtc_state: new_crtc_state);
6515	}
6516
6517	if (new_crtc_state->joiner_pipes) {
6518	if (intel_pipes_need_modeset(state, pipes: new_crtc_state->joiner_pipes))
6519	intel_crtc_flag_modeset(crtc_state: new_crtc_state);
6520	}
6521	}
6522
6523	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6524	new_crtc_state, i) {
6525	if (!intel_crtc_needs_modeset(crtc_state: new_crtc_state))
6526	continue;
6527
6528	intel_dpll_release(state, crtc);
6529	}
6530
6531	if (intel_any_crtc_needs_modeset(state) && !check_digital_port_conflicts(state)) {
6532	drm_dbg_kms(display->drm, "rejecting conflicting digital port configuration\n");
6533	ret = -EINVAL;
6534	goto fail;
6535	}
6536
6537	ret = intel_plane_atomic_check(state);
6538	if (ret)
6539	goto fail;
6540
6541	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
6542	new_crtc_state->min_cdclk = intel_crtc_min_cdclk(crtc_state: new_crtc_state);
6543
6544	ret = intel_compute_global_watermarks(state);
6545	if (ret)
6546	goto fail;
6547
6548	ret = intel_bw_atomic_check(state);
6549	if (ret)
6550	goto fail;
6551
6552	ret = intel_cdclk_atomic_check(state);
6553	if (ret)
6554	goto fail;
6555
6556	if (intel_any_crtc_needs_modeset(state)) {
6557	ret = intel_modeset_checks(state);
6558	if (ret)
6559	goto fail;
6560	}
6561
6562	ret = intel_pmdemand_atomic_check(state);
6563	if (ret)
6564	goto fail;
6565
6566	ret = intel_atomic_check_crtcs(state);
6567	if (ret)
6568	goto fail;
6569
6570	ret = intel_fbc_atomic_check(state);
6571	if (ret)
6572	goto fail;
6573
6574	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6575	new_crtc_state, i) {
6576	intel_color_assert_luts(crtc_state: new_crtc_state);
6577
6578	ret = intel_async_flip_check_hw(state, crtc);
6579	if (ret)
6580	goto fail;
6581
6582	/* Either full modeset or fastset (or neither), never both */
6583	drm_WARN_ON(display->drm,
6584	intel_crtc_needs_modeset(new_crtc_state) &&
6585	intel_crtc_needs_fastset(new_crtc_state));
6586
6587	if (!intel_crtc_needs_modeset(crtc_state: new_crtc_state) &&
6588	!intel_crtc_needs_fastset(crtc_state: new_crtc_state))
6589	continue;
6590
6591	intel_crtc_state_dump(crtc_state: new_crtc_state, state,
6592	context: intel_crtc_needs_modeset(crtc_state: new_crtc_state) ?
6593	"modeset" : "fastset");
6594	}
6595
6596	return 0;
6597
6598	fail:
6599	if (ret == -EDEADLK)
6600	return ret;
6601
6602	/*
6603	* FIXME would probably be nice to know which crtc specifically
6604	* caused the failure, in cases where we can pinpoint it.
6605	*/
6606	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6607	new_crtc_state, i)
6608	intel_crtc_state_dump(crtc_state: new_crtc_state, state, context: "failed");
6609
6610	return ret;
6611	}
6612
6613	static int intel_atomic_prepare_commit(struct intel_atomic_state *state)
6614	{
6615	int ret;
6616
6617	ret = drm_atomic_helper_prepare_planes(dev: state->base.dev, state: &state->base);
6618	if (ret < 0)
6619	return ret;
6620
6621	return 0;
6622	}
6623
6624	void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
6625	struct intel_crtc_state *crtc_state)
6626	{
6627	struct intel_display *display = to_intel_display(crtc);
6628
6629	if (DISPLAY_VER(display) != 2 || crtc_state->active_planes)
6630	intel_set_cpu_fifo_underrun_reporting(display, pipe: crtc->pipe, enable: true);
6631
6632	if (crtc_state->has_pch_encoder) {
6633	enum pipe pch_transcoder =
6634	intel_crtc_pch_transcoder(crtc);
6635
6636	intel_set_pch_fifo_underrun_reporting(display, pch_transcoder, enable: true);
6637	}
6638	}
6639
6640	static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
6641	const struct intel_crtc_state *new_crtc_state)
6642	{
6643	struct intel_display *display = to_intel_display(new_crtc_state);
6644	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
6645
6646	/*
6647	* Update pipe size and adjust fitter if needed: the reason for this is
6648	* that in compute_mode_changes we check the native mode (not the pfit
6649	* mode) to see if we can flip rather than do a full mode set. In the
6650	* fastboot case, we'll flip, but if we don't update the pipesrc and
6651	* pfit state, we'll end up with a big fb scanned out into the wrong
6652	* sized surface.
6653	*/
6654	intel_set_pipe_src_size(crtc_state: new_crtc_state);
6655
6656	/* on skylake this is done by detaching scalers */
6657	if (DISPLAY_VER(display) >= 9) {
6658	if (new_crtc_state->pch_pfit.enabled)
6659	skl_pfit_enable(crtc_state: new_crtc_state);
6660	} else if (HAS_PCH_SPLIT(display)) {
6661	if (new_crtc_state->pch_pfit.enabled)
6662	ilk_pfit_enable(crtc_state: new_crtc_state);
6663	else if (old_crtc_state->pch_pfit.enabled)
6664	ilk_pfit_disable(old_crtc_state);
6665	}
6666
6667	/*
6668	* The register is supposedly single buffered so perhaps
6669	* not 100% correct to do this here. But SKL+ calculate
6670	* this based on the adjust pixel rate so pfit changes do
6671	* affect it and so it must be updated for fastsets.
6672	* HSW/BDW only really need this here for fastboot, after
6673	* that the value should not change without a full modeset.
6674	*/
6675	if (DISPLAY_VER(display) >= 9 ||
6676	display->platform.broadwell || display->platform.haswell)
6677	hsw_set_linetime_wm(crtc_state: new_crtc_state);
6678
6679	if (new_crtc_state->update_m_n)
6680	intel_cpu_transcoder_set_m1_n1(crtc, transcoder: new_crtc_state->cpu_transcoder,
6681	m_n: &new_crtc_state->dp_m_n);
6682
6683	if (new_crtc_state->update_lrr)
6684	intel_set_transcoder_timings_lrr(crtc_state: new_crtc_state);
6685	}
6686
6687	static void commit_pipe_pre_planes(struct intel_atomic_state *state,
6688	struct intel_crtc *crtc)
6689	{
6690	struct intel_display *display = to_intel_display(state);
6691	const struct intel_crtc_state *old_crtc_state =
6692	intel_atomic_get_old_crtc_state(state, crtc);
6693	const struct intel_crtc_state *new_crtc_state =
6694	intel_atomic_get_new_crtc_state(state, crtc);
6695	bool modeset = intel_crtc_needs_modeset(crtc_state: new_crtc_state);
6696
6697	drm_WARN_ON(display->drm, new_crtc_state->use_dsb || new_crtc_state->use_flipq);
6698
6699	/*
6700	* During modesets pipe configuration was programmed as the
6701	* CRTC was enabled.
6702	*/
6703	if (!modeset) {
6704	if (intel_crtc_needs_color_update(crtc_state: new_crtc_state))
6705	intel_color_commit_arm(NULL, crtc_state: new_crtc_state);
6706
6707	if (DISPLAY_VER(display) >= 9 || display->platform.broadwell)
6708	bdw_set_pipe_misc(NULL, crtc_state: new_crtc_state);
6709
6710	if (intel_crtc_needs_fastset(crtc_state: new_crtc_state))
6711	intel_pipe_fastset(old_crtc_state, new_crtc_state);
6712	}
6713
6714	intel_psr2_program_trans_man_trk_ctl(NULL, crtc_state: new_crtc_state);
6715
6716	intel_atomic_update_watermarks(state, crtc);
6717	}
6718
6719	static void commit_pipe_post_planes(struct intel_atomic_state *state,
6720	struct intel_crtc *crtc)
6721	{
6722	struct intel_display *display = to_intel_display(state);
6723	const struct intel_crtc_state *new_crtc_state =
6724	intel_atomic_get_new_crtc_state(state, crtc);
6725	bool modeset = intel_crtc_needs_modeset(crtc_state: new_crtc_state);
6726
6727	drm_WARN_ON(display->drm, new_crtc_state->use_dsb || new_crtc_state->use_flipq);
6728
6729	/*
6730	* Disable the scaler(s) after the plane(s) so that we don't
6731	* get a catastrophic underrun even if the two operations
6732	* end up happening in two different frames.
6733	*/
6734	if (DISPLAY_VER(display) >= 9 && !modeset)
6735	skl_detach_scalers(NULL, crtc_state: new_crtc_state);
6736
6737	if (!modeset &&
6738	intel_crtc_needs_color_update(crtc_state: new_crtc_state) &&
6739	!intel_color_uses_dsb(crtc_state: new_crtc_state) &&
6740	HAS_DOUBLE_BUFFERED_LUT(display))
6741	intel_color_load_luts(crtc_state: new_crtc_state);
6742
6743	if (intel_crtc_vrr_enabling(state, crtc))
6744	intel_vrr_enable(crtc_state: new_crtc_state);
6745	}
6746
6747	static void intel_enable_crtc(struct intel_atomic_state *state,
6748	struct intel_crtc *crtc)
6749	{
6750	struct intel_display *display = to_intel_display(state);
6751	const struct intel_crtc_state *new_crtc_state =
6752	intel_atomic_get_new_crtc_state(state, crtc);
6753	struct intel_crtc *pipe_crtc;
6754
6755	if (!intel_crtc_needs_modeset(crtc_state: new_crtc_state))
6756	return;
6757
6758	for_each_intel_crtc_in_pipe_mask_reverse(display->drm, pipe_crtc,
6759	intel_crtc_joined_pipe_mask(new_crtc_state)) {
6760	const struct intel_crtc_state *pipe_crtc_state =
6761	intel_atomic_get_new_crtc_state(state, crtc: pipe_crtc);
6762
6763	/* VRR will be enable later, if required */
6764	intel_crtc_update_active_timings(crtc_state: pipe_crtc_state, vrr_enable: false);
6765	}
6766
6767	intel_psr_notify_pipe_change(state, crtc, enable: true);
6768
6769	display->funcs.display->crtc_enable(state, crtc);
6770
6771	/* vblanks work again, re-enable pipe CRC. */
6772	intel_crtc_enable_pipe_crc(crtc);
6773	}
6774
6775	static void intel_pre_update_crtc(struct intel_atomic_state *state,
6776	struct intel_crtc *crtc)
6777	{
6778	struct intel_display *display = to_intel_display(state);
6779	const struct intel_crtc_state *old_crtc_state =
6780	intel_atomic_get_old_crtc_state(state, crtc);
6781	struct intel_crtc_state *new_crtc_state =
6782	intel_atomic_get_new_crtc_state(state, crtc);
6783	bool modeset = intel_crtc_needs_modeset(crtc_state: new_crtc_state);
6784
6785	if (old_crtc_state->inherited ||
6786	intel_crtc_needs_modeset(crtc_state: new_crtc_state)) {
6787	if (HAS_DPT(display))
6788	intel_dpt_configure(crtc);
6789	}
6790
6791	if (!modeset) {
6792	if (new_crtc_state->preload_luts &&
6793	intel_crtc_needs_color_update(crtc_state: new_crtc_state))
6794	intel_color_load_luts(crtc_state: new_crtc_state);
6795
6796	intel_pre_plane_update(state, crtc);
6797
6798	if (intel_crtc_needs_fastset(crtc_state: new_crtc_state))
6799	intel_encoders_update_pipe(state, crtc);
6800
6801	if (DISPLAY_VER(display) >= 11 &&
6802	intel_crtc_needs_fastset(crtc_state: new_crtc_state))
6803	icl_set_pipe_chicken(crtc_state: new_crtc_state);
6804
6805	if (vrr_params_changed(old_crtc_state, new_crtc_state) ||
6806	cmrr_params_changed(old_crtc_state, new_crtc_state))
6807	intel_vrr_set_transcoder_timings(crtc_state: new_crtc_state);
6808	}
6809
6810	if (intel_casf_enabling(new_crtc_state, old_crtc_state))
6811	intel_casf_enable(crtc_state: new_crtc_state);
6812	else if (new_crtc_state->hw.casf_params.strength != old_crtc_state->hw.casf_params.strength)
6813	intel_casf_update_strength(new_crtc_state);
6814
6815	intel_fbc_update(state, crtc);
6816
6817	drm_WARN_ON(display->drm, !intel_display_power_is_enabled(display, POWER_DOMAIN_DC_OFF));
6818
6819	if (!modeset &&
6820	intel_crtc_needs_color_update(crtc_state: new_crtc_state) &&
6821	!new_crtc_state->use_dsb && !new_crtc_state->use_flipq)
6822	intel_color_commit_noarm(NULL, crtc_state: new_crtc_state);
6823
6824	if (!new_crtc_state->use_dsb && !new_crtc_state->use_flipq)
6825	intel_crtc_planes_update_noarm(NULL, state, crtc);
6826	}
6827
6828	static void intel_update_crtc(struct intel_atomic_state *state,
6829	struct intel_crtc *crtc)
6830	{
6831	const struct intel_crtc_state *old_crtc_state =
6832	intel_atomic_get_old_crtc_state(state, crtc);
6833	struct intel_crtc_state *new_crtc_state =
6834	intel_atomic_get_new_crtc_state(state, crtc);
6835
6836	if (new_crtc_state->use_flipq) {
6837	intel_flipq_enable(crtc_state: new_crtc_state);
6838
6839	intel_crtc_prepare_vblank_event(crtc_state: new_crtc_state, event: &crtc->flipq_event);
6840
6841	intel_flipq_add(crtc, flip_queue_id: INTEL_FLIPQ_PLANE_1, pts: 0, dsb_id: INTEL_DSB_0,
6842	dsb: new_crtc_state->dsb_commit);
6843	} else if (new_crtc_state->use_dsb) {
6844	intel_crtc_prepare_vblank_event(crtc_state: new_crtc_state, event: &crtc->dsb_event);
6845
6846	intel_dsb_commit(dsb: new_crtc_state->dsb_commit);
6847	} else {
6848	/* Perform vblank evasion around commit operation */
6849	intel_pipe_update_start(state, crtc);
6850
6851	if (new_crtc_state->dsb_commit)
6852	intel_dsb_commit(dsb: new_crtc_state->dsb_commit);
6853
6854	commit_pipe_pre_planes(state, crtc);
6855
6856	intel_crtc_planes_update_arm(NULL, state, crtc);
6857
6858	commit_pipe_post_planes(state, crtc);
6859
6860	intel_pipe_update_end(state, crtc);
6861	}
6862
6863	/*
6864	* VRR/Seamless M/N update may need to update frame timings.
6865	*
6866	* FIXME Should be synchronized with the start of vblank somehow...
6867	*/
6868	if (intel_crtc_vrr_enabling(state, crtc) ||
6869	new_crtc_state->update_m_n || new_crtc_state->update_lrr)
6870	intel_crtc_update_active_timings(crtc_state: new_crtc_state,
6871	vrr_enable: new_crtc_state->vrr.enable);
6872
6873	/*
6874	* We usually enable FIFO underrun interrupts as part of the
6875	* CRTC enable sequence during modesets. But when we inherit a
6876	* valid pipe configuration from the BIOS we need to take care
6877	* of enabling them on the CRTC's first fastset.
6878	*/
6879	if (intel_crtc_needs_fastset(crtc_state: new_crtc_state) &&
6880	old_crtc_state->inherited)
6881	intel_crtc_arm_fifo_underrun(crtc, crtc_state: new_crtc_state);
6882	}
6883
6884	static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
6885	struct intel_crtc *crtc)
6886	{
6887	struct intel_display *display = to_intel_display(state);
6888	const struct intel_crtc_state *old_crtc_state =
6889	intel_atomic_get_old_crtc_state(state, crtc);
6890	struct intel_crtc *pipe_crtc;
6891
6892	/*
6893	* We need to disable pipe CRC before disabling the pipe,
6894	* or we race against vblank off.
6895	*/
6896	for_each_intel_crtc_in_pipe_mask(display->drm, pipe_crtc,
6897	intel_crtc_joined_pipe_mask(old_crtc_state))
6898	intel_crtc_disable_pipe_crc(crtc: pipe_crtc);
6899
6900	intel_psr_notify_pipe_change(state, crtc, enable: false);
6901
6902	display->funcs.display->crtc_disable(state, crtc);
6903
6904	for_each_intel_crtc_in_pipe_mask(display->drm, pipe_crtc,
6905	intel_crtc_joined_pipe_mask(old_crtc_state)) {
6906	const struct intel_crtc_state *new_pipe_crtc_state =
6907	intel_atomic_get_new_crtc_state(state, crtc: pipe_crtc);
6908
6909	pipe_crtc->active = false;
6910	intel_fbc_disable(crtc: pipe_crtc);
6911
6912	if (!new_pipe_crtc_state->hw.active)
6913	intel_initial_watermarks(state, crtc: pipe_crtc);
6914	}
6915	}
6916
6917	static void intel_commit_modeset_disables(struct intel_atomic_state *state)
6918	{
6919	struct intel_display *display = to_intel_display(state);
6920	const struct intel_crtc_state *new_crtc_state, *old_crtc_state;
6921	struct intel_crtc *crtc;
6922	u8 disable_pipes = 0;
6923	int i;
6924
6925	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6926	new_crtc_state, i) {
6927	if (!intel_crtc_needs_modeset(crtc_state: new_crtc_state))
6928	continue;
6929
6930	/*
6931	* Needs to be done even for pipes
6932	* that weren't enabled previously.
6933	*/
6934	intel_pre_plane_update(state, crtc);
6935
6936	if (!old_crtc_state->hw.active)
6937	continue;
6938
6939	disable_pipes |= BIT(crtc->pipe);
6940	}
6941
6942	for_each_old_intel_crtc_in_state(state, crtc, old_crtc_state, i) {
6943	if ((disable_pipes & BIT(crtc->pipe)) == 0)
6944	continue;
6945
6946	intel_crtc_disable_planes(state, crtc);
6947
6948	drm_vblank_work_flush_all(crtc: &crtc->base);
6949	}
6950
6951	/* Only disable port sync and MST slaves */
6952	for_each_old_intel_crtc_in_state(state, crtc, old_crtc_state, i) {
6953	if ((disable_pipes & BIT(crtc->pipe)) == 0)
6954	continue;
6955
6956	if (intel_crtc_is_joiner_secondary(crtc_state: old_crtc_state))
6957	continue;
6958
6959	/* In case of Transcoder port Sync master slave CRTCs can be
6960	* assigned in any order and we need to make sure that
6961	* slave CRTCs are disabled first and then master CRTC since
6962	* Slave vblanks are masked till Master Vblanks.
6963	*/
6964	if (!is_trans_port_sync_slave(crtc_state: old_crtc_state) &&
6965	!intel_dp_mst_is_slave_trans(crtc_state: old_crtc_state))
6966	continue;
6967
6968	intel_old_crtc_state_disables(state, crtc);
6969
6970	disable_pipes &= ~intel_crtc_joined_pipe_mask(crtc_state: old_crtc_state);
6971	}
6972
6973	/* Disable everything else left on */
6974	for_each_old_intel_crtc_in_state(state, crtc, old_crtc_state, i) {
6975	if ((disable_pipes & BIT(crtc->pipe)) == 0)
6976	continue;
6977
6978	if (intel_crtc_is_joiner_secondary(crtc_state: old_crtc_state))
6979	continue;
6980
6981	intel_old_crtc_state_disables(state, crtc);
6982
6983	disable_pipes &= ~intel_crtc_joined_pipe_mask(crtc_state: old_crtc_state);
6984	}
6985
6986	drm_WARN_ON(display->drm, disable_pipes);
6987	}
6988
6989	static void intel_commit_modeset_enables(struct intel_atomic_state *state)
6990	{
6991	struct intel_crtc_state *new_crtc_state;
6992	struct intel_crtc *crtc;
6993	int i;
6994
6995	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6996	if (!new_crtc_state->hw.active)
6997	continue;
6998
6999	intel_enable_crtc(state, crtc);
7000	intel_pre_update_crtc(state, crtc);
7001	}
7002
7003	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7004	if (!new_crtc_state->hw.active)
7005	continue;
7006
7007	intel_update_crtc(state, crtc);
7008	}
7009	}
7010
7011	static void skl_commit_modeset_enables(struct intel_atomic_state *state)
7012	{
7013	struct intel_display *display = to_intel_display(state);
7014	struct intel_crtc *crtc;
7015	struct intel_crtc_state *old_crtc_state, *new_crtc_state;
7016	struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
7017	u8 update_pipes = 0, modeset_pipes = 0;
7018	int i;
7019
7020	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
7021	enum pipe pipe = crtc->pipe;
7022
7023	if (!new_crtc_state->hw.active)
7024	continue;
7025
7026	/* ignore allocations for crtc's that have been turned off. */
7027	if (!intel_crtc_needs_modeset(crtc_state: new_crtc_state)) {
7028	entries[pipe] = old_crtc_state->wm.skl.ddb;
7029	update_pipes |= BIT(pipe);
7030	} else {
7031	modeset_pipes |= BIT(pipe);
7032	}
7033	}
7034
7035	/*
7036	* Whenever the number of active pipes changes, we need to make sure we
7037	* update the pipes in the right order so that their ddb allocations
7038	* never overlap with each other between CRTC updates. Otherwise we'll
7039	* cause pipe underruns and other bad stuff.
7040	*
7041	* So first lets enable all pipes that do not need a fullmodeset as
7042	* those don't have any external dependency.
7043	*/
7044	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7045	enum pipe pipe = crtc->pipe;
7046
7047	if ((update_pipes & BIT(pipe)) == 0)
7048	continue;
7049
7050	intel_pre_update_crtc(state, crtc);
7051	}
7052
7053	intel_dbuf_mbus_pre_ddb_update(state);
7054
7055	while (update_pipes) {
7056	/*
7057	* Commit in reverse order to make joiner primary
7058	* send the uapi events after secondaries are done.
7059	*/
7060	for_each_oldnew_intel_crtc_in_state_reverse(state, crtc, old_crtc_state,
7061	new_crtc_state, i) {
7062	enum pipe pipe = crtc->pipe;
7063
7064	if ((update_pipes & BIT(pipe)) == 0)
7065	continue;
7066
7067	if (skl_ddb_allocation_overlaps(ddb: &new_crtc_state->wm.skl.ddb,
7068	entries, num_entries: I915_MAX_PIPES, ignore_idx: pipe))
7069	continue;
7070
7071	entries[pipe] = new_crtc_state->wm.skl.ddb;
7072	update_pipes &= ~BIT(pipe);
7073
7074	intel_update_crtc(state, crtc);
7075
7076	/*
7077	* If this is an already active pipe, it's DDB changed,
7078	* and this isn't the last pipe that needs updating
7079	* then we need to wait for a vblank to pass for the
7080	* new ddb allocation to take effect.
7081	*/
7082	if (!skl_ddb_entry_equal(e1: &new_crtc_state->wm.skl.ddb,
7083	e2: &old_crtc_state->wm.skl.ddb) &&
7084	(update_pipes | modeset_pipes))
7085	intel_crtc_wait_for_next_vblank(crtc);
7086	}
7087	}
7088
7089	intel_dbuf_mbus_post_ddb_update(state);
7090
7091	update_pipes = modeset_pipes;
7092
7093	/*
7094	* Enable all pipes that needs a modeset and do not depends on other
7095	* pipes
7096	*/
7097	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7098	enum pipe pipe = crtc->pipe;
7099
7100	if ((modeset_pipes & BIT(pipe)) == 0)
7101	continue;
7102
7103	if (intel_crtc_is_joiner_secondary(crtc_state: new_crtc_state))
7104	continue;
7105
7106	if (intel_dp_mst_is_slave_trans(crtc_state: new_crtc_state) ||
7107	is_trans_port_sync_master(crtc_state: new_crtc_state))
7108	continue;
7109
7110	modeset_pipes &= ~intel_crtc_joined_pipe_mask(crtc_state: new_crtc_state);
7111
7112	intel_enable_crtc(state, crtc);
7113	}
7114
7115	/*
7116	* Then we enable all remaining pipes that depend on other
7117	* pipes: MST slaves and port sync masters
7118	*/
7119	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7120	enum pipe pipe = crtc->pipe;
7121
7122	if ((modeset_pipes & BIT(pipe)) == 0)
7123	continue;
7124
7125	if (intel_crtc_is_joiner_secondary(crtc_state: new_crtc_state))
7126	continue;
7127
7128	modeset_pipes &= ~intel_crtc_joined_pipe_mask(crtc_state: new_crtc_state);
7129
7130	intel_enable_crtc(state, crtc);
7131	}
7132
7133	/*
7134	* Finally we do the plane updates/etc. for all pipes that got enabled.
7135	*/
7136	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7137	enum pipe pipe = crtc->pipe;
7138
7139	if ((update_pipes & BIT(pipe)) == 0)
7140	continue;
7141
7142	intel_pre_update_crtc(state, crtc);
7143	}
7144
7145	/*
7146	* Commit in reverse order to make joiner primary
7147	* send the uapi events after secondaries are done.
7148	*/
7149	for_each_new_intel_crtc_in_state_reverse(state, crtc, new_crtc_state, i) {
7150	enum pipe pipe = crtc->pipe;
7151
7152	if ((update_pipes & BIT(pipe)) == 0)
7153	continue;
7154
7155	drm_WARN_ON(display->drm,
7156	skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
7157	entries, I915_MAX_PIPES, pipe));
7158
7159	entries[pipe] = new_crtc_state->wm.skl.ddb;
7160	update_pipes &= ~BIT(pipe);
7161
7162	intel_update_crtc(state, crtc);
7163	}
7164
7165	drm_WARN_ON(display->drm, modeset_pipes);
7166	drm_WARN_ON(display->drm, update_pipes);
7167	}
7168
7169	static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state)
7170	{
7171	struct drm_i915_private *i915 = to_i915(dev: intel_state->base.dev);
7172	struct drm_plane *plane;
7173	struct drm_plane_state *new_plane_state;
7174	long ret;
7175	int i;
7176
7177	for_each_new_plane_in_state(&intel_state->base, plane, new_plane_state, i) {
7178	if (new_plane_state->fence) {
7179	ret = dma_fence_wait_timeout(new_plane_state->fence, intr: false,
7180	timeout: i915_fence_timeout(i915));
7181	if (ret <= 0)
7182	break;
7183
7184	dma_fence_put(fence: new_plane_state->fence);
7185	new_plane_state->fence = NULL;
7186	}
7187	}
7188	}
7189
7190	static void intel_atomic_dsb_wait_commit(struct intel_crtc_state *crtc_state)
7191	{
7192	if (crtc_state->dsb_commit)
7193	intel_dsb_wait(dsb: crtc_state->dsb_commit);
7194
7195	intel_color_wait_commit(crtc_state);
7196	}
7197
7198	static void intel_atomic_dsb_cleanup(struct intel_crtc_state *crtc_state)
7199	{
7200	if (crtc_state->dsb_commit) {
7201	intel_dsb_cleanup(dsb: crtc_state->dsb_commit);
7202	crtc_state->dsb_commit = NULL;
7203	}
7204
7205	intel_color_cleanup_commit(crtc_state);
7206	}
7207
7208	static void intel_atomic_cleanup_work(struct work_struct *work)
7209	{
7210	struct intel_atomic_state *state =
7211	container_of(work, struct intel_atomic_state, cleanup_work);
7212	struct intel_display *display = to_intel_display(state);
7213	struct intel_crtc_state *old_crtc_state;
7214	struct intel_crtc *crtc;
7215	int i;
7216
7217	for_each_old_intel_crtc_in_state(state, crtc, old_crtc_state, i)
7218	intel_atomic_dsb_cleanup(crtc_state: old_crtc_state);
7219
7220	drm_atomic_helper_cleanup_planes(dev: display->drm, old_state: &state->base);
7221	drm_atomic_helper_commit_cleanup_done(state: &state->base);
7222	drm_atomic_state_put(state: &state->base);
7223	}
7224
7225	static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *state)
7226	{
7227	struct intel_display *display = to_intel_display(state);
7228	struct intel_plane *plane;
7229	struct intel_plane_state *plane_state;
7230	int i;
7231
7232	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
7233	struct drm_framebuffer *fb = plane_state->hw.fb;
7234	int cc_plane;
7235	int ret;
7236
7237	if (!fb)
7238	continue;
7239
7240	cc_plane = intel_fb_rc_ccs_cc_plane(fb);
7241	if (cc_plane < 0)
7242	continue;
7243
7244	/*
7245	* The layout of the fast clear color value expected by HW
7246	* (the DRM ABI requiring this value to be located in fb at
7247	* offset 0 of cc plane, plane #2 previous generations or
7248	* plane #1 for flat ccs):
7249	* - 4 x 4 bytes per-channel value
7250	* (in surface type specific float/int format provided by the fb user)
7251	* - 8 bytes native color value used by the display
7252	* (converted/written by GPU during a fast clear operation using the
7253	* above per-channel values)
7254	*
7255	* The commit's FB prepare hook already ensured that FB obj is pinned and the
7256	* caller made sure that the object is synced wrt. the related color clear value
7257	* GPU write on it.
7258	*/
7259	ret = intel_bo_read_from_page(obj: intel_fb_bo(fb),
7260	offset: fb->offsets[cc_plane] + 16,
7261	dst: &plane_state->ccval,
7262	size: sizeof(plane_state->ccval));
7263	/* The above could only fail if the FB obj has an unexpected backing store type. */
7264	drm_WARN_ON(display->drm, ret);
7265	}
7266	}
7267
7268	static void intel_atomic_dsb_prepare(struct intel_atomic_state *state,
7269	struct intel_crtc *crtc)
7270	{
7271	struct intel_display *display = to_intel_display(state);
7272	struct intel_crtc_state *new_crtc_state =
7273	intel_atomic_get_new_crtc_state(state, crtc);
7274
7275	if (!new_crtc_state->hw.active)
7276	return;
7277
7278	if (state->base.legacy_cursor_update)
7279	return;
7280
7281	/* FIXME deal with everything */
7282	new_crtc_state->use_flipq =
7283	intel_flipq_supported(display) &&
7284	!new_crtc_state->do_async_flip &&
7285	!new_crtc_state->vrr.enable &&
7286	!new_crtc_state->has_psr &&
7287	!intel_crtc_needs_modeset(crtc_state: new_crtc_state) &&
7288	!intel_crtc_needs_fastset(crtc_state: new_crtc_state) &&
7289	!intel_crtc_needs_color_update(crtc_state: new_crtc_state);
7290
7291	new_crtc_state->use_dsb =
7292	!new_crtc_state->use_flipq &&
7293	!new_crtc_state->do_async_flip &&
7294	(DISPLAY_VER(display) >= 20 || !new_crtc_state->has_psr) &&
7295	!intel_crtc_needs_modeset(crtc_state: new_crtc_state) &&
7296	!intel_crtc_needs_fastset(crtc_state: new_crtc_state);
7297
7298	intel_color_prepare_commit(state, crtc);
7299	}
7300
7301	static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
7302	struct intel_crtc *crtc)
7303	{
7304	struct intel_display *display = to_intel_display(state);
7305	struct intel_crtc_state *new_crtc_state =
7306	intel_atomic_get_new_crtc_state(state, crtc);
7307	unsigned int size = new_crtc_state->plane_color_changed ? 8192 : 1024;
7308
7309	if (!new_crtc_state->use_flipq &&
7310	!new_crtc_state->use_dsb &&
7311	!new_crtc_state->dsb_color)
7312	return;
7313
7314	/*
7315	* Rough estimate:
7316	* ~64 registers per each plane * 8 planes = 512
7317	* Double that for pipe stuff and other overhead.
7318	* ~4913 registers for 3DLUT
7319	* ~200 color registers * 3 HDR planes
7320	*/
7321	new_crtc_state->dsb_commit = intel_dsb_prepare(state, crtc, dsb_id: INTEL_DSB_0,
7322	max_cmds: new_crtc_state->use_dsb ||
7323	new_crtc_state->use_flipq ? size : 16);
7324	if (!new_crtc_state->dsb_commit) {
7325	new_crtc_state->use_flipq = false;
7326	new_crtc_state->use_dsb = false;
7327	intel_color_cleanup_commit(crtc_state: new_crtc_state);
7328	return;
7329	}
7330
7331	if (new_crtc_state->use_flipq || new_crtc_state->use_dsb) {
7332	/* Wa_18034343758 */
7333	if (new_crtc_state->use_flipq)
7334	intel_flipq_wait_dmc_halt(dsb: new_crtc_state->dsb_commit, crtc);
7335
7336	if (intel_crtc_needs_color_update(crtc_state: new_crtc_state))
7337	intel_color_commit_noarm(dsb: new_crtc_state->dsb_commit,
7338	crtc_state: new_crtc_state);
7339	intel_crtc_planes_update_noarm(dsb: new_crtc_state->dsb_commit,
7340	state, crtc);
7341
7342	/*
7343	* Ensure we have "Frame Change" event when PSR state is
7344	* SRDENT(PSR1) or DEEP_SLEEP(PSR2). Otherwise DSB vblank
7345	* evasion hangs as PIPEDSL is reading as 0.
7346	*/
7347	intel_psr_trigger_frame_change_event(dsb: new_crtc_state->dsb_commit,
7348	state, crtc);
7349
7350	intel_psr_wait_for_idle_dsb(dsb: new_crtc_state->dsb_commit,
7351	new_crtc_state);
7352
7353	if (new_crtc_state->use_dsb)
7354	intel_dsb_vblank_evade(state, dsb: new_crtc_state->dsb_commit);
7355
7356	if (intel_crtc_needs_color_update(crtc_state: new_crtc_state))
7357	intel_color_commit_arm(dsb: new_crtc_state->dsb_commit,
7358	crtc_state: new_crtc_state);
7359	bdw_set_pipe_misc(dsb: new_crtc_state->dsb_commit,
7360	crtc_state: new_crtc_state);
7361	intel_psr2_program_trans_man_trk_ctl(dsb: new_crtc_state->dsb_commit,
7362	crtc_state: new_crtc_state);
7363	intel_crtc_planes_update_arm(dsbx: new_crtc_state->dsb_commit,
7364	state, crtc);
7365
7366	if (DISPLAY_VER(display) >= 9)
7367	skl_detach_scalers(dsb: new_crtc_state->dsb_commit,
7368	crtc_state: new_crtc_state);
7369
7370	/* Wa_18034343758 */
7371	if (new_crtc_state->use_flipq)
7372	intel_flipq_unhalt_dmc(dsb: new_crtc_state->dsb_commit, crtc);
7373	}
7374
7375	if (intel_color_uses_chained_dsb(crtc_state: new_crtc_state))
7376	intel_dsb_chain(state, dsb: new_crtc_state->dsb_commit,
7377	chained_dsb: new_crtc_state->dsb_color, wait_for_vblank: true);
7378	else if (intel_color_uses_gosub_dsb(crtc_state: new_crtc_state))
7379	intel_dsb_gosub(dsb: new_crtc_state->dsb_commit,
7380	sub_dsb: new_crtc_state->dsb_color);
7381
7382	if (new_crtc_state->use_dsb && !intel_color_uses_chained_dsb(crtc_state: new_crtc_state)) {
7383	intel_dsb_wait_vblanks(dsb: new_crtc_state->dsb_commit, count: 1);
7384
7385	intel_vrr_send_push(dsb: new_crtc_state->dsb_commit, crtc_state: new_crtc_state);
7386	intel_dsb_wait_for_delayed_vblank(state, dsb: new_crtc_state->dsb_commit);
7387	intel_vrr_check_push_sent(dsb: new_crtc_state->dsb_commit,
7388	crtc_state: new_crtc_state);
7389	intel_dsb_interrupt(dsb: new_crtc_state->dsb_commit);
7390	}
7391
7392	intel_dsb_finish(dsb: new_crtc_state->dsb_commit);
7393	}
7394
7395	static void intel_atomic_commit_tail(struct intel_atomic_state *state)
7396	{
7397	struct intel_display *display = to_intel_display(state);
7398	struct drm_i915_private __maybe_unused *dev_priv = to_i915(dev: display->drm);
7399	struct intel_crtc_state *new_crtc_state, *old_crtc_state;
7400	struct intel_crtc *crtc;
7401	struct intel_power_domain_mask put_domains[I915_MAX_PIPES] = {};
7402	intel_wakeref_t wakeref = NULL;
7403	int i;
7404
7405	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
7406	intel_atomic_dsb_prepare(state, crtc);
7407
7408	intel_atomic_commit_fence_wait(intel_state: state);
7409
7410	intel_td_flush(display);
7411
7412	intel_atomic_prepare_plane_clear_colors(state);
7413
7414	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
7415	intel_fbc_prepare_dirty_rect(state, crtc);
7416
7417	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
7418	intel_atomic_dsb_finish(state, crtc);
7419
7420	drm_atomic_helper_wait_for_dependencies(state: &state->base);
7421	drm_dp_mst_atomic_wait_for_dependencies(state: &state->base);
7422	intel_atomic_global_state_wait_for_dependencies(state);
7423
7424	/*
7425	* During full modesets we write a lot of registers, wait
7426	* for PLLs, etc. Doing that while DC states are enabled
7427	* is not a good idea.
7428	*
7429	* During fastsets and other updates we also need to
7430	* disable DC states due to the following scenario:
7431	* 1. DC5 exit and PSR exit happen
7432	* 2. Some or all _noarm() registers are written
7433	* 3. Due to some long delay PSR is re-entered
7434	* 4. DC5 entry -> DMC saves the already written new
7435	* _noarm() registers and the old not yet written
7436	* _arm() registers
7437	* 5. DC5 exit -> DMC restores a mixture of old and
7438	* new register values and arms the update
7439	* 6. PSR exit -> hardware latches a mixture of old and
7440	* new register values -> corrupted frame, or worse
7441	* 7. New _arm() registers are finally written
7442	* 8. Hardware finally latches a complete set of new
7443	* register values, and subsequent frames will be OK again
7444	*
7445	* Also note that due to the pipe CSC hardware issues on
7446	* SKL/GLK DC states must remain off until the pipe CSC
7447	* state readout has happened. Otherwise we risk corrupting
7448	* the CSC latched register values with the readout (see
7449	* skl_read_csc() and skl_color_commit_noarm()).
7450	*/
7451	wakeref = intel_display_power_get(display, domain: POWER_DOMAIN_DC_OFF);
7452
7453	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
7454	new_crtc_state, i) {
7455	if (intel_crtc_needs_modeset(crtc_state: new_crtc_state) ||
7456	intel_crtc_needs_fastset(crtc_state: new_crtc_state))
7457	intel_modeset_get_crtc_power_domains(crtc_state: new_crtc_state, old_domains: &put_domains[crtc->pipe]);
7458	}
7459
7460	intel_commit_modeset_disables(state);
7461
7462	intel_dp_tunnel_atomic_alloc_bw(state);
7463
7464	/* FIXME: Eventually get rid of our crtc->config pointer */
7465	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
7466	crtc->config = new_crtc_state;
7467
7468	/*
7469	* In XE_LPD+ Pmdemand combines many parameters such as voltage index,
7470	* plls, cdclk frequency, QGV point selection parameter etc. Voltage
7471	* index, cdclk/ddiclk frequencies are supposed to be configured before
7472	* the cdclk config is set.
7473	*/
7474	intel_pmdemand_pre_plane_update(state);
7475
7476	if (state->modeset)
7477	drm_atomic_helper_update_legacy_modeset_state(dev: display->drm, old_state: &state->base);
7478
7479	intel_set_cdclk_pre_plane_update(state);
7480
7481	if (state->modeset)
7482	intel_modeset_verify_disabled(state);
7483
7484	intel_sagv_pre_plane_update(state);
7485
7486	/* Complete the events for pipes that have now been disabled */
7487	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7488	bool modeset = intel_crtc_needs_modeset(crtc_state: new_crtc_state);
7489
7490	/* Complete events for now disable pipes here. */
7491	if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) {
7492	spin_lock_irq(lock: &display->drm->event_lock);
7493	drm_crtc_send_vblank_event(crtc: &crtc->base,
7494	e: new_crtc_state->uapi.event);
7495	spin_unlock_irq(lock: &display->drm->event_lock);
7496
7497	new_crtc_state->uapi.event = NULL;
7498	}
7499	}
7500
7501	intel_encoders_update_prepare(state);
7502
7503	intel_dbuf_pre_plane_update(state);
7504
7505	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7506	if (new_crtc_state->do_async_flip)
7507	intel_crtc_enable_flip_done(state, crtc);
7508	}
7509
7510	/* Now enable the clocks, plane, pipe, and connectors that we set up. */
7511	display->funcs.display->commit_modeset_enables(state);
7512
7513	/* FIXME probably need to sequence this properly */
7514	intel_program_dpkgc_latency(state);
7515
7516	intel_wait_for_vblank_workers(state);
7517
7518	/* FIXME: We should call drm_atomic_helper_commit_hw_done() here
7519	* already, but still need the state for the delayed optimization. To
7520	* fix this:
7521	* - wrap the optimization/post_plane_update stuff into a per-crtc work.
7522	* - schedule that vblank worker _before_ calling hw_done
7523	* - at the start of commit_tail, cancel it _synchrously
7524	* - switch over to the vblank wait helper in the core after that since
7525	* we don't need out special handling any more.
7526	*/
7527	drm_atomic_helper_wait_for_flip_done(dev: display->drm, old_state: &state->base);
7528
7529	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7530	if (new_crtc_state->do_async_flip)
7531	intel_crtc_disable_flip_done(state, crtc);
7532
7533	intel_atomic_dsb_wait_commit(crtc_state: new_crtc_state);
7534
7535	if (!state->base.legacy_cursor_update && !new_crtc_state->use_dsb)
7536	intel_vrr_check_push_sent(NULL, crtc_state: new_crtc_state);
7537
7538	if (new_crtc_state->use_flipq)
7539	intel_flipq_disable(old_crtc_state: new_crtc_state);
7540	}
7541
7542	/*
7543	* Now that the vblank has passed, we can go ahead and program the
7544	* optimal watermarks on platforms that need two-step watermark
7545	* programming.
7546	*
7547	* TODO: Move this (and other cleanup) to an async worker eventually.
7548	*/
7549	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
7550	new_crtc_state, i) {
7551	/*
7552	* Gen2 reports pipe underruns whenever all planes are disabled.
7553	* So re-enable underrun reporting after some planes get enabled.
7554	*
7555	* We do this before .optimize_watermarks() so that we have a
7556	* chance of catching underruns with the intermediate watermarks
7557	* vs. the new plane configuration.
7558	*/
7559	if (DISPLAY_VER(display) == 2 && planes_enabling(old_crtc_state, new_crtc_state))
7560	intel_set_cpu_fifo_underrun_reporting(display, pipe: crtc->pipe, enable: true);
7561
7562	intel_optimize_watermarks(state, crtc);
7563	}
7564
7565	intel_dbuf_post_plane_update(state);
7566
7567	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
7568	intel_post_plane_update(state, crtc);
7569
7570	intel_modeset_put_crtc_power_domains(crtc, domains: &put_domains[crtc->pipe]);
7571
7572	intel_modeset_verify_crtc(state, crtc);
7573
7574	intel_post_plane_update_after_readout(state, crtc);
7575
7576	/*
7577	* DSB cleanup is done in cleanup_work aligning with framebuffer
7578	* cleanup. So copy and reset the dsb structure to sync with
7579	* commit_done and later do dsb cleanup in cleanup_work.
7580	*
7581	* FIXME get rid of this funny new->old swapping
7582	*/
7583	old_crtc_state->dsb_color = fetch_and_zero(&new_crtc_state->dsb_color);
7584	old_crtc_state->dsb_commit = fetch_and_zero(&new_crtc_state->dsb_commit);
7585	}
7586
7587	/* Underruns don't always raise interrupts, so check manually */
7588	intel_check_cpu_fifo_underruns(display);
7589	intel_check_pch_fifo_underruns(display);
7590
7591	if (state->modeset)
7592	intel_verify_planes(state);
7593
7594	intel_sagv_post_plane_update(state);
7595	intel_set_cdclk_post_plane_update(state);
7596	intel_pmdemand_post_plane_update(state);
7597
7598	drm_atomic_helper_commit_hw_done(state: &state->base);
7599	intel_atomic_global_state_commit_done(state);
7600
7601	if (state->modeset) {
7602	/* As one of the primary mmio accessors, KMS has a high
7603	* likelihood of triggering bugs in unclaimed access. After we
7604	* finish modesetting, see if an error has been flagged, and if
7605	* so enable debugging for the next modeset - and hope we catch
7606	* the culprit.
7607	*/
7608	intel_uncore_arm_unclaimed_mmio_detection(uncore: &dev_priv->uncore);
7609	}
7610	/*
7611	* Delay re-enabling DC states by 17 ms to avoid the off->on->off
7612	* toggling overhead at and above 60 FPS.
7613	*/
7614	intel_display_power_put_async_delay(display, domain: POWER_DOMAIN_DC_OFF, wakeref, delay_ms: 17);
7615	intel_display_rpm_put(display, wakeref: state->wakeref);
7616
7617	/*
7618	* Defer the cleanup of the old state to a separate worker to not
7619	* impede the current task (userspace for blocking modesets) that
7620	* are executed inline. For out-of-line asynchronous modesets/flips,
7621	* deferring to a new worker seems overkill, but we would place a
7622	* schedule point (cond_resched()) here anyway to keep latencies
7623	* down.
7624	*/
7625	INIT_WORK(&state->cleanup_work, intel_atomic_cleanup_work);
7626	queue_work(wq: display->wq.cleanup, work: &state->cleanup_work);
7627	}
7628
7629	static void intel_atomic_commit_work(struct work_struct *work)
7630	{
7631	struct intel_atomic_state *state =
7632	container_of(work, struct intel_atomic_state, base.commit_work);
7633
7634	intel_atomic_commit_tail(state);
7635	}
7636
7637	static void intel_atomic_track_fbs(struct intel_atomic_state *state)
7638	{
7639	struct intel_plane_state *old_plane_state, *new_plane_state;
7640	struct intel_plane *plane;
7641	int i;
7642
7643	for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
7644	new_plane_state, i)
7645	intel_frontbuffer_track(old: to_intel_frontbuffer(fb: old_plane_state->hw.fb),
7646	new: to_intel_frontbuffer(fb: new_plane_state->hw.fb),
7647	frontbuffer_bits: plane->frontbuffer_bit);
7648	}
7649
7650	static int intel_atomic_setup_commit(struct intel_atomic_state *state, bool nonblock)
7651	{
7652	int ret;
7653
7654	ret = drm_atomic_helper_setup_commit(state: &state->base, nonblock);
7655	if (ret)
7656	return ret;
7657
7658	ret = intel_atomic_global_state_setup_commit(state);
7659	if (ret)
7660	return ret;
7661
7662	return 0;
7663	}
7664
7665	static int intel_atomic_swap_state(struct intel_atomic_state *state)
7666	{
7667	int ret;
7668
7669	ret = drm_atomic_helper_swap_state(state: &state->base, stall: true);
7670	if (ret)
7671	return ret;
7672
7673	intel_atomic_swap_global_state(state);
7674
7675	intel_dpll_swap_state(state);
7676
7677	intel_atomic_track_fbs(state);
7678
7679	return 0;
7680	}
7681
7682	int intel_atomic_commit(struct drm_device *dev, struct drm_atomic_state *_state,
7683	bool nonblock)
7684	{
7685	struct intel_display *display = to_intel_display(dev);
7686	struct intel_atomic_state *state = to_intel_atomic_state(_state);
7687	int ret = 0;
7688
7689	state->wakeref = intel_display_rpm_get(display);
7690
7691	/*
7692	* The intel_legacy_cursor_update() fast path takes care
7693	* of avoiding the vblank waits for simple cursor
7694	* movement and flips. For cursor on/off and size changes,
7695	* we want to perform the vblank waits so that watermark
7696	* updates happen during the correct frames. Gen9+ have
7697	* double buffered watermarks and so shouldn't need this.
7698	*
7699	* Unset state->legacy_cursor_update before the call to
7700	* drm_atomic_helper_setup_commit() because otherwise
7701	* drm_atomic_helper_wait_for_flip_done() is a noop and
7702	* we get FIFO underruns because we didn't wait
7703	* for vblank.
7704	*
7705	* FIXME doing watermarks and fb cleanup from a vblank worker
7706	* (assuming we had any) would solve these problems.
7707	*/
7708	if (DISPLAY_VER(display) < 9 && state->base.legacy_cursor_update) {
7709	struct intel_crtc_state *new_crtc_state;
7710	struct intel_crtc *crtc;
7711	int i;
7712
7713	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
7714	if (new_crtc_state->wm.need_postvbl_update ||
7715	new_crtc_state->update_wm_post)
7716	state->base.legacy_cursor_update = false;
7717	}
7718
7719	ret = intel_atomic_prepare_commit(state);
7720	if (ret) {
7721	drm_dbg_atomic(display->drm,
7722	"Preparing state failed with %i\n", ret);
7723	intel_display_rpm_put(display, wakeref: state->wakeref);
7724	return ret;
7725	}
7726
7727	ret = intel_atomic_setup_commit(state, nonblock);
7728	if (!ret)
7729	ret = intel_atomic_swap_state(state);
7730
7731	if (ret) {
7732	drm_atomic_helper_unprepare_planes(dev, state: &state->base);
7733	intel_display_rpm_put(display, wakeref: state->wakeref);
7734	return ret;
7735	}
7736
7737	drm_atomic_state_get(state: &state->base);
7738	INIT_WORK(&state->base.commit_work, intel_atomic_commit_work);
7739
7740	if (nonblock && state->modeset) {
7741	queue_work(wq: display->wq.modeset, work: &state->base.commit_work);
7742	} else if (nonblock) {
7743	queue_work(wq: display->wq.flip, work: &state->base.commit_work);
7744	} else {
7745	if (state->modeset)
7746	flush_workqueue(display->wq.modeset);
7747	intel_atomic_commit_tail(state);
7748	}
7749
7750	return 0;
7751	}
7752
7753	static u32 intel_encoder_possible_clones(struct intel_encoder *encoder)
7754	{
7755	struct intel_display *display = to_intel_display(encoder);
7756	struct intel_encoder *source_encoder;
7757	u32 possible_clones = 0;
7758
7759	for_each_intel_encoder(display->drm, source_encoder) {
7760	if (encoders_cloneable(a: encoder, b: source_encoder))
7761	possible_clones |= drm_encoder_mask(encoder: &source_encoder->base);
7762	}
7763
7764	return possible_clones;
7765	}
7766
7767	static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder)
7768	{
7769	struct intel_display *display = to_intel_display(encoder);
7770	struct intel_crtc *crtc;
7771	u32 possible_crtcs = 0;
7772
7773	for_each_intel_crtc_in_pipe_mask(display->drm, crtc, encoder->pipe_mask)
7774	possible_crtcs |= drm_crtc_mask(crtc: &crtc->base);
7775
7776	return possible_crtcs;
7777	}
7778
7779	static bool ilk_has_edp_a(struct intel_display *display)
7780	{
7781	if (!display->platform.mobile)
7782	return false;
7783
7784	if ((intel_de_read(display, DP_A) & DP_DETECTED) == 0)
7785	return false;
7786
7787	if (display->platform.ironlake && (intel_de_read(display, FUSE_STRAP) & ILK_eDP_A_DISABLE))
7788	return false;
7789
7790	return true;
7791	}
7792
7793	static bool intel_ddi_crt_present(struct intel_display *display)
7794	{
7795	if (DISPLAY_VER(display) >= 9)
7796	return false;
7797
7798	if (display->platform.haswell_ult || display->platform.broadwell_ult)
7799	return false;
7800
7801	if (HAS_PCH_LPT_H(display) &&
7802	intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
7803	return false;
7804
7805	/* DDI E can't be used if DDI A requires 4 lanes */
7806	if (intel_de_read(display, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
7807	return false;
7808
7809	if (!display->vbt.int_crt_support)
7810	return false;
7811
7812	return true;
7813	}
7814
7815	bool assert_port_valid(struct intel_display *display, enum port port)
7816	{
7817	return !drm_WARN(display->drm, !(DISPLAY_RUNTIME_INFO(display)->port_mask & BIT(port)),
7818	"Platform does not support port %c\n", port_name(port));
7819	}
7820
7821	void intel_setup_outputs(struct intel_display *display)
7822	{
7823	struct intel_encoder *encoder;
7824	bool dpd_is_edp = false;
7825
7826	intel_pps_unlock_regs_wa(display);
7827
7828	if (!HAS_DISPLAY(display))
7829	return;
7830
7831	if (HAS_DDI(display)) {
7832	if (intel_ddi_crt_present(display))
7833	intel_crt_init(display);
7834
7835	intel_bios_for_each_encoder(display, func: intel_ddi_init);
7836
7837	if (display->platform.geminilake || display->platform.broxton)
7838	vlv_dsi_init(display);
7839	} else if (HAS_PCH_SPLIT(display)) {
7840	int found;
7841
7842	/*
7843	* intel_edp_init_connector() depends on this completing first,
7844	* to prevent the registration of both eDP and LVDS and the
7845	* incorrect sharing of the PPS.
7846	*/
7847	intel_lvds_init(display);
7848	intel_crt_init(display);
7849
7850	dpd_is_edp = intel_dp_is_port_edp(display, port: PORT_D);
7851
7852	if (ilk_has_edp_a(display))
7853	g4x_dp_init(display, DP_A, port: PORT_A);
7854
7855	if (intel_de_read(display, PCH_HDMIB) & SDVO_DETECTED) {
7856	/* PCH SDVOB multiplex with HDMIB */
7857	found = intel_sdvo_init(display, PCH_SDVOB, port: PORT_B);
7858	if (!found)
7859	g4x_hdmi_init(display, PCH_HDMIB, port: PORT_B);
7860	if (!found && (intel_de_read(display, PCH_DP_B) & DP_DETECTED))
7861	g4x_dp_init(display, PCH_DP_B, port: PORT_B);
7862	}
7863
7864	if (intel_de_read(display, PCH_HDMIC) & SDVO_DETECTED)
7865	g4x_hdmi_init(display, PCH_HDMIC, port: PORT_C);
7866
7867	if (!dpd_is_edp && intel_de_read(display, PCH_HDMID) & SDVO_DETECTED)
7868	g4x_hdmi_init(display, PCH_HDMID, port: PORT_D);
7869
7870	if (intel_de_read(display, PCH_DP_C) & DP_DETECTED)
7871	g4x_dp_init(display, PCH_DP_C, port: PORT_C);
7872
7873	if (intel_de_read(display, PCH_DP_D) & DP_DETECTED)
7874	g4x_dp_init(display, PCH_DP_D, port: PORT_D);
7875	} else if (display->platform.valleyview || display->platform.cherryview) {
7876	bool has_edp, has_port;
7877
7878	if (display->platform.valleyview && display->vbt.int_crt_support)
7879	intel_crt_init(display);
7880
7881	/*
7882	* The DP_DETECTED bit is the latched state of the DDC
7883	* SDA pin at boot. However since eDP doesn't require DDC
7884	* (no way to plug in a DP->HDMI dongle) the DDC pins for
7885	* eDP ports may have been muxed to an alternate function.
7886	* Thus we can't rely on the DP_DETECTED bit alone to detect
7887	* eDP ports. Consult the VBT as well as DP_DETECTED to
7888	* detect eDP ports.
7889	*
7890	* Sadly the straps seem to be missing sometimes even for HDMI
7891	* ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
7892	* and VBT for the presence of the port. Additionally we can't
7893	* trust the port type the VBT declares as we've seen at least
7894	* HDMI ports that the VBT claim are DP or eDP.
7895	*/
7896	has_edp = intel_dp_is_port_edp(display, port: PORT_B);
7897	has_port = intel_bios_is_port_present(display, port: PORT_B);
7898	if (intel_de_read(display, VLV_DP_B) & DP_DETECTED || has_port)
7899	has_edp &= g4x_dp_init(display, VLV_DP_B, port: PORT_B);
7900	if ((intel_de_read(display, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
7901	g4x_hdmi_init(display, VLV_HDMIB, port: PORT_B);
7902
7903	has_edp = intel_dp_is_port_edp(display, port: PORT_C);
7904	has_port = intel_bios_is_port_present(display, port: PORT_C);
7905	if (intel_de_read(display, VLV_DP_C) & DP_DETECTED || has_port)
7906	has_edp &= g4x_dp_init(display, VLV_DP_C, port: PORT_C);
7907	if ((intel_de_read(display, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
7908	g4x_hdmi_init(display, VLV_HDMIC, port: PORT_C);
7909
7910	if (display->platform.cherryview) {
7911	/*
7912	* eDP not supported on port D,
7913	* so no need to worry about it
7914	*/
7915	has_port = intel_bios_is_port_present(display, port: PORT_D);
7916	if (intel_de_read(display, CHV_DP_D) & DP_DETECTED || has_port)
7917	g4x_dp_init(display, CHV_DP_D, port: PORT_D);
7918	if (intel_de_read(display, CHV_HDMID) & SDVO_DETECTED || has_port)
7919	g4x_hdmi_init(display, CHV_HDMID, port: PORT_D);
7920	}
7921
7922	vlv_dsi_init(display);
7923	} else if (display->platform.pineview) {
7924	intel_lvds_init(display);
7925	intel_crt_init(display);
7926	} else if (IS_DISPLAY_VER(display, 3, 4)) {
7927	bool found = false;
7928
7929	if (display->platform.mobile)
7930	intel_lvds_init(display);
7931
7932	intel_crt_init(display);
7933
7934	if (intel_de_read(display, GEN3_SDVOB) & SDVO_DETECTED) {
7935	drm_dbg_kms(display->drm, "probing SDVOB\n");
7936	found = intel_sdvo_init(display, GEN3_SDVOB, port: PORT_B);
7937	if (!found && display->platform.g4x) {
7938	drm_dbg_kms(display->drm,
7939	"probing HDMI on SDVOB\n");
7940	g4x_hdmi_init(display, GEN4_HDMIB, port: PORT_B);
7941	}
7942
7943	if (!found && display->platform.g4x)
7944	g4x_dp_init(display, DP_B, port: PORT_B);
7945	}
7946
7947	/* Before G4X SDVOC doesn't have its own detect register */
7948
7949	if (intel_de_read(display, GEN3_SDVOB) & SDVO_DETECTED) {
7950	drm_dbg_kms(display->drm, "probing SDVOC\n");
7951	found = intel_sdvo_init(display, GEN3_SDVOC, port: PORT_C);
7952	}
7953
7954	if (!found && (intel_de_read(display, GEN3_SDVOC) & SDVO_DETECTED)) {
7955
7956	if (display->platform.g4x) {
7957	drm_dbg_kms(display->drm,
7958	"probing HDMI on SDVOC\n");
7959	g4x_hdmi_init(display, GEN4_HDMIC, port: PORT_C);
7960	}
7961	if (display->platform.g4x)
7962	g4x_dp_init(display, DP_C, port: PORT_C);
7963	}
7964
7965	if (display->platform.g4x && (intel_de_read(display, DP_D) & DP_DETECTED))
7966	g4x_dp_init(display, DP_D, port: PORT_D);
7967
7968	if (SUPPORTS_TV(display))
7969	intel_tv_init(display);
7970	} else if (DISPLAY_VER(display) == 2) {
7971	if (display->platform.i85x)
7972	intel_lvds_init(display);
7973
7974	intel_crt_init(display);
7975	intel_dvo_init(display);
7976	}
7977
7978	for_each_intel_encoder(display->drm, encoder) {
7979	encoder->base.possible_crtcs =
7980	intel_encoder_possible_crtcs(encoder);
7981	encoder->base.possible_clones =
7982	intel_encoder_possible_clones(encoder);
7983	}
7984
7985	intel_init_pch_refclk(display);
7986
7987	drm_helper_move_panel_connectors_to_head(display->drm);
7988	}
7989
7990	static int max_dotclock(struct intel_display *display)
7991	{
7992	int max_dotclock = display->cdclk.max_dotclk_freq;
7993
7994	if (HAS_ULTRAJOINER(display))
7995	max_dotclock *= 4;
7996	else if (HAS_UNCOMPRESSED_JOINER(display) || HAS_BIGJOINER(display))
7997	max_dotclock *= 2;
7998
7999	return max_dotclock;
8000	}
8001
8002	enum drm_mode_status intel_mode_valid(struct drm_device *dev,
8003	const struct drm_display_mode *mode)
8004	{
8005	struct intel_display *display = to_intel_display(dev);
8006	int hdisplay_max, htotal_max;
8007	int vdisplay_max, vtotal_max;
8008
8009	/*
8010	* Can't reject DBLSCAN here because Xorg ddxen can add piles
8011	* of DBLSCAN modes to the output's mode list when they detect
8012	* the scaling mode property on the connector. And they don't
8013	* ask the kernel to validate those modes in any way until
8014	* modeset time at which point the client gets a protocol error.
8015	* So in order to not upset those clients we silently ignore the
8016	* DBLSCAN flag on such connectors. For other connectors we will
8017	* reject modes with the DBLSCAN flag in encoder->compute_config().
8018	* And we always reject DBLSCAN modes in connector->mode_valid()
8019	* as we never want such modes on the connector's mode list.
8020	*/
8021
8022	if (mode->vscan > 1)
8023	return MODE_NO_VSCAN;
8024
8025	if (mode->flags & DRM_MODE_FLAG_HSKEW)
8026	return MODE_H_ILLEGAL;
8027
8028	if (mode->flags & (DRM_MODE_FLAG_CSYNC |
8029	DRM_MODE_FLAG_NCSYNC |
8030	DRM_MODE_FLAG_PCSYNC))
8031	return MODE_HSYNC;
8032
8033	if (mode->flags & (DRM_MODE_FLAG_BCAST |
8034	DRM_MODE_FLAG_PIXMUX |
8035	DRM_MODE_FLAG_CLKDIV2))
8036	return MODE_BAD;
8037
8038	/*
8039	* Reject clearly excessive dotclocks early to
8040	* avoid having to worry about huge integers later.
8041	*/
8042	if (mode->clock > max_dotclock(display))
8043	return MODE_CLOCK_HIGH;
8044
8045	/* Transcoder timing limits */
8046	if (DISPLAY_VER(display) >= 11) {
8047	hdisplay_max = 16384;
8048	vdisplay_max = 8192;
8049	htotal_max = 16384;
8050	vtotal_max = 8192;
8051	} else if (DISPLAY_VER(display) >= 9 ||
8052	display->platform.broadwell || display->platform.haswell) {
8053	hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */
8054	vdisplay_max = 4096;
8055	htotal_max = 8192;
8056	vtotal_max = 8192;
8057	} else if (DISPLAY_VER(display) >= 3) {
8058	hdisplay_max = 4096;
8059	vdisplay_max = 4096;
8060	htotal_max = 8192;
8061	vtotal_max = 8192;
8062	} else {
8063	hdisplay_max = 2048;
8064	vdisplay_max = 2048;
8065	htotal_max = 4096;
8066	vtotal_max = 4096;
8067	}
8068
8069	if (mode->hdisplay > hdisplay_max ||
8070	mode->hsync_start > htotal_max ||
8071	mode->hsync_end > htotal_max ||
8072	mode->htotal > htotal_max)
8073	return MODE_H_ILLEGAL;
8074
8075	if (mode->vdisplay > vdisplay_max ||
8076	mode->vsync_start > vtotal_max ||
8077	mode->vsync_end > vtotal_max ||
8078	mode->vtotal > vtotal_max)
8079	return MODE_V_ILLEGAL;
8080
8081	/*
8082	* WM_LINETIME only goes up to (almost) 64 usec, and also
8083	* knowing that the linetime is always bounded will ease the
8084	* mind during various calculations.
8085	*/
8086	if (DIV_ROUND_UP(mode->htotal * 1000, mode->clock) > 64)
8087	return MODE_H_ILLEGAL;
8088
8089	return MODE_OK;
8090	}
8091
8092	enum drm_mode_status intel_cpu_transcoder_mode_valid(struct intel_display *display,
8093	const struct drm_display_mode *mode)
8094	{
8095	/*
8096	* Additional transcoder timing limits,
8097	* excluding BXT/GLK DSI transcoders.
8098	*/
8099	if (DISPLAY_VER(display) >= 5) {
8100	if (mode->hdisplay < 64 ||
8101	mode->htotal - mode->hdisplay < 32)
8102	return MODE_H_ILLEGAL;
8103
8104	if (mode->vtotal - mode->vdisplay < 5)
8105	return MODE_V_ILLEGAL;
8106	} else {
8107	if (mode->htotal - mode->hdisplay < 32)
8108	return MODE_H_ILLEGAL;
8109
8110	if (mode->vtotal - mode->vdisplay < 3)
8111	return MODE_V_ILLEGAL;
8112	}
8113
8114	/*
8115	* Cantiga+ cannot handle modes with a hsync front porch of 0.
8116	* WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
8117	*/
8118	if ((DISPLAY_VER(display) >= 5 || display->platform.g4x) &&
8119	mode->hsync_start == mode->hdisplay)
8120	return MODE_H_ILLEGAL;
8121
8122	return MODE_OK;
8123	}
8124
8125	enum drm_mode_status
8126	intel_mode_valid_max_plane_size(struct intel_display *display,
8127	const struct drm_display_mode *mode,
8128	int num_joined_pipes)
8129	{
8130	int plane_width_max, plane_height_max;
8131
8132	/*
8133	* intel_mode_valid() should be
8134	* sufficient on older platforms.
8135	*/
8136	if (DISPLAY_VER(display) < 9)
8137	return MODE_OK;
8138
8139	/*
8140	* Most people will probably want a fullscreen
8141	* plane so let's not advertize modes that are
8142	* too big for that.
8143	*/
8144	if (DISPLAY_VER(display) >= 30) {
8145	plane_width_max = 6144 * num_joined_pipes;
8146	plane_height_max = 4800;
8147	} else if (DISPLAY_VER(display) >= 11) {
8148	plane_width_max = 5120 * num_joined_pipes;
8149	plane_height_max = 4320;
8150	} else {
8151	plane_width_max = 5120;
8152	plane_height_max = 4096;
8153	}
8154
8155	if (mode->hdisplay > plane_width_max)
8156	return MODE_H_ILLEGAL;
8157
8158	if (mode->vdisplay > plane_height_max)
8159	return MODE_V_ILLEGAL;
8160
8161	return MODE_OK;
8162	}
8163
8164	static const struct intel_display_funcs skl_display_funcs = {
8165	.get_pipe_config = hsw_get_pipe_config,
8166	.crtc_enable = hsw_crtc_enable,
8167	.crtc_disable = hsw_crtc_disable,
8168	.commit_modeset_enables = skl_commit_modeset_enables,
8169	.get_initial_plane_config = skl_get_initial_plane_config,
8170	.fixup_initial_plane_config = skl_fixup_initial_plane_config,
8171	};
8172
8173	static const struct intel_display_funcs ddi_display_funcs = {
8174	.get_pipe_config = hsw_get_pipe_config,
8175	.crtc_enable = hsw_crtc_enable,
8176	.crtc_disable = hsw_crtc_disable,
8177	.commit_modeset_enables = intel_commit_modeset_enables,
8178	.get_initial_plane_config = i9xx_get_initial_plane_config,
8179	.fixup_initial_plane_config = i9xx_fixup_initial_plane_config,
8180	};
8181
8182	static const struct intel_display_funcs pch_split_display_funcs = {
8183	.get_pipe_config = ilk_get_pipe_config,
8184	.crtc_enable = ilk_crtc_enable,
8185	.crtc_disable = ilk_crtc_disable,
8186	.commit_modeset_enables = intel_commit_modeset_enables,
8187	.get_initial_plane_config = i9xx_get_initial_plane_config,
8188	.fixup_initial_plane_config = i9xx_fixup_initial_plane_config,
8189	};
8190
8191	static const struct intel_display_funcs vlv_display_funcs = {
8192	.get_pipe_config = i9xx_get_pipe_config,
8193	.crtc_enable = valleyview_crtc_enable,
8194	.crtc_disable = i9xx_crtc_disable,
8195	.commit_modeset_enables = intel_commit_modeset_enables,
8196	.get_initial_plane_config = i9xx_get_initial_plane_config,
8197	.fixup_initial_plane_config = i9xx_fixup_initial_plane_config,
8198	};
8199
8200	static const struct intel_display_funcs i9xx_display_funcs = {
8201	.get_pipe_config = i9xx_get_pipe_config,
8202	.crtc_enable = i9xx_crtc_enable,
8203	.crtc_disable = i9xx_crtc_disable,
8204	.commit_modeset_enables = intel_commit_modeset_enables,
8205	.get_initial_plane_config = i9xx_get_initial_plane_config,
8206	.fixup_initial_plane_config = i9xx_fixup_initial_plane_config,
8207	};
8208
8209	/**
8210	* intel_init_display_hooks - initialize the display modesetting hooks
8211	* @display: display device private
8212	*/
8213	void intel_init_display_hooks(struct intel_display *display)
8214	{
8215	if (DISPLAY_VER(display) >= 9) {
8216	display->funcs.display = &skl_display_funcs;
8217	} else if (HAS_DDI(display)) {
8218	display->funcs.display = &ddi_display_funcs;
8219	} else if (HAS_PCH_SPLIT(display)) {
8220	display->funcs.display = &pch_split_display_funcs;
8221	} else if (display->platform.cherryview ||
8222	display->platform.valleyview) {
8223	display->funcs.display = &vlv_display_funcs;
8224	} else {
8225	display->funcs.display = &i9xx_display_funcs;
8226	}
8227	}
8228
8229	int intel_initial_commit(struct intel_display *display)
8230	{
8231	struct drm_atomic_state *state = NULL;
8232	struct drm_modeset_acquire_ctx ctx;
8233	struct intel_crtc *crtc;
8234	int ret = 0;
8235
8236	state = drm_atomic_state_alloc(dev: display->drm);
8237	if (!state)
8238	return -ENOMEM;
8239
8240	drm_modeset_acquire_init(ctx: &ctx, flags: 0);
8241
8242	state->acquire_ctx = &ctx;
8243	to_intel_atomic_state(state)->internal = true;
8244
8245	retry:
8246	for_each_intel_crtc(display->drm, crtc) {
8247	struct intel_crtc_state *crtc_state =
8248	intel_atomic_get_crtc_state(state, crtc);
8249
8250	if (IS_ERR(ptr: crtc_state)) {
8251	ret = PTR_ERR(ptr: crtc_state);
8252	goto out;
8253	}
8254
8255	if (!crtc_state->hw.active)
8256	crtc_state->inherited = false;
8257
8258	if (crtc_state->hw.active) {
8259	struct intel_encoder *encoder;
8260
8261	ret = drm_atomic_add_affected_planes(state, crtc: &crtc->base);
8262	if (ret)
8263	goto out;
8264
8265	/*
8266	* FIXME hack to force a LUT update to avoid the
8267	* plane update forcing the pipe gamma on without
8268	* having a proper LUT loaded. Remove once we
8269	* have readout for pipe gamma enable.
8270	*/
8271	crtc_state->uapi.color_mgmt_changed = true;
8272
8273	for_each_intel_encoder_mask(display->drm, encoder,
8274	crtc_state->uapi.encoder_mask) {
8275	if (encoder->initial_fastset_check &&
8276	!encoder->initial_fastset_check(encoder, crtc_state)) {
8277	ret = drm_atomic_add_affected_connectors(state,
8278	crtc: &crtc->base);
8279	if (ret)
8280	goto out;
8281	}
8282	}
8283	}
8284	}
8285
8286	ret = drm_atomic_commit(state);
8287
8288	out:
8289	if (ret == -EDEADLK) {
8290	drm_atomic_state_clear(state);
8291	drm_modeset_backoff(ctx: &ctx);
8292	goto retry;
8293	}
8294
8295	drm_atomic_state_put(state);
8296
8297	drm_modeset_drop_locks(ctx: &ctx);
8298	drm_modeset_acquire_fini(ctx: &ctx);
8299
8300	return ret;
8301	}
8302
8303	void i830_enable_pipe(struct intel_display *display, enum pipe pipe)
8304	{
8305	struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);
8306	enum transcoder cpu_transcoder = (enum transcoder)pipe;
8307	/* 640x480@60Hz, ~25175 kHz */
8308	struct dpll clock = {
8309	.m1 = 18,
8310	.m2 = 7,
8311	.p1 = 13,
8312	.p2 = 4,
8313	.n = 2,
8314	};
8315	u32 dpll, fp;
8316	int i;
8317
8318	drm_WARN_ON(display->drm,
8319	i9xx_calc_dpll_params(48000, &clock) != 25154);
8320
8321	drm_dbg_kms(display->drm,
8322	"enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
8323	pipe_name(pipe), clock.vco, clock.dot);
8324
8325	fp = i9xx_dpll_compute_fp(dpll: &clock);
8326	dpll = DPLL_DVO_2X_MODE |
8327	DPLL_VGA_MODE_DIS |
8328	((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
8329	PLL_P2_DIVIDE_BY_4 |
8330	PLL_REF_INPUT_DREFCLK |
8331	DPLL_VCO_ENABLE;
8332
8333	intel_de_write(display, TRANS_HTOTAL(display, cpu_transcoder),
8334	HACTIVE(640 - 1) | HTOTAL(800 - 1));
8335	intel_de_write(display, TRANS_HBLANK(display, cpu_transcoder),
8336	HBLANK_START(640 - 1) | HBLANK_END(800 - 1));
8337	intel_de_write(display, TRANS_HSYNC(display, cpu_transcoder),
8338	HSYNC_START(656 - 1) | HSYNC_END(752 - 1));
8339	intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder),
8340	VACTIVE(480 - 1) | VTOTAL(525 - 1));
8341	intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder),
8342	VBLANK_START(480 - 1) | VBLANK_END(525 - 1));
8343	intel_de_write(display, TRANS_VSYNC(display, cpu_transcoder),
8344	VSYNC_START(490 - 1) | VSYNC_END(492 - 1));
8345	intel_de_write(display, PIPESRC(display, pipe),
8346	PIPESRC_WIDTH(640 - 1) | PIPESRC_HEIGHT(480 - 1));
8347
8348	intel_de_write(display, FP0(pipe), val: fp);
8349	intel_de_write(display, FP1(pipe), val: fp);
8350
8351	/*
8352	* Apparently we need to have VGA mode enabled prior to changing
8353	* the P1/P2 dividers. Otherwise the DPLL will keep using the old
8354	* dividers, even though the register value does change.
8355	*/
8356	intel_de_write(display, DPLL(display, pipe),
8357	val: dpll & ~DPLL_VGA_MODE_DIS);
8358	intel_de_write(display, DPLL(display, pipe), val: dpll);
8359
8360	/* Wait for the clocks to stabilize. */
8361	intel_de_posting_read(display, DPLL(display, pipe));
8362	udelay(usec: 150);
8363
8364	/* The pixel multiplier can only be updated once the
8365	* DPLL is enabled and the clocks are stable.
8366	*
8367	* So write it again.
8368	*/
8369	intel_de_write(display, DPLL(display, pipe), val: dpll);
8370
8371	/* We do this three times for luck */
8372	for (i = 0; i < 3 ; i++) {
8373	intel_de_write(display, DPLL(display, pipe), val: dpll);
8374	intel_de_posting_read(display, DPLL(display, pipe));
8375	udelay(usec: 150); /* wait for warmup */
8376	}
8377
8378	intel_de_write(display, TRANSCONF(display, pipe), TRANSCONF_ENABLE);
8379	intel_de_posting_read(display, TRANSCONF(display, pipe));
8380
8381	intel_wait_for_pipe_scanline_moving(crtc);
8382	}
8383
8384	void i830_disable_pipe(struct intel_display *display, enum pipe pipe)
8385	{
8386	struct intel_crtc *crtc = intel_crtc_for_pipe(display, pipe);
8387
8388	drm_dbg_kms(display->drm, "disabling pipe %c due to force quirk\n",
8389	pipe_name(pipe));
8390
8391	drm_WARN_ON(display->drm,
8392	intel_de_read(display, DSPCNTR(display, PLANE_A)) & DISP_ENABLE);
8393	drm_WARN_ON(display->drm,
8394	intel_de_read(display, DSPCNTR(display, PLANE_B)) & DISP_ENABLE);
8395	drm_WARN_ON(display->drm,
8396	intel_de_read(display, DSPCNTR(display, PLANE_C)) & DISP_ENABLE);
8397	drm_WARN_ON(display->drm,
8398	intel_de_read(display, CURCNTR(display, PIPE_A)) & MCURSOR_MODE_MASK);
8399	drm_WARN_ON(display->drm,
8400	intel_de_read(display, CURCNTR(display, PIPE_B)) & MCURSOR_MODE_MASK);
8401
8402	intel_de_write(display, TRANSCONF(display, pipe), val: 0);
8403	intel_de_posting_read(display, TRANSCONF(display, pipe));
8404
8405	intel_wait_for_pipe_scanline_stopped(crtc);
8406
8407	intel_de_write(display, DPLL(display, pipe), DPLL_VGA_MODE_DIS);
8408	intel_de_posting_read(display, DPLL(display, pipe));
8409	}
8410
8411	bool intel_scanout_needs_vtd_wa(struct intel_display *display)
8412	{
8413	return IS_DISPLAY_VER(display, 6, 11) && intel_display_vtd_active(display);
8414	}
8415