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Refactor PSRAM clock frequency handling #19224

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Refactor PSRAM clock frequency handling #19224

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3dcad92
Refactor PSRAM clock frequency handling
phuzzyday May 15, 2026
6436206
Remove redundant comment in rp2_psram.c
phuzzyday May 15, 2026
a21b9b0
Fix formatting of comments in rp2_psram.c
phuzzyday May 15, 2026
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7 changes: 5 additions & 2 deletions ports/rp2/rp2_psram.c
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Original file line number Diff line number Diff line change
Expand Up @@ -119,6 +119,11 @@ size_t __no_inline_not_in_flash_func(psram_init)(uint cs_pin) {
return 0;
}

// Read clock speed before entering direct mode (flash access is
// unavailable while QMI direct mode is enabled)
const int max_psram_freq = 133000000;
const int clock_hz = clock_get_hz(clk_sys);

// Enable direct mode, PSRAM CS, clkdiv of 10.
qmi_hw->direct_csr = 10 << QMI_DIRECT_CSR_CLKDIV_LSB | \
QMI_DIRECT_CSR_EN_BITS | \
Expand All @@ -138,8 +143,6 @@ size_t __no_inline_not_in_flash_func(psram_init)(uint cs_pin) {
// Using an rxdelay equal to the divisor isn't enough when running the APS6404 close to 133MHz.
// So: don't allow running at divisor 1 above 100MHz (because delay of 2 would be too late),
// and add an extra 1 to the rxdelay if the divided clock is > 100MHz (i.e. sys clock > 200MHz).
const int max_psram_freq = 133000000;
const int clock_hz = clock_get_hz(clk_sys);
int divisor = (clock_hz + max_psram_freq - 1) / max_psram_freq;
if (divisor == 1 && clock_hz > 100000000) {
divisor = 2;
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