1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2021 Intel Corporation
4 */
5
6#include "xe_pci.h"
7
8#include <kunit/static_stub.h>
9#include <linux/device/driver.h>
10#include <linux/module.h>
11#include <linux/pci.h>
12#include <linux/pm_runtime.h>
13
14#include <drm/drm_color_mgmt.h>
15#include <drm/drm_drv.h>
16#include <drm/intel/pciids.h>
17
18#include "display/xe_display.h"
19#include "regs/xe_gt_regs.h"
20#include "regs/xe_regs.h"
21#include "xe_configfs.h"
22#include "xe_device.h"
23#include "xe_drv.h"
24#include "xe_gt.h"
25#include "xe_gt_sriov_vf.h"
26#include "xe_guc.h"
27#include "xe_macros.h"
28#include "xe_mmio.h"
29#include "xe_module.h"
30#include "xe_pci_sriov.h"
31#include "xe_pci_types.h"
32#include "xe_pm.h"
33#include "xe_printk.h"
34#include "xe_sriov.h"
35#include "xe_step.h"
36#include "xe_survivability_mode.h"
37#include "xe_tile.h"
38
39enum toggle_d3cold {
40 D3COLD_DISABLE,
41 D3COLD_ENABLE,
42};
43
44__diag_push();
45__diag_ignore_all("-Woverride-init", "Allow field overrides in table");
46
47#define PLATFORM(x) \
48 .platform = XE_##x, \
49 .platform_name = #x
50
51#define NOP(x) x
52
53static const struct xe_graphics_desc graphics_xelp = {
54 .hw_engine_mask = BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0),
55};
56
57#define XE_HP_FEATURES \
58 .has_range_tlb_inval = true
59
60static const struct xe_graphics_desc graphics_xehpg = {
61 .hw_engine_mask =
62 BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0) |
63 BIT(XE_HW_ENGINE_CCS0) | BIT(XE_HW_ENGINE_CCS1) |
64 BIT(XE_HW_ENGINE_CCS2) | BIT(XE_HW_ENGINE_CCS3),
65
66 XE_HP_FEATURES,
67};
68
69static const struct xe_graphics_desc graphics_xehpc = {
70 .hw_engine_mask =
71 BIT(XE_HW_ENGINE_BCS0) | BIT(XE_HW_ENGINE_BCS1) |
72 BIT(XE_HW_ENGINE_BCS2) | BIT(XE_HW_ENGINE_BCS3) |
73 BIT(XE_HW_ENGINE_BCS4) | BIT(XE_HW_ENGINE_BCS5) |
74 BIT(XE_HW_ENGINE_BCS6) | BIT(XE_HW_ENGINE_BCS7) |
75 BIT(XE_HW_ENGINE_BCS8) |
76 BIT(XE_HW_ENGINE_CCS0) | BIT(XE_HW_ENGINE_CCS1) |
77 BIT(XE_HW_ENGINE_CCS2) | BIT(XE_HW_ENGINE_CCS3),
78
79 XE_HP_FEATURES,
80
81 .has_asid = 1,
82 .has_atomic_enable_pte_bit = 1,
83 .has_usm = 1,
84};
85
86static const struct xe_graphics_desc graphics_xelpg = {
87 .hw_engine_mask =
88 BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0) |
89 BIT(XE_HW_ENGINE_CCS0),
90
91 XE_HP_FEATURES,
92};
93
94#define XE2_GFX_FEATURES \
95 .has_asid = 1, \
96 .has_atomic_enable_pte_bit = 1, \
97 .has_range_tlb_inval = 1, \
98 .has_usm = 1, \
99 .has_64bit_timestamp = 1, \
100 .hw_engine_mask = \
101 BIT(XE_HW_ENGINE_RCS0) | \
102 BIT(XE_HW_ENGINE_BCS8) | BIT(XE_HW_ENGINE_BCS0) | \
103 GENMASK(XE_HW_ENGINE_CCS3, XE_HW_ENGINE_CCS0)
104
105static const struct xe_graphics_desc graphics_xe2 = {
106 XE2_GFX_FEATURES,
107};
108
109static const struct xe_graphics_desc graphics_xe3p_xpc = {
110 XE2_GFX_FEATURES,
111 .hw_engine_mask =
112 GENMASK(XE_HW_ENGINE_BCS8, XE_HW_ENGINE_BCS1) |
113 GENMASK(XE_HW_ENGINE_CCS3, XE_HW_ENGINE_CCS0),
114};
115
116static const struct xe_media_desc media_xem = {
117 .hw_engine_mask =
118 GENMASK(XE_HW_ENGINE_VCS7, XE_HW_ENGINE_VCS0) |
119 GENMASK(XE_HW_ENGINE_VECS3, XE_HW_ENGINE_VECS0),
120};
121
122static const struct xe_media_desc media_xelpmp = {
123 .hw_engine_mask =
124 GENMASK(XE_HW_ENGINE_VCS7, XE_HW_ENGINE_VCS0) |
125 GENMASK(XE_HW_ENGINE_VECS3, XE_HW_ENGINE_VECS0) |
126 BIT(XE_HW_ENGINE_GSCCS0)
127};
128
129/* Pre-GMDID Graphics IPs */
130static const struct xe_ip graphics_ip_xelp = { 1200, "Xe_LP", &graphics_xelp };
131static const struct xe_ip graphics_ip_xelpp = { 1210, "Xe_LP+", &graphics_xelp };
132static const struct xe_ip graphics_ip_xehpg = { 1255, "Xe_HPG", &graphics_xehpg };
133static const struct xe_ip graphics_ip_xehpc = { 1260, "Xe_HPC", &graphics_xehpc };
134
135/* GMDID-based Graphics IPs */
136static const struct xe_ip graphics_ips[] = {
137 { 1270, "Xe_LPG", &graphics_xelpg },
138 { 1271, "Xe_LPG", &graphics_xelpg },
139 { 1274, "Xe_LPG+", &graphics_xelpg },
140 { 2001, "Xe2_HPG", &graphics_xe2 },
141 { 2002, "Xe2_HPG", &graphics_xe2 },
142 { 2004, "Xe2_LPG", &graphics_xe2 },
143 { 3000, "Xe3_LPG", &graphics_xe2 },
144 { 3001, "Xe3_LPG", &graphics_xe2 },
145 { 3003, "Xe3_LPG", &graphics_xe2 },
146 { 3004, "Xe3_LPG", &graphics_xe2 },
147 { 3005, "Xe3_LPG", &graphics_xe2 },
148 { 3511, "Xe3p_XPC", &graphics_xe3p_xpc },
149};
150
151/* Pre-GMDID Media IPs */
152static const struct xe_ip media_ip_xem = { 1200, "Xe_M", &media_xem };
153static const struct xe_ip media_ip_xehpm = { 1255, "Xe_HPM", &media_xem };
154
155/* GMDID-based Media IPs */
156static const struct xe_ip media_ips[] = {
157 { 1300, "Xe_LPM+", &media_xelpmp },
158 { 1301, "Xe2_HPM", &media_xelpmp },
159 { 2000, "Xe2_LPM", &media_xelpmp },
160 { 3000, "Xe3_LPM", &media_xelpmp },
161 { 3002, "Xe3_LPM", &media_xelpmp },
162 { 3500, "Xe3p_LPM", &media_xelpmp },
163 { 3503, "Xe3p_HPM", &media_xelpmp },
164};
165
166static const struct xe_device_desc tgl_desc = {
167 .pre_gmdid_graphics_ip = &graphics_ip_xelp,
168 .pre_gmdid_media_ip = &media_ip_xem,
169 PLATFORM(TIGERLAKE),
170 .dma_mask_size = 39,
171 .has_display = true,
172 .has_llc = true,
173 .has_sriov = true,
174 .max_gt_per_tile = 1,
175 .require_force_probe = true,
176 .va_bits = 48,
177 .vm_max_level = 3,
178};
179
180static const struct xe_device_desc rkl_desc = {
181 .pre_gmdid_graphics_ip = &graphics_ip_xelp,
182 .pre_gmdid_media_ip = &media_ip_xem,
183 PLATFORM(ROCKETLAKE),
184 .dma_mask_size = 39,
185 .has_display = true,
186 .has_llc = true,
187 .max_gt_per_tile = 1,
188 .require_force_probe = true,
189 .va_bits = 48,
190 .vm_max_level = 3,
191};
192
193static const u16 adls_rpls_ids[] = { INTEL_RPLS_IDS(NOP), 0 };
194
195static const struct xe_device_desc adl_s_desc = {
196 .pre_gmdid_graphics_ip = &graphics_ip_xelp,
197 .pre_gmdid_media_ip = &media_ip_xem,
198 PLATFORM(ALDERLAKE_S),
199 .dma_mask_size = 39,
200 .has_display = true,
201 .has_llc = true,
202 .has_sriov = true,
203 .max_gt_per_tile = 1,
204 .require_force_probe = true,
205 .subplatforms = (const struct xe_subplatform_desc[]) {
206 { XE_SUBPLATFORM_ALDERLAKE_S_RPLS, "RPLS", adls_rpls_ids },
207 {},
208 },
209 .va_bits = 48,
210 .vm_max_level = 3,
211};
212
213static const u16 adlp_rplu_ids[] = { INTEL_RPLU_IDS(NOP), 0 };
214
215static const struct xe_device_desc adl_p_desc = {
216 .pre_gmdid_graphics_ip = &graphics_ip_xelp,
217 .pre_gmdid_media_ip = &media_ip_xem,
218 PLATFORM(ALDERLAKE_P),
219 .dma_mask_size = 39,
220 .has_display = true,
221 .has_llc = true,
222 .has_sriov = true,
223 .max_gt_per_tile = 1,
224 .require_force_probe = true,
225 .subplatforms = (const struct xe_subplatform_desc[]) {
226 { XE_SUBPLATFORM_ALDERLAKE_P_RPLU, "RPLU", adlp_rplu_ids },
227 {},
228 },
229 .va_bits = 48,
230 .vm_max_level = 3,
231};
232
233static const struct xe_device_desc adl_n_desc = {
234 .pre_gmdid_graphics_ip = &graphics_ip_xelp,
235 .pre_gmdid_media_ip = &media_ip_xem,
236 PLATFORM(ALDERLAKE_N),
237 .dma_mask_size = 39,
238 .has_display = true,
239 .has_llc = true,
240 .has_sriov = true,
241 .max_gt_per_tile = 1,
242 .require_force_probe = true,
243 .va_bits = 48,
244 .vm_max_level = 3,
245};
246
247#define DGFX_FEATURES \
248 .is_dgfx = 1
249
250static const struct xe_device_desc dg1_desc = {
251 .pre_gmdid_graphics_ip = &graphics_ip_xelpp,
252 .pre_gmdid_media_ip = &media_ip_xem,
253 DGFX_FEATURES,
254 PLATFORM(DG1),
255 .dma_mask_size = 39,
256 .has_display = true,
257 .has_gsc_nvm = 1,
258 .has_heci_gscfi = 1,
259 .max_gt_per_tile = 1,
260 .require_force_probe = true,
261 .va_bits = 48,
262 .vm_max_level = 3,
263};
264
265static const u16 dg2_g10_ids[] = { INTEL_DG2_G10_IDS(NOP), INTEL_ATS_M150_IDS(NOP), 0 };
266static const u16 dg2_g11_ids[] = { INTEL_DG2_G11_IDS(NOP), INTEL_ATS_M75_IDS(NOP), 0 };
267static const u16 dg2_g12_ids[] = { INTEL_DG2_G12_IDS(NOP), 0 };
268
269#define DG2_FEATURES \
270 DGFX_FEATURES, \
271 PLATFORM(DG2), \
272 .has_flat_ccs = 1, \
273 .has_gsc_nvm = 1, \
274 .has_heci_gscfi = 1, \
275 .subplatforms = (const struct xe_subplatform_desc[]) { \
276 { XE_SUBPLATFORM_DG2_G10, "G10", dg2_g10_ids }, \
277 { XE_SUBPLATFORM_DG2_G11, "G11", dg2_g11_ids }, \
278 { XE_SUBPLATFORM_DG2_G12, "G12", dg2_g12_ids }, \
279 { } \
280 }, \
281 .va_bits = 48, \
282 .vm_max_level = 3, \
283 .vram_flags = XE_VRAM_FLAGS_NEED64K
284
285static const struct xe_device_desc ats_m_desc = {
286 .pre_gmdid_graphics_ip = &graphics_ip_xehpg,
287 .pre_gmdid_media_ip = &media_ip_xehpm,
288 .dma_mask_size = 46,
289 .max_gt_per_tile = 1,
290 .require_force_probe = true,
291
292 DG2_FEATURES,
293 .has_display = false,
294 .has_sriov = true,
295};
296
297static const struct xe_device_desc dg2_desc = {
298 .pre_gmdid_graphics_ip = &graphics_ip_xehpg,
299 .pre_gmdid_media_ip = &media_ip_xehpm,
300 .dma_mask_size = 46,
301 .max_gt_per_tile = 1,
302 .require_force_probe = true,
303
304 DG2_FEATURES,
305 .has_display = true,
306 .has_fan_control = true,
307 .has_mbx_power_limits = false,
308};
309
310static const __maybe_unused struct xe_device_desc pvc_desc = {
311 .pre_gmdid_graphics_ip = &graphics_ip_xehpc,
312 DGFX_FEATURES,
313 PLATFORM(PVC),
314 .dma_mask_size = 52,
315 .has_display = false,
316 .has_gsc_nvm = 1,
317 .has_heci_gscfi = 1,
318 .max_gt_per_tile = 1,
319 .max_remote_tiles = 1,
320 .require_force_probe = true,
321 .va_bits = 57,
322 .vm_max_level = 4,
323 .vram_flags = XE_VRAM_FLAGS_NEED64K,
324 .has_mbx_power_limits = false,
325};
326
327static const struct xe_device_desc mtl_desc = {
328 /* .graphics and .media determined via GMD_ID */
329 .require_force_probe = true,
330 PLATFORM(METEORLAKE),
331 .dma_mask_size = 46,
332 .has_display = true,
333 .has_pxp = true,
334 .max_gt_per_tile = 2,
335 .va_bits = 48,
336 .vm_max_level = 3,
337};
338
339static const struct xe_device_desc lnl_desc = {
340 PLATFORM(LUNARLAKE),
341 .dma_mask_size = 46,
342 .has_display = true,
343 .has_flat_ccs = 1,
344 .has_pxp = true,
345 .max_gt_per_tile = 2,
346 .needs_scratch = true,
347 .va_bits = 48,
348 .vm_max_level = 4,
349};
350
351static const u16 bmg_g21_ids[] = { INTEL_BMG_G21_IDS(NOP), 0 };
352
353static const struct xe_device_desc bmg_desc = {
354 DGFX_FEATURES,
355 PLATFORM(BATTLEMAGE),
356 .dma_mask_size = 46,
357 .has_display = true,
358 .has_fan_control = true,
359 .has_flat_ccs = 1,
360 .has_mbx_power_limits = true,
361 .has_gsc_nvm = 1,
362 .has_heci_cscfi = 1,
363 .has_late_bind = true,
364 .has_sriov = true,
365 .max_gt_per_tile = 2,
366 .needs_scratch = true,
367 .subplatforms = (const struct xe_subplatform_desc[]) {
368 { XE_SUBPLATFORM_BATTLEMAGE_G21, "G21", bmg_g21_ids },
369 { }
370 },
371 .va_bits = 48,
372 .vm_max_level = 4,
373};
374
375static const struct xe_device_desc ptl_desc = {
376 PLATFORM(PANTHERLAKE),
377 .dma_mask_size = 46,
378 .has_display = true,
379 .has_flat_ccs = 1,
380 .has_sriov = true,
381 .max_gt_per_tile = 2,
382 .needs_scratch = true,
383 .needs_shared_vf_gt_wq = true,
384 .va_bits = 48,
385 .vm_max_level = 4,
386};
387
388static const struct xe_device_desc nvls_desc = {
389 PLATFORM(NOVALAKE_S),
390 .dma_mask_size = 46,
391 .has_display = true,
392 .has_flat_ccs = 1,
393 .max_gt_per_tile = 2,
394 .require_force_probe = true,
395 .va_bits = 48,
396 .vm_max_level = 4,
397};
398
399static const struct xe_device_desc cri_desc = {
400 DGFX_FEATURES,
401 PLATFORM(CRESCENTISLAND),
402 .dma_mask_size = 52,
403 .has_display = false,
404 .has_flat_ccs = false,
405 .has_mbx_power_limits = true,
406 .has_sriov = true,
407 .max_gt_per_tile = 2,
408 .require_force_probe = true,
409 .va_bits = 57,
410 .vm_max_level = 4,
411};
412
413#undef PLATFORM
414__diag_pop();
415
416/*
417 * Make sure any device matches here are from most specific to most
418 * general. For example, since the Quanta match is based on the subsystem
419 * and subvendor IDs, we need it to come before the more general IVB
420 * PCI ID matches, otherwise we'll use the wrong info struct above.
421 */
422static const struct pci_device_id pciidlist[] = {
423 INTEL_TGL_IDS(INTEL_VGA_DEVICE, &tgl_desc),
424 INTEL_RKL_IDS(INTEL_VGA_DEVICE, &rkl_desc),
425 INTEL_ADLS_IDS(INTEL_VGA_DEVICE, &adl_s_desc),
426 INTEL_ADLP_IDS(INTEL_VGA_DEVICE, &adl_p_desc),
427 INTEL_ADLN_IDS(INTEL_VGA_DEVICE, &adl_n_desc),
428 INTEL_RPLU_IDS(INTEL_VGA_DEVICE, &adl_p_desc),
429 INTEL_RPLP_IDS(INTEL_VGA_DEVICE, &adl_p_desc),
430 INTEL_RPLS_IDS(INTEL_VGA_DEVICE, &adl_s_desc),
431 INTEL_DG1_IDS(INTEL_VGA_DEVICE, &dg1_desc),
432 INTEL_ATS_M_IDS(INTEL_VGA_DEVICE, &ats_m_desc),
433 INTEL_ARL_IDS(INTEL_VGA_DEVICE, &mtl_desc),
434 INTEL_DG2_IDS(INTEL_VGA_DEVICE, &dg2_desc),
435 INTEL_MTL_IDS(INTEL_VGA_DEVICE, &mtl_desc),
436 INTEL_LNL_IDS(INTEL_VGA_DEVICE, &lnl_desc),
437 INTEL_BMG_IDS(INTEL_VGA_DEVICE, &bmg_desc),
438 INTEL_PTL_IDS(INTEL_VGA_DEVICE, &ptl_desc),
439 INTEL_WCL_IDS(INTEL_VGA_DEVICE, &ptl_desc),
440 INTEL_NVLS_IDS(INTEL_VGA_DEVICE, &nvls_desc),
441 INTEL_CRI_IDS(INTEL_PCI_DEVICE, &cri_desc),
442 { }
443};
444MODULE_DEVICE_TABLE(pci, pciidlist);
445
446/* is device_id present in comma separated list of ids */
447static bool device_id_in_list(u16 device_id, const char *devices, bool negative)
448{
449 char *s, *p, *tok;
450 bool ret;
451
452 if (!devices || !*devices)
453 return false;
454
455 /* match everything */
456 if (negative && strcmp(devices, "!*") == 0)
457 return true;
458 if (!negative && strcmp(devices, "*") == 0)
459 return true;
460
461 s = kstrdup(s: devices, GFP_KERNEL);
462 if (!s)
463 return false;
464
465 for (p = s, ret = false; (tok = strsep(&p, ",")) != NULL; ) {
466 u16 val;
467
468 if (negative && tok[0] == '!')
469 tok++;
470 else if ((negative && tok[0] != '!') ||
471 (!negative && tok[0] == '!'))
472 continue;
473
474 if (kstrtou16(s: tok, base: 16, res: &val) == 0 && val == device_id) {
475 ret = true;
476 break;
477 }
478 }
479
480 kfree(objp: s);
481
482 return ret;
483}
484
485static bool id_forced(u16 device_id)
486{
487 return device_id_in_list(device_id, devices: xe_modparam.force_probe, negative: false);
488}
489
490static bool id_blocked(u16 device_id)
491{
492 return device_id_in_list(device_id, devices: xe_modparam.force_probe, negative: true);
493}
494
495static const struct xe_subplatform_desc *
496find_subplatform(const struct xe_device *xe, const struct xe_device_desc *desc)
497{
498 const struct xe_subplatform_desc *sp;
499 const u16 *id;
500
501 for (sp = desc->subplatforms; sp && sp->subplatform; sp++)
502 for (id = sp->pciidlist; *id; id++)
503 if (*id == xe->info.devid)
504 return sp;
505
506 return NULL;
507}
508
509enum xe_gmdid_type {
510 GMDID_GRAPHICS,
511 GMDID_MEDIA
512};
513
514static int read_gmdid(struct xe_device *xe, enum xe_gmdid_type type, u32 *ver, u32 *revid)
515{
516 struct xe_mmio *mmio = xe_root_tile_mmio(xe);
517 struct xe_reg gmdid_reg = GMD_ID;
518 u32 val;
519
520 KUNIT_STATIC_STUB_REDIRECT(read_gmdid, xe, type, ver, revid);
521
522 if (IS_SRIOV_VF(xe)) {
523 /*
524 * To get the value of the GMDID register, VFs must obtain it
525 * from the GuC using MMIO communication.
526 *
527 * Note that at this point the GTs are not initialized and only
528 * tile-level access to MMIO registers is possible. To use our
529 * existing GuC communication functions we must create a dummy
530 * GT structure and perform at least basic xe_gt and xe_guc
531 * initialization.
532 */
533 struct xe_gt *gt __free(kfree) = NULL;
534 int err;
535
536 gt = kzalloc(sizeof(*gt), GFP_KERNEL);
537 if (!gt)
538 return -ENOMEM;
539
540 gt->tile = &xe->tiles[0];
541 if (type == GMDID_MEDIA) {
542 gt->info.id = 1;
543 gt->info.type = XE_GT_TYPE_MEDIA;
544 } else {
545 gt->info.id = 0;
546 gt->info.type = XE_GT_TYPE_MAIN;
547 }
548
549 xe_gt_mmio_init(gt);
550 xe_guc_comm_init_early(guc: &gt->uc.guc);
551
552 err = xe_gt_sriov_vf_bootstrap(gt);
553 if (err)
554 return err;
555
556 val = xe_gt_sriov_vf_gmdid(gt);
557 } else {
558 /*
559 * GMD_ID is a GT register, but at this point in the driver
560 * init we haven't fully initialized the GT yet so we need to
561 * read the register with the tile's MMIO accessor. That means
562 * we need to apply the GSI offset manually since it won't get
563 * automatically added as it would if we were using a GT mmio
564 * accessor.
565 */
566 if (type == GMDID_MEDIA)
567 gmdid_reg.addr += MEDIA_GT_GSI_OFFSET;
568
569 val = xe_mmio_read32(mmio, reg: gmdid_reg);
570 }
571
572 *ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val) * 100 + REG_FIELD_GET(GMD_ID_RELEASE_MASK, val);
573 *revid = REG_FIELD_GET(GMD_ID_REVID, val);
574
575 return 0;
576}
577
578static const struct xe_ip *find_graphics_ip(unsigned int verx100)
579{
580 KUNIT_STATIC_STUB_REDIRECT(find_graphics_ip, verx100);
581
582 for (int i = 0; i < ARRAY_SIZE(graphics_ips); i++)
583 if (graphics_ips[i].verx100 == verx100)
584 return &graphics_ips[i];
585 return NULL;
586}
587
588static const struct xe_ip *find_media_ip(unsigned int verx100)
589{
590 KUNIT_STATIC_STUB_REDIRECT(find_media_ip, verx100);
591
592 for (int i = 0; i < ARRAY_SIZE(media_ips); i++)
593 if (media_ips[i].verx100 == verx100)
594 return &media_ips[i];
595 return NULL;
596}
597
598/*
599 * Read IP version from hardware and select graphics/media IP descriptors
600 * based on the result.
601 */
602static int handle_gmdid(struct xe_device *xe,
603 const struct xe_ip **graphics_ip,
604 const struct xe_ip **media_ip,
605 u32 *graphics_revid,
606 u32 *media_revid)
607{
608 u32 ver;
609 int ret;
610
611 *graphics_ip = NULL;
612 *media_ip = NULL;
613
614 ret = read_gmdid(xe, type: GMDID_GRAPHICS, ver: &ver, revid: graphics_revid);
615 if (ret)
616 return ret;
617
618 *graphics_ip = find_graphics_ip(verx100: ver);
619 if (!*graphics_ip) {
620 drm_err(&xe->drm, "Hardware reports unknown graphics version %u.%02u\n",
621 ver / 100, ver % 100);
622 }
623
624 ret = read_gmdid(xe, type: GMDID_MEDIA, ver: &ver, revid: media_revid);
625 if (ret)
626 return ret;
627
628 /* Media may legitimately be fused off / not present */
629 if (ver == 0)
630 return 0;
631
632 *media_ip = find_media_ip(verx100: ver);
633 if (!*media_ip) {
634 drm_err(&xe->drm, "Hardware reports unknown media version %u.%02u\n",
635 ver / 100, ver % 100);
636 }
637
638 return 0;
639}
640
641/*
642 * Initialize device info content that only depends on static driver_data
643 * passed to the driver at probe time from PCI ID table.
644 */
645static int xe_info_init_early(struct xe_device *xe,
646 const struct xe_device_desc *desc,
647 const struct xe_subplatform_desc *subplatform_desc)
648{
649 int err;
650
651 xe->info.platform_name = desc->platform_name;
652 xe->info.platform = desc->platform;
653 xe->info.subplatform = subplatform_desc ?
654 subplatform_desc->subplatform : XE_SUBPLATFORM_NONE;
655
656 xe->info.dma_mask_size = desc->dma_mask_size;
657 xe->info.va_bits = desc->va_bits;
658 xe->info.vm_max_level = desc->vm_max_level;
659 xe->info.vram_flags = desc->vram_flags;
660
661 xe->info.is_dgfx = desc->is_dgfx;
662 xe->info.has_fan_control = desc->has_fan_control;
663 /* runtime fusing may force flat_ccs to disabled later */
664 xe->info.has_flat_ccs = desc->has_flat_ccs;
665 xe->info.has_mbx_power_limits = desc->has_mbx_power_limits;
666 xe->info.has_gsc_nvm = desc->has_gsc_nvm;
667 xe->info.has_heci_gscfi = desc->has_heci_gscfi;
668 xe->info.has_heci_cscfi = desc->has_heci_cscfi;
669 xe->info.has_late_bind = desc->has_late_bind;
670 xe->info.has_llc = desc->has_llc;
671 xe->info.has_pxp = desc->has_pxp;
672 xe->info.has_sriov = xe_configfs_primary_gt_allowed(to_pci_dev(xe->drm.dev)) &&
673 desc->has_sriov;
674 xe->info.skip_guc_pc = desc->skip_guc_pc;
675 xe->info.skip_mtcfg = desc->skip_mtcfg;
676 xe->info.skip_pcode = desc->skip_pcode;
677 xe->info.needs_scratch = desc->needs_scratch;
678 xe->info.needs_shared_vf_gt_wq = desc->needs_shared_vf_gt_wq;
679
680 xe->info.probe_display = IS_ENABLED(CONFIG_DRM_XE_DISPLAY) &&
681 xe_modparam.probe_display &&
682 desc->has_display;
683
684 xe_assert(xe, desc->max_gt_per_tile > 0);
685 xe_assert(xe, desc->max_gt_per_tile <= XE_MAX_GT_PER_TILE);
686 xe->info.max_gt_per_tile = desc->max_gt_per_tile;
687 xe->info.tile_count = 1 + desc->max_remote_tiles;
688
689 err = xe_tile_init_early(tile: xe_device_get_root_tile(xe), xe, id: 0);
690 if (err)
691 return err;
692
693 return 0;
694}
695
696/*
697 * Possibly override number of tile based on configuration register.
698 */
699static void xe_info_probe_tile_count(struct xe_device *xe)
700{
701 struct xe_mmio *mmio;
702 u8 tile_count;
703 u32 mtcfg;
704
705 KUNIT_STATIC_STUB_REDIRECT(xe_info_probe_tile_count, xe);
706
707 /*
708 * Probe for tile count only for platforms that support multiple
709 * tiles.
710 */
711 if (xe->info.tile_count == 1)
712 return;
713
714 if (xe->info.skip_mtcfg)
715 return;
716
717 mmio = xe_root_tile_mmio(xe);
718
719 /*
720 * Although the per-tile mmio regs are not yet initialized, this
721 * is fine as it's going to the root tile's mmio, that's
722 * guaranteed to be initialized earlier in xe_mmio_probe_early()
723 */
724 mtcfg = xe_mmio_read32(mmio, XEHP_MTCFG_ADDR);
725 tile_count = REG_FIELD_GET(TILE_COUNT, mtcfg) + 1;
726
727 if (tile_count < xe->info.tile_count) {
728 drm_info(&xe->drm, "tile_count: %d, reduced_tile_count %d\n",
729 xe->info.tile_count, tile_count);
730 xe->info.tile_count = tile_count;
731 }
732}
733
734static struct xe_gt *alloc_primary_gt(struct xe_tile *tile,
735 const struct xe_graphics_desc *graphics_desc,
736 const struct xe_media_desc *media_desc)
737{
738 struct xe_device *xe = tile_to_xe(tile);
739 struct xe_gt *gt;
740
741 if (!xe_configfs_primary_gt_allowed(to_pci_dev(xe->drm.dev))) {
742 xe_info(xe, "Primary GT disabled via configfs\n");
743 return NULL;
744 }
745
746 gt = xe_gt_alloc(tile);
747 if (IS_ERR(ptr: gt))
748 return gt;
749
750 gt->info.type = XE_GT_TYPE_MAIN;
751 gt->info.id = tile->id * xe->info.max_gt_per_tile;
752 gt->info.has_indirect_ring_state = graphics_desc->has_indirect_ring_state;
753 gt->info.engine_mask = graphics_desc->hw_engine_mask;
754
755 /*
756 * Before media version 13, the media IP was part of the primary GT
757 * so we need to add the media engines to the primary GT's engine list.
758 */
759 if (MEDIA_VER(xe) < 13 && media_desc)
760 gt->info.engine_mask |= media_desc->hw_engine_mask;
761
762 return gt;
763}
764
765static struct xe_gt *alloc_media_gt(struct xe_tile *tile,
766 const struct xe_media_desc *media_desc)
767{
768 struct xe_device *xe = tile_to_xe(tile);
769 struct xe_gt *gt;
770
771 if (!xe_configfs_media_gt_allowed(to_pci_dev(xe->drm.dev))) {
772 xe_info(xe, "Media GT disabled via configfs\n");
773 return NULL;
774 }
775
776 if (MEDIA_VER(xe) < 13 || !media_desc)
777 return NULL;
778
779 gt = xe_gt_alloc(tile);
780 if (IS_ERR(ptr: gt))
781 return gt;
782
783 gt->info.type = XE_GT_TYPE_MEDIA;
784 gt->info.id = tile->id * xe->info.max_gt_per_tile + 1;
785 gt->info.has_indirect_ring_state = media_desc->has_indirect_ring_state;
786 gt->info.engine_mask = media_desc->hw_engine_mask;
787
788 return gt;
789}
790
791/*
792 * Initialize device info content that does require knowledge about
793 * graphics / media IP version.
794 * Make sure that GT / tile structures allocated by the driver match the data
795 * present in device info.
796 */
797static int xe_info_init(struct xe_device *xe,
798 const struct xe_device_desc *desc)
799{
800 u32 graphics_gmdid_revid = 0, media_gmdid_revid = 0;
801 const struct xe_ip *graphics_ip;
802 const struct xe_ip *media_ip;
803 const struct xe_graphics_desc *graphics_desc;
804 const struct xe_media_desc *media_desc;
805 struct xe_tile *tile;
806 struct xe_gt *gt;
807 int ret;
808 u8 id;
809
810 /*
811 * If this platform supports GMD_ID, we'll detect the proper IP
812 * descriptor to use from hardware registers.
813 * desc->pre_gmdid_graphics_ip will only ever be set at this point for
814 * platforms before GMD_ID. In that case the IP descriptions and
815 * versions are simply derived from that.
816 */
817 if (desc->pre_gmdid_graphics_ip) {
818 graphics_ip = desc->pre_gmdid_graphics_ip;
819 media_ip = desc->pre_gmdid_media_ip;
820 xe->info.step = xe_step_pre_gmdid_get(xe);
821 } else {
822 xe_assert(xe, !desc->pre_gmdid_media_ip);
823 ret = handle_gmdid(xe, graphics_ip: &graphics_ip, media_ip: &media_ip,
824 graphics_revid: &graphics_gmdid_revid, media_revid: &media_gmdid_revid);
825 if (ret)
826 return ret;
827
828 xe->info.step = xe_step_gmdid_get(xe,
829 graphics_gmdid_revid,
830 media_gmdid_revid);
831 }
832
833 /*
834 * If we couldn't detect the graphics IP, that's considered a fatal
835 * error and we should abort driver load. Failing to detect media
836 * IP is non-fatal; we'll just proceed without enabling media support.
837 */
838 if (!graphics_ip)
839 return -ENODEV;
840
841 xe->info.graphics_verx100 = graphics_ip->verx100;
842 xe->info.graphics_name = graphics_ip->name;
843 graphics_desc = graphics_ip->desc;
844
845 if (media_ip) {
846 xe->info.media_verx100 = media_ip->verx100;
847 xe->info.media_name = media_ip->name;
848 media_desc = media_ip->desc;
849 } else {
850 xe->info.media_name = "none";
851 media_desc = NULL;
852 }
853
854 xe->info.has_asid = graphics_desc->has_asid;
855 xe->info.has_atomic_enable_pte_bit = graphics_desc->has_atomic_enable_pte_bit;
856 if (xe->info.platform != XE_PVC)
857 xe->info.has_device_atomics_on_smem = 1;
858
859 xe->info.has_range_tlb_inval = graphics_desc->has_range_tlb_inval;
860 xe->info.has_usm = graphics_desc->has_usm;
861 xe->info.has_64bit_timestamp = graphics_desc->has_64bit_timestamp;
862 xe->info.has_mem_copy_instr = GRAPHICS_VER(xe) >= 20;
863
864 xe_info_probe_tile_count(xe);
865
866 for_each_remote_tile(tile, xe, id) {
867 int err;
868
869 err = xe_tile_init_early(tile, xe, id);
870 if (err)
871 return err;
872 }
873
874 /* Allocate any GT and VRAM structures necessary for the platform. */
875 for_each_tile(tile, xe, id) {
876 int err;
877
878 err = xe_tile_alloc_vram(tile);
879 if (err)
880 return err;
881
882 tile->primary_gt = alloc_primary_gt(tile, graphics_desc, media_desc);
883 if (IS_ERR(ptr: tile->primary_gt))
884 return PTR_ERR(ptr: tile->primary_gt);
885
886 /*
887 * It's not currently possible to probe a device with the
888 * primary GT disabled. With some work, this may be future in
889 * the possible for igpu platforms (although probably not for
890 * dgpu's since access to the primary GT's BCS engines is
891 * required for VRAM management).
892 */
893 if (!tile->primary_gt) {
894 drm_err(&xe->drm, "Cannot probe device with without a primary GT\n");
895 return -ENODEV;
896 }
897
898 tile->media_gt = alloc_media_gt(tile, media_desc);
899 if (IS_ERR(ptr: tile->media_gt))
900 return PTR_ERR(ptr: tile->media_gt);
901 }
902
903 /*
904 * Now that we have tiles and GTs defined, let's loop over valid GTs
905 * in order to define gt_count.
906 */
907 for_each_gt(gt, xe, id)
908 xe->info.gt_count++;
909
910 return 0;
911}
912
913static void xe_pci_remove(struct pci_dev *pdev)
914{
915 struct xe_device *xe = pdev_to_xe_device(pdev);
916
917 if (IS_SRIOV_PF(xe))
918 xe_pci_sriov_configure(pdev, num_vfs: 0);
919
920 if (xe_survivability_mode_is_boot_enabled(xe))
921 return;
922
923 xe_device_remove(xe);
924 xe_pm_fini(xe);
925}
926
927/*
928 * Probe the PCI device, initialize various parts of the driver.
929 *
930 * Fault injection is used to test the error paths of some initialization
931 * functions called either directly from xe_pci_probe() or indirectly for
932 * example through xe_device_probe(). Those functions use the kernel fault
933 * injection capabilities infrastructure, see
934 * Documentation/fault-injection/fault-injection.rst for details. The macro
935 * ALLOW_ERROR_INJECTION() is used to conditionally skip function execution
936 * at runtime and use a provided return value. The first requirement for
937 * error injectable functions is proper handling of the error code by the
938 * caller for recovery, which is always the case here. The second
939 * requirement is that no state is changed before the first error return.
940 * It is not strictly fulfilled for all initialization functions using the
941 * ALLOW_ERROR_INJECTION() macro but this is acceptable because for those
942 * error cases at probe time, the error code is simply propagated up by the
943 * caller. Therefore there is no consequence on those specific callers when
944 * function error injection skips the whole function.
945 */
946static int xe_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
947{
948 const struct xe_device_desc *desc = (const void *)ent->driver_data;
949 const struct xe_subplatform_desc *subplatform_desc;
950 struct xe_device *xe;
951 int err;
952
953 xe_configfs_check_device(pdev);
954
955 if (desc->require_force_probe && !id_forced(device_id: pdev->device)) {
956 dev_info(&pdev->dev,
957 "Your graphics device %04x is not officially supported\n"
958 "by xe driver in this kernel version. To force Xe probe,\n"
959 "use xe.force_probe='%04x' and i915.force_probe='!%04x'\n"
960 "module parameters or CONFIG_DRM_XE_FORCE_PROBE='%04x' and\n"
961 "CONFIG_DRM_I915_FORCE_PROBE='!%04x' configuration options.\n",
962 pdev->device, pdev->device, pdev->device,
963 pdev->device, pdev->device);
964 return -ENODEV;
965 }
966
967 if (id_blocked(device_id: pdev->device)) {
968 dev_info(&pdev->dev, "Probe blocked for device [%04x:%04x].\n",
969 pdev->vendor, pdev->device);
970 return -ENODEV;
971 }
972
973 if (xe_display_driver_probe_defer(pdev))
974 return -EPROBE_DEFER;
975
976 err = pcim_enable_device(pdev);
977 if (err)
978 return err;
979
980 xe = xe_device_create(pdev, ent);
981 if (IS_ERR(ptr: xe))
982 return PTR_ERR(ptr: xe);
983
984 pci_set_drvdata(pdev, data: &xe->drm);
985
986 xe_pm_assert_unbounded_bridge(xe);
987 subplatform_desc = find_subplatform(xe, desc);
988
989 pci_set_master(dev: pdev);
990
991 err = xe_info_init_early(xe, desc, subplatform_desc);
992 if (err)
993 return err;
994
995 xe_vram_resize_bar(xe);
996
997 err = xe_device_probe_early(xe);
998 /*
999 * In Boot Survivability mode, no drm card is exposed and driver
1000 * is loaded with bare minimum to allow for firmware to be
1001 * flashed through mei. Return success, if survivability mode
1002 * is enabled due to pcode failure or configfs being set
1003 */
1004 if (xe_survivability_mode_is_boot_enabled(xe))
1005 return 0;
1006
1007 if (err)
1008 return err;
1009
1010 err = xe_info_init(xe, desc);
1011 if (err)
1012 return err;
1013
1014 err = xe_display_probe(xe);
1015 if (err)
1016 return err;
1017
1018 drm_dbg(&xe->drm, "%s %s %04x:%04x dgfx:%d gfx:%s (%d.%02d) media:%s (%d.%02d) display:%s dma_m_s:%d tc:%d gscfi:%d cscfi:%d",
1019 desc->platform_name,
1020 subplatform_desc ? subplatform_desc->name : "",
1021 xe->info.devid, xe->info.revid,
1022 xe->info.is_dgfx,
1023 xe->info.graphics_name,
1024 xe->info.graphics_verx100 / 100,
1025 xe->info.graphics_verx100 % 100,
1026 xe->info.media_name,
1027 xe->info.media_verx100 / 100,
1028 xe->info.media_verx100 % 100,
1029 str_yes_no(xe->info.probe_display),
1030 xe->info.dma_mask_size, xe->info.tile_count,
1031 xe->info.has_heci_gscfi, xe->info.has_heci_cscfi);
1032
1033 drm_dbg(&xe->drm, "Stepping = (G:%s, M:%s, B:%s)\n",
1034 xe_step_name(xe->info.step.graphics),
1035 xe_step_name(xe->info.step.media),
1036 xe_step_name(xe->info.step.basedie));
1037
1038 drm_dbg(&xe->drm, "SR-IOV support: %s (mode: %s)\n",
1039 str_yes_no(xe_device_has_sriov(xe)),
1040 xe_sriov_mode_to_string(xe_device_sriov_mode(xe)));
1041
1042 err = xe_pm_init_early(xe);
1043 if (err)
1044 return err;
1045
1046 err = xe_device_probe(xe);
1047 if (err)
1048 return err;
1049
1050 err = xe_pm_init(xe);
1051 if (err)
1052 goto err_driver_cleanup;
1053
1054 drm_dbg(&xe->drm, "d3cold: capable=%s\n",
1055 str_yes_no(xe->d3cold.capable));
1056
1057 return 0;
1058
1059err_driver_cleanup:
1060 xe_pci_remove(pdev);
1061 return err;
1062}
1063
1064static void xe_pci_shutdown(struct pci_dev *pdev)
1065{
1066 xe_device_shutdown(xe: pdev_to_xe_device(pdev));
1067}
1068
1069#ifdef CONFIG_PM_SLEEP
1070static void d3cold_toggle(struct pci_dev *pdev, enum toggle_d3cold toggle)
1071{
1072 struct xe_device *xe = pdev_to_xe_device(pdev);
1073 struct pci_dev *root_pdev;
1074
1075 if (!xe->d3cold.capable)
1076 return;
1077
1078 root_pdev = pcie_find_root_port(dev: pdev);
1079 if (!root_pdev)
1080 return;
1081
1082 switch (toggle) {
1083 case D3COLD_DISABLE:
1084 pci_d3cold_disable(dev: root_pdev);
1085 break;
1086 case D3COLD_ENABLE:
1087 pci_d3cold_enable(dev: root_pdev);
1088 break;
1089 }
1090}
1091
1092static int xe_pci_suspend(struct device *dev)
1093{
1094 struct pci_dev *pdev = to_pci_dev(dev);
1095 struct xe_device *xe = pdev_to_xe_device(pdev);
1096 int err;
1097
1098 if (xe_survivability_mode_is_boot_enabled(xe))
1099 return -EBUSY;
1100
1101 err = xe_pm_suspend(xe);
1102 if (err)
1103 return err;
1104
1105 /*
1106 * Enabling D3Cold is needed for S2Idle/S0ix.
1107 * It is save to allow here since xe_pm_suspend has evicted
1108 * the local memory and the direct complete optimization is disabled.
1109 */
1110 d3cold_toggle(pdev, toggle: D3COLD_ENABLE);
1111
1112 pci_save_state(dev: pdev);
1113 pci_disable_device(dev: pdev);
1114 pci_set_power_state(dev: pdev, PCI_D3cold);
1115
1116 return 0;
1117}
1118
1119static int xe_pci_resume(struct device *dev)
1120{
1121 struct pci_dev *pdev = to_pci_dev(dev);
1122 int err;
1123
1124 /* Give back the D3Cold decision to the runtime P M*/
1125 d3cold_toggle(pdev, toggle: D3COLD_DISABLE);
1126
1127 err = pci_set_power_state(dev: pdev, PCI_D0);
1128 if (err)
1129 return err;
1130
1131 pci_restore_state(dev: pdev);
1132
1133 err = pci_enable_device(dev: pdev);
1134 if (err)
1135 return err;
1136
1137 pci_set_master(dev: pdev);
1138
1139 err = xe_pm_resume(xe: pdev_to_xe_device(pdev));
1140 if (err)
1141 return err;
1142
1143 return 0;
1144}
1145
1146static int xe_pci_runtime_suspend(struct device *dev)
1147{
1148 struct pci_dev *pdev = to_pci_dev(dev);
1149 struct xe_device *xe = pdev_to_xe_device(pdev);
1150 int err;
1151
1152 err = xe_pm_runtime_suspend(xe);
1153 if (err)
1154 return err;
1155
1156 pci_save_state(dev: pdev);
1157
1158 if (xe->d3cold.allowed) {
1159 d3cold_toggle(pdev, toggle: D3COLD_ENABLE);
1160 pci_disable_device(dev: pdev);
1161 pci_ignore_hotplug(dev: pdev);
1162 pci_set_power_state(dev: pdev, PCI_D3cold);
1163 } else {
1164 d3cold_toggle(pdev, toggle: D3COLD_DISABLE);
1165 pci_set_power_state(dev: pdev, PCI_D3hot);
1166 }
1167
1168 return 0;
1169}
1170
1171static int xe_pci_runtime_resume(struct device *dev)
1172{
1173 struct pci_dev *pdev = to_pci_dev(dev);
1174 struct xe_device *xe = pdev_to_xe_device(pdev);
1175 int err;
1176
1177 err = pci_set_power_state(dev: pdev, PCI_D0);
1178 if (err)
1179 return err;
1180
1181 pci_restore_state(dev: pdev);
1182
1183 if (xe->d3cold.allowed) {
1184 err = pci_enable_device(dev: pdev);
1185 if (err)
1186 return err;
1187
1188 pci_set_master(dev: pdev);
1189 }
1190
1191 return xe_pm_runtime_resume(xe);
1192}
1193
1194static int xe_pci_runtime_idle(struct device *dev)
1195{
1196 struct pci_dev *pdev = to_pci_dev(dev);
1197 struct xe_device *xe = pdev_to_xe_device(pdev);
1198
1199 xe_pm_d3cold_allowed_toggle(xe);
1200
1201 return 0;
1202}
1203
1204static const struct dev_pm_ops xe_pm_ops = {
1205 SET_SYSTEM_SLEEP_PM_OPS(xe_pci_suspend, xe_pci_resume)
1206 SET_RUNTIME_PM_OPS(xe_pci_runtime_suspend, xe_pci_runtime_resume, xe_pci_runtime_idle)
1207};
1208#endif
1209
1210static struct pci_driver xe_pci_driver = {
1211 .name = DRIVER_NAME,
1212 .id_table = pciidlist,
1213 .probe = xe_pci_probe,
1214 .remove = xe_pci_remove,
1215 .shutdown = xe_pci_shutdown,
1216 .sriov_configure = xe_pci_sriov_configure,
1217#ifdef CONFIG_PM_SLEEP
1218 .driver.pm = &xe_pm_ops,
1219#endif
1220};
1221
1222/**
1223 * xe_pci_to_pf_device() - Get PF &xe_device.
1224 * @pdev: the VF &pci_dev device
1225 *
1226 * Return: pointer to PF &xe_device, NULL otherwise.
1227 */
1228struct xe_device *xe_pci_to_pf_device(struct pci_dev *pdev)
1229{
1230 struct drm_device *drm;
1231
1232 drm = pci_iov_get_pf_drvdata(dev: pdev, pf_driver: &xe_pci_driver);
1233 if (IS_ERR(ptr: drm))
1234 return NULL;
1235
1236 return to_xe_device(dev: drm);
1237}
1238
1239int xe_register_pci_driver(void)
1240{
1241 return pci_register_driver(&xe_pci_driver);
1242}
1243
1244void xe_unregister_pci_driver(void)
1245{
1246 pci_unregister_driver(dev: &xe_pci_driver);
1247}
1248
1249#if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST)
1250#include "tests/xe_pci.c"
1251#endif
1252

source code of linux/drivers/gpu/drm/xe/xe_pci.c