1/* SPDX-License-Identifier: MIT */
2/*
3 * Copyright © 2024 Intel Corporation
4 */
5
6#ifndef _XE_HW_ENGINE_GROUP_TYPES_H_
7#define _XE_HW_ENGINE_GROUP_TYPES_H_
8
9#include "xe_force_wake_types.h"
10#include "xe_lrc_types.h"
11#include "xe_reg_sr_types.h"
12
13/**
14 * enum xe_hw_engine_group_execution_mode - possible execution modes of a hw
15 * engine group
16 *
17 * @EXEC_MODE_LR: execution in long-running mode
18 * @EXEC_MODE_DMA_FENCE: execution in dma fence mode
19 */
20enum xe_hw_engine_group_execution_mode {
21 EXEC_MODE_LR,
22 EXEC_MODE_DMA_FENCE,
23};
24
25/**
26 * struct xe_hw_engine_group - Hardware engine group
27 *
28 * hw engines belong to the same group if they share hardware resources in a way
29 * that prevents them from making progress when one is stuck on a page fault.
30 */
31struct xe_hw_engine_group {
32 /**
33 * @exec_queue_list: list of exec queues attached to this
34 * xe_hw_engine_group
35 */
36 struct list_head exec_queue_list;
37 /** @resume_work: worker to resume faulting LR exec queues */
38 struct work_struct resume_work;
39 /** @resume_wq: workqueue to resume faulting LR exec queues */
40 struct workqueue_struct *resume_wq;
41 /**
42 * @mode_sem: used to protect this group's hardware resources and ensure
43 * mutual exclusion between execution only in faulting LR mode and
44 * execution only in DMA_FENCE mode
45 */
46 struct rw_semaphore mode_sem;
47 /** @cur_mode: current execution mode of this hw engine group */
48 enum xe_hw_engine_group_execution_mode cur_mode;
49};
50
51#endif
52

source code of linux/drivers/gpu/drm/xe/xe_hw_engine_group_types.h