| 1 | /* SPDX-License-Identifier: MIT */ |
| 2 | /* |
| 3 | * Copyright © 2022 Intel Corporation |
| 4 | */ |
| 5 | |
| 6 | #ifndef _XE_FORCE_WAKE_TYPES_H_ |
| 7 | #define _XE_FORCE_WAKE_TYPES_H_ |
| 8 | |
| 9 | #include <linux/mutex.h> |
| 10 | #include <linux/types.h> |
| 11 | |
| 12 | #include "regs/xe_reg_defs.h" |
| 13 | |
| 14 | enum xe_force_wake_domain_id { |
| 15 | XE_FW_DOMAIN_ID_GT = 0, |
| 16 | XE_FW_DOMAIN_ID_RENDER, |
| 17 | XE_FW_DOMAIN_ID_MEDIA, |
| 18 | XE_FW_DOMAIN_ID_MEDIA_VDBOX0, |
| 19 | XE_FW_DOMAIN_ID_MEDIA_VDBOX1, |
| 20 | XE_FW_DOMAIN_ID_MEDIA_VDBOX2, |
| 21 | XE_FW_DOMAIN_ID_MEDIA_VDBOX3, |
| 22 | XE_FW_DOMAIN_ID_MEDIA_VDBOX4, |
| 23 | XE_FW_DOMAIN_ID_MEDIA_VDBOX5, |
| 24 | XE_FW_DOMAIN_ID_MEDIA_VDBOX6, |
| 25 | XE_FW_DOMAIN_ID_MEDIA_VDBOX7, |
| 26 | XE_FW_DOMAIN_ID_MEDIA_VEBOX0, |
| 27 | XE_FW_DOMAIN_ID_MEDIA_VEBOX1, |
| 28 | XE_FW_DOMAIN_ID_MEDIA_VEBOX2, |
| 29 | XE_FW_DOMAIN_ID_MEDIA_VEBOX3, |
| 30 | XE_FW_DOMAIN_ID_GSC, |
| 31 | XE_FW_DOMAIN_ID_COUNT |
| 32 | }; |
| 33 | |
| 34 | enum xe_force_wake_domains { |
| 35 | XE_FW_GT = BIT(XE_FW_DOMAIN_ID_GT), |
| 36 | XE_FW_RENDER = BIT(XE_FW_DOMAIN_ID_RENDER), |
| 37 | XE_FW_MEDIA = BIT(XE_FW_DOMAIN_ID_MEDIA), |
| 38 | XE_FW_MEDIA_VDBOX0 = BIT(XE_FW_DOMAIN_ID_MEDIA_VDBOX0), |
| 39 | XE_FW_MEDIA_VDBOX1 = BIT(XE_FW_DOMAIN_ID_MEDIA_VDBOX1), |
| 40 | XE_FW_MEDIA_VDBOX2 = BIT(XE_FW_DOMAIN_ID_MEDIA_VDBOX2), |
| 41 | XE_FW_MEDIA_VDBOX3 = BIT(XE_FW_DOMAIN_ID_MEDIA_VDBOX3), |
| 42 | XE_FW_MEDIA_VDBOX4 = BIT(XE_FW_DOMAIN_ID_MEDIA_VDBOX4), |
| 43 | XE_FW_MEDIA_VDBOX5 = BIT(XE_FW_DOMAIN_ID_MEDIA_VDBOX5), |
| 44 | XE_FW_MEDIA_VDBOX6 = BIT(XE_FW_DOMAIN_ID_MEDIA_VDBOX6), |
| 45 | XE_FW_MEDIA_VDBOX7 = BIT(XE_FW_DOMAIN_ID_MEDIA_VDBOX7), |
| 46 | XE_FW_MEDIA_VEBOX0 = BIT(XE_FW_DOMAIN_ID_MEDIA_VEBOX0), |
| 47 | XE_FW_MEDIA_VEBOX1 = BIT(XE_FW_DOMAIN_ID_MEDIA_VEBOX1), |
| 48 | XE_FW_MEDIA_VEBOX2 = BIT(XE_FW_DOMAIN_ID_MEDIA_VEBOX2), |
| 49 | XE_FW_MEDIA_VEBOX3 = BIT(XE_FW_DOMAIN_ID_MEDIA_VEBOX3), |
| 50 | XE_FW_GSC = BIT(XE_FW_DOMAIN_ID_GSC), |
| 51 | XE_FORCEWAKE_ALL = BIT(XE_FW_DOMAIN_ID_COUNT) |
| 52 | }; |
| 53 | |
| 54 | /** |
| 55 | * struct xe_force_wake_domain - Xe force wake power domain |
| 56 | * |
| 57 | * Represents an individual device-internal power domain. The driver must |
| 58 | * ensure the power domain is awake before accessing registers or other |
| 59 | * hardware functionality that is part of the power domain. Since different |
| 60 | * driver threads may access hardware units simultaneously, a reference count |
| 61 | * is used to ensure that the domain remains awake as long as any software |
| 62 | * is using the part of the hardware covered by the power domain. |
| 63 | * |
| 64 | * Hardware provides a register interface to allow the driver to request |
| 65 | * wake/sleep of power domains, although in most cases the actual action of |
| 66 | * powering the hardware up/down is handled by firmware (and may be subject to |
| 67 | * requirements and constraints outside of the driver's visibility) so the |
| 68 | * driver needs to wait for an acknowledgment that a wake request has been |
| 69 | * acted upon before accessing the parts of the hardware that reside within the |
| 70 | * power domain. |
| 71 | */ |
| 72 | struct xe_force_wake_domain { |
| 73 | /** @id: domain force wake id */ |
| 74 | enum xe_force_wake_domain_id id; |
| 75 | /** @reg_ctl: domain wake control register address */ |
| 76 | struct xe_reg reg_ctl; |
| 77 | /** @reg_ack: domain ack register address */ |
| 78 | struct xe_reg reg_ack; |
| 79 | /** @val: domain wake write value */ |
| 80 | u32 val; |
| 81 | /** @mask: domain mask */ |
| 82 | u32 mask; |
| 83 | /** @ref: domain reference */ |
| 84 | u32 ref; |
| 85 | }; |
| 86 | |
| 87 | /** |
| 88 | * struct xe_force_wake - Xe force wake collection |
| 89 | * |
| 90 | * Represents a collection of related power domains (struct |
| 91 | * xe_force_wake_domain) associated with a subunit of the device. |
| 92 | * |
| 93 | * Currently only used for GT power domains (where the term "forcewake" is used |
| 94 | * in the hardware documentation), although the interface could be extended to |
| 95 | * power wells in other parts of the hardware in the future. |
| 96 | */ |
| 97 | struct xe_force_wake { |
| 98 | /** @gt: back pointers to GT */ |
| 99 | struct xe_gt *gt; |
| 100 | /** @lock: protects everything force wake struct */ |
| 101 | spinlock_t lock; |
| 102 | /** @awake_domains: mask of all domains awake */ |
| 103 | unsigned int awake_domains; |
| 104 | /** @initialized_domains: mask of all initialized domains */ |
| 105 | unsigned int initialized_domains; |
| 106 | /** @domains: force wake domains */ |
| 107 | struct xe_force_wake_domain domains[XE_FW_DOMAIN_ID_COUNT]; |
| 108 | }; |
| 109 | |
| 110 | #endif |
| 111 | |