1/* SPDX-License-Identifier: MIT */
2/*
3 * Copyright © 2022-2023 Intel Corporation
4 */
5
6#ifndef _XE_GT_TYPES_H_
7#define _XE_GT_TYPES_H_
8
9#include "xe_device_types.h"
10#include "xe_force_wake_types.h"
11#include "xe_gt_idle_types.h"
12#include "xe_gt_sriov_pf_types.h"
13#include "xe_gt_sriov_vf_types.h"
14#include "xe_gt_stats_types.h"
15#include "xe_hw_engine_types.h"
16#include "xe_hw_fence_types.h"
17#include "xe_oa_types.h"
18#include "xe_reg_sr_types.h"
19#include "xe_sa_types.h"
20#include "xe_tlb_inval_types.h"
21#include "xe_uc_types.h"
22
23struct xe_exec_queue_ops;
24struct xe_migrate;
25struct xe_ring_ops;
26
27enum xe_gt_type {
28 XE_GT_TYPE_UNINITIALIZED,
29 XE_GT_TYPE_MAIN,
30 XE_GT_TYPE_MEDIA,
31};
32
33enum xe_gt_eu_type {
34 XE_GT_EU_TYPE_SIMD8,
35 XE_GT_EU_TYPE_SIMD16,
36};
37
38#define XE_MAX_DSS_FUSE_REGS 3
39#define XE_MAX_DSS_FUSE_BITS (32 * XE_MAX_DSS_FUSE_REGS)
40#define XE_MAX_EU_FUSE_REGS 1
41#define XE_MAX_EU_FUSE_BITS (32 * XE_MAX_EU_FUSE_REGS)
42#define XE_MAX_L3_BANK_MASK_BITS 64
43
44typedef unsigned long xe_dss_mask_t[BITS_TO_LONGS(XE_MAX_DSS_FUSE_BITS)];
45typedef unsigned long xe_eu_mask_t[BITS_TO_LONGS(XE_MAX_EU_FUSE_BITS)];
46typedef unsigned long xe_l3_bank_mask_t[BITS_TO_LONGS(XE_MAX_L3_BANK_MASK_BITS)];
47
48struct xe_mmio_range {
49 u32 start;
50 u32 end;
51};
52
53/*
54 * The hardware has multiple kinds of multicast register ranges that need
55 * special register steering (and future platforms are expected to add
56 * additional types).
57 *
58 * During driver startup, we initialize the steering control register to
59 * direct reads to a slice/subslice that are valid for the 'subslice' class
60 * of multicast registers. If another type of steering does not have any
61 * overlap in valid steering targets with 'subslice' style registers, we will
62 * need to explicitly re-steer reads of registers of the other type.
63 *
64 * Only the replication types that may need additional non-default steering
65 * are listed here.
66 */
67enum xe_steering_type {
68 L3BANK,
69 NODE,
70 MSLICE,
71 LNCF,
72 DSS,
73 OADDRM,
74 SQIDI_PSMI,
75
76 /*
77 * Although most GAM ranges must be steered to (0,0) and thus use the
78 * INSTANCE0 type farther down, some platforms have special rules
79 * for specific subtypes that require steering to (1,0) instead.
80 */
81 GAM1,
82
83 /*
84 * On some platforms there are multiple types of MCR registers that
85 * will always return a non-terminated value at instance (0, 0). We'll
86 * lump those all into a single category to keep things simple.
87 */
88 INSTANCE0,
89
90 /*
91 * Register ranges that don't need special steering for each register:
92 * it's sufficient to keep the HW-default for the selector, or only
93 * change it once, on GT initialization. This needs to be the last
94 * steering type.
95 */
96 IMPLICIT_STEERING,
97 NUM_STEERING_TYPES
98};
99
100#define gt_to_tile(gt__) \
101 _Generic(gt__, \
102 const struct xe_gt * : (const struct xe_tile *)((gt__)->tile), \
103 struct xe_gt * : (gt__)->tile)
104
105#define gt_to_xe(gt__) \
106 _Generic(gt__, \
107 const struct xe_gt * : (const struct xe_device *)(gt_to_tile(gt__)->xe), \
108 struct xe_gt * : gt_to_tile(gt__)->xe)
109
110/**
111 * struct xe_gt - A "Graphics Technology" unit of the GPU
112 *
113 * A GT ("Graphics Technology") is the subset of a GPU primarily responsible
114 * for implementing the graphics, compute, and/or media IP. It encapsulates
115 * the hardware engines, programmable execution units, and GuC. Each GT has
116 * its own handling of power management (RC6+forcewake) and multicast register
117 * steering.
118 *
119 * A GPU/tile may have a single GT that supplies all graphics, compute, and
120 * media functionality, or the graphics/compute and media may be split into
121 * separate GTs within a tile.
122 */
123struct xe_gt {
124 /** @tile: Backpointer to GT's tile */
125 struct xe_tile *tile;
126
127 /** @info: GT info */
128 struct {
129 /** @info.type: type of GT */
130 enum xe_gt_type type;
131 /** @info.reference_clock: clock frequency */
132 u32 reference_clock;
133 /** @info.timestamp_base: GT timestamp base */
134 u32 timestamp_base;
135 /**
136 * @info.engine_mask: mask of engines present on GT. Some of
137 * them may be reserved in runtime and not available for user.
138 * See @user_engines.mask
139 */
140 u64 engine_mask;
141 /** @info.gmdid: raw GMD_ID value from hardware */
142 u32 gmdid;
143 /** @info.id: Unique ID of this GT within the PCI Device */
144 u8 id;
145 /** @info.has_indirect_ring_state: GT has indirect ring state support */
146 u8 has_indirect_ring_state:1;
147 } info;
148
149#if IS_ENABLED(CONFIG_DEBUG_FS)
150 /** @stats: GT stats */
151 struct {
152 /** @stats.counters: counters for various GT stats */
153 atomic64_t counters[__XE_GT_STATS_NUM_IDS];
154 } stats;
155#endif
156
157 /**
158 * @mmio: mmio info for GT. All GTs within a tile share the same
159 * register space, but have their own copy of GSI registers at a
160 * specific offset.
161 */
162 struct xe_mmio mmio;
163
164 /**
165 * @pm: power management info for GT. The driver uses the GT's
166 * "force wake" interface to wake up specific parts of the GT hardware
167 * from C6 sleep states and ensure the hardware remains awake while it
168 * is being actively used.
169 */
170 struct {
171 /** @pm.fw: force wake for GT */
172 struct xe_force_wake fw;
173 } pm;
174
175 /** @sriov: virtualization data related to GT */
176 union {
177 /** @sriov.pf: PF data. Valid only if driver is running as PF */
178 struct xe_gt_sriov_pf pf;
179 /** @sriov.vf: VF data. Valid only if driver is running as VF */
180 struct xe_gt_sriov_vf vf;
181 } sriov;
182
183 /**
184 * @reg_sr: table with registers to be restored on GT init/resume/reset
185 */
186 struct xe_reg_sr reg_sr;
187
188 /** @reset: state for GT resets */
189 struct {
190 /**
191 * @reset.worker: work so GT resets can done async allowing to reset
192 * code to safely flush all code paths
193 */
194 struct work_struct worker;
195 } reset;
196
197 /** @tlb_inval: TLB invalidation state */
198 struct xe_tlb_inval tlb_inval;
199
200 /**
201 * @ccs_mode: Number of compute engines enabled.
202 * Allows fixed mapping of available compute slices to compute engines.
203 * By default only the first available compute engine is enabled and all
204 * available compute slices are allocated to it.
205 */
206 u32 ccs_mode;
207
208 /** @usm: unified shared memory state */
209 struct {
210 /**
211 * @usm.bb_pool: Pool from which batchbuffers, for USM operations
212 * (e.g. migrations, fixing page tables), are allocated.
213 * Dedicated pool needed so USM operations do not get blocked
214 * behind any user operations which may have resulted in a
215 * fault.
216 */
217 struct xe_sa_manager *bb_pool;
218 /**
219 * @usm.reserved_bcs_instance: reserved BCS instance used for USM
220 * operations (e.g. migrations, fixing page tables)
221 */
222 u16 reserved_bcs_instance;
223 } usm;
224
225 /** @ordered_wq: used to serialize GT resets and TDRs */
226 struct workqueue_struct *ordered_wq;
227
228 /** @uc: micro controllers on the GT */
229 struct xe_uc uc;
230
231 /** @gtidle: idle properties of GT */
232 struct xe_gt_idle gtidle;
233
234 /** @exec_queue_ops: submission backend exec queue operations */
235 const struct xe_exec_queue_ops *exec_queue_ops;
236
237 /**
238 * @ring_ops: ring operations for this hw engine (1 per engine class)
239 */
240 const struct xe_ring_ops *ring_ops[XE_ENGINE_CLASS_MAX];
241
242 /** @fence_irq: fence IRQs (1 per engine class) */
243 struct xe_hw_fence_irq fence_irq[XE_ENGINE_CLASS_MAX];
244
245 /** @default_lrc: default LRC state */
246 void *default_lrc[XE_ENGINE_CLASS_MAX];
247
248 /** @hw_engines: hardware engines on the GT */
249 struct xe_hw_engine hw_engines[XE_NUM_HW_ENGINES];
250
251 /** @eclass: per hardware engine class interface on the GT */
252 struct xe_hw_engine_class_intf eclass[XE_ENGINE_CLASS_MAX];
253
254 /** @sysfs: sysfs' kobj used by xe_gt_sysfs */
255 struct kobject *sysfs;
256
257 /** @freq: Main GT freq sysfs control */
258 struct kobject *freq;
259
260 /** @mocs: info */
261 struct {
262 /** @mocs.uc_index: UC index */
263 u8 uc_index;
264 /** @mocs.wb_index: WB index, only used on L3_CCS platforms */
265 u8 wb_index;
266 } mocs;
267
268 /** @fuse_topo: GT topology reported by fuse registers */
269 struct {
270 /** @fuse_topo.g_dss_mask: dual-subslices usable by geometry */
271 xe_dss_mask_t g_dss_mask;
272
273 /** @fuse_topo.c_dss_mask: dual-subslices usable by compute */
274 xe_dss_mask_t c_dss_mask;
275
276 /** @fuse_topo.eu_mask_per_dss: EU mask per DSS*/
277 xe_eu_mask_t eu_mask_per_dss;
278
279 /** @fuse_topo.l3_bank_mask: L3 bank mask */
280 xe_l3_bank_mask_t l3_bank_mask;
281
282 /**
283 * @fuse_topo.eu_type: type/width of EU stored in
284 * fuse_topo.eu_mask_per_dss
285 */
286 enum xe_gt_eu_type eu_type;
287 } fuse_topo;
288
289 /** @steering: register steering for individual HW units */
290 struct {
291 /** @steering.ranges: register ranges used for this steering type */
292 const struct xe_mmio_range *ranges;
293
294 /** @steering.group_target: target to steer accesses to */
295 u16 group_target;
296 /** @steering.instance_target: instance to steer accesses to */
297 u16 instance_target;
298 /** @steering.initialized: Whether this steering range is initialized */
299 bool initialized;
300 } steering[NUM_STEERING_TYPES];
301
302 /**
303 * @steering_dss_per_grp: number of DSS per steering group (gslice,
304 * cslice, etc.).
305 */
306 unsigned int steering_dss_per_grp;
307
308 /**
309 * @mcr_lock: protects the MCR_SELECTOR register for the duration
310 * of a steered operation
311 */
312 spinlock_t mcr_lock;
313
314 /**
315 * @global_invl_lock: protects the register for the duration
316 * of a global invalidation of l2 cache
317 */
318 spinlock_t global_invl_lock;
319
320 /** @wa_active: keep track of active workarounds */
321 struct {
322 /** @wa_active.gt: bitmap with active GT workarounds */
323 unsigned long *gt;
324 /** @wa_active.engine: bitmap with active engine workarounds */
325 unsigned long *engine;
326 /** @wa_active.lrc: bitmap with active LRC workarounds */
327 unsigned long *lrc;
328 /** @wa_active.oob: bitmap with active OOB workarounds */
329 unsigned long *oob;
330 /**
331 * @wa_active.oob_initialized: mark oob as initialized to help
332 * detecting misuse of XE_GT_WA() - it can only be called on
333 * initialization after OOB WAs have been processed
334 */
335 bool oob_initialized;
336 } wa_active;
337
338 /** @tuning_active: keep track of active tunings */
339 struct {
340 /** @tuning_active.gt: bitmap with active GT tunings */
341 unsigned long *gt;
342 /** @tuning_active.engine: bitmap with active engine tunings */
343 unsigned long *engine;
344 /** @tuning_active.lrc: bitmap with active LRC tunings */
345 unsigned long *lrc;
346 } tuning_active;
347
348 /** @user_engines: engines present in GT and available to userspace */
349 struct {
350 /**
351 * @user_engines.mask: like @info->engine_mask, but take in
352 * consideration only engines available to userspace
353 */
354 u64 mask;
355
356 /**
357 * @user_engines.instances_per_class: aggregate per class the
358 * number of engines available to userspace
359 */
360 u8 instances_per_class[XE_ENGINE_CLASS_MAX];
361 } user_engines;
362
363 /** @oa: oa observation subsystem per gt info */
364 struct xe_oa_gt oa;
365
366 /** @eu_stall: EU stall counters subsystem per gt info */
367 struct xe_eu_stall_gt *eu_stall;
368};
369
370#endif
371

source code of linux/drivers/gpu/drm/xe/xe_gt_types.h