| 1 | /* SPDX-License-Identifier: MIT */ |
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| 2 | /* |
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| 3 | * Copyright © 2024 Intel Corporation |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef _XE_GTT_DEFS_H_ |
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| 7 | #define _XE_GTT_DEFS_H_ |
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| 8 | |
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| 9 | #define XELPG_GGTT_PTE_PAT0 BIT_ULL(52) |
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| 10 | #define XELPG_GGTT_PTE_PAT1 BIT_ULL(53) |
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| 11 | |
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| 12 | #define GGTT_PTE_VFID GENMASK_ULL(11, 2) |
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| 13 | |
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| 14 | #define GUC_GGTT_TOP 0xFEE00000 |
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| 15 | |
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| 16 | #define XELPG_PPGTT_PTE_PAT3 BIT_ULL(62) |
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| 17 | #define XE2_PPGTT_PTE_PAT4 BIT_ULL(61) |
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| 18 | #define XE_PPGTT_PDE_PDPE_PAT2 BIT_ULL(12) |
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| 19 | #define XE_PPGTT_PTE_PAT2 BIT_ULL(7) |
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| 20 | #define XE_PPGTT_PTE_PAT1 BIT_ULL(4) |
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| 21 | #define XE_PPGTT_PTE_PAT0 BIT_ULL(3) |
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| 22 | |
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| 23 | #define XE_PDE_PS_2M BIT_ULL(7) |
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| 24 | #define XE_PDPE_PS_1G BIT_ULL(7) |
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| 25 | #define XE_PDE_IPS_64K BIT_ULL(11) |
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| 26 | |
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| 27 | #define XE_GGTT_PTE_DM BIT_ULL(1) |
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| 28 | #define XE_USM_PPGTT_PTE_AE BIT_ULL(10) |
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| 29 | #define XE_PPGTT_PTE_DM BIT_ULL(11) |
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| 30 | #define XE_PDE_64K BIT_ULL(6) |
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| 31 | #define XE_PTE_PS64 BIT_ULL(8) |
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| 32 | #define XE_PTE_NULL BIT_ULL(9) |
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| 33 | |
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| 34 | #define XE_PAGE_PRESENT BIT_ULL(0) |
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| 35 | #define XE_PAGE_RW BIT_ULL(1) |
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| 36 | |
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| 37 | #endif |
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| 38 | |
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