1// SPDX-License-Identifier: GPL-2.0
2/*
3 * MediaTek HDMI v2 IP driver
4 *
5 * Copyright (c) 2022 MediaTek Inc.
6 * Copyright (c) 2022 BayLibre, SAS
7 * Copyright (c) 2024 Collabora Ltd.
8 * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
9 */
10
11#include <linux/bitfield.h>
12#include <linux/clk.h>
13#include <linux/debugfs.h>
14#include <linux/delay.h>
15#include <linux/device.h>
16#include <linux/err.h>
17#include <linux/interrupt.h>
18#include <linux/irq.h>
19#include <linux/kernel.h>
20#include <linux/mutex.h>
21#include <linux/of.h>
22#include <linux/of_platform.h>
23#include <linux/pm_runtime.h>
24#include <linux/regmap.h>
25#include <linux/suspend.h>
26#include <linux/units.h>
27#include <linux/phy/phy.h>
28
29#include <drm/display/drm_hdmi_helper.h>
30#include <drm/display/drm_hdmi_state_helper.h>
31#include <drm/display/drm_scdc_helper.h>
32#include <drm/drm_drv.h>
33#include <drm/drm_edid.h>
34#include <drm/drm_print.h>
35#include <drm/drm_probe_helper.h>
36
37#include "mtk_hdmi_common.h"
38#include "mtk_hdmi_regs_v2.h"
39
40#define MTK_HDMI_V2_CLOCK_MIN 27000
41#define MTK_HDMI_V2_CLOCK_MAX 594000
42
43#define HPD_PORD_HWIRQS (HTPLG_R_INT | HTPLG_F_INT | PORD_F_INT | PORD_R_INT)
44
45enum mtk_hdmi_v2_clk_id {
46 MTK_HDMI_V2_CLK_HDCP_SEL,
47 MTK_HDMI_V2_CLK_HDCP_24M_SEL,
48 MTK_HDMI_V2_CLK_VPP_SPLIT_HDMI,
49 MTK_HDMI_V2_CLK_HDMI_APB_SEL,
50 MTK_HDMI_V2_CLK_COUNT,
51};
52
53const char *const mtk_hdmi_v2_clk_names[MTK_HDMI_V2_CLK_COUNT] = {
54 [MTK_HDMI_V2_CLK_HDMI_APB_SEL] = "bus",
55 [MTK_HDMI_V2_CLK_HDCP_SEL] = "hdcp",
56 [MTK_HDMI_V2_CLK_HDCP_24M_SEL] = "hdcp24m",
57 [MTK_HDMI_V2_CLK_VPP_SPLIT_HDMI] = "hdmi-split",
58};
59
60static inline void mtk_hdmi_v2_hwirq_disable(struct mtk_hdmi *hdmi)
61{
62 regmap_write(map: hdmi->regs, TOP_INT_ENABLE00, val: 0);
63 regmap_write(map: hdmi->regs, TOP_INT_ENABLE01, val: 0);
64}
65
66static inline void mtk_hdmi_v2_enable_hpd_pord_irq(struct mtk_hdmi *hdmi, bool enable)
67{
68 if (enable)
69 regmap_set_bits(map: hdmi->regs, TOP_INT_ENABLE00, HPD_PORD_HWIRQS);
70 else
71 regmap_clear_bits(map: hdmi->regs, TOP_INT_ENABLE00, HPD_PORD_HWIRQS);
72}
73
74static inline void mtk_hdmi_v2_set_sw_hpd(struct mtk_hdmi *hdmi, bool enable)
75{
76 if (enable) {
77 regmap_set_bits(map: hdmi->regs, reg: hdmi->conf->reg_hdmi_tx_cfg, HDMITX_SW_HPD);
78 regmap_set_bits(map: hdmi->regs, HDCP2X_CTRL_0, HDCP2X_HPD_OVR);
79 regmap_set_bits(map: hdmi->regs, HDCP2X_CTRL_0, HDCP2X_HPD_SW);
80 } else {
81 regmap_clear_bits(map: hdmi->regs, HDCP2X_CTRL_0, HDCP2X_HPD_OVR);
82 regmap_clear_bits(map: hdmi->regs, HDCP2X_CTRL_0, HDCP2X_HPD_SW);
83 regmap_clear_bits(map: hdmi->regs, reg: hdmi->conf->reg_hdmi_tx_cfg, HDMITX_SW_HPD);
84 }
85}
86
87static inline void mtk_hdmi_v2_enable_scrambling(struct mtk_hdmi *hdmi, bool enable)
88{
89 struct drm_scdc *scdc = &hdmi->curr_conn->display_info.hdmi.scdc;
90
91 if (enable)
92 regmap_set_bits(map: hdmi->regs, TOP_CFG00, SCR_ON | HDMI2_ON);
93 else
94 regmap_clear_bits(map: hdmi->regs, TOP_CFG00, SCR_ON | HDMI2_ON);
95
96 if (scdc->supported) {
97 if (scdc->scrambling.supported)
98 drm_scdc_set_scrambling(connector: hdmi->curr_conn, enable);
99 drm_scdc_set_high_tmds_clock_ratio(connector: hdmi->curr_conn, set: enable);
100 }
101}
102
103static void mtk_hdmi_v2_hw_vid_mute(struct mtk_hdmi *hdmi, bool enable)
104{
105 /* If enabled, sends a black image */
106 if (enable)
107 regmap_set_bits(map: hdmi->regs, TOP_VMUTE_CFG1, REG_VMUTE_EN);
108 else
109 regmap_clear_bits(map: hdmi->regs, TOP_VMUTE_CFG1, REG_VMUTE_EN);
110}
111
112static void mtk_hdmi_v2_hw_aud_mute(struct mtk_hdmi *hdmi, bool enable)
113{
114 u32 aip, val;
115
116 if (!enable) {
117 regmap_clear_bits(map: hdmi->regs, AIP_TXCTRL, AUD_MUTE_FIFO_EN);
118 return;
119 }
120
121 regmap_read(map: hdmi->regs, AIP_CTRL, val: &aip);
122
123 val = AUD_MUTE_FIFO_EN;
124 if (aip & DSD_EN)
125 val |= DSD_MUTE_EN;
126
127 regmap_update_bits(map: hdmi->regs, AIP_TXCTRL, mask: val, val);
128}
129
130static void mtk_hdmi_v2_hw_reset(struct mtk_hdmi *hdmi)
131{
132 regmap_clear_bits(map: hdmi->regs, reg: hdmi->conf->reg_hdmi_tx_cfg, HDMITX_SW_RSTB);
133 udelay(usec: 5);
134 regmap_set_bits(map: hdmi->regs, reg: hdmi->conf->reg_hdmi_tx_cfg, HDMITX_SW_RSTB);
135}
136
137static inline u32 mtk_hdmi_v2_format_hw_packet(const u8 *buffer, u8 len)
138{
139 unsigned short i;
140 u32 val = 0;
141
142 for (i = 0; i < len; i++)
143 val |= buffer[i] << (i * 8);
144
145 return val;
146}
147
148static void mtk_hdmi_v2_hw_write_audio_infoframe(struct mtk_hdmi *hdmi, const u8 *buffer)
149{
150 regmap_clear_bits(map: hdmi->regs, TOP_INFO_EN, AUD_EN | AUD_EN_WR);
151 regmap_clear_bits(map: hdmi->regs, TOP_INFO_RPT, AUD_RPT_EN);
152
153 regmap_write(map: hdmi->regs, TOP_AIF_HEADER, val: mtk_hdmi_v2_format_hw_packet(buffer: &buffer[0], len: 3));
154 regmap_write(map: hdmi->regs, TOP_AIF_PKT00, val: mtk_hdmi_v2_format_hw_packet(buffer: &buffer[3], len: 3));
155 regmap_write(map: hdmi->regs, TOP_AIF_PKT01, val: mtk_hdmi_v2_format_hw_packet(buffer: &buffer[7], len: 2));
156 regmap_write(map: hdmi->regs, TOP_AIF_PKT02, val: 0);
157 regmap_write(map: hdmi->regs, TOP_AIF_PKT03, val: 0);
158
159 regmap_set_bits(map: hdmi->regs, TOP_INFO_RPT, AUD_RPT_EN);
160 regmap_set_bits(map: hdmi->regs, TOP_INFO_EN, AUD_EN | AUD_EN_WR);
161}
162
163static void mtk_hdmi_v2_hw_write_avi_infoframe(struct mtk_hdmi *hdmi, const u8 *buffer)
164{
165 regmap_clear_bits(map: hdmi->regs, TOP_INFO_EN, AVI_EN_WR | AVI_EN);
166 regmap_clear_bits(map: hdmi->regs, TOP_INFO_RPT, AVI_RPT_EN);
167
168 regmap_write(map: hdmi->regs, TOP_AVI_HEADER, val: mtk_hdmi_v2_format_hw_packet(buffer: &buffer[0], len: 3));
169 regmap_write(map: hdmi->regs, TOP_AVI_PKT00, val: mtk_hdmi_v2_format_hw_packet(buffer: &buffer[3], len: 4));
170 regmap_write(map: hdmi->regs, TOP_AVI_PKT01, val: mtk_hdmi_v2_format_hw_packet(buffer: &buffer[7], len: 3));
171 regmap_write(map: hdmi->regs, TOP_AVI_PKT02, val: mtk_hdmi_v2_format_hw_packet(buffer: &buffer[10], len: 4));
172 regmap_write(map: hdmi->regs, TOP_AVI_PKT03, val: mtk_hdmi_v2_format_hw_packet(buffer: &buffer[14], len: 3));
173 regmap_write(map: hdmi->regs, TOP_AVI_PKT04, val: 0);
174 regmap_write(map: hdmi->regs, TOP_AVI_PKT05, val: 0);
175
176 regmap_set_bits(map: hdmi->regs, TOP_INFO_RPT, AVI_RPT_EN);
177 regmap_set_bits(map: hdmi->regs, TOP_INFO_EN, AVI_EN_WR | AVI_EN);
178}
179
180static void mtk_hdmi_v2_hw_write_spd_infoframe(struct mtk_hdmi *hdmi, const u8 *buffer)
181{
182 regmap_clear_bits(map: hdmi->regs, TOP_INFO_EN, SPD_EN_WR | SPD_EN);
183 regmap_clear_bits(map: hdmi->regs, TOP_INFO_RPT, SPD_RPT_EN);
184
185 regmap_write(map: hdmi->regs, TOP_SPDIF_HEADER, val: mtk_hdmi_v2_format_hw_packet(buffer: &buffer[0], len: 3));
186 regmap_write(map: hdmi->regs, TOP_SPDIF_PKT00, val: mtk_hdmi_v2_format_hw_packet(buffer: &buffer[3], len: 4));
187 regmap_write(map: hdmi->regs, TOP_SPDIF_PKT01, val: mtk_hdmi_v2_format_hw_packet(buffer: &buffer[7], len: 3));
188 regmap_write(map: hdmi->regs, TOP_SPDIF_PKT02, val: mtk_hdmi_v2_format_hw_packet(buffer: &buffer[10], len: 4));
189 regmap_write(map: hdmi->regs, TOP_SPDIF_PKT03, val: mtk_hdmi_v2_format_hw_packet(buffer: &buffer[14], len: 3));
190 regmap_write(map: hdmi->regs, TOP_SPDIF_PKT04, val: mtk_hdmi_v2_format_hw_packet(buffer: &buffer[17], len: 4));
191 regmap_write(map: hdmi->regs, TOP_SPDIF_PKT05, val: mtk_hdmi_v2_format_hw_packet(buffer: &buffer[21], len: 3));
192 regmap_write(map: hdmi->regs, TOP_SPDIF_PKT06, val: mtk_hdmi_v2_format_hw_packet(buffer: &buffer[24], len: 4));
193 regmap_write(map: hdmi->regs, TOP_SPDIF_PKT07, val: buffer[28]);
194
195 regmap_set_bits(map: hdmi->regs, TOP_INFO_EN, SPD_EN_WR | SPD_EN);
196 regmap_set_bits(map: hdmi->regs, TOP_INFO_RPT, SPD_RPT_EN);
197}
198
199static void mtk_hdmi_v2_hw_write_vendor_infoframe(struct mtk_hdmi *hdmi, const u8 *buffer)
200{
201 regmap_clear_bits(map: hdmi->regs, TOP_INFO_EN, VSIF_EN_WR | VSIF_EN);
202 regmap_clear_bits(map: hdmi->regs, TOP_INFO_RPT, VSIF_RPT_EN);
203
204 regmap_write(map: hdmi->regs, TOP_VSIF_HEADER, val: mtk_hdmi_v2_format_hw_packet(buffer: &buffer[0], len: 3));
205 regmap_write(map: hdmi->regs, TOP_VSIF_PKT00, val: mtk_hdmi_v2_format_hw_packet(buffer: &buffer[3], len: 4));
206 regmap_write(map: hdmi->regs, TOP_VSIF_PKT01, val: mtk_hdmi_v2_format_hw_packet(buffer: &buffer[7], len: 2));
207 regmap_write(map: hdmi->regs, TOP_VSIF_PKT02, val: 0);
208 regmap_write(map: hdmi->regs, TOP_VSIF_PKT03, val: 0);
209 regmap_write(map: hdmi->regs, TOP_VSIF_PKT04, val: 0);
210 regmap_write(map: hdmi->regs, TOP_VSIF_PKT05, val: 0);
211 regmap_write(map: hdmi->regs, TOP_VSIF_PKT06, val: 0);
212 regmap_write(map: hdmi->regs, TOP_VSIF_PKT07, val: 0);
213
214 regmap_set_bits(map: hdmi->regs, TOP_INFO_EN, VSIF_EN_WR | VSIF_EN);
215 regmap_set_bits(map: hdmi->regs, TOP_INFO_RPT, VSIF_RPT_EN);
216}
217
218static void mtk_hdmi_yuv420_downsampling(struct mtk_hdmi *hdmi, bool enable)
219{
220 u32 val;
221
222 regmap_read(map: hdmi->regs, VID_DOWNSAMPLE_CONFIG, val: &val);
223
224 if (enable) {
225 regmap_set_bits(map: hdmi->regs, reg: hdmi->conf->reg_hdmi_tx_cfg, HDMI_YUV420_MODE);
226
227 val |= C444_C422_CONFIG_ENABLE | C422_C420_CONFIG_ENABLE;
228 val |= C422_C420_CONFIG_OUT_CB_OR_CR;
229 val &= ~C422_C420_CONFIG_BYPASS;
230 regmap_write(map: hdmi->regs, VID_DOWNSAMPLE_CONFIG, val);
231
232 regmap_set_bits(map: hdmi->regs, VID_OUT_FORMAT, OUTPUT_FORMAT_DEMUX_420_ENABLE);
233 } else {
234 regmap_clear_bits(map: hdmi->regs, reg: hdmi->conf->reg_hdmi_tx_cfg, HDMI_YUV420_MODE);
235
236 val &= ~(C444_C422_CONFIG_ENABLE | C422_C420_CONFIG_ENABLE);
237 val &= ~C422_C420_CONFIG_OUT_CB_OR_CR;
238 val |= C422_C420_CONFIG_BYPASS;
239 regmap_write(map: hdmi->regs, VID_DOWNSAMPLE_CONFIG, val);
240
241 regmap_clear_bits(map: hdmi->regs, VID_OUT_FORMAT, OUTPUT_FORMAT_DEMUX_420_ENABLE);
242 }
243}
244
245static int mtk_hdmi_v2_setup_audio_infoframe(struct mtk_hdmi *hdmi)
246{
247 struct hdmi_codec_params *params = &hdmi->aud_param.codec_params;
248 struct hdmi_audio_infoframe frame;
249 u8 buffer[14];
250 ssize_t ret;
251
252 memcpy(&frame, &params->cea, sizeof(frame));
253
254 ret = hdmi_audio_infoframe_pack(frame: &frame, buffer, size: sizeof(buffer));
255 if (ret < 0)
256 return ret;
257
258 mtk_hdmi_v2_hw_write_audio_infoframe(hdmi, buffer);
259
260 return 0;
261}
262
263static inline void mtk_hdmi_v2_hw_gcp_avmute(struct mtk_hdmi *hdmi, bool mute)
264{
265 u32 val;
266
267 regmap_read(map: hdmi->regs, TOP_CFG01, val: &val);
268 val &= ~(CP_CLR_MUTE_EN | CP_SET_MUTE_EN);
269
270 if (mute) {
271 val |= CP_SET_MUTE_EN;
272 val &= ~CP_CLR_MUTE_EN;
273 } else {
274 val |= CP_CLR_MUTE_EN;
275 val &= ~CP_SET_MUTE_EN;
276 }
277 regmap_write(map: hdmi->regs, TOP_CFG01, val);
278
279 regmap_set_bits(map: hdmi->regs, TOP_INFO_RPT, CP_RPT_EN);
280 regmap_set_bits(map: hdmi->regs, TOP_INFO_EN, CP_EN | CP_EN_WR);
281}
282
283static void mtk_hdmi_v2_hw_ncts_enable(struct mtk_hdmi *hdmi, bool enable)
284{
285 if (enable)
286 regmap_set_bits(map: hdmi->regs, AIP_CTRL, CTS_SW_SEL);
287 else
288 regmap_clear_bits(map: hdmi->regs, AIP_CTRL, CTS_SW_SEL);
289}
290
291static void mtk_hdmi_v2_hw_aud_set_channel_status(struct mtk_hdmi *hdmi)
292{
293 u8 *ch_status = hdmi->aud_param.codec_params.iec.status;
294
295 /* Only the first 5 to 7 bytes of Channel Status contain useful information */
296 regmap_write(map: hdmi->regs, AIP_I2S_CHST0, val: mtk_hdmi_v2_format_hw_packet(buffer: &ch_status[0], len: 4));
297 regmap_write(map: hdmi->regs, AIP_I2S_CHST1, val: mtk_hdmi_v2_format_hw_packet(buffer: &ch_status[4], len: 3));
298}
299
300static void mtk_hdmi_v2_hw_aud_set_ncts(struct mtk_hdmi *hdmi,
301 unsigned int sample_rate,
302 unsigned int clock)
303{
304 unsigned int n, cts;
305
306 mtk_hdmi_get_ncts(sample_rate, clock, n: &n, cts: &cts);
307
308 regmap_write(map: hdmi->regs, AIP_N_VAL, val: n);
309 regmap_write(map: hdmi->regs, AIP_CTS_SVAL, val: cts);
310}
311
312static void mtk_hdmi_v2_hw_aud_enable(struct mtk_hdmi *hdmi, bool enable)
313{
314 if (enable)
315 regmap_clear_bits(map: hdmi->regs, AIP_TXCTRL, AUD_PACKET_DROP);
316 else
317 regmap_set_bits(map: hdmi->regs, AIP_TXCTRL, AUD_PACKET_DROP);
318}
319
320static u32 mtk_hdmi_v2_aud_output_channel_map(u8 sd0, u8 sd1, u8 sd2, u8 sd3,
321 u8 sd4, u8 sd5, u8 sd6, u8 sd7)
322{
323 u32 val;
324
325 /*
326 * Each of the Output Channels (0-7) can be mapped to get their input
327 * from any of the available Input Channels (0-7): this function
328 * takes input channel numbers and formats a value that must then
329 * be written to the TOP_AUD_MAP hardware register by the caller.
330 */
331 val = FIELD_PREP(SD0_MAP, sd0) | FIELD_PREP(SD1_MAP, sd1);
332 val |= FIELD_PREP(SD2_MAP, sd2) | FIELD_PREP(SD3_MAP, sd3);
333 val |= FIELD_PREP(SD4_MAP, sd4) | FIELD_PREP(SD5_MAP, sd5);
334 val |= FIELD_PREP(SD6_MAP, sd6) | FIELD_PREP(SD7_MAP, sd7);
335
336 return val;
337}
338
339static void mtk_hdmi_audio_dsd_config(struct mtk_hdmi *hdmi,
340 unsigned char chnum, bool dsd_bypass)
341{
342 u32 channel_map;
343
344 regmap_update_bits(map: hdmi->regs, AIP_CTRL, SPDIF_EN | DSD_EN | HBRA_ON, DSD_EN);
345 regmap_set_bits(map: hdmi->regs, AIP_TXCTRL, DSD_MUTE_EN);
346
347 if (dsd_bypass)
348 channel_map = mtk_hdmi_v2_aud_output_channel_map(sd0: 0, sd1: 2, sd2: 4, sd3: 6, sd4: 1, sd5: 3, sd6: 5, sd7: 7);
349 else
350 channel_map = mtk_hdmi_v2_aud_output_channel_map(sd0: 0, sd1: 5, sd2: 1, sd3: 0, sd4: 3, sd5: 2, sd6: 4, sd7: 0);
351
352 regmap_write(map: hdmi->regs, TOP_AUD_MAP, val: channel_map);
353 regmap_clear_bits(map: hdmi->regs, AIP_SPDIF_CTRL, I2S2DSD_EN);
354}
355
356static inline void mtk_hdmi_v2_hw_i2s_fifo_map(struct mtk_hdmi *hdmi, u32 fifo_mapping)
357{
358 regmap_update_bits(map: hdmi->regs, AIP_I2S_CTRL,
359 FIFO0_MAP | FIFO1_MAP | FIFO2_MAP | FIFO3_MAP, val: fifo_mapping);
360}
361
362static inline void mtk_hdmi_v2_hw_i2s_ch_number(struct mtk_hdmi *hdmi, u8 chnum)
363{
364 regmap_update_bits(map: hdmi->regs, AIP_CTRL, I2S_EN, FIELD_PREP(I2S_EN, chnum));
365}
366
367static void mtk_hdmi_v2_hw_i2s_ch_mapping(struct mtk_hdmi *hdmi, u8 chnum, u8 mapping)
368{
369 u32 fifo_map;
370 u8 bdata;
371
372 switch (chnum) {
373 default:
374 case 2:
375 bdata = 0x1;
376 break;
377 case 3:
378 bdata = 0x3;
379 break;
380 case 6:
381 if (mapping == 0x0e) {
382 bdata = 0xf;
383 break;
384 }
385 fallthrough;
386 case 5:
387 bdata = 0x7;
388 break;
389 case 7:
390 case 8:
391 bdata = 0xf;
392 break;
393 }
394
395 /* Assign default FIFO mapping: SD0 to FIFO0, SD1 to FIFO1, etc. */
396 fifo_map = FIELD_PREP(FIFO0_MAP, 0) | FIELD_PREP(FIFO1_MAP, 1);
397 fifo_map |= FIELD_PREP(FIFO2_MAP, 2) | FIELD_PREP(FIFO3_MAP, 3);
398 mtk_hdmi_v2_hw_i2s_fifo_map(hdmi, fifo_mapping: fifo_map);
399 mtk_hdmi_v2_hw_i2s_ch_number(hdmi, chnum: bdata);
400
401 /*
402 * Set HDMI Audio packet layout indicator:
403 * Layout 0 is for two channels
404 * Layout 1 is for up to eight channels
405 */
406 if (chnum == 2)
407 regmap_set_bits(map: hdmi->regs, AIP_TXCTRL, AUD_LAYOUT_1);
408 else
409 regmap_clear_bits(map: hdmi->regs, AIP_TXCTRL, AUD_LAYOUT_1);
410}
411
412static void mtk_hdmi_i2s_data_fmt(struct mtk_hdmi *hdmi, unsigned char fmt)
413{
414 u32 val;
415
416 regmap_read(map: hdmi->regs, AIP_I2S_CTRL, val: &val);
417 val &= ~(WS_HIGH | I2S_1ST_BIT_NOSHIFT | JUSTIFY_RIGHT);
418
419 switch (fmt) {
420 case HDMI_I2S_MODE_RJT_24BIT:
421 case HDMI_I2S_MODE_RJT_16BIT:
422 val |= (WS_HIGH | I2S_1ST_BIT_NOSHIFT | JUSTIFY_RIGHT);
423 break;
424 case HDMI_I2S_MODE_LJT_24BIT:
425 case HDMI_I2S_MODE_LJT_16BIT:
426 val |= (WS_HIGH | I2S_1ST_BIT_NOSHIFT);
427 break;
428 case HDMI_I2S_MODE_I2S_24BIT:
429 case HDMI_I2S_MODE_I2S_16BIT:
430 default:
431 break;
432 }
433
434 regmap_write(map: hdmi->regs, AIP_I2S_CTRL, val);
435}
436
437static inline void mtk_hdmi_i2s_sck_edge_rise(struct mtk_hdmi *hdmi, bool rise)
438{
439 if (rise)
440 regmap_set_bits(map: hdmi->regs, AIP_I2S_CTRL, SCK_EDGE_RISE);
441 else
442 regmap_clear_bits(map: hdmi->regs, AIP_I2S_CTRL, SCK_EDGE_RISE);
443}
444
445static inline void mtk_hdmi_i2s_cbit_order(struct mtk_hdmi *hdmi, unsigned int cbit)
446{
447 regmap_update_bits(map: hdmi->regs, AIP_I2S_CTRL, CBIT_ORDER_SAME, val: cbit);
448}
449
450static inline void mtk_hdmi_i2s_vbit(struct mtk_hdmi *hdmi, unsigned int vbit)
451{
452 /* V bit: 0 for PCM, 1 for Compressed data */
453 regmap_update_bits(map: hdmi->regs, AIP_I2S_CTRL, VBIT_COMPRESSED, val: vbit);
454}
455
456static inline void mtk_hdmi_i2s_data_direction(struct mtk_hdmi *hdmi, unsigned int is_lsb)
457{
458 regmap_update_bits(map: hdmi->regs, AIP_I2S_CTRL, I2S_DATA_DIR_LSB, val: is_lsb);
459}
460
461static inline void mtk_hdmi_v2_hw_audio_type(struct mtk_hdmi *hdmi, unsigned int spdif_i2s)
462{
463 regmap_update_bits(map: hdmi->regs, AIP_CTRL, SPDIF_EN, FIELD_PREP(SPDIF_EN, spdif_i2s));
464}
465
466static u8 mtk_hdmi_v2_get_i2s_ch_mapping(struct mtk_hdmi *hdmi, u8 channel_type)
467{
468 switch (channel_type) {
469 case HDMI_AUD_CHAN_TYPE_1_1:
470 case HDMI_AUD_CHAN_TYPE_2_1:
471 return 0x01;
472 case HDMI_AUD_CHAN_TYPE_3_0:
473 return 0x02;
474 case HDMI_AUD_CHAN_TYPE_3_1:
475 return 0x03;
476 case HDMI_AUD_CHAN_TYPE_3_0_LRS:
477 case HDMI_AUD_CHAN_TYPE_4_0:
478 return 0x08;
479 case HDMI_AUD_CHAN_TYPE_5_1:
480 return 0x0b;
481 case HDMI_AUD_CHAN_TYPE_4_1_CLRS:
482 case HDMI_AUD_CHAN_TYPE_6_0:
483 case HDMI_AUD_CHAN_TYPE_6_0_CS:
484 case HDMI_AUD_CHAN_TYPE_6_0_CH:
485 case HDMI_AUD_CHAN_TYPE_6_0_OH:
486 case HDMI_AUD_CHAN_TYPE_6_0_CHR:
487 return 0x0e;
488 case HDMI_AUD_CHAN_TYPE_1_0:
489 case HDMI_AUD_CHAN_TYPE_2_0:
490 case HDMI_AUD_CHAN_TYPE_3_1_LRS:
491 case HDMI_AUD_CHAN_TYPE_4_1:
492 case HDMI_AUD_CHAN_TYPE_5_0:
493 case HDMI_AUD_CHAN_TYPE_4_0_CLRS:
494 case HDMI_AUD_CHAN_TYPE_6_1:
495 case HDMI_AUD_CHAN_TYPE_6_1_CS:
496 case HDMI_AUD_CHAN_TYPE_6_1_CH:
497 case HDMI_AUD_CHAN_TYPE_6_1_OH:
498 case HDMI_AUD_CHAN_TYPE_6_1_CHR:
499 case HDMI_AUD_CHAN_TYPE_7_0:
500 case HDMI_AUD_CHAN_TYPE_7_0_LH_RH:
501 case HDMI_AUD_CHAN_TYPE_7_0_LSR_RSR:
502 case HDMI_AUD_CHAN_TYPE_7_0_LC_RC:
503 case HDMI_AUD_CHAN_TYPE_7_0_LW_RW:
504 case HDMI_AUD_CHAN_TYPE_7_0_LSD_RSD:
505 case HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS:
506 case HDMI_AUD_CHAN_TYPE_7_0_LHS_RHS:
507 case HDMI_AUD_CHAN_TYPE_7_0_CS_CH:
508 case HDMI_AUD_CHAN_TYPE_7_0_CS_OH:
509 case HDMI_AUD_CHAN_TYPE_7_0_CS_CHR:
510 case HDMI_AUD_CHAN_TYPE_7_0_CH_OH:
511 case HDMI_AUD_CHAN_TYPE_7_0_CH_CHR:
512 case HDMI_AUD_CHAN_TYPE_7_0_OH_CHR:
513 case HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS_LSR_RSR:
514 case HDMI_AUD_CHAN_TYPE_8_0_LH_RH_CS:
515 case HDMI_AUD_CHAN_TYPE_7_1:
516 case HDMI_AUD_CHAN_TYPE_7_1_LH_RH:
517 case HDMI_AUD_CHAN_TYPE_7_1_LSR_RSR:
518 case HDMI_AUD_CHAN_TYPE_7_1_LC_RC:
519 case HDMI_AUD_CHAN_TYPE_7_1_LW_RW:
520 case HDMI_AUD_CHAN_TYPE_7_1_LSD_RSD:
521 case HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS:
522 case HDMI_AUD_CHAN_TYPE_7_1_LHS_RHS:
523 case HDMI_AUD_CHAN_TYPE_7_1_CS_CH:
524 case HDMI_AUD_CHAN_TYPE_7_1_CS_OH:
525 case HDMI_AUD_CHAN_TYPE_7_1_CS_CHR:
526 case HDMI_AUD_CHAN_TYPE_7_1_CH_OH:
527 case HDMI_AUD_CHAN_TYPE_7_1_CH_CHR:
528 case HDMI_AUD_CHAN_TYPE_7_1_OH_CHR:
529 case HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS_LSR_RSR:
530 default:
531 return 0;
532 }
533
534 return 0;
535}
536
537static inline void mtk_hdmi_v2_hw_i2s_ch_swap(struct mtk_hdmi *hdmi)
538{
539 regmap_update_bits(map: hdmi->regs, AIP_SPDIF_CTRL, MAX_2UI_I2S_HI_WRITE,
540 FIELD_PREP(MAX_2UI_I2S_HI_WRITE, MAX_2UI_I2S_LFE_CC_SWAP));
541}
542
543static void mtk_hdmi_hbr_config(struct mtk_hdmi *hdmi, bool dsd_bypass)
544{
545 const u32 hbr_mask = SPDIF_EN | DSD_EN | HBRA_ON;
546
547 if (dsd_bypass) {
548 regmap_update_bits(map: hdmi->regs, AIP_CTRL, mask: hbr_mask, HBRA_ON);
549 regmap_set_bits(map: hdmi->regs, AIP_CTRL, I2S_EN);
550 } else {
551 regmap_update_bits(map: hdmi->regs, AIP_CTRL, mask: hbr_mask, SPDIF_EN);
552 regmap_set_bits(map: hdmi->regs, AIP_CTRL, SPDIF_INTERNAL_MODULE);
553 regmap_set_bits(map: hdmi->regs, AIP_CTRL, HBR_FROM_SPDIF);
554 regmap_set_bits(map: hdmi->regs, AIP_CTRL, CTS_CAL_N4);
555 }
556}
557
558static inline void mtk_hdmi_v2_hw_spdif_config(struct mtk_hdmi *hdmi)
559{
560 regmap_clear_bits(map: hdmi->regs, AIP_SPDIF_CTRL, WR_1UI_LOCK);
561 regmap_clear_bits(map: hdmi->regs, AIP_SPDIF_CTRL, FS_OVERRIDE_WRITE);
562 regmap_clear_bits(map: hdmi->regs, AIP_SPDIF_CTRL, WR_2UI_LOCK);
563
564 regmap_update_bits(map: hdmi->regs, AIP_SPDIF_CTRL, MAX_1UI_WRITE,
565 FIELD_PREP(MAX_1UI_WRITE, 4));
566 regmap_update_bits(map: hdmi->regs, AIP_SPDIF_CTRL, MAX_2UI_SPDIF_WRITE,
567 FIELD_PREP(MAX_2UI_SPDIF_WRITE, 9));
568 regmap_update_bits(map: hdmi->regs, AIP_SPDIF_CTRL, AUD_ERR_THRESH,
569 FIELD_PREP(AUD_ERR_THRESH, 4));
570
571 regmap_set_bits(map: hdmi->regs, AIP_SPDIF_CTRL, I2S2DSD_EN);
572}
573
574static void mtk_hdmi_v2_aud_set_input(struct mtk_hdmi *hdmi)
575{
576 struct hdmi_audio_param *aud_param = &hdmi->aud_param;
577 struct hdmi_codec_params *codec_params = &aud_param->codec_params;
578 u8 i2s_ch_map;
579 u32 out_ch_map;
580
581 /* Write the default output channel map. CH0 maps to SD0, CH1 maps to SD1, etc */
582 out_ch_map = mtk_hdmi_v2_aud_output_channel_map(sd0: 0, sd1: 1, sd2: 2, sd3: 3, sd4: 4, sd5: 5, sd6: 6, sd7: 7);
583 regmap_write(map: hdmi->regs, TOP_AUD_MAP, val: out_ch_map);
584
585 regmap_update_bits(map: hdmi->regs, AIP_SPDIF_CTRL, MAX_2UI_I2S_HI_WRITE, val: 0);
586 regmap_clear_bits(map: hdmi->regs, AIP_CTRL,
587 SPDIF_EN | DSD_EN | HBRA_ON | CTS_CAL_N4 |
588 HBR_FROM_SPDIF | SPDIF_INTERNAL_MODULE);
589 regmap_clear_bits(map: hdmi->regs, AIP_TXCTRL, DSD_MUTE_EN | AUD_LAYOUT_1);
590
591 if (aud_param->aud_input_type == HDMI_AUD_INPUT_I2S) {
592 switch (aud_param->aud_codec) {
593 case HDMI_AUDIO_CODING_TYPE_DTS_HD:
594 case HDMI_AUDIO_CODING_TYPE_MLP:
595 mtk_hdmi_i2s_data_fmt(hdmi, fmt: aud_param->aud_i2s_fmt);
596 mtk_hdmi_hbr_config(hdmi, dsd_bypass: true);
597 break;
598 case HDMI_AUDIO_CODING_TYPE_DSD:
599 mtk_hdmi_audio_dsd_config(hdmi, chnum: codec_params->channels, dsd_bypass: 0);
600 mtk_hdmi_v2_hw_i2s_ch_mapping(hdmi, chnum: codec_params->channels, mapping: 1);
601 break;
602 default:
603 mtk_hdmi_i2s_data_fmt(hdmi, fmt: aud_param->aud_i2s_fmt);
604 mtk_hdmi_i2s_sck_edge_rise(hdmi, rise: true);
605 mtk_hdmi_i2s_cbit_order(hdmi, CBIT_ORDER_SAME);
606 mtk_hdmi_i2s_vbit(hdmi, vbit: 0); /* PCM data */
607 mtk_hdmi_i2s_data_direction(hdmi, is_lsb: 0); /* MSB first */
608 mtk_hdmi_v2_hw_audio_type(hdmi, spdif_i2s: HDMI_AUD_INPUT_I2S);
609 i2s_ch_map = mtk_hdmi_v2_get_i2s_ch_mapping(hdmi,
610 channel_type: aud_param->aud_input_chan_type);
611 mtk_hdmi_v2_hw_i2s_ch_mapping(hdmi, chnum: codec_params->channels, mapping: i2s_ch_map);
612 mtk_hdmi_v2_hw_i2s_ch_swap(hdmi);
613 }
614 } else {
615 if (codec_params->sample_rate == 768000 &&
616 (aud_param->aud_codec == HDMI_AUDIO_CODING_TYPE_DTS_HD ||
617 aud_param->aud_codec == HDMI_AUDIO_CODING_TYPE_MLP)) {
618 mtk_hdmi_hbr_config(hdmi, dsd_bypass: false);
619 } else {
620 mtk_hdmi_v2_hw_spdif_config(hdmi);
621 mtk_hdmi_v2_hw_i2s_ch_mapping(hdmi, chnum: 2, mapping: 0);
622 }
623 }
624}
625
626static inline void mtk_hdmi_v2_hw_audio_input_enable(struct mtk_hdmi *hdmi, bool ena)
627{
628 if (ena)
629 regmap_set_bits(map: hdmi->regs, AIP_CTRL, AUD_IN_EN);
630 else
631 regmap_clear_bits(map: hdmi->regs, AIP_CTRL, AUD_IN_EN);
632}
633
634static void mtk_hdmi_v2_aip_ctrl_init(struct mtk_hdmi *hdmi)
635{
636 regmap_set_bits(map: hdmi->regs, AIP_CTRL,
637 AUD_SEL_OWRT | NO_MCLK_CTSGEN_SEL | MCLK_EN | CTS_REQ_EN);
638 regmap_clear_bits(map: hdmi->regs, AIP_TPI_CTRL, TPI_AUDIO_LOOKUP_EN);
639}
640
641static void mtk_hdmi_v2_audio_reset(struct mtk_hdmi *hdmi, bool reset)
642{
643 const u32 arst_bits = RST4AUDIO | RST4AUDIO_FIFO | RST4AUDIO_ACR;
644
645 if (reset)
646 regmap_set_bits(map: hdmi->regs, AIP_TXCTRL, bits: arst_bits);
647 else
648 regmap_clear_bits(map: hdmi->regs, AIP_TXCTRL, bits: arst_bits);
649}
650
651static void mtk_hdmi_v2_aud_output_config(struct mtk_hdmi *hdmi,
652 struct drm_display_mode *display_mode)
653{
654 /* Shut down and reset the HDMI Audio HW to avoid glitching */
655 mtk_hdmi_v2_hw_aud_mute(hdmi, enable: true);
656 mtk_hdmi_v2_hw_aud_enable(hdmi, enable: false);
657 mtk_hdmi_v2_audio_reset(hdmi, reset: true);
658
659 /* Configure the main hardware params and get out of reset */
660 mtk_hdmi_v2_aip_ctrl_init(hdmi);
661 mtk_hdmi_v2_aud_set_input(hdmi);
662 mtk_hdmi_v2_hw_aud_set_channel_status(hdmi);
663 mtk_hdmi_v2_setup_audio_infoframe(hdmi);
664 mtk_hdmi_v2_hw_audio_input_enable(hdmi, ena: true);
665 mtk_hdmi_v2_audio_reset(hdmi, reset: false);
666
667 /* Ignore N/CTS packet transmission requests and configure */
668 mtk_hdmi_v2_hw_ncts_enable(hdmi, enable: false);
669 mtk_hdmi_v2_hw_aud_set_ncts(hdmi, sample_rate: hdmi->aud_param.codec_params.sample_rate,
670 clock: display_mode->clock);
671
672 /* Wait for the HW to apply settings */
673 usleep_range(min: 25, max: 50);
674
675 /* Hardware is fully configured: enable TX of N/CTS pkts and unmute */
676 mtk_hdmi_v2_hw_ncts_enable(hdmi, enable: true);
677 mtk_hdmi_v2_hw_aud_enable(hdmi, enable: true);
678 mtk_hdmi_v2_hw_aud_mute(hdmi, enable: false);
679}
680
681static void mtk_hdmi_v2_change_video_resolution(struct mtk_hdmi *hdmi,
682 struct drm_connector_state *conn_state)
683{
684 mtk_hdmi_v2_hw_reset(hdmi);
685 mtk_hdmi_v2_set_sw_hpd(hdmi, enable: true);
686 udelay(usec: 2);
687
688 regmap_write(map: hdmi->regs, HDCP_TOP_CTRL, val: 0);
689
690 /*
691 * Enable HDCP reauthentication interrupt: the HW uses this internally
692 * for the HPD state machine even if HDCP encryption is not enabled.
693 */
694 regmap_set_bits(map: hdmi->regs, TOP_INT_ENABLE00, HDCP2X_RX_REAUTH_REQ_DDCM_INT);
695
696 /* Enable hotplug and pord interrupts */
697 mtk_hdmi_v2_enable_hpd_pord_irq(hdmi, enable: true);
698
699 /* Force enabling HDCP HPD */
700 regmap_set_bits(map: hdmi->regs, HDCP2X_CTRL_0, HDCP2X_HPD_OVR);
701 regmap_set_bits(map: hdmi->regs, HDCP2X_CTRL_0, HDCP2X_HPD_SW);
702
703 /* Set 8 bits per pixel */
704 regmap_update_bits(map: hdmi->regs, TOP_CFG00, TMDS_PACK_MODE,
705 FIELD_PREP(TMDS_PACK_MODE, TMDS_PACK_MODE_8BPP));
706 /* Disable generating deepcolor packets */
707 regmap_clear_bits(map: hdmi->regs, TOP_CFG00, DEEPCOLOR_PKT_EN);
708 /* Disable adding deepcolor information to the general packet */
709 regmap_clear_bits(map: hdmi->regs, TOP_MISC_CTLR, DEEP_COLOR_ADD);
710
711 if (hdmi->curr_conn->display_info.is_hdmi)
712 regmap_set_bits(map: hdmi->regs, TOP_CFG00, HDMI_MODE_HDMI);
713 else
714 regmap_clear_bits(map: hdmi->regs, TOP_CFG00, HDMI_MODE_HDMI);
715
716 udelay(usec: 5);
717 mtk_hdmi_v2_hw_vid_mute(hdmi, enable: true);
718 mtk_hdmi_v2_hw_aud_mute(hdmi, enable: true);
719 mtk_hdmi_v2_hw_gcp_avmute(hdmi, mute: false);
720
721 regmap_update_bits(map: hdmi->regs, TOP_CFG01,
722 NULL_PKT_VSYNC_HIGH_EN | NULL_PKT_EN, NULL_PKT_VSYNC_HIGH_EN);
723 usleep_range(min: 100, max: 150);
724
725 /* Enable scrambling if tmds clock is 340MHz or more */
726 mtk_hdmi_v2_enable_scrambling(hdmi, enable: hdmi->mode.clock >= 340 * KILO);
727
728 switch (conn_state->hdmi.output_format) {
729 default:
730 case HDMI_COLORSPACE_RGB:
731 case HDMI_COLORSPACE_YUV444:
732 /* Disable YUV420 downsampling for RGB and YUV444 */
733 mtk_hdmi_yuv420_downsampling(hdmi, enable: false);
734 break;
735 case HDMI_COLORSPACE_YUV422:
736 /*
737 * YUV420 downsampling is special and needs a bit of setup
738 * so we disable everything there before doing anything else.
739 *
740 * YUV422 downsampling instead just needs one bit to be set.
741 */
742 mtk_hdmi_yuv420_downsampling(hdmi, enable: false);
743 regmap_set_bits(map: hdmi->regs, VID_DOWNSAMPLE_CONFIG,
744 C444_C422_CONFIG_ENABLE);
745 break;
746 case HDMI_COLORSPACE_YUV420:
747 mtk_hdmi_yuv420_downsampling(hdmi, enable: true);
748 break;
749 };
750}
751
752static void mtk_hdmi_v2_output_set_display_mode(struct mtk_hdmi *hdmi,
753 struct drm_connector_state *conn_state,
754 struct drm_display_mode *mode)
755{
756 union phy_configure_opts opts = {
757 .dp = { .link_rate = hdmi->mode.clock * KILO }
758 };
759 int ret;
760
761 ret = phy_configure(phy: hdmi->phy, opts: &opts);
762 if (ret)
763 dev_err(hdmi->dev, "Setting clock=%d failed: %d", mode->clock, ret);
764
765 mtk_hdmi_v2_change_video_resolution(hdmi, conn_state);
766 mtk_hdmi_v2_aud_output_config(hdmi, display_mode: mode);
767}
768
769static int mtk_hdmi_v2_clk_enable(struct mtk_hdmi *hdmi)
770{
771 int ret;
772
773 ret = clk_prepare_enable(clk: hdmi->clk[MTK_HDMI_V2_CLK_HDCP_SEL]);
774 if (ret)
775 return ret;
776
777 ret = clk_prepare_enable(clk: hdmi->clk[MTK_HDMI_V2_CLK_HDCP_24M_SEL]);
778 if (ret)
779 goto disable_hdcp_clk;
780
781 ret = clk_prepare_enable(clk: hdmi->clk[MTK_HDMI_V2_CLK_HDMI_APB_SEL]);
782 if (ret)
783 goto disable_hdcp_24m_clk;
784
785 ret = clk_prepare_enable(clk: hdmi->clk[MTK_HDMI_V2_CLK_VPP_SPLIT_HDMI]);
786 if (ret)
787 goto disable_bus_clk;
788
789 return 0;
790
791disable_bus_clk:
792 clk_disable_unprepare(clk: hdmi->clk[MTK_HDMI_V2_CLK_HDMI_APB_SEL]);
793disable_hdcp_24m_clk:
794 clk_disable_unprepare(clk: hdmi->clk[MTK_HDMI_V2_CLK_HDCP_24M_SEL]);
795disable_hdcp_clk:
796 clk_disable_unprepare(clk: hdmi->clk[MTK_HDMI_V2_CLK_HDCP_SEL]);
797
798 return ret;
799}
800
801static void mtk_hdmi_v2_clk_disable(struct mtk_hdmi *hdmi)
802{
803 clk_disable_unprepare(clk: hdmi->clk[MTK_HDMI_V2_CLK_VPP_SPLIT_HDMI]);
804 clk_disable_unprepare(clk: hdmi->clk[MTK_HDMI_V2_CLK_HDMI_APB_SEL]);
805 clk_disable_unprepare(clk: hdmi->clk[MTK_HDMI_V2_CLK_HDCP_24M_SEL]);
806 clk_disable_unprepare(clk: hdmi->clk[MTK_HDMI_V2_CLK_HDCP_SEL]);
807}
808
809static enum hdmi_hpd_state mtk_hdmi_v2_hpd_pord_status(struct mtk_hdmi *hdmi)
810{
811 u8 hpd_pin_sta, pord_pin_sta;
812 u32 hpd_status;
813
814 regmap_read(map: hdmi->regs, HPD_DDC_STATUS, val: &hpd_status);
815 hpd_pin_sta = FIELD_GET(HPD_PIN_STA, hpd_status);
816 pord_pin_sta = FIELD_GET(PORD_PIN_STA, hpd_status);
817
818 /*
819 * Inform that the cable is plugged in (hpd_pin_sta) so that the
820 * sink can be powered on by switching the 5V VBUS as required by
821 * the HDMI spec for reading EDID and for HDMI Audio registers to
822 * be accessible.
823 *
824 * PORD detection succeeds only when the cable is plugged in and
825 * the sink is powered on: reaching that state means that the
826 * communication with the sink can be started.
827 *
828 * Please note that when the cable is plugged out the HPD pin will
829 * be the first one to fall, while PORD may still be in rise state
830 * for a few more milliseconds, so we decide HDMI_PLUG_OUT without
831 * checking PORD at all (we check only HPD falling for that).
832 */
833 if (hpd_pin_sta && pord_pin_sta)
834 return HDMI_PLUG_IN_AND_SINK_POWER_ON;
835 else if (hpd_pin_sta)
836 return HDMI_PLUG_IN_ONLY;
837 else
838 return HDMI_PLUG_OUT;
839}
840
841static irqreturn_t mtk_hdmi_v2_isr(int irq, void *arg)
842{
843 struct mtk_hdmi *hdmi = arg;
844 unsigned int irq_sta;
845 int ret = IRQ_HANDLED;
846
847 regmap_read(map: hdmi->regs, TOP_INT_STA00, val: &irq_sta);
848
849 /* Handle Hotplug Detection interrupts */
850 if (irq_sta & HPD_PORD_HWIRQS) {
851 /*
852 * Disable the HPD/PORD IRQs now and until thread done to
853 * avoid interrupt storm that could happen with bad cables
854 */
855 mtk_hdmi_v2_enable_hpd_pord_irq(hdmi, enable: false);
856 ret = IRQ_WAKE_THREAD;
857
858 /* Clear HPD/PORD irqs to avoid unwanted retriggering */
859 regmap_write(map: hdmi->regs, TOP_INT_CLR00, HPD_PORD_HWIRQS);
860 regmap_write(map: hdmi->regs, TOP_INT_CLR00, val: 0);
861 }
862
863 return ret;
864}
865
866static irqreturn_t __mtk_hdmi_v2_isr_thread(struct mtk_hdmi *hdmi)
867{
868 enum hdmi_hpd_state hpd;
869
870 hpd = mtk_hdmi_v2_hpd_pord_status(hdmi);
871 if (hpd != hdmi->hpd) {
872 struct drm_encoder *encoder = hdmi->bridge.encoder;
873
874 hdmi->hpd = hpd;
875
876 if (encoder && encoder->dev)
877 drm_helper_hpd_irq_event(dev: hdmi->bridge.encoder->dev);
878 }
879
880 mtk_hdmi_v2_enable_hpd_pord_irq(hdmi, enable: true);
881 return IRQ_HANDLED;
882}
883
884static irqreturn_t mtk_hdmi_v2_isr_thread(int irq, void *arg)
885{
886 struct mtk_hdmi *hdmi = arg;
887
888 /*
889 * Debounce HDMI monitor HPD status.
890 * Empirical testing shows that 30ms is enough wait
891 */
892 msleep(msecs: 30);
893
894 return __mtk_hdmi_v2_isr_thread(hdmi);
895}
896
897static int mtk_hdmi_v2_enable(struct mtk_hdmi *hdmi)
898{
899 bool was_active = pm_runtime_active(dev: hdmi->dev);
900 int ret;
901
902 ret = pm_runtime_resume_and_get(dev: hdmi->dev);
903 if (ret) {
904 dev_err(hdmi->dev, "Cannot resume HDMI\n");
905 return ret;
906 }
907
908 ret = mtk_hdmi_v2_clk_enable(hdmi);
909 if (ret) {
910 pm_runtime_put(dev: hdmi->dev);
911 return ret;
912 }
913
914 if (!was_active) {
915 mtk_hdmi_v2_hw_reset(hdmi);
916 mtk_hdmi_v2_set_sw_hpd(hdmi, enable: true);
917 }
918
919 return 0;
920}
921
922static void mtk_hdmi_v2_disable(struct mtk_hdmi *hdmi)
923{
924 mtk_hdmi_v2_clk_disable(hdmi);
925 pm_runtime_put_sync(dev: hdmi->dev);
926}
927
928/*
929 * Bridge callbacks
930 */
931
932static int mtk_hdmi_v2_bridge_attach(struct drm_bridge *bridge,
933 struct drm_encoder *encoder,
934 enum drm_bridge_attach_flags flags)
935{
936 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(b: bridge);
937 int ret;
938
939 if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) {
940 DRM_ERROR("The flag DRM_BRIDGE_ATTACH_NO_CONNECTOR must be supplied\n");
941 return -EINVAL;
942 }
943 if (hdmi->next_bridge) {
944 ret = drm_bridge_attach(encoder, bridge: hdmi->next_bridge, previous: bridge, flags);
945 if (ret)
946 return ret;
947 }
948
949 ret = mtk_hdmi_v2_enable(hdmi);
950 if (ret)
951 return ret;
952
953 /* Enable Hotplug and Pord pins internal debouncing */
954 regmap_set_bits(map: hdmi->regs, HPD_DDC_CTRL,
955 HPD_DDC_HPD_DBNC_EN | HPD_DDC_PORD_DBNC_EN);
956
957 irq_clear_status_flags(irq: hdmi->irq, clr: IRQ_NOAUTOEN);
958 enable_irq(irq: hdmi->irq);
959
960 /*
961 * Check if any HDMI monitor was connected before probing this driver
962 * and/or attaching the bridge, without debouncing: if so, we want to
963 * notify the DRM so that we start outputting an image ASAP.
964 * Note that calling the ISR thread function will also perform a HW
965 * registers write that enables both the HPD and Pord interrupts.
966 */
967 __mtk_hdmi_v2_isr_thread(hdmi);
968
969 mtk_hdmi_v2_disable(hdmi);
970
971 return 0;
972}
973
974static void mtk_hdmi_v2_bridge_detach(struct drm_bridge *bridge)
975{
976 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(b: bridge);
977
978 WARN_ON(pm_runtime_active(hdmi->dev));
979
980 /* The controller is already powered off, just disable irq here */
981 disable_irq(irq: hdmi->irq);
982}
983
984static void mtk_hdmi_v2_handle_plugged_change(struct mtk_hdmi *hdmi, bool plugged)
985{
986 mutex_lock(&hdmi->update_plugged_status_lock);
987 if (hdmi->plugged_cb && hdmi->codec_dev)
988 hdmi->plugged_cb(hdmi->codec_dev, plugged);
989 mutex_unlock(lock: &hdmi->update_plugged_status_lock);
990}
991
992static void mtk_hdmi_v2_bridge_pre_enable(struct drm_bridge *bridge,
993 struct drm_atomic_state *state)
994{
995 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(b: bridge);
996 struct drm_connector_state *conn_state;
997 union phy_configure_opts opts = {
998 .dp = { .link_rate = hdmi->mode.clock * KILO }
999 };
1000 int ret;
1001
1002 /* Power on the controller before trying to write to registers */
1003 ret = mtk_hdmi_v2_enable(hdmi);
1004 if (WARN_ON(ret))
1005 return;
1006
1007 /* Retrieve the connector through the atomic state */
1008 hdmi->curr_conn = drm_atomic_get_new_connector_for_encoder(state, encoder: bridge->encoder);
1009
1010 conn_state = drm_atomic_get_new_connector_state(state, connector: hdmi->curr_conn);
1011 if (WARN_ON(!conn_state))
1012 return;
1013
1014 /*
1015 * Preconfigure the HDMI controller and the HDMI PHY at pre_enable
1016 * stage to make sure that this IP is ready and clocked before the
1017 * mtk_dpi gets powered on and before it enables the output.
1018 */
1019 mtk_hdmi_v2_output_set_display_mode(hdmi, conn_state, mode: &hdmi->mode);
1020
1021 /* Reconfigure phy clock link with appropriate rate */
1022 phy_configure(phy: hdmi->phy, opts: &opts);
1023
1024 /* Power on the PHY here to make sure that DPI_HDMI is clocked */
1025 phy_power_on(phy: hdmi->phy);
1026
1027 hdmi->powered = true;
1028}
1029
1030static void mtk_hdmi_v2_bridge_enable(struct drm_bridge *bridge,
1031 struct drm_atomic_state *state)
1032{
1033 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(b: bridge);
1034 int ret;
1035
1036 if (WARN_ON(!hdmi->powered))
1037 return;
1038
1039 ret = drm_atomic_helper_connector_hdmi_update_infoframes(connector: hdmi->curr_conn, state);
1040 if (ret)
1041 dev_err(hdmi->dev, "Could not update infoframes: %d\n", ret);
1042
1043 mtk_hdmi_v2_hw_vid_mute(hdmi, enable: false);
1044
1045 /* signal the connect event to audio codec */
1046 mtk_hdmi_v2_handle_plugged_change(hdmi, plugged: true);
1047
1048 hdmi->enabled = true;
1049}
1050
1051static void mtk_hdmi_v2_bridge_disable(struct drm_bridge *bridge,
1052 struct drm_atomic_state *state)
1053{
1054 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(b: bridge);
1055
1056 if (!hdmi->enabled)
1057 return;
1058
1059 mtk_hdmi_v2_hw_gcp_avmute(hdmi, mute: true);
1060 msleep(msecs: 50);
1061 mtk_hdmi_v2_hw_vid_mute(hdmi, enable: true);
1062 mtk_hdmi_v2_hw_aud_mute(hdmi, enable: true);
1063 msleep(msecs: 50);
1064
1065 hdmi->enabled = false;
1066}
1067
1068static void mtk_hdmi_v2_bridge_post_disable(struct drm_bridge *bridge,
1069 struct drm_atomic_state *state)
1070{
1071 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(b: bridge);
1072
1073 if (!hdmi->powered)
1074 return;
1075
1076 phy_power_off(phy: hdmi->phy);
1077 hdmi->powered = false;
1078
1079 /* signal the disconnect event to audio codec */
1080 mtk_hdmi_v2_handle_plugged_change(hdmi, plugged: false);
1081
1082 /* Power off */
1083 mtk_hdmi_v2_disable(hdmi);
1084}
1085
1086static enum drm_connector_status mtk_hdmi_v2_bridge_detect(struct drm_bridge *bridge,
1087 struct drm_connector *connector)
1088{
1089 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(b: bridge);
1090
1091 return hdmi->hpd != HDMI_PLUG_OUT ?
1092 connector_status_connected : connector_status_disconnected;
1093}
1094
1095static const struct drm_edid *mtk_hdmi_v2_bridge_edid_read(struct drm_bridge *bridge,
1096 struct drm_connector *connector)
1097{
1098 return drm_edid_read(connector);
1099}
1100
1101static void mtk_hdmi_v2_hpd_enable(struct drm_bridge *bridge)
1102{
1103 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(b: bridge);
1104 int ret;
1105
1106 ret = mtk_hdmi_v2_enable(hdmi);
1107 if (ret) {
1108 dev_err(hdmi->dev, "Cannot power on controller for HPD: %d\n", ret);
1109 return;
1110 }
1111
1112 mtk_hdmi_v2_enable_hpd_pord_irq(hdmi, enable: true);
1113}
1114
1115static void mtk_hdmi_v2_hpd_disable(struct drm_bridge *bridge)
1116{
1117 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(b: bridge);
1118
1119 mtk_hdmi_v2_enable_hpd_pord_irq(hdmi, enable: false);
1120 mtk_hdmi_v2_disable(hdmi);
1121}
1122
1123static enum drm_mode_status
1124mtk_hdmi_v2_hdmi_tmds_char_rate_valid(const struct drm_bridge *bridge,
1125 const struct drm_display_mode *mode,
1126 unsigned long long tmds_rate)
1127{
1128 if (mode->clock < MTK_HDMI_V2_CLOCK_MIN)
1129 return MODE_CLOCK_LOW;
1130 else if (mode->clock > MTK_HDMI_V2_CLOCK_MAX)
1131 return MODE_CLOCK_HIGH;
1132 else
1133 return MODE_OK;
1134}
1135
1136static int mtk_hdmi_v2_hdmi_clear_infoframe(struct drm_bridge *bridge,
1137 enum hdmi_infoframe_type type)
1138{
1139 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(b: bridge);
1140
1141 switch (type) {
1142 case HDMI_INFOFRAME_TYPE_AUDIO:
1143 regmap_clear_bits(map: hdmi->regs, TOP_INFO_EN, AUD_EN_WR | AUD_EN);
1144 regmap_clear_bits(map: hdmi->regs, TOP_INFO_RPT, AUD_RPT_EN);
1145 break;
1146 case HDMI_INFOFRAME_TYPE_AVI:
1147 regmap_clear_bits(map: hdmi->regs, TOP_INFO_EN, AVI_EN_WR | AVI_EN);
1148 regmap_clear_bits(map: hdmi->regs, TOP_INFO_RPT, AVI_RPT_EN);
1149 break;
1150 case HDMI_INFOFRAME_TYPE_SPD:
1151 regmap_clear_bits(map: hdmi->regs, TOP_INFO_EN, SPD_EN_WR | SPD_EN);
1152 regmap_clear_bits(map: hdmi->regs, TOP_INFO_RPT, SPD_RPT_EN);
1153 break;
1154 case HDMI_INFOFRAME_TYPE_VENDOR:
1155 regmap_clear_bits(map: hdmi->regs, TOP_INFO_EN, VSIF_EN_WR | VSIF_EN);
1156 regmap_clear_bits(map: hdmi->regs, TOP_INFO_RPT, VSIF_RPT_EN);
1157 break;
1158 case HDMI_INFOFRAME_TYPE_DRM:
1159 default:
1160 break;
1161 };
1162
1163 return 0;
1164}
1165
1166static int mtk_hdmi_v2_hdmi_write_infoframe(struct drm_bridge *bridge,
1167 enum hdmi_infoframe_type type,
1168 const u8 *buffer, size_t len)
1169{
1170 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(b: bridge);
1171
1172 switch (type) {
1173 case HDMI_INFOFRAME_TYPE_AUDIO:
1174 mtk_hdmi_v2_hw_write_audio_infoframe(hdmi, buffer);
1175 break;
1176 case HDMI_INFOFRAME_TYPE_AVI:
1177 mtk_hdmi_v2_hw_write_avi_infoframe(hdmi, buffer);
1178 break;
1179 case HDMI_INFOFRAME_TYPE_SPD:
1180 mtk_hdmi_v2_hw_write_spd_infoframe(hdmi, buffer);
1181 break;
1182 case HDMI_INFOFRAME_TYPE_VENDOR:
1183 mtk_hdmi_v2_hw_write_vendor_infoframe(hdmi, buffer);
1184 break;
1185 case HDMI_INFOFRAME_TYPE_DRM:
1186 default:
1187 dev_err(hdmi->dev, "Unsupported HDMI infoframe type %u\n", type);
1188 break;
1189 };
1190
1191 return 0;
1192}
1193
1194static int mtk_hdmi_v2_set_abist(struct mtk_hdmi *hdmi, bool enable)
1195{
1196 struct drm_display_mode *mode = &hdmi->mode;
1197 int abist_format = -EINVAL;
1198 bool interlaced;
1199
1200 if (!enable) {
1201 regmap_clear_bits(map: hdmi->regs, TOP_CFG00, HDMI_ABIST_ENABLE);
1202 return 0;
1203 }
1204
1205 if (!mode->hdisplay || !mode->vdisplay)
1206 return -EINVAL;
1207
1208 interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
1209
1210 switch (mode->hdisplay) {
1211 case 720:
1212 if (mode->vdisplay == 480)
1213 abist_format = 2;
1214 else if (mode->vdisplay == 576)
1215 abist_format = 11;
1216 break;
1217 case 1280:
1218 if (mode->vdisplay == 720)
1219 abist_format = 3;
1220 break;
1221 case 1440:
1222 if (mode->vdisplay == 480)
1223 abist_format = interlaced ? 5 : 9;
1224 else if (mode->vdisplay == 576)
1225 abist_format = interlaced ? 14 : 18;
1226 break;
1227 case 1920:
1228 if (mode->vdisplay == 1080)
1229 abist_format = interlaced ? 4 : 10;
1230 break;
1231 case 3840:
1232 if (mode->vdisplay == 2160)
1233 abist_format = 25;
1234 break;
1235 case 4096:
1236 if (mode->vdisplay == 2160)
1237 abist_format = 26;
1238 break;
1239 default:
1240 break;
1241 }
1242 if (abist_format < 0)
1243 return abist_format;
1244
1245 regmap_update_bits(map: hdmi->regs, TOP_CFG00, HDMI_ABIST_VIDEO_FORMAT,
1246 FIELD_PREP(HDMI_ABIST_VIDEO_FORMAT, abist_format));
1247 regmap_set_bits(map: hdmi->regs, TOP_CFG00, HDMI_ABIST_ENABLE);
1248 return 0;
1249}
1250
1251static int mtk_hdmi_v2_debug_abist_show(struct seq_file *m, void *arg)
1252{
1253 struct mtk_hdmi *hdmi = m->private;
1254 bool en;
1255 u32 val;
1256 int ret;
1257
1258 if (!hdmi)
1259 return -EINVAL;
1260
1261 ret = regmap_read(map: hdmi->regs, TOP_CFG00, val: &val);
1262 if (ret)
1263 return ret;
1264
1265 en = FIELD_GET(HDMI_ABIST_ENABLE, val);
1266
1267 seq_printf(m, fmt: "HDMI Automated Built-In Self Test: %s\n",
1268 en ? "Enabled" : "Disabled");
1269
1270 return 0;
1271}
1272
1273static ssize_t mtk_hdmi_v2_debug_abist_write(struct file *file,
1274 const char __user *ubuf,
1275 size_t len, loff_t *offp)
1276{
1277 struct seq_file *m = file->private_data;
1278 int ret;
1279 u32 en;
1280
1281 if (!m || !m->private || *offp)
1282 return -EINVAL;
1283
1284 ret = kstrtouint_from_user(s: ubuf, count: len, base: 0, res: &en);
1285 if (ret)
1286 return ret;
1287
1288 if (en < 0 || en > 1)
1289 return -EINVAL;
1290
1291 mtk_hdmi_v2_set_abist(hdmi: (struct mtk_hdmi *)m->private, enable: en);
1292 return len;
1293}
1294
1295static int mtk_hdmi_v2_debug_abist_open(struct inode *inode, struct file *file)
1296{
1297 return single_open(file, mtk_hdmi_v2_debug_abist_show, inode->i_private);
1298}
1299
1300static const struct file_operations mtk_hdmi_debug_abist_fops = {
1301 .owner = THIS_MODULE,
1302 .open = mtk_hdmi_v2_debug_abist_open,
1303 .read = seq_read,
1304 .write = mtk_hdmi_v2_debug_abist_write,
1305 .llseek = seq_lseek,
1306 .release = single_release,
1307};
1308
1309static void mtk_hdmi_v2_debugfs_init(struct drm_bridge *bridge, struct dentry *root)
1310{
1311 struct mtk_hdmi *dpi = hdmi_ctx_from_bridge(b: bridge);
1312
1313 debugfs_create_file("hdmi_abist", 0640, root, dpi, &mtk_hdmi_debug_abist_fops);
1314}
1315
1316static const struct drm_bridge_funcs mtk_v2_hdmi_bridge_funcs = {
1317 .attach = mtk_hdmi_v2_bridge_attach,
1318 .detach = mtk_hdmi_v2_bridge_detach,
1319 .mode_fixup = mtk_hdmi_bridge_mode_fixup,
1320 .mode_set = mtk_hdmi_bridge_mode_set,
1321 .atomic_pre_enable = mtk_hdmi_v2_bridge_pre_enable,
1322 .atomic_enable = mtk_hdmi_v2_bridge_enable,
1323 .atomic_disable = mtk_hdmi_v2_bridge_disable,
1324 .atomic_post_disable = mtk_hdmi_v2_bridge_post_disable,
1325 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
1326 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
1327 .atomic_reset = drm_atomic_helper_bridge_reset,
1328 .detect = mtk_hdmi_v2_bridge_detect,
1329 .edid_read = mtk_hdmi_v2_bridge_edid_read,
1330 .hpd_enable = mtk_hdmi_v2_hpd_enable,
1331 .hpd_disable = mtk_hdmi_v2_hpd_disable,
1332 .hdmi_tmds_char_rate_valid = mtk_hdmi_v2_hdmi_tmds_char_rate_valid,
1333 .hdmi_clear_infoframe = mtk_hdmi_v2_hdmi_clear_infoframe,
1334 .hdmi_write_infoframe = mtk_hdmi_v2_hdmi_write_infoframe,
1335 .debugfs_init = mtk_hdmi_v2_debugfs_init,
1336};
1337
1338/*
1339 * HDMI audio codec callbacks
1340 */
1341static int mtk_hdmi_v2_audio_hook_plugged_cb(struct device *dev, void *data,
1342 hdmi_codec_plugged_cb fn,
1343 struct device *codec_dev)
1344{
1345 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1346 bool plugged;
1347
1348 if (!hdmi)
1349 return -ENODEV;
1350
1351 mtk_hdmi_audio_set_plugged_cb(hdmi, fn, codec_dev);
1352 plugged = (hdmi->hpd == HDMI_PLUG_IN_AND_SINK_POWER_ON);
1353 mtk_hdmi_v2_handle_plugged_change(hdmi, plugged);
1354
1355 return 0;
1356}
1357
1358static int mtk_hdmi_v2_audio_hw_params(struct device *dev, void *data,
1359 struct hdmi_codec_daifmt *daifmt,
1360 struct hdmi_codec_params *params)
1361{
1362 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1363
1364 if (hdmi->audio_enable) {
1365 mtk_hdmi_audio_params(hdmi, daifmt, params);
1366 mtk_hdmi_v2_aud_output_config(hdmi, display_mode: &hdmi->mode);
1367 }
1368 return 0;
1369}
1370
1371static int mtk_hdmi_v2_audio_startup(struct device *dev, void *data)
1372{
1373 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1374
1375 mtk_hdmi_v2_hw_aud_enable(hdmi, enable: true);
1376 hdmi->audio_enable = true;
1377
1378 return 0;
1379}
1380
1381static void mtk_hdmi_v2_audio_shutdown(struct device *dev, void *data)
1382{
1383 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1384
1385 hdmi->audio_enable = false;
1386 mtk_hdmi_v2_hw_aud_enable(hdmi, enable: false);
1387}
1388
1389static int mtk_hdmi_v2_audio_mute(struct device *dev, void *data, bool enable, int dir)
1390{
1391 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1392
1393 mtk_hdmi_v2_hw_aud_mute(hdmi, enable);
1394
1395 return 0;
1396}
1397
1398static const struct hdmi_codec_ops mtk_hdmi_v2_audio_codec_ops = {
1399 .hw_params = mtk_hdmi_v2_audio_hw_params,
1400 .audio_startup = mtk_hdmi_v2_audio_startup,
1401 .audio_shutdown = mtk_hdmi_v2_audio_shutdown,
1402 .mute_stream = mtk_hdmi_v2_audio_mute,
1403 .get_eld = mtk_hdmi_audio_get_eld,
1404 .hook_plugged_cb = mtk_hdmi_v2_audio_hook_plugged_cb,
1405};
1406
1407static __maybe_unused int mtk_hdmi_v2_suspend(struct device *dev)
1408{
1409 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1410
1411 mtk_hdmi_v2_disable(hdmi);
1412
1413 return 0;
1414}
1415
1416static __maybe_unused int mtk_hdmi_v2_resume(struct device *dev)
1417{
1418 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1419
1420 return mtk_hdmi_v2_enable(hdmi);
1421}
1422
1423static SIMPLE_DEV_PM_OPS(mtk_hdmi_v2_pm_ops, mtk_hdmi_v2_suspend, mtk_hdmi_v2_resume);
1424
1425static const struct mtk_hdmi_ver_conf mtk_hdmi_conf_v2 = {
1426 .bridge_funcs = &mtk_v2_hdmi_bridge_funcs,
1427 .codec_ops = &mtk_hdmi_v2_audio_codec_ops,
1428 .mtk_hdmi_clock_names = mtk_hdmi_v2_clk_names,
1429 .num_clocks = MTK_HDMI_V2_CLK_COUNT,
1430 .interlace_allowed = true,
1431};
1432
1433static const struct mtk_hdmi_conf mtk_hdmi_conf_mt8188 = {
1434 .ver_conf = &mtk_hdmi_conf_v2,
1435 .reg_hdmi_tx_cfg = HDMITX_CONFIG_MT8188
1436};
1437
1438static const struct mtk_hdmi_conf mtk_hdmi_conf_mt8195 = {
1439 .ver_conf = &mtk_hdmi_conf_v2,
1440 .reg_hdmi_tx_cfg = HDMITX_CONFIG_MT8195
1441};
1442
1443static int mtk_hdmi_v2_probe(struct platform_device *pdev)
1444{
1445 struct mtk_hdmi *hdmi;
1446 int ret;
1447
1448 /* Populate HDMI sub-devices if present */
1449 ret = devm_of_platform_populate(dev: &pdev->dev);
1450 if (ret)
1451 return ret;
1452
1453 hdmi = mtk_hdmi_common_probe(pdev);
1454 if (IS_ERR(ptr: hdmi))
1455 return PTR_ERR(ptr: hdmi);
1456
1457 hdmi->hpd = HDMI_PLUG_OUT;
1458
1459 /* Disable all HW interrupts at probe stage */
1460 mtk_hdmi_v2_hwirq_disable(hdmi);
1461
1462 /*
1463 * In case bootloader leaves HDMI enabled before booting, make
1464 * sure that any interrupt that was left is cleared by setting
1465 * all bits in the INT_CLR registers for all 32+19 interrupts.
1466 */
1467 regmap_write(map: hdmi->regs, TOP_INT_CLR00, GENMASK(31, 0));
1468 regmap_write(map: hdmi->regs, TOP_INT_CLR01, GENMASK(18, 0));
1469
1470 /* Restore interrupt clearing registers to zero */
1471 regmap_write(map: hdmi->regs, TOP_INT_CLR00, val: 0);
1472 regmap_write(map: hdmi->regs, TOP_INT_CLR01, val: 0);
1473
1474 /*
1475 * Install the ISR but keep it disabled: as the interrupts are
1476 * being set up in the .bridge_attach() callback which will
1477 * enable both the right HW IRQs and the ISR.
1478 */
1479 irq_set_status_flags(irq: hdmi->irq, set: IRQ_NOAUTOEN);
1480 ret = devm_request_threaded_irq(dev: &pdev->dev, irq: hdmi->irq, handler: mtk_hdmi_v2_isr,
1481 thread_fn: mtk_hdmi_v2_isr_thread,
1482 irqflags: IRQ_TYPE_LEVEL_HIGH,
1483 devname: dev_name(dev: &pdev->dev), dev_id: hdmi);
1484 if (ret)
1485 return dev_err_probe(dev: &pdev->dev, err: ret, fmt: "Cannot request IRQ\n");
1486
1487 ret = devm_pm_runtime_enable(dev: &pdev->dev);
1488 if (ret)
1489 return dev_err_probe(dev: &pdev->dev, err: ret, fmt: "Cannot enable Runtime PM\n");
1490
1491 return 0;
1492}
1493
1494static void mtk_hdmi_v2_remove(struct platform_device *pdev)
1495{
1496 struct mtk_hdmi *hdmi = platform_get_drvdata(pdev);
1497
1498 i2c_put_adapter(adap: hdmi->ddc_adpt);
1499}
1500
1501static const struct of_device_id mtk_drm_hdmi_v2_of_ids[] = {
1502 { .compatible = "mediatek,mt8188-hdmi-tx", .data = &mtk_hdmi_conf_mt8188 },
1503 { .compatible = "mediatek,mt8195-hdmi-tx", .data = &mtk_hdmi_conf_mt8195 },
1504 { /* sentinel */ }
1505};
1506MODULE_DEVICE_TABLE(of, mtk_drm_hdmi_v2_of_ids);
1507
1508static struct platform_driver mtk_hdmi_v2_driver = {
1509 .probe = mtk_hdmi_v2_probe,
1510 .remove = mtk_hdmi_v2_remove,
1511 .driver = {
1512 .name = "mediatek-drm-hdmi-v2",
1513 .of_match_table = mtk_drm_hdmi_v2_of_ids,
1514 .pm = &mtk_hdmi_v2_pm_ops,
1515 },
1516};
1517module_platform_driver(mtk_hdmi_v2_driver);
1518
1519MODULE_AUTHOR("AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>>");
1520MODULE_DESCRIPTION("MediaTek HDMIv2 Driver");
1521MODULE_LICENSE("GPL");
1522MODULE_IMPORT_NS("DRM_MTK_HDMI");
1523

source code of linux/drivers/gpu/drm/mediatek/mtk_hdmi_v2.c