1/*
2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Ke Yu
25 * Zhiyuan Lv <zhiyuan.lv@intel.com>
26 *
27 * Contributors:
28 * Terrence Xu <terrence.xu@intel.com>
29 * Changbin Du <changbin.du@intel.com>
30 * Bing Niu <bing.niu@intel.com>
31 * Zhi Wang <zhi.a.wang@intel.com>
32 *
33 */
34
35#include <drm/display/drm_dp.h>
36#include <drm/drm_print.h>
37
38#include "display/intel_dp_aux_regs.h"
39#include "display/intel_gmbus.h"
40#include "display/intel_gmbus_regs.h"
41#include "gvt.h"
42#include "i915_drv.h"
43#include "i915_reg.h"
44
45#define GMBUS1_TOTAL_BYTES_SHIFT 16
46#define GMBUS1_TOTAL_BYTES_MASK 0x1ff
47#define gmbus1_total_byte_count(v) (((v) >> \
48 GMBUS1_TOTAL_BYTES_SHIFT) & GMBUS1_TOTAL_BYTES_MASK)
49#define gmbus1_target_addr(v) (((v) & 0xff) >> 1)
50#define gmbus1_target_index(v) (((v) >> 8) & 0xff)
51#define gmbus1_bus_cycle(v) (((v) >> 25) & 0x7)
52
53/* GMBUS0 bits definitions */
54#define _GMBUS_PIN_SEL_MASK (0x7)
55
56static unsigned char edid_get_byte(struct intel_vgpu *vgpu)
57{
58 struct intel_vgpu_i2c_edid *edid = &vgpu->display.i2c_edid;
59 unsigned char chr = 0;
60
61 if (edid->state == I2C_NOT_SPECIFIED || !edid->target_selected) {
62 gvt_vgpu_err("Driver tries to read EDID without proper sequence!\n");
63 return 0;
64 }
65 if (edid->current_edid_read >= EDID_SIZE) {
66 gvt_vgpu_err("edid_get_byte() exceeds the size of EDID!\n");
67 return 0;
68 }
69
70 if (!edid->edid_available) {
71 gvt_vgpu_err("Reading EDID but EDID is not available!\n");
72 return 0;
73 }
74
75 if (intel_vgpu_has_monitor_on_port(vgpu, edid->port)) {
76 struct intel_vgpu_edid_data *edid_data =
77 intel_vgpu_port(vgpu, edid->port)->edid;
78
79 chr = edid_data->edid_block[edid->current_edid_read];
80 edid->current_edid_read++;
81 } else {
82 gvt_vgpu_err("No EDID available during the reading?\n");
83 }
84 return chr;
85}
86
87static inline int cnp_get_port_from_gmbus0(u32 gmbus0)
88{
89 int port_select = gmbus0 & _GMBUS_PIN_SEL_MASK;
90 int port = -EINVAL;
91
92 if (port_select == GMBUS_PIN_1_BXT)
93 port = PORT_B;
94 else if (port_select == GMBUS_PIN_2_BXT)
95 port = PORT_C;
96 else if (port_select == GMBUS_PIN_3_BXT)
97 port = PORT_D;
98 else if (port_select == GMBUS_PIN_4_CNP)
99 port = PORT_E;
100 return port;
101}
102
103static inline int bxt_get_port_from_gmbus0(u32 gmbus0)
104{
105 int port_select = gmbus0 & _GMBUS_PIN_SEL_MASK;
106 int port = -EINVAL;
107
108 if (port_select == GMBUS_PIN_1_BXT)
109 port = PORT_B;
110 else if (port_select == GMBUS_PIN_2_BXT)
111 port = PORT_C;
112 else if (port_select == GMBUS_PIN_3_BXT)
113 port = PORT_D;
114 return port;
115}
116
117static inline int get_port_from_gmbus0(u32 gmbus0)
118{
119 int port_select = gmbus0 & _GMBUS_PIN_SEL_MASK;
120 int port = -EINVAL;
121
122 if (port_select == GMBUS_PIN_VGADDC)
123 port = PORT_E;
124 else if (port_select == GMBUS_PIN_DPC)
125 port = PORT_C;
126 else if (port_select == GMBUS_PIN_DPB)
127 port = PORT_B;
128 else if (port_select == GMBUS_PIN_DPD)
129 port = PORT_D;
130 return port;
131}
132
133static void reset_gmbus_controller(struct intel_vgpu *vgpu)
134{
135 vgpu_vreg_t(vgpu, PCH_GMBUS2) = GMBUS_HW_RDY;
136 if (!vgpu->display.i2c_edid.edid_available)
137 vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_SATOER;
138 vgpu->display.i2c_edid.gmbus.phase = GMBUS_IDLE_PHASE;
139}
140
141/* GMBUS0 */
142static int gmbus0_mmio_write(struct intel_vgpu *vgpu,
143 unsigned int offset, void *p_data, unsigned int bytes)
144{
145 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
146 int port, pin_select;
147
148 memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes);
149
150 pin_select = vgpu_vreg(vgpu, offset) & _GMBUS_PIN_SEL_MASK;
151
152 intel_vgpu_init_i2c_edid(vgpu);
153
154 if (pin_select == 0)
155 return 0;
156
157 if (IS_BROXTON(i915))
158 port = bxt_get_port_from_gmbus0(gmbus0: pin_select);
159 else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915))
160 port = cnp_get_port_from_gmbus0(gmbus0: pin_select);
161 else
162 port = get_port_from_gmbus0(gmbus0: pin_select);
163 if (drm_WARN_ON(&i915->drm, port < 0))
164 return 0;
165
166 vgpu->display.i2c_edid.state = I2C_GMBUS;
167 vgpu->display.i2c_edid.gmbus.phase = GMBUS_IDLE_PHASE;
168
169 vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_ACTIVE;
170 vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_HW_RDY | GMBUS_HW_WAIT_PHASE;
171
172 if (intel_vgpu_has_monitor_on_port(vgpu, port) &&
173 !intel_vgpu_port_is_dp(vgpu, port)) {
174 vgpu->display.i2c_edid.port = port;
175 vgpu->display.i2c_edid.edid_available = true;
176 vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_SATOER;
177 } else
178 vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_SATOER;
179 return 0;
180}
181
182static int gmbus1_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
183 void *p_data, unsigned int bytes)
184{
185 struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid;
186 u32 target_addr;
187 u32 wvalue = *(u32 *)p_data;
188
189 if (vgpu_vreg(vgpu, offset) & GMBUS_SW_CLR_INT) {
190 if (!(wvalue & GMBUS_SW_CLR_INT)) {
191 vgpu_vreg(vgpu, offset) &= ~GMBUS_SW_CLR_INT;
192 reset_gmbus_controller(vgpu);
193 }
194 /*
195 * TODO: "This bit is cleared to zero when an event
196 * causes the HW_RDY bit transition to occur "
197 */
198 } else {
199 /*
200 * per bspec setting this bit can cause:
201 * 1) INT status bit cleared
202 * 2) HW_RDY bit asserted
203 */
204 if (wvalue & GMBUS_SW_CLR_INT) {
205 vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_INT;
206 vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_HW_RDY;
207 }
208
209 /* For virtualization, we suppose that HW is always ready,
210 * so GMBUS_SW_RDY should always be cleared
211 */
212 if (wvalue & GMBUS_SW_RDY)
213 wvalue &= ~GMBUS_SW_RDY;
214
215 i2c_edid->gmbus.total_byte_count =
216 gmbus1_total_byte_count(wvalue);
217 target_addr = gmbus1_target_addr(wvalue);
218
219 /* vgpu gmbus only support EDID */
220 if (target_addr == EDID_ADDR) {
221 i2c_edid->target_selected = true;
222 } else if (target_addr != 0) {
223 gvt_dbg_dpy(
224 "vgpu%d: unsupported gmbus target addr(0x%x)\n"
225 " gmbus operations will be ignored.\n",
226 vgpu->id, target_addr);
227 }
228
229 if (wvalue & GMBUS_CYCLE_INDEX)
230 i2c_edid->current_edid_read =
231 gmbus1_target_index(wvalue);
232
233 i2c_edid->gmbus.cycle_type = gmbus1_bus_cycle(wvalue);
234 switch (gmbus1_bus_cycle(wvalue)) {
235 case GMBUS_NOCYCLE:
236 break;
237 case GMBUS_STOP:
238 /* From spec:
239 * This can only cause a STOP to be generated
240 * if a GMBUS cycle is generated, the GMBUS is
241 * currently in a data/wait/idle phase, or it is in a
242 * WAIT phase
243 */
244 if (gmbus1_bus_cycle(vgpu_vreg(vgpu, offset))
245 != GMBUS_NOCYCLE) {
246 intel_vgpu_init_i2c_edid(vgpu);
247 /* After the 'stop' cycle, hw state would become
248 * 'stop phase' and then 'idle phase' after a
249 * few milliseconds. In emulation, we just set
250 * it as 'idle phase' ('stop phase' is not
251 * visible in gmbus interface)
252 */
253 i2c_edid->gmbus.phase = GMBUS_IDLE_PHASE;
254 vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_ACTIVE;
255 }
256 break;
257 case NIDX_NS_W:
258 case IDX_NS_W:
259 case NIDX_STOP:
260 case IDX_STOP:
261 /* From hw spec the GMBUS phase
262 * transition like this:
263 * START (-->INDEX) -->DATA
264 */
265 i2c_edid->gmbus.phase = GMBUS_DATA_PHASE;
266 vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_ACTIVE;
267 break;
268 default:
269 gvt_vgpu_err("Unknown/reserved GMBUS cycle detected!\n");
270 break;
271 }
272 /*
273 * From hw spec the WAIT state will be
274 * cleared:
275 * (1) in a new GMBUS cycle
276 * (2) by generating a stop
277 */
278 vgpu_vreg(vgpu, offset) = wvalue;
279 }
280 return 0;
281}
282
283static int gmbus3_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
284 void *p_data, unsigned int bytes)
285{
286 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
287
288 drm_WARN_ON(&i915->drm, 1);
289 return 0;
290}
291
292static int gmbus3_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
293 void *p_data, unsigned int bytes)
294{
295 int i;
296 unsigned char byte_data;
297 struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid;
298 int byte_left = i2c_edid->gmbus.total_byte_count -
299 i2c_edid->current_edid_read;
300 int byte_count = byte_left;
301 u32 reg_data = 0;
302
303 /* Data can only be received if previous settings correct */
304 if (vgpu_vreg_t(vgpu, PCH_GMBUS1) & GMBUS_SLAVE_READ) {
305 if (byte_left <= 0) {
306 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
307 return 0;
308 }
309
310 if (byte_count > 4)
311 byte_count = 4;
312 for (i = 0; i < byte_count; i++) {
313 byte_data = edid_get_byte(vgpu);
314 reg_data |= (byte_data << (i << 3));
315 }
316
317 memcpy(&vgpu_vreg(vgpu, offset), &reg_data, byte_count);
318 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
319
320 if (byte_left <= 4) {
321 switch (i2c_edid->gmbus.cycle_type) {
322 case NIDX_STOP:
323 case IDX_STOP:
324 i2c_edid->gmbus.phase = GMBUS_IDLE_PHASE;
325 break;
326 case NIDX_NS_W:
327 case IDX_NS_W:
328 default:
329 i2c_edid->gmbus.phase = GMBUS_WAIT_PHASE;
330 break;
331 }
332 intel_vgpu_init_i2c_edid(vgpu);
333 }
334 /*
335 * Read GMBUS3 during send operation,
336 * return the latest written value
337 */
338 } else {
339 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
340 gvt_vgpu_err("warning: gmbus3 read with nothing returned\n");
341 }
342 return 0;
343}
344
345static int gmbus2_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
346 void *p_data, unsigned int bytes)
347{
348 u32 value = vgpu_vreg(vgpu, offset);
349
350 if (!(vgpu_vreg(vgpu, offset) & GMBUS_INUSE))
351 vgpu_vreg(vgpu, offset) |= GMBUS_INUSE;
352 memcpy(p_data, (void *)&value, bytes);
353 return 0;
354}
355
356static int gmbus2_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
357 void *p_data, unsigned int bytes)
358{
359 u32 wvalue = *(u32 *)p_data;
360
361 if (wvalue & GMBUS_INUSE)
362 vgpu_vreg(vgpu, offset) &= ~GMBUS_INUSE;
363 /* All other bits are read-only */
364 return 0;
365}
366
367/**
368 * intel_gvt_i2c_handle_gmbus_read - emulate gmbus register mmio read
369 * @vgpu: a vGPU
370 * @offset: reg offset
371 * @p_data: data return buffer
372 * @bytes: access data length
373 *
374 * This function is used to emulate gmbus register mmio read
375 *
376 * Returns:
377 * Zero on success, negative error code if failed.
378 *
379 */
380int intel_gvt_i2c_handle_gmbus_read(struct intel_vgpu *vgpu,
381 unsigned int offset, void *p_data, unsigned int bytes)
382{
383 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
384
385 if (drm_WARN_ON(&i915->drm, bytes > 8 && (offset & (bytes - 1))))
386 return -EINVAL;
387
388 if (offset == i915_mmio_reg_offset(PCH_GMBUS2))
389 return gmbus2_mmio_read(vgpu, offset, p_data, bytes);
390 else if (offset == i915_mmio_reg_offset(PCH_GMBUS3))
391 return gmbus3_mmio_read(vgpu, offset, p_data, bytes);
392
393 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
394 return 0;
395}
396
397/**
398 * intel_gvt_i2c_handle_gmbus_write - emulate gmbus register mmio write
399 * @vgpu: a vGPU
400 * @offset: reg offset
401 * @p_data: data return buffer
402 * @bytes: access data length
403 *
404 * This function is used to emulate gmbus register mmio write
405 *
406 * Returns:
407 * Zero on success, negative error code if failed.
408 *
409 */
410int intel_gvt_i2c_handle_gmbus_write(struct intel_vgpu *vgpu,
411 unsigned int offset, void *p_data, unsigned int bytes)
412{
413 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
414
415 if (drm_WARN_ON(&i915->drm, bytes > 8 && (offset & (bytes - 1))))
416 return -EINVAL;
417
418 if (offset == i915_mmio_reg_offset(PCH_GMBUS0))
419 return gmbus0_mmio_write(vgpu, offset, p_data, bytes);
420 else if (offset == i915_mmio_reg_offset(PCH_GMBUS1))
421 return gmbus1_mmio_write(vgpu, offset, p_data, bytes);
422 else if (offset == i915_mmio_reg_offset(PCH_GMBUS2))
423 return gmbus2_mmio_write(vgpu, offset, p_data, bytes);
424 else if (offset == i915_mmio_reg_offset(PCH_GMBUS3))
425 return gmbus3_mmio_write(vgpu, offset, p_data, bytes);
426
427 memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes);
428 return 0;
429}
430
431enum {
432 AUX_CH_CTL = 0,
433 AUX_CH_DATA1,
434 AUX_CH_DATA2,
435 AUX_CH_DATA3,
436 AUX_CH_DATA4,
437 AUX_CH_DATA5
438};
439
440static inline int get_aux_ch_reg(unsigned int offset)
441{
442 int reg;
443
444 switch (offset & 0xff) {
445 case 0x10:
446 reg = AUX_CH_CTL;
447 break;
448 case 0x14:
449 reg = AUX_CH_DATA1;
450 break;
451 case 0x18:
452 reg = AUX_CH_DATA2;
453 break;
454 case 0x1c:
455 reg = AUX_CH_DATA3;
456 break;
457 case 0x20:
458 reg = AUX_CH_DATA4;
459 break;
460 case 0x24:
461 reg = AUX_CH_DATA5;
462 break;
463 default:
464 reg = -1;
465 break;
466 }
467 return reg;
468}
469
470/**
471 * intel_gvt_i2c_handle_aux_ch_write - emulate AUX channel register write
472 * @vgpu: a vGPU
473 * @port_idx: port index
474 * @offset: reg offset
475 * @p_data: write ptr
476 *
477 * This function is used to emulate AUX channel register write
478 *
479 */
480void intel_gvt_i2c_handle_aux_ch_write(struct intel_vgpu *vgpu,
481 int port_idx,
482 unsigned int offset,
483 void *p_data)
484{
485 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
486 struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid;
487 int msg_length, ret_msg_size;
488 int msg, addr, ctrl, op;
489 u32 value = *(u32 *)p_data;
490 int aux_data_for_write = 0;
491 int reg = get_aux_ch_reg(offset);
492
493 if (reg != AUX_CH_CTL) {
494 vgpu_vreg(vgpu, offset) = value;
495 return;
496 }
497
498 msg_length = REG_FIELD_GET(DP_AUX_CH_CTL_MESSAGE_SIZE_MASK, value);
499
500 // check the msg in DATA register.
501 msg = vgpu_vreg(vgpu, offset + 4);
502 addr = (msg >> 8) & 0xffff;
503 ctrl = (msg >> 24) & 0xff;
504 op = ctrl >> 4;
505 if (!(value & DP_AUX_CH_CTL_SEND_BUSY)) {
506 /* The ctl write to clear some states */
507 return;
508 }
509
510 /* Always set the wanted value for vms. */
511 ret_msg_size = (((op & 0x1) == DP_AUX_I2C_READ) ? 2 : 1);
512 vgpu_vreg(vgpu, offset) =
513 DP_AUX_CH_CTL_DONE |
514 DP_AUX_CH_CTL_MESSAGE_SIZE(ret_msg_size);
515
516 if (msg_length == 3) {
517 if (!(op & DP_AUX_I2C_MOT)) {
518 /* stop */
519 intel_vgpu_init_i2c_edid(vgpu);
520 } else {
521 /* start or restart */
522 i2c_edid->aux_ch.i2c_over_aux_ch = true;
523 i2c_edid->aux_ch.aux_ch_mot = true;
524 if (addr == 0) {
525 /* reset the address */
526 intel_vgpu_init_i2c_edid(vgpu);
527 } else if (addr == EDID_ADDR) {
528 i2c_edid->state = I2C_AUX_CH;
529 i2c_edid->port = port_idx;
530 i2c_edid->target_selected = true;
531 if (intel_vgpu_has_monitor_on_port(vgpu,
532 port_idx) &&
533 intel_vgpu_port_is_dp(vgpu, port_idx))
534 i2c_edid->edid_available = true;
535 }
536 }
537 } else if ((op & 0x1) == DP_AUX_I2C_WRITE) {
538 /* TODO
539 * We only support EDID reading from I2C_over_AUX. And
540 * we do not expect the index mode to be used. Right now
541 * the WRITE operation is ignored. It is good enough to
542 * support the gfx driver to do EDID access.
543 */
544 } else {
545 if (drm_WARN_ON(&i915->drm, (op & 0x1) != DP_AUX_I2C_READ))
546 return;
547 if (drm_WARN_ON(&i915->drm, msg_length != 4))
548 return;
549 if (i2c_edid->edid_available && i2c_edid->target_selected) {
550 unsigned char val = edid_get_byte(vgpu);
551
552 aux_data_for_write = (val << 16);
553 } else
554 aux_data_for_write = (0xff << 16);
555 }
556 /* write the return value in AUX_CH_DATA reg which includes:
557 * ACK of I2C_WRITE
558 * returned byte if it is READ
559 */
560 aux_data_for_write |= DP_AUX_I2C_REPLY_ACK << 24;
561 vgpu_vreg(vgpu, offset + 4) = aux_data_for_write;
562}
563
564/**
565 * intel_vgpu_init_i2c_edid - initialize vGPU i2c edid emulation
566 * @vgpu: a vGPU
567 *
568 * This function is used to initialize vGPU i2c edid emulation stuffs
569 *
570 */
571void intel_vgpu_init_i2c_edid(struct intel_vgpu *vgpu)
572{
573 struct intel_vgpu_i2c_edid *edid = &vgpu->display.i2c_edid;
574
575 edid->state = I2C_NOT_SPECIFIED;
576
577 edid->port = -1;
578 edid->target_selected = false;
579 edid->edid_available = false;
580 edid->current_edid_read = 0;
581
582 memset(&edid->gmbus, 0, sizeof(struct intel_vgpu_i2c_gmbus));
583
584 edid->aux_ch.i2c_over_aux_ch = false;
585 edid->aux_ch.aux_ch_mot = false;
586}
587

source code of linux/drivers/gpu/drm/i915/gvt/edid.c