1/*
2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Ke Yu
25 * Zhiyuan Lv <zhiyuan.lv@intel.com>
26 *
27 * Contributors:
28 * Terrence Xu <terrence.xu@intel.com>
29 * Changbin Du <changbin.du@intel.com>
30 * Bing Niu <bing.niu@intel.com>
31 * Zhi Wang <zhi.a.wang@intel.com>
32 *
33 */
34
35#ifndef _GVT_EDID_H_
36#define _GVT_EDID_H_
37
38#include <linux/types.h>
39
40struct intel_vgpu;
41
42#define EDID_SIZE 128
43#define EDID_ADDR 0x50 /* Linux hvm EDID addr */
44
45struct intel_vgpu_edid_data {
46 bool data_valid;
47 unsigned char edid_block[EDID_SIZE];
48};
49
50enum gmbus_cycle_type {
51 GMBUS_NOCYCLE = 0x0,
52 NIDX_NS_W = 0x1,
53 IDX_NS_W = 0x3,
54 GMBUS_STOP = 0x4,
55 NIDX_STOP = 0x5,
56 IDX_STOP = 0x7
57};
58
59/*
60 * States of GMBUS
61 *
62 * GMBUS0-3 could be related to the EDID virtualization. Another two GMBUS
63 * registers, GMBUS4 (interrupt mask) and GMBUS5 (2 byte indes register), are
64 * not considered here. Below describes the usage of GMBUS registers that are
65 * cared by the EDID virtualization
66 *
67 * GMBUS0:
68 * R/W
69 * port selection. value of bit0 - bit2 corresponds to the GPIO registers.
70 *
71 * GMBUS1:
72 * R/W Protect
73 * Command and Status.
74 * bit0 is the direction bit: 1 is read; 0 is write.
75 * bit1 - bit7 is target 7-bit address.
76 * bit16 - bit24 total byte count (ignore?)
77 *
78 * GMBUS2:
79 * Most of bits are read only except bit 15 (IN_USE)
80 * Status register
81 * bit0 - bit8 current byte count
82 * bit 11: hardware ready;
83 *
84 * GMBUS3:
85 * Read/Write
86 * Data for transfer
87 */
88
89/* From hw specs, Other phases like START, ADDRESS, INDEX
90 * are invisible to GMBUS MMIO interface. So no definitions
91 * in below enum types
92 */
93enum gvt_gmbus_phase {
94 GMBUS_IDLE_PHASE = 0,
95 GMBUS_DATA_PHASE,
96 GMBUS_WAIT_PHASE,
97 //GMBUS_STOP_PHASE,
98 GMBUS_MAX_PHASE
99};
100
101struct intel_vgpu_i2c_gmbus {
102 unsigned int total_byte_count; /* from GMBUS1 */
103 enum gmbus_cycle_type cycle_type;
104 enum gvt_gmbus_phase phase;
105};
106
107struct intel_vgpu_i2c_aux_ch {
108 bool i2c_over_aux_ch;
109 bool aux_ch_mot;
110};
111
112enum i2c_state {
113 I2C_NOT_SPECIFIED = 0,
114 I2C_GMBUS = 1,
115 I2C_AUX_CH = 2
116};
117
118/* I2C sequences cannot interleave.
119 * GMBUS and AUX_CH sequences cannot interleave.
120 */
121struct intel_vgpu_i2c_edid {
122 enum i2c_state state;
123
124 unsigned int port;
125 bool target_selected;
126 bool edid_available;
127 unsigned int current_edid_read;
128
129 struct intel_vgpu_i2c_gmbus gmbus;
130 struct intel_vgpu_i2c_aux_ch aux_ch;
131};
132
133void intel_vgpu_init_i2c_edid(struct intel_vgpu *vgpu);
134
135int intel_gvt_i2c_handle_gmbus_read(struct intel_vgpu *vgpu,
136 unsigned int offset, void *p_data, unsigned int bytes);
137
138int intel_gvt_i2c_handle_gmbus_write(struct intel_vgpu *vgpu,
139 unsigned int offset, void *p_data, unsigned int bytes);
140
141void intel_gvt_i2c_handle_aux_ch_write(struct intel_vgpu *vgpu,
142 int port_idx,
143 unsigned int offset,
144 void *p_data);
145
146#endif /*_GVT_EDID_H_*/
147

source code of linux/drivers/gpu/drm/i915/gvt/edid.h