1/*
2 * Copyright © 2006-2007 Intel Corporation
3 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 * Dave Airlie <airlied@linux.ie>
27 * Jesse Barnes <jesse.barnes@intel.com>
28 */
29
30#include <acpi/button.h>
31#include <linux/acpi.h>
32#include <linux/dmi.h>
33#include <linux/i2c.h>
34#include <linux/slab.h>
35#include <linux/vga_switcheroo.h>
36
37#include <drm/drm_atomic_helper.h>
38#include <drm/drm_crtc.h>
39#include <drm/drm_edid.h>
40#include <drm/drm_print.h>
41#include <drm/drm_probe_helper.h>
42
43#include "intel_atomic.h"
44#include "intel_backlight.h"
45#include "intel_connector.h"
46#include "intel_de.h"
47#include "intel_display_types.h"
48#include "intel_dpll.h"
49#include "intel_fdi.h"
50#include "intel_gmbus.h"
51#include "intel_link_bw.h"
52#include "intel_lvds.h"
53#include "intel_lvds_regs.h"
54#include "intel_panel.h"
55#include "intel_pfit.h"
56#include "intel_pfit_regs.h"
57#include "intel_pps_regs.h"
58
59/* Private structure for the integrated LVDS support */
60struct intel_lvds_pps {
61 struct intel_pps_delays delays;
62
63 int divider;
64
65 int port;
66 bool powerdown_on_reset;
67};
68
69struct intel_lvds_encoder {
70 struct intel_encoder base;
71
72 bool is_dual_link;
73 i915_reg_t reg;
74 u32 a3_power;
75
76 struct intel_lvds_pps init_pps;
77 u32 init_lvds_val;
78
79 struct intel_connector *attached_connector;
80};
81
82static struct intel_lvds_encoder *to_lvds_encoder(struct intel_encoder *encoder)
83{
84 return container_of(encoder, struct intel_lvds_encoder, base);
85}
86
87bool intel_lvds_port_enabled(struct intel_display *display,
88 i915_reg_t lvds_reg, enum pipe *pipe)
89{
90 u32 val;
91
92 val = intel_de_read(display, reg: lvds_reg);
93
94 /* asserts want to know the pipe even if the port is disabled */
95 if (HAS_PCH_CPT(display))
96 *pipe = REG_FIELD_GET(LVDS_PIPE_SEL_MASK_CPT, val);
97 else
98 *pipe = REG_FIELD_GET(LVDS_PIPE_SEL_MASK, val);
99
100 return val & LVDS_PORT_EN;
101}
102
103static bool intel_lvds_get_hw_state(struct intel_encoder *encoder,
104 enum pipe *pipe)
105{
106 struct intel_display *display = to_intel_display(encoder);
107 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder);
108 intel_wakeref_t wakeref;
109 bool ret;
110
111 wakeref = intel_display_power_get_if_enabled(display, domain: encoder->power_domain);
112 if (!wakeref)
113 return false;
114
115 ret = intel_lvds_port_enabled(display, lvds_reg: lvds_encoder->reg, pipe);
116
117 intel_display_power_put(display, domain: encoder->power_domain, wakeref);
118
119 return ret;
120}
121
122static void intel_lvds_get_config(struct intel_encoder *encoder,
123 struct intel_crtc_state *crtc_state)
124{
125 struct intel_display *display = to_intel_display(encoder);
126 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder);
127 u32 tmp, flags = 0;
128
129 crtc_state->output_types |= BIT(INTEL_OUTPUT_LVDS);
130
131 tmp = intel_de_read(display, reg: lvds_encoder->reg);
132 if (tmp & LVDS_HSYNC_POLARITY)
133 flags |= DRM_MODE_FLAG_NHSYNC;
134 else
135 flags |= DRM_MODE_FLAG_PHSYNC;
136 if (tmp & LVDS_VSYNC_POLARITY)
137 flags |= DRM_MODE_FLAG_NVSYNC;
138 else
139 flags |= DRM_MODE_FLAG_PVSYNC;
140
141 crtc_state->hw.adjusted_mode.flags |= flags;
142
143 if (DISPLAY_VER(display) < 5)
144 crtc_state->gmch_pfit.lvds_border_bits =
145 tmp & LVDS_BORDER_ENABLE;
146
147 /* gen2/3 store dither state in pfit control, needs to match */
148 if (DISPLAY_VER(display) < 4) {
149 tmp = intel_de_read(display, PFIT_CONTROL(display));
150
151 crtc_state->gmch_pfit.control |= tmp & PFIT_PANEL_8TO6_DITHER_ENABLE;
152 }
153
154 crtc_state->hw.adjusted_mode.crtc_clock = crtc_state->port_clock;
155}
156
157static void intel_lvds_pps_get_hw_state(struct intel_display *display,
158 struct intel_lvds_pps *pps)
159{
160 u32 val;
161
162 pps->powerdown_on_reset = intel_de_read(display,
163 PP_CONTROL(display, 0)) & PANEL_POWER_RESET;
164
165 val = intel_de_read(display, PP_ON_DELAYS(display, 0));
166 pps->port = REG_FIELD_GET(PANEL_PORT_SELECT_MASK, val);
167 pps->delays.power_up = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, val);
168 pps->delays.backlight_on = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, val);
169
170 val = intel_de_read(display, PP_OFF_DELAYS(display, 0));
171 pps->delays.power_down = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, val);
172 pps->delays.backlight_off = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, val);
173
174 val = intel_de_read(display, PP_DIVISOR(display, 0));
175 pps->divider = REG_FIELD_GET(PP_REFERENCE_DIVIDER_MASK, val);
176 val = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, val);
177 /*
178 * Remove the BSpec specified +1 (100ms) offset that accounts for a
179 * too short power-cycle delay due to the asynchronous programming of
180 * the register.
181 */
182 if (val)
183 val--;
184 /* Convert from 100ms to 100us units */
185 pps->delays.power_cycle = val * 1000;
186
187 if (DISPLAY_VER(display) < 5 &&
188 pps->delays.power_up == 0 &&
189 pps->delays.backlight_on == 0 &&
190 pps->delays.power_down == 0 &&
191 pps->delays.backlight_off == 0) {
192 drm_dbg_kms(display->drm,
193 "Panel power timings uninitialized, "
194 "setting defaults\n");
195 /* Set T2 to 40ms and T5 to 200ms in 100 usec units */
196 pps->delays.power_up = 40 * 10;
197 pps->delays.backlight_on = 200 * 10;
198 /* Set T3 to 35ms and Tx to 200ms in 100 usec units */
199 pps->delays.power_down = 35 * 10;
200 pps->delays.backlight_off = 200 * 10;
201 }
202
203 drm_dbg(display->drm, "LVDS PPS:power_up %d power_down %d power_cycle %d backlight_on %d backlight_off %d "
204 "divider %d port %d powerdown_on_reset %d\n",
205 pps->delays.power_up, pps->delays.power_down,
206 pps->delays.power_cycle, pps->delays.backlight_on,
207 pps->delays.backlight_off, pps->divider,
208 pps->port, pps->powerdown_on_reset);
209}
210
211static void intel_lvds_pps_init_hw(struct intel_display *display,
212 struct intel_lvds_pps *pps)
213{
214 u32 val;
215
216 val = intel_de_read(display, PP_CONTROL(display, 0));
217 drm_WARN_ON(display->drm,
218 (val & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS);
219 if (pps->powerdown_on_reset)
220 val |= PANEL_POWER_RESET;
221 intel_de_write(display, PP_CONTROL(display, 0), val);
222
223 intel_de_write(display, PP_ON_DELAYS(display, 0),
224 REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, pps->port) |
225 REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, pps->delays.power_up) |
226 REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, pps->delays.backlight_on));
227
228 intel_de_write(display, PP_OFF_DELAYS(display, 0),
229 REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, pps->delays.power_down) |
230 REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, pps->delays.backlight_off));
231
232 intel_de_write(display, PP_DIVISOR(display, 0),
233 REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, pps->divider) |
234 REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK,
235 DIV_ROUND_UP(pps->delays.power_cycle, 1000) + 1));
236}
237
238static void intel_pre_enable_lvds(struct intel_atomic_state *state,
239 struct intel_encoder *encoder,
240 const struct intel_crtc_state *crtc_state,
241 const struct drm_connector_state *conn_state)
242{
243 struct intel_display *display = to_intel_display(state);
244 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder);
245 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
246 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
247 enum pipe pipe = crtc->pipe;
248 u32 temp;
249
250 if (HAS_PCH_SPLIT(display)) {
251 assert_fdi_rx_pll_disabled(display, pipe);
252 assert_dpll_disabled(display, crtc_state->intel_dpll);
253 } else {
254 assert_pll_disabled(display, pipe);
255 }
256
257 intel_lvds_pps_init_hw(display, pps: &lvds_encoder->init_pps);
258
259 temp = lvds_encoder->init_lvds_val;
260 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
261
262 if (HAS_PCH_CPT(display)) {
263 temp &= ~LVDS_PIPE_SEL_MASK_CPT;
264 temp |= LVDS_PIPE_SEL_CPT(pipe);
265 } else {
266 temp &= ~LVDS_PIPE_SEL_MASK;
267 temp |= LVDS_PIPE_SEL(pipe);
268 }
269
270 /* set the corresponding LVDS_BORDER bit */
271 temp &= ~LVDS_BORDER_ENABLE;
272 temp |= crtc_state->gmch_pfit.lvds_border_bits;
273
274 /*
275 * Set the B0-B3 data pairs corresponding to whether we're going to
276 * set the DPLLs for dual-channel mode or not.
277 */
278 if (lvds_encoder->is_dual_link)
279 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
280 else
281 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
282
283 /*
284 * It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
285 * appropriately here, but we need to look more thoroughly into how
286 * panels behave in the two modes. For now, let's just maintain the
287 * value we got from the BIOS.
288 */
289 temp &= ~LVDS_A3_POWER_MASK;
290 temp |= lvds_encoder->a3_power;
291
292 /*
293 * Set the dithering flag on LVDS as needed, note that there is no
294 * special lvds dither control bit on pch-split platforms, dithering is
295 * only controlled through the TRANSCONF reg.
296 */
297 if (DISPLAY_VER(display) == 4) {
298 /*
299 * Bspec wording suggests that LVDS port dithering only exists
300 * for 18bpp panels.
301 */
302 if (crtc_state->dither && crtc_state->pipe_bpp == 18)
303 temp |= LVDS_ENABLE_DITHER;
304 else
305 temp &= ~LVDS_ENABLE_DITHER;
306 }
307 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
308 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
309 temp |= LVDS_HSYNC_POLARITY;
310 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
311 temp |= LVDS_VSYNC_POLARITY;
312
313 intel_de_write(display, reg: lvds_encoder->reg, val: temp);
314}
315
316/*
317 * Sets the power state for the panel.
318 */
319static void intel_enable_lvds(struct intel_atomic_state *state,
320 struct intel_encoder *encoder,
321 const struct intel_crtc_state *crtc_state,
322 const struct drm_connector_state *conn_state)
323{
324 struct intel_display *display = to_intel_display(encoder);
325 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder);
326
327 intel_de_rmw(display, reg: lvds_encoder->reg, clear: 0, LVDS_PORT_EN);
328
329 intel_de_rmw(display, PP_CONTROL(display, 0), clear: 0, PANEL_POWER_ON);
330 intel_de_posting_read(display, reg: lvds_encoder->reg);
331
332 if (intel_de_wait_for_set_ms(display, PP_STATUS(display, 0), PP_ON, timeout_ms: 5000))
333 drm_err(display->drm,
334 "timed out waiting for panel to power on\n");
335
336 intel_backlight_enable(crtc_state, conn_state);
337}
338
339static void intel_disable_lvds(struct intel_atomic_state *state,
340 struct intel_encoder *encoder,
341 const struct intel_crtc_state *old_crtc_state,
342 const struct drm_connector_state *old_conn_state)
343{
344 struct intel_display *display = to_intel_display(encoder);
345 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder);
346
347 intel_de_rmw(display, PP_CONTROL(display, 0), PANEL_POWER_ON, set: 0);
348 if (intel_de_wait_for_clear_ms(display, PP_STATUS(display, 0), PP_ON, timeout_ms: 1000))
349 drm_err(display->drm,
350 "timed out waiting for panel to power off\n");
351
352 intel_de_rmw(display, reg: lvds_encoder->reg, LVDS_PORT_EN, set: 0);
353 intel_de_posting_read(display, reg: lvds_encoder->reg);
354}
355
356static void gmch_disable_lvds(struct intel_atomic_state *state,
357 struct intel_encoder *encoder,
358 const struct intel_crtc_state *old_crtc_state,
359 const struct drm_connector_state *old_conn_state)
360
361{
362 intel_backlight_disable(old_conn_state);
363
364 intel_disable_lvds(state, encoder, old_crtc_state, old_conn_state);
365}
366
367static void pch_disable_lvds(struct intel_atomic_state *state,
368 struct intel_encoder *encoder,
369 const struct intel_crtc_state *old_crtc_state,
370 const struct drm_connector_state *old_conn_state)
371{
372 intel_backlight_disable(old_conn_state);
373}
374
375static void pch_post_disable_lvds(struct intel_atomic_state *state,
376 struct intel_encoder *encoder,
377 const struct intel_crtc_state *old_crtc_state,
378 const struct drm_connector_state *old_conn_state)
379{
380 intel_disable_lvds(state, encoder, old_crtc_state, old_conn_state);
381}
382
383static void intel_lvds_shutdown(struct intel_encoder *encoder)
384{
385 struct intel_display *display = to_intel_display(encoder);
386
387 if (intel_de_wait_for_clear_ms(display, PP_STATUS(display, 0), PP_CYCLE_DELAY_ACTIVE, timeout_ms: 5000))
388 drm_err(display->drm,
389 "timed out waiting for panel power cycle delay\n");
390}
391
392static enum drm_mode_status
393intel_lvds_mode_valid(struct drm_connector *_connector,
394 const struct drm_display_mode *mode)
395{
396 struct intel_display *display = to_intel_display(_connector->dev);
397 struct intel_connector *connector = to_intel_connector(_connector);
398 const struct drm_display_mode *fixed_mode =
399 intel_panel_fixed_mode(connector, mode);
400 int max_pixclk = display->cdclk.max_dotclk_freq;
401 enum drm_mode_status status;
402
403 status = intel_cpu_transcoder_mode_valid(display, mode);
404 if (status != MODE_OK)
405 return status;
406
407 status = intel_panel_mode_valid(connector, mode);
408 if (status != MODE_OK)
409 return status;
410
411 if (fixed_mode->clock > max_pixclk)
412 return MODE_CLOCK_HIGH;
413
414 return MODE_OK;
415}
416
417static int intel_lvds_compute_config(struct intel_encoder *encoder,
418 struct intel_crtc_state *crtc_state,
419 struct drm_connector_state *conn_state)
420{
421 struct intel_display *display = to_intel_display(encoder);
422 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder);
423 struct intel_connector *connector = lvds_encoder->attached_connector;
424 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
425 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
426 unsigned int lvds_bpp;
427 int ret;
428
429 /* Should never happen!! */
430 if (DISPLAY_VER(display) < 4 && crtc->pipe == 0) {
431 drm_err(display->drm, "Can't support LVDS on pipe A\n");
432 return -EINVAL;
433 }
434
435 if (HAS_PCH_SPLIT(display)) {
436 crtc_state->has_pch_encoder = true;
437 if (!intel_link_bw_compute_pipe_bpp(crtc_state))
438 return -EINVAL;
439 }
440
441 if (lvds_encoder->a3_power == LVDS_A3_POWER_UP)
442 lvds_bpp = 8*3;
443 else
444 lvds_bpp = 6*3;
445
446 /* TODO: Check crtc_state->max_link_bpp_x16 instead of bw_constrained */
447 if (lvds_bpp != crtc_state->pipe_bpp && !crtc_state->bw_constrained) {
448 drm_dbg_kms(display->drm,
449 "forcing display bpp (was %d) to LVDS (%d)\n",
450 crtc_state->pipe_bpp, lvds_bpp);
451 crtc_state->pipe_bpp = lvds_bpp;
452 }
453
454 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB;
455 crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB;
456
457 /*
458 * We have timings from the BIOS for the panel, put them in
459 * to the adjusted mode. The CRTC will be set up for this mode,
460 * with the panel scaling set up to source from the H/VDisplay
461 * of the original mode.
462 */
463 ret = intel_panel_compute_config(connector, adjusted_mode);
464 if (ret)
465 return ret;
466
467 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
468 return -EINVAL;
469
470 ret = intel_pfit_compute_config(crtc_state, conn_state);
471 if (ret)
472 return ret;
473
474 /*
475 * XXX: It would be nice to support lower refresh rates on the
476 * panels to reduce power consumption, and perhaps match the
477 * user's requested refresh rate.
478 */
479
480 return 0;
481}
482
483/*
484 * Return the list of DDC modes if available, or the BIOS fixed mode otherwise.
485 */
486static int intel_lvds_get_modes(struct drm_connector *_connector)
487{
488 struct intel_connector *connector = to_intel_connector(_connector);
489 const struct drm_edid *fixed_edid = connector->panel.fixed_edid;
490
491 /* Use panel fixed edid if we have one */
492 if (!IS_ERR_OR_NULL(ptr: fixed_edid)) {
493 drm_edid_connector_update(connector: &connector->base, edid: fixed_edid);
494
495 return drm_edid_connector_add_modes(connector: &connector->base);
496 }
497
498 return intel_panel_get_modes(connector);
499}
500
501static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = {
502 .get_modes = intel_lvds_get_modes,
503 .mode_valid = intel_lvds_mode_valid,
504 .atomic_check = intel_digital_connector_atomic_check,
505};
506
507static const struct drm_connector_funcs intel_lvds_connector_funcs = {
508 .detect = intel_panel_detect,
509 .fill_modes = drm_helper_probe_single_connector_modes,
510 .atomic_get_property = intel_digital_connector_atomic_get_property,
511 .atomic_set_property = intel_digital_connector_atomic_set_property,
512 .late_register = intel_connector_register,
513 .early_unregister = intel_connector_unregister,
514 .destroy = intel_connector_destroy,
515 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
516 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
517};
518
519static const struct drm_encoder_funcs intel_lvds_enc_funcs = {
520 .destroy = intel_encoder_destroy,
521};
522
523static int intel_no_lvds_dmi_callback(const struct dmi_system_id *id)
524{
525 DRM_INFO("Skipping LVDS initialization for %s\n", id->ident);
526 return 1;
527}
528
529/* These systems claim to have LVDS, but really don't */
530static const struct dmi_system_id intel_no_lvds[] = {
531 {
532 .callback = intel_no_lvds_dmi_callback,
533 .ident = "Apple Mac Mini (Core series)",
534 .matches = {
535 DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
536 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"),
537 },
538 },
539 {
540 .callback = intel_no_lvds_dmi_callback,
541 .ident = "Apple Mac Mini (Core 2 series)",
542 .matches = {
543 DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
544 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"),
545 },
546 },
547 {
548 .callback = intel_no_lvds_dmi_callback,
549 .ident = "MSI IM-945GSE-A",
550 .matches = {
551 DMI_MATCH(DMI_SYS_VENDOR, "MSI"),
552 DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"),
553 },
554 },
555 {
556 .callback = intel_no_lvds_dmi_callback,
557 .ident = "Dell Studio Hybrid",
558 .matches = {
559 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
560 DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"),
561 },
562 },
563 {
564 .callback = intel_no_lvds_dmi_callback,
565 .ident = "Dell OptiPlex FX170",
566 .matches = {
567 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
568 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"),
569 },
570 },
571 {
572 .callback = intel_no_lvds_dmi_callback,
573 .ident = "AOpen Mini PC",
574 .matches = {
575 DMI_MATCH(DMI_SYS_VENDOR, "AOpen"),
576 DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"),
577 },
578 },
579 {
580 .callback = intel_no_lvds_dmi_callback,
581 .ident = "AOpen Mini PC MP915",
582 .matches = {
583 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
584 DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"),
585 },
586 },
587 {
588 .callback = intel_no_lvds_dmi_callback,
589 .ident = "AOpen i915GMm-HFS",
590 .matches = {
591 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
592 DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"),
593 },
594 },
595 {
596 .callback = intel_no_lvds_dmi_callback,
597 .ident = "AOpen i45GMx-I",
598 .matches = {
599 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
600 DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"),
601 },
602 },
603 {
604 .callback = intel_no_lvds_dmi_callback,
605 .ident = "Aopen i945GTt-VFA",
606 .matches = {
607 DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"),
608 },
609 },
610 {
611 .callback = intel_no_lvds_dmi_callback,
612 .ident = "Clientron U800",
613 .matches = {
614 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
615 DMI_MATCH(DMI_PRODUCT_NAME, "U800"),
616 },
617 },
618 {
619 .callback = intel_no_lvds_dmi_callback,
620 .ident = "Clientron E830",
621 .matches = {
622 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
623 DMI_MATCH(DMI_PRODUCT_NAME, "E830"),
624 },
625 },
626 {
627 .callback = intel_no_lvds_dmi_callback,
628 .ident = "Asus EeeBox PC EB1007",
629 .matches = {
630 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."),
631 DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"),
632 },
633 },
634 {
635 .callback = intel_no_lvds_dmi_callback,
636 .ident = "Asus AT5NM10T-I",
637 .matches = {
638 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
639 DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"),
640 },
641 },
642 {
643 .callback = intel_no_lvds_dmi_callback,
644 .ident = "Hewlett-Packard HP t5740",
645 .matches = {
646 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
647 DMI_MATCH(DMI_PRODUCT_NAME, " t5740"),
648 },
649 },
650 {
651 .callback = intel_no_lvds_dmi_callback,
652 .ident = "Hewlett-Packard t5745",
653 .matches = {
654 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
655 DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"),
656 },
657 },
658 {
659 .callback = intel_no_lvds_dmi_callback,
660 .ident = "Hewlett-Packard st5747",
661 .matches = {
662 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
663 DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"),
664 },
665 },
666 {
667 .callback = intel_no_lvds_dmi_callback,
668 .ident = "MSI Wind Box DC500",
669 .matches = {
670 DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"),
671 DMI_MATCH(DMI_BOARD_NAME, "MS-7469"),
672 },
673 },
674 {
675 .callback = intel_no_lvds_dmi_callback,
676 .ident = "Gigabyte GA-D525TUD",
677 .matches = {
678 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),
679 DMI_MATCH(DMI_BOARD_NAME, "D525TUD"),
680 },
681 },
682 {
683 .callback = intel_no_lvds_dmi_callback,
684 .ident = "Supermicro X7SPA-H",
685 .matches = {
686 DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"),
687 DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"),
688 },
689 },
690 {
691 .callback = intel_no_lvds_dmi_callback,
692 .ident = "Fujitsu Esprimo Q900",
693 .matches = {
694 DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"),
695 DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"),
696 },
697 },
698 {
699 .callback = intel_no_lvds_dmi_callback,
700 .ident = "Intel D410PT",
701 .matches = {
702 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
703 DMI_MATCH(DMI_BOARD_NAME, "D410PT"),
704 },
705 },
706 {
707 .callback = intel_no_lvds_dmi_callback,
708 .ident = "Intel D425KT",
709 .matches = {
710 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
711 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D425KT"),
712 },
713 },
714 {
715 .callback = intel_no_lvds_dmi_callback,
716 .ident = "Intel D510MO",
717 .matches = {
718 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
719 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D510MO"),
720 },
721 },
722 {
723 .callback = intel_no_lvds_dmi_callback,
724 .ident = "Intel D525MW",
725 .matches = {
726 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
727 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D525MW"),
728 },
729 },
730 {
731 .callback = intel_no_lvds_dmi_callback,
732 .ident = "Radiant P845",
733 .matches = {
734 DMI_MATCH(DMI_SYS_VENDOR, "Radiant Systems Inc"),
735 DMI_MATCH(DMI_PRODUCT_NAME, "P845"),
736 },
737 },
738
739 { } /* terminating entry */
740};
741
742static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
743{
744 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
745 return 1;
746}
747
748static const struct dmi_system_id intel_dual_link_lvds[] = {
749 {
750 .callback = intel_dual_link_lvds_callback,
751 .ident = "Apple MacBook Pro 15\" (2010)",
752 .matches = {
753 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
754 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro6,2"),
755 },
756 },
757 {
758 .callback = intel_dual_link_lvds_callback,
759 .ident = "Apple MacBook Pro 15\" (2011)",
760 .matches = {
761 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
762 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
763 },
764 },
765 {
766 .callback = intel_dual_link_lvds_callback,
767 .ident = "Apple MacBook Pro 15\" (2012)",
768 .matches = {
769 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
770 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro9,1"),
771 },
772 },
773 { } /* terminating entry */
774};
775
776struct intel_encoder *intel_get_lvds_encoder(struct intel_display *display)
777{
778 struct intel_encoder *encoder;
779
780 for_each_intel_encoder(display->drm, encoder) {
781 if (encoder->type == INTEL_OUTPUT_LVDS)
782 return encoder;
783 }
784
785 return NULL;
786}
787
788bool intel_is_dual_link_lvds(struct intel_display *display)
789{
790 struct intel_encoder *encoder = intel_get_lvds_encoder(display);
791
792 return encoder && to_lvds_encoder(encoder)->is_dual_link;
793}
794
795static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder)
796{
797 struct intel_display *display = to_intel_display(&lvds_encoder->base);
798 struct intel_connector *connector = lvds_encoder->attached_connector;
799 const struct drm_display_mode *fixed_mode =
800 intel_panel_preferred_fixed_mode(connector);
801 unsigned int val;
802
803 /* use the module option value if specified */
804 if (display->params.lvds_channel_mode > 0)
805 return display->params.lvds_channel_mode == 2;
806
807 /* single channel LVDS is limited to 112 MHz */
808 if (fixed_mode->clock > 112999)
809 return true;
810
811 if (dmi_check_system(list: intel_dual_link_lvds))
812 return true;
813
814 /*
815 * BIOS should set the proper LVDS register value at boot, but
816 * in reality, it doesn't set the value when the lid is closed;
817 * we need to check "the value to be set" in VBT when LVDS
818 * register is uninitialized.
819 */
820 val = intel_de_read(display, reg: lvds_encoder->reg);
821 if (HAS_PCH_CPT(display))
822 val &= ~(LVDS_DETECTED | LVDS_PIPE_SEL_MASK_CPT);
823 else
824 val &= ~(LVDS_DETECTED | LVDS_PIPE_SEL_MASK);
825 if (val == 0)
826 val = connector->panel.vbt.bios_lvds_val;
827
828 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
829}
830
831static void intel_lvds_add_properties(struct drm_connector *connector)
832{
833 intel_attach_scaling_mode_property(connector);
834}
835
836/**
837 * intel_lvds_init - setup LVDS connectors on this device
838 * @display: display device
839 *
840 * Create the connector, register the LVDS DDC bus, and try to figure out what
841 * modes we can display on the LVDS panel (if present).
842 */
843void intel_lvds_init(struct intel_display *display)
844{
845 struct intel_lvds_encoder *lvds_encoder;
846 struct intel_connector *connector;
847 const struct drm_edid *drm_edid;
848 struct intel_encoder *encoder;
849 i915_reg_t lvds_reg;
850 u32 lvds;
851 u8 ddc_pin;
852
853 /* Skip init on machines we know falsely report LVDS */
854 if (dmi_check_system(list: intel_no_lvds)) {
855 drm_WARN(display->drm, !display->vbt.int_lvds_support,
856 "Useless DMI match. Internal LVDS support disabled by VBT\n");
857 return;
858 }
859
860 if (!display->vbt.int_lvds_support) {
861 drm_dbg_kms(display->drm,
862 "Internal LVDS support disabled by VBT\n");
863 return;
864 }
865
866 if (HAS_PCH_SPLIT(display))
867 lvds_reg = PCH_LVDS;
868 else
869 lvds_reg = LVDS;
870
871 lvds = intel_de_read(display, reg: lvds_reg);
872
873 if (HAS_PCH_SPLIT(display)) {
874 if ((lvds & LVDS_DETECTED) == 0)
875 return;
876 }
877
878 ddc_pin = GMBUS_PIN_PANEL;
879 if (!intel_bios_is_lvds_present(display, i2c_pin: &ddc_pin)) {
880 if ((lvds & LVDS_PORT_EN) == 0) {
881 drm_dbg_kms(display->drm,
882 "LVDS is not present in VBT\n");
883 return;
884 }
885 drm_dbg_kms(display->drm,
886 "LVDS is not present in VBT, but enabled anyway\n");
887 }
888
889 lvds_encoder = kzalloc(sizeof(*lvds_encoder), GFP_KERNEL);
890 if (!lvds_encoder)
891 return;
892
893 connector = intel_connector_alloc();
894 if (!connector) {
895 kfree(objp: lvds_encoder);
896 return;
897 }
898
899 lvds_encoder->attached_connector = connector;
900 encoder = &lvds_encoder->base;
901
902 drm_connector_init_with_ddc(dev: display->drm, connector: &connector->base,
903 funcs: &intel_lvds_connector_funcs,
904 DRM_MODE_CONNECTOR_LVDS,
905 ddc: intel_gmbus_get_adapter(display, pin: ddc_pin));
906
907 drm_encoder_init(dev: display->drm, encoder: &encoder->base, funcs: &intel_lvds_enc_funcs,
908 DRM_MODE_ENCODER_LVDS, name: "LVDS");
909
910 encoder->enable = intel_enable_lvds;
911 encoder->pre_enable = intel_pre_enable_lvds;
912 encoder->compute_config = intel_lvds_compute_config;
913 if (HAS_PCH_SPLIT(display)) {
914 encoder->disable = pch_disable_lvds;
915 encoder->post_disable = pch_post_disable_lvds;
916 } else {
917 encoder->disable = gmch_disable_lvds;
918 }
919 encoder->get_hw_state = intel_lvds_get_hw_state;
920 encoder->get_config = intel_lvds_get_config;
921 encoder->update_pipe = intel_backlight_update;
922 encoder->shutdown = intel_lvds_shutdown;
923 connector->get_hw_state = intel_connector_get_hw_state;
924
925 intel_connector_attach_encoder(connector, encoder);
926
927 encoder->type = INTEL_OUTPUT_LVDS;
928 encoder->power_domain = POWER_DOMAIN_PORT_OTHER;
929 encoder->port = PORT_NONE;
930 encoder->cloneable = 0;
931 if (DISPLAY_VER(display) < 4)
932 encoder->pipe_mask = BIT(PIPE_B);
933 else
934 encoder->pipe_mask = ~0;
935
936 drm_connector_helper_add(connector: &connector->base, funcs: &intel_lvds_connector_helper_funcs);
937 connector->base.display_info.subpixel_order = SubPixelHorizontalRGB;
938
939 lvds_encoder->reg = lvds_reg;
940
941 intel_lvds_add_properties(connector: &connector->base);
942
943 intel_lvds_pps_get_hw_state(display, pps: &lvds_encoder->init_pps);
944 lvds_encoder->init_lvds_val = lvds;
945
946 /*
947 * LVDS discovery:
948 * 1) check for EDID on DDC
949 * 2) check for VBT data
950 * 3) check to see if LVDS is already on
951 * if none of the above, no panel
952 */
953
954 /*
955 * Attempt to get the fixed panel mode from DDC. Assume that the
956 * preferred mode is the right one.
957 */
958 mutex_lock(&display->drm->mode_config.mutex);
959 if (vga_switcheroo_handler_flags() & VGA_SWITCHEROO_CAN_SWITCH_DDC)
960 drm_edid = drm_edid_read_switcheroo(connector: &connector->base, adapter: connector->base.ddc);
961 else
962 drm_edid = drm_edid_read_ddc(connector: &connector->base, adapter: connector->base.ddc);
963 if (drm_edid) {
964 if (drm_edid_connector_update(connector: &connector->base, edid: drm_edid) ||
965 !drm_edid_connector_add_modes(connector: &connector->base)) {
966 drm_edid_connector_update(connector: &connector->base, NULL);
967 drm_edid_free(drm_edid);
968 drm_edid = ERR_PTR(error: -EINVAL);
969 }
970 } else {
971 drm_edid = ERR_PTR(error: -ENOENT);
972 }
973 intel_bios_init_panel_late(display, panel: &connector->panel, NULL,
974 drm_edid: IS_ERR(ptr: drm_edid) ? NULL : drm_edid);
975
976 /* Try EDID first */
977 intel_panel_add_edid_fixed_modes(connector, use_alt_fixed_modes: true);
978
979 /* Failed to get EDID, what about VBT? */
980 if (!intel_panel_preferred_fixed_mode(connector))
981 intel_panel_add_vbt_lfp_fixed_mode(connector);
982
983 /*
984 * If we didn't get a fixed mode from EDID or VBT, try checking
985 * if the panel is already turned on. If so, assume that
986 * whatever is currently programmed is the correct mode.
987 */
988 if (!intel_panel_preferred_fixed_mode(connector))
989 intel_panel_add_encoder_fixed_mode(connector, encoder);
990
991 mutex_unlock(lock: &display->drm->mode_config.mutex);
992
993 /* If we still don't have a mode after all that, give up. */
994 if (!intel_panel_preferred_fixed_mode(connector))
995 goto failed;
996
997 intel_panel_init(connector, fixed_edid: drm_edid);
998
999 intel_backlight_setup(connector, pipe: INVALID_PIPE);
1000
1001 lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder);
1002 drm_dbg_kms(display->drm, "detected %s-link lvds configuration\n",
1003 lvds_encoder->is_dual_link ? "dual" : "single");
1004
1005 lvds_encoder->a3_power = lvds & LVDS_A3_POWER_MASK;
1006
1007 return;
1008
1009failed:
1010 drm_dbg_kms(display->drm, "No LVDS modes found, disabling.\n");
1011 drm_connector_cleanup(connector: &connector->base);
1012 drm_encoder_cleanup(encoder: &encoder->base);
1013 kfree(objp: lvds_encoder);
1014 intel_connector_free(connector);
1015 return;
1016}
1017

source code of linux/drivers/gpu/drm/i915/display/intel_lvds.c