1	/*
2	* Copyright © 2006-2017 Intel Corporation
3	*
4	* Permission is hereby granted, free of charge, to any person obtaining a
5	* copy of this software and associated documentation files (the "Software"),
6	* to deal in the Software without restriction, including without limitation
7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8	* and/or sell copies of the Software, and to permit persons to whom the
9	* Software is furnished to do so, subject to the following conditions:
10	*
11	* The above copyright notice and this permission notice (including the next
12	* paragraph) shall be included in all copies or substantial portions of the
13	* Software.
14	*
15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21	* DEALINGS IN THE SOFTWARE.
22	*/
23
24	#include <linux/debugfs.h>
25	#include <linux/iopoll.h>
26	#include <linux/time.h>
27
28	#include <drm/drm_fixed.h>
29	#include <drm/drm_print.h>
30
31	#include "soc/intel_dram.h"
32
33	#include "hsw_ips.h"
34	#include "i915_drv.h"
35	#include "i915_reg.h"
36	#include "intel_atomic.h"
37	#include "intel_audio.h"
38	#include "intel_cdclk.h"
39	#include "intel_crtc.h"
40	#include "intel_dbuf_bw.h"
41	#include "intel_de.h"
42	#include "intel_display_regs.h"
43	#include "intel_display_types.h"
44	#include "intel_display_utils.h"
45	#include "intel_mchbar_regs.h"
46	#include "intel_pci_config.h"
47	#include "intel_pcode.h"
48	#include "intel_plane.h"
49	#include "intel_psr.h"
50	#include "intel_vdsc.h"
51	#include "skl_watermark.h"
52	#include "skl_watermark_regs.h"
53	#include "vlv_clock.h"
54	#include "vlv_dsi.h"
55	#include "vlv_sideband.h"
56
57	/**
58	* DOC: CDCLK / RAWCLK
59	*
60	* The display engine uses several different clocks to do its work. There
61	* are two main clocks involved that aren't directly related to the actual
62	* pixel clock or any symbol/bit clock of the actual output port. These
63	* are the core display clock (CDCLK) and RAWCLK.
64	*
65	* CDCLK clocks most of the display pipe logic, and thus its frequency
66	* must be high enough to support the rate at which pixels are flowing
67	* through the pipes. Downscaling must also be accounted as that increases
68	* the effective pixel rate.
69	*
70	* On several platforms the CDCLK frequency can be changed dynamically
71	* to minimize power consumption for a given display configuration.
72	* Typically changes to the CDCLK frequency require all the display pipes
73	* to be shut down while the frequency is being changed.
74	*
75	* On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit.
76	* DMC will not change the active CDCLK frequency however, so that part
77	* will still be performed by the driver directly.
78	*
79	* There are multiple components involved in the generation of the CDCLK
80	* frequency:
81	*
82	* - We have the CDCLK PLL, which generates an output clock based on a
83	* reference clock and a ratio parameter.
84	* - The CD2X Divider, which divides the output of the PLL based on a
85	* divisor selected from a set of pre-defined choices.
86	* - The CD2X Squasher, which further divides the output based on a
87	* waveform represented as a sequence of bits where each zero
88	* "squashes out" a clock cycle.
89	* - And, finally, a fixed divider that divides the output frequency by 2.
90	*
91	* As such, the resulting CDCLK frequency can be calculated with the
92	* following formula:
93	*
94	* cdclk = vco / cd2x_div / (sq_len / sq_div) / 2
95	*
96	* , where vco is the frequency generated by the PLL; cd2x_div
97	* represents the CD2X Divider; sq_len and sq_div are the bit length
98	* and the number of high bits for the CD2X Squasher waveform, respectively;
99	* and 2 represents the fixed divider.
100	*
101	* Note that some older platforms do not contain the CD2X Divider
102	* and/or CD2X Squasher, in which case we can ignore their respective
103	* factors in the formula above.
104	*
105	* Several methods exist to change the CDCLK frequency, which ones are
106	* supported depends on the platform:
107	*
108	* - Full PLL disable + re-enable with new VCO frequency. Pipes must be inactive.
109	* - CD2X divider update. Single pipe can be active as the divider update
110	* can be synchronized with the pipe's start of vblank.
111	* - Crawl the PLL smoothly to the new VCO frequency. Pipes can be active.
112	* - Squash waveform update. Pipes can be active.
113	* - Crawl and squash can also be done back to back. Pipes can be active.
114	*
115	* RAWCLK is a fixed frequency clock, often used by various auxiliary
116	* blocks such as AUX CH or backlight PWM. Hence the only thing we
117	* really need to know about RAWCLK is its frequency so that various
118	* dividers can be programmed correctly.
119	*/
120
121	struct intel_cdclk_state {
122	struct intel_global_state base;
123
124	/*
125	* Logical configuration of cdclk (used for all scaling,
126	* watermark, etc. calculations and checks). This is
127	* computed as if all enabled crtcs were active.
128	*/
129	struct intel_cdclk_config logical;
130
131	/*
132	* Actual configuration of cdclk, can be different from the
133	* logical configuration only when all crtc's are DPMS off.
134	*/
135	struct intel_cdclk_config actual;
136
137	/* minimum acceptable cdclk to satisfy DBUF bandwidth requirements */
138	int dbuf_bw_min_cdclk;
139	/* minimum acceptable cdclk for each pipe */
140	int min_cdclk[I915_MAX_PIPES];
141	/* minimum acceptable voltage level for each pipe */
142	u8 min_voltage_level[I915_MAX_PIPES];
143
144	/* pipe to which cd2x update is synchronized */
145	enum pipe pipe;
146
147	/* forced minimum cdclk for glk+ audio w/a */
148	int force_min_cdclk;
149
150	/* bitmask of enabled pipes */
151	u8 enabled_pipes;
152
153	/* bitmask of active pipes */
154	u8 active_pipes;
155
156	/* update cdclk with pipes disabled */
157	bool disable_pipes;
158	};
159
160	struct intel_cdclk_funcs {
161	void (*get_cdclk)(struct intel_display *display,
162	struct intel_cdclk_config *cdclk_config);
163	void (*set_cdclk)(struct intel_display *display,
164	const struct intel_cdclk_config *cdclk_config,
165	enum pipe pipe);
166	int (*modeset_calc_cdclk)(struct intel_atomic_state *state);
167	u8 (*calc_voltage_level)(int cdclk);
168	};
169
170	void intel_cdclk_get_cdclk(struct intel_display *display,
171	struct intel_cdclk_config *cdclk_config)
172	{
173	display->funcs.cdclk->get_cdclk(display, cdclk_config);
174	}
175
176	static void intel_cdclk_set_cdclk(struct intel_display *display,
177	const struct intel_cdclk_config *cdclk_config,
178	enum pipe pipe)
179	{
180	display->funcs.cdclk->set_cdclk(display, cdclk_config, pipe);
181	}
182
183	static int intel_cdclk_modeset_calc_cdclk(struct intel_atomic_state *state)
184	{
185	struct intel_display *display = to_intel_display(state);
186
187	return display->funcs.cdclk->modeset_calc_cdclk(state);
188	}
189
190	static u8 intel_cdclk_calc_voltage_level(struct intel_display *display,
191	int cdclk)
192	{
193	return display->funcs.cdclk->calc_voltage_level(cdclk);
194	}
195
196	static void fixed_133mhz_get_cdclk(struct intel_display *display,
197	struct intel_cdclk_config *cdclk_config)
198	{
199	cdclk_config->cdclk = 133333;
200	}
201
202	static void fixed_200mhz_get_cdclk(struct intel_display *display,
203	struct intel_cdclk_config *cdclk_config)
204	{
205	cdclk_config->cdclk = 200000;
206	}
207
208	static void fixed_266mhz_get_cdclk(struct intel_display *display,
209	struct intel_cdclk_config *cdclk_config)
210	{
211	cdclk_config->cdclk = 266667;
212	}
213
214	static void fixed_333mhz_get_cdclk(struct intel_display *display,
215	struct intel_cdclk_config *cdclk_config)
216	{
217	cdclk_config->cdclk = 333333;
218	}
219
220	static void fixed_400mhz_get_cdclk(struct intel_display *display,
221	struct intel_cdclk_config *cdclk_config)
222	{
223	cdclk_config->cdclk = 400000;
224	}
225
226	static void fixed_450mhz_get_cdclk(struct intel_display *display,
227	struct intel_cdclk_config *cdclk_config)
228	{
229	cdclk_config->cdclk = 450000;
230	}
231
232	static void i85x_get_cdclk(struct intel_display *display,
233	struct intel_cdclk_config *cdclk_config)
234	{
235	struct pci_dev *pdev = to_pci_dev(display->drm->dev);
236	u16 hpllcc = 0;
237
238	/*
239	* 852GM/852GMV only supports 133 MHz and the HPLLCC
240	* encoding is different :(
241	* FIXME is this the right way to detect 852GM/852GMV?
242	*/
243	if (pdev->revision == 0x1) {
244	cdclk_config->cdclk = 133333;
245	return;
246	}
247
248	pci_bus_read_config_word(bus: pdev->bus,
249	PCI_DEVFN(0, 3), HPLLCC, val: &hpllcc);
250
251	/* Assume that the hardware is in the high speed state. This
252	* should be the default.
253	*/
254	switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
255	case GC_CLOCK_133_200:
256	case GC_CLOCK_133_200_2:
257	case GC_CLOCK_100_200:
258	cdclk_config->cdclk = 200000;
259	break;
260	case GC_CLOCK_166_250:
261	cdclk_config->cdclk = 250000;
262	break;
263	case GC_CLOCK_100_133:
264	cdclk_config->cdclk = 133333;
265	break;
266	case GC_CLOCK_133_266:
267	case GC_CLOCK_133_266_2:
268	case GC_CLOCK_166_266:
269	cdclk_config->cdclk = 266667;
270	break;
271	}
272	}
273
274	static void i915gm_get_cdclk(struct intel_display *display,
275	struct intel_cdclk_config *cdclk_config)
276	{
277	struct pci_dev *pdev = to_pci_dev(display->drm->dev);
278	u16 gcfgc = 0;
279
280	pci_read_config_word(dev: pdev, GCFGC, val: &gcfgc);
281
282	if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
283	cdclk_config->cdclk = 133333;
284	return;
285	}
286
287	switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
288	case GC_DISPLAY_CLOCK_333_320_MHZ:
289	cdclk_config->cdclk = 333333;
290	break;
291	default:
292	case GC_DISPLAY_CLOCK_190_200_MHZ:
293	cdclk_config->cdclk = 190000;
294	break;
295	}
296	}
297
298	static void i945gm_get_cdclk(struct intel_display *display,
299	struct intel_cdclk_config *cdclk_config)
300	{
301	struct pci_dev *pdev = to_pci_dev(display->drm->dev);
302	u16 gcfgc = 0;
303
304	pci_read_config_word(dev: pdev, GCFGC, val: &gcfgc);
305
306	if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
307	cdclk_config->cdclk = 133333;
308	return;
309	}
310
311	switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
312	case GC_DISPLAY_CLOCK_333_320_MHZ:
313	cdclk_config->cdclk = 320000;
314	break;
315	default:
316	case GC_DISPLAY_CLOCK_190_200_MHZ:
317	cdclk_config->cdclk = 200000;
318	break;
319	}
320	}
321
322	static unsigned int intel_hpll_vco(struct intel_display *display)
323	{
324	static const unsigned int blb_vco[8] = {
325	[0] = 3200000,
326	[1] = 4000000,
327	[2] = 5333333,
328	[3] = 4800000,
329	[4] = 6400000,
330	};
331	static const unsigned int pnv_vco[8] = {
332	[0] = 3200000,
333	[1] = 4000000,
334	[2] = 5333333,
335	[3] = 4800000,
336	[4] = 2666667,
337	};
338	static const unsigned int cl_vco[8] = {
339	[0] = 3200000,
340	[1] = 4000000,
341	[2] = 5333333,
342	[3] = 6400000,
343	[4] = 3333333,
344	[5] = 3566667,
345	[6] = 4266667,
346	};
347	static const unsigned int elk_vco[8] = {
348	[0] = 3200000,
349	[1] = 4000000,
350	[2] = 5333333,
351	[3] = 4800000,
352	};
353	static const unsigned int ctg_vco[8] = {
354	[0] = 3200000,
355	[1] = 4000000,
356	[2] = 5333333,
357	[3] = 6400000,
358	[4] = 2666667,
359	[5] = 4266667,
360	};
361	const unsigned int *vco_table;
362	unsigned int vco;
363	u8 tmp = 0;
364
365	/* FIXME other chipsets? */
366	if (display->platform.gm45)
367	vco_table = ctg_vco;
368	else if (display->platform.g45)
369	vco_table = elk_vco;
370	else if (display->platform.i965gm)
371	vco_table = cl_vco;
372	else if (display->platform.pineview)
373	vco_table = pnv_vco;
374	else if (display->platform.g33)
375	vco_table = blb_vco;
376	else
377	return 0;
378
379	tmp = intel_de_read(display, reg: display->platform.pineview ||
380	display->platform.mobile ? HPLLVCO_MOBILE : HPLLVCO);
381
382	vco = vco_table[tmp & 0x7];
383	if (vco == 0)
384	drm_err(display->drm, "Bad HPLL VCO (HPLLVCO=0x%02x)\n",
385	tmp);
386	else
387	drm_dbg_kms(display->drm, "HPLL VCO %u kHz\n", vco);
388
389	return vco;
390	}
391
392	static void g33_get_cdclk(struct intel_display *display,
393	struct intel_cdclk_config *cdclk_config)
394	{
395	struct pci_dev *pdev = to_pci_dev(display->drm->dev);
396	static const u8 div_3200[] = { 12, 10, 8, 7, 5, 16 };
397	static const u8 div_4000[] = { 14, 12, 10, 8, 6, 20 };
398	static const u8 div_4800[] = { 20, 14, 12, 10, 8, 24 };
399	static const u8 div_5333[] = { 20, 16, 12, 12, 8, 28 };
400	const u8 *div_table;
401	unsigned int cdclk_sel;
402	u16 tmp = 0;
403
404	cdclk_config->vco = intel_hpll_vco(display);
405
406	pci_read_config_word(dev: pdev, GCFGC, val: &tmp);
407
408	cdclk_sel = (tmp >> 4) & 0x7;
409
410	if (cdclk_sel >= ARRAY_SIZE(div_3200))
411	goto fail;
412
413	switch (cdclk_config->vco) {
414	case 3200000:
415	div_table = div_3200;
416	break;
417	case 4000000:
418	div_table = div_4000;
419	break;
420	case 4800000:
421	div_table = div_4800;
422	break;
423	case 5333333:
424	div_table = div_5333;
425	break;
426	default:
427	goto fail;
428	}
429
430	cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco,
431	div_table[cdclk_sel]);
432	return;
433
434	fail:
435	drm_err(display->drm,
436	"Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n",
437	cdclk_config->vco, tmp);
438	cdclk_config->cdclk = 190476;
439	}
440
441	static void pnv_get_cdclk(struct intel_display *display,
442	struct intel_cdclk_config *cdclk_config)
443	{
444	struct pci_dev *pdev = to_pci_dev(display->drm->dev);
445	u16 gcfgc = 0;
446
447	pci_read_config_word(dev: pdev, GCFGC, val: &gcfgc);
448
449	switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
450	case GC_DISPLAY_CLOCK_267_MHZ_PNV:
451	cdclk_config->cdclk = 266667;
452	break;
453	case GC_DISPLAY_CLOCK_333_MHZ_PNV:
454	cdclk_config->cdclk = 333333;
455	break;
456	case GC_DISPLAY_CLOCK_444_MHZ_PNV:
457	cdclk_config->cdclk = 444444;
458	break;
459	case GC_DISPLAY_CLOCK_200_MHZ_PNV:
460	cdclk_config->cdclk = 200000;
461	break;
462	default:
463	drm_err(display->drm,
464	"Unknown pnv display core clock 0x%04x\n", gcfgc);
465	fallthrough;
466	case GC_DISPLAY_CLOCK_133_MHZ_PNV:
467	cdclk_config->cdclk = 133333;
468	break;
469	case GC_DISPLAY_CLOCK_167_MHZ_PNV:
470	cdclk_config->cdclk = 166667;
471	break;
472	}
473	}
474
475	static void i965gm_get_cdclk(struct intel_display *display,
476	struct intel_cdclk_config *cdclk_config)
477	{
478	struct pci_dev *pdev = to_pci_dev(display->drm->dev);
479	static const u8 div_3200[] = { 16, 10, 8 };
480	static const u8 div_4000[] = { 20, 12, 10 };
481	static const u8 div_5333[] = { 24, 16, 14 };
482	const u8 *div_table;
483	unsigned int cdclk_sel;
484	u16 tmp = 0;
485
486	cdclk_config->vco = intel_hpll_vco(display);
487
488	pci_read_config_word(dev: pdev, GCFGC, val: &tmp);
489
490	cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
491
492	if (cdclk_sel >= ARRAY_SIZE(div_3200))
493	goto fail;
494
495	switch (cdclk_config->vco) {
496	case 3200000:
497	div_table = div_3200;
498	break;
499	case 4000000:
500	div_table = div_4000;
501	break;
502	case 5333333:
503	div_table = div_5333;
504	break;
505	default:
506	goto fail;
507	}
508
509	cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco,
510	div_table[cdclk_sel]);
511	return;
512
513	fail:
514	drm_err(display->drm,
515	"Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n",
516	cdclk_config->vco, tmp);
517	cdclk_config->cdclk = 200000;
518	}
519
520	static void gm45_get_cdclk(struct intel_display *display,
521	struct intel_cdclk_config *cdclk_config)
522	{
523	struct pci_dev *pdev = to_pci_dev(display->drm->dev);
524	unsigned int cdclk_sel;
525	u16 tmp = 0;
526
527	cdclk_config->vco = intel_hpll_vco(display);
528
529	pci_read_config_word(dev: pdev, GCFGC, val: &tmp);
530
531	cdclk_sel = (tmp >> 12) & 0x1;
532
533	switch (cdclk_config->vco) {
534	case 2666667:
535	case 4000000:
536	case 5333333:
537	cdclk_config->cdclk = cdclk_sel ? 333333 : 222222;
538	break;
539	case 3200000:
540	cdclk_config->cdclk = cdclk_sel ? 320000 : 228571;
541	break;
542	default:
543	drm_err(display->drm,
544	"Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n",
545	cdclk_config->vco, tmp);
546	cdclk_config->cdclk = 222222;
547	break;
548	}
549	}
550
551	static void hsw_get_cdclk(struct intel_display *display,
552	struct intel_cdclk_config *cdclk_config)
553	{
554	u32 lcpll = intel_de_read(display, LCPLL_CTL);
555	u32 freq = lcpll & LCPLL_CLK_FREQ_MASK;
556
557	if (lcpll & LCPLL_CD_SOURCE_FCLK)
558	cdclk_config->cdclk = 800000;
559	else if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT)
560	cdclk_config->cdclk = 450000;
561	else if (freq == LCPLL_CLK_FREQ_450)
562	cdclk_config->cdclk = 450000;
563	else if (display->platform.haswell_ult)
564	cdclk_config->cdclk = 337500;
565	else
566	cdclk_config->cdclk = 540000;
567	}
568
569	static int vlv_calc_cdclk(struct intel_display *display, int min_cdclk)
570	{
571	int freq_320 = (vlv_clock_get_hpll_vco(drm: display->drm) << 1) % 320000 != 0 ?
572	333333 : 320000;
573
574	/*
575	* We seem to get an unstable or solid color picture at 200MHz.
576	* Not sure what's wrong. For now use 200MHz only when all pipes
577	* are off.
578	*/
579	if (display->platform.valleyview && min_cdclk > freq_320)
580	return 400000;
581	else if (min_cdclk > 266667)
582	return freq_320;
583	else if (min_cdclk > 0)
584	return 266667;
585	else
586	return 200000;
587	}
588
589	static u8 vlv_calc_voltage_level(struct intel_display *display, int cdclk)
590	{
591	if (display->platform.valleyview) {
592	if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
593	return 2;
594	else if (cdclk >= 266667)
595	return 1;
596	else
597	return 0;
598	} else {
599	/*
600	* Specs are full of misinformation, but testing on actual
601	* hardware has shown that we just need to write the desired
602	* CCK divider into the Punit register.
603	*/
604	return DIV_ROUND_CLOSEST(vlv_clock_get_hpll_vco(display->drm) << 1, cdclk) - 1;
605	}
606	}
607
608	static void vlv_get_cdclk(struct intel_display *display,
609	struct intel_cdclk_config *cdclk_config)
610	{
611	u32 val;
612
613	cdclk_config->vco = vlv_clock_get_hpll_vco(drm: display->drm);
614	cdclk_config->cdclk = vlv_clock_get_cdclk(drm: display->drm);
615
616	vlv_punit_get(drm: display->drm);
617	val = vlv_punit_read(drm: display->drm, PUNIT_REG_DSPSSPM);
618	vlv_punit_put(drm: display->drm);
619
620	if (display->platform.valleyview)
621	cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK) >>
622	DSPFREQGUAR_SHIFT;
623	else
624	cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK_CHV) >>
625	DSPFREQGUAR_SHIFT_CHV;
626	}
627
628	static void vlv_program_pfi_credits(struct intel_display *display)
629	{
630	unsigned int credits, default_credits;
631
632	if (display->platform.cherryview)
633	default_credits = PFI_CREDIT(12);
634	else
635	default_credits = PFI_CREDIT(8);
636
637	if (display->cdclk.hw.cdclk >= vlv_clock_get_czclk(drm: display->drm)) {
638	/* CHV suggested value is 31 or 63 */
639	if (display->platform.cherryview)
640	credits = PFI_CREDIT_63;
641	else
642	credits = PFI_CREDIT(15);
643	} else {
644	credits = default_credits;
645	}
646
647	/*
648	* WA - write default credits before re-programming
649	* FIXME: should we also set the resend bit here?
650	*/
651	intel_de_write(display, GCI_CONTROL,
652	VGA_FAST_MODE_DISABLE | default_credits);
653
654	intel_de_write(display, GCI_CONTROL,
655	VGA_FAST_MODE_DISABLE | credits | PFI_CREDIT_RESEND);
656
657	/*
658	* FIXME is this guaranteed to clear
659	* immediately or should we poll for it?
660	*/
661	drm_WARN_ON(display->drm,
662	intel_de_read(display, GCI_CONTROL) & PFI_CREDIT_RESEND);
663	}
664
665	static void vlv_set_cdclk(struct intel_display *display,
666	const struct intel_cdclk_config *cdclk_config,
667	enum pipe pipe)
668	{
669	int cdclk = cdclk_config->cdclk;
670	u32 val, cmd = cdclk_config->voltage_level;
671	intel_wakeref_t wakeref;
672	int ret;
673
674	switch (cdclk) {
675	case 400000:
676	case 333333:
677	case 320000:
678	case 266667:
679	case 200000:
680	break;
681	default:
682	MISSING_CASE(cdclk);
683	return;
684	}
685
686	/* There are cases where we can end up here with power domains
687	* off and a CDCLK frequency other than the minimum, like when
688	* issuing a modeset without actually changing any display after
689	* a system suspend. So grab the display core domain, which covers
690	* the HW blocks needed for the following programming.
691	*/
692	wakeref = intel_display_power_get(display, domain: POWER_DOMAIN_DISPLAY_CORE);
693
694	vlv_iosf_sb_get(drm: display->drm,
695	BIT(VLV_IOSF_SB_CCK) |
696	BIT(VLV_IOSF_SB_BUNIT) |
697	BIT(VLV_IOSF_SB_PUNIT));
698
699	val = vlv_punit_read(drm: display->drm, PUNIT_REG_DSPSSPM);
700	val &= ~DSPFREQGUAR_MASK;
701	val |= (cmd << DSPFREQGUAR_SHIFT);
702	vlv_punit_write(drm: display->drm, PUNIT_REG_DSPSSPM, val);
703
704	ret = poll_timeout_us(val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM),
705	(val & DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
706	500, 50 * 1000, false);
707	if (ret)
708	drm_err(display->drm, "timed out waiting for CDCLK change\n");
709
710	if (cdclk == 400000) {
711	u32 divider;
712
713	divider = DIV_ROUND_CLOSEST(vlv_clock_get_hpll_vco(display->drm) << 1,
714	cdclk) - 1;
715
716	/* adjust cdclk divider */
717	val = vlv_cck_read(drm: display->drm, CCK_DISPLAY_CLOCK_CONTROL);
718	val &= ~CCK_FREQUENCY_VALUES;
719	val |= divider;
720	vlv_cck_write(drm: display->drm, CCK_DISPLAY_CLOCK_CONTROL, val);
721
722	ret = poll_timeout_us(val = vlv_cck_read(display->drm, CCK_DISPLAY_CLOCK_CONTROL),
723	(val & CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
724	500, 50 * 1000, false);
725	if (ret)
726	drm_err(display->drm, "timed out waiting for CDCLK change\n");
727	}
728
729	/* adjust self-refresh exit latency value */
730	val = vlv_bunit_read(drm: display->drm, BUNIT_REG_BISOC);
731	val &= ~0x7f;
732
733	/*
734	* For high bandwidth configs, we set a higher latency in the bunit
735	* so that the core display fetch happens in time to avoid underruns.
736	*/
737	if (cdclk == 400000)
738	val |= 4500 / 250; /* 4.5 usec */
739	else
740	val |= 3000 / 250; /* 3.0 usec */
741	vlv_bunit_write(drm: display->drm, BUNIT_REG_BISOC, val);
742
743	vlv_iosf_sb_put(drm: display->drm,
744	BIT(VLV_IOSF_SB_CCK) |
745	BIT(VLV_IOSF_SB_BUNIT) |
746	BIT(VLV_IOSF_SB_PUNIT));
747
748	intel_update_cdclk(display);
749
750	vlv_program_pfi_credits(display);
751
752	intel_display_power_put(display, domain: POWER_DOMAIN_DISPLAY_CORE, wakeref);
753	}
754
755	static void chv_set_cdclk(struct intel_display *display,
756	const struct intel_cdclk_config *cdclk_config,
757	enum pipe pipe)
758	{
759	int cdclk = cdclk_config->cdclk;
760	u32 val, cmd = cdclk_config->voltage_level;
761	intel_wakeref_t wakeref;
762	int ret;
763
764	switch (cdclk) {
765	case 333333:
766	case 320000:
767	case 266667:
768	case 200000:
769	break;
770	default:
771	MISSING_CASE(cdclk);
772	return;
773	}
774
775	/* There are cases where we can end up here with power domains
776	* off and a CDCLK frequency other than the minimum, like when
777	* issuing a modeset without actually changing any display after
778	* a system suspend. So grab the display core domain, which covers
779	* the HW blocks needed for the following programming.
780	*/
781	wakeref = intel_display_power_get(display, domain: POWER_DOMAIN_DISPLAY_CORE);
782
783	vlv_punit_get(drm: display->drm);
784	val = vlv_punit_read(drm: display->drm, PUNIT_REG_DSPSSPM);
785	val &= ~DSPFREQGUAR_MASK_CHV;
786	val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
787	vlv_punit_write(drm: display->drm, PUNIT_REG_DSPSSPM, val);
788
789	ret = poll_timeout_us(val = vlv_punit_read(display->drm, PUNIT_REG_DSPSSPM),
790	(val & DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
791	500, 50 * 1000, false);
792	if (ret)
793	drm_err(display->drm, "timed out waiting for CDCLK change\n");
794
795	vlv_punit_put(drm: display->drm);
796
797	intel_update_cdclk(display);
798
799	vlv_program_pfi_credits(display);
800
801	intel_display_power_put(display, domain: POWER_DOMAIN_DISPLAY_CORE, wakeref);
802	}
803
804	static int bdw_calc_cdclk(int min_cdclk)
805	{
806	if (min_cdclk > 540000)
807	return 675000;
808	else if (min_cdclk > 450000)
809	return 540000;
810	else if (min_cdclk > 337500)
811	return 450000;
812	else
813	return 337500;
814	}
815
816	static u8 bdw_calc_voltage_level(int cdclk)
817	{
818	switch (cdclk) {
819	default:
820	case 337500:
821	return 2;
822	case 450000:
823	return 0;
824	case 540000:
825	return 1;
826	case 675000:
827	return 3;
828	}
829	}
830
831	static void bdw_get_cdclk(struct intel_display *display,
832	struct intel_cdclk_config *cdclk_config)
833	{
834	u32 lcpll = intel_de_read(display, LCPLL_CTL);
835	u32 freq = lcpll & LCPLL_CLK_FREQ_MASK;
836
837	if (lcpll & LCPLL_CD_SOURCE_FCLK)
838	cdclk_config->cdclk = 800000;
839	else if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT)
840	cdclk_config->cdclk = 450000;
841	else if (freq == LCPLL_CLK_FREQ_450)
842	cdclk_config->cdclk = 450000;
843	else if (freq == LCPLL_CLK_FREQ_54O_BDW)
844	cdclk_config->cdclk = 540000;
845	else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
846	cdclk_config->cdclk = 337500;
847	else
848	cdclk_config->cdclk = 675000;
849
850	/*
851	* Can't read this out :( Let's assume it's
852	* at least what the CDCLK frequency requires.
853	*/
854	cdclk_config->voltage_level =
855	bdw_calc_voltage_level(cdclk: cdclk_config->cdclk);
856	}
857
858	static u32 bdw_cdclk_freq_sel(int cdclk)
859	{
860	switch (cdclk) {
861	default:
862	MISSING_CASE(cdclk);
863	fallthrough;
864	case 337500:
865	return LCPLL_CLK_FREQ_337_5_BDW;
866	case 450000:
867	return LCPLL_CLK_FREQ_450;
868	case 540000:
869	return LCPLL_CLK_FREQ_54O_BDW;
870	case 675000:
871	return LCPLL_CLK_FREQ_675_BDW;
872	}
873	}
874
875	static void bdw_set_cdclk(struct intel_display *display,
876	const struct intel_cdclk_config *cdclk_config,
877	enum pipe pipe)
878	{
879	int cdclk = cdclk_config->cdclk;
880	int ret;
881
882	if (drm_WARN(display->drm,
883	(intel_de_read(display, LCPLL_CTL) &
884	(LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
885	LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
886	LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
887	LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
888	"trying to change cdclk frequency with cdclk not enabled\n"))
889	return;
890
891	ret = intel_pcode_write(display->drm, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
892	if (ret) {
893	drm_err(display->drm,
894	"failed to inform pcode about cdclk change\n");
895	return;
896	}
897
898	intel_de_rmw(display, LCPLL_CTL,
899	clear: 0, LCPLL_CD_SOURCE_FCLK);
900
901	/*
902	* According to the spec, it should be enough to poll for this 1 us.
903	* However, extensive testing shows that this can take longer.
904	*/
905	ret = intel_de_wait_for_set_us(display, LCPLL_CTL,
906	LCPLL_CD_SOURCE_FCLK_DONE, timeout_us: 100);
907	if (ret)
908	drm_err(display->drm, "Switching to FCLK failed\n");
909
910	intel_de_rmw(display, LCPLL_CTL,
911	LCPLL_CLK_FREQ_MASK, set: bdw_cdclk_freq_sel(cdclk));
912
913	intel_de_rmw(display, LCPLL_CTL,
914	LCPLL_CD_SOURCE_FCLK, set: 0);
915
916	ret = intel_de_wait_for_clear_us(display, LCPLL_CTL,
917	LCPLL_CD_SOURCE_FCLK_DONE, timeout_us: 1);
918	if (ret)
919	drm_err(display->drm, "Switching back to LCPLL failed\n");
920
921	intel_pcode_write(display->drm, HSW_PCODE_DE_WRITE_FREQ_REQ,
922	cdclk_config->voltage_level);
923
924	intel_de_write(display, CDCLK_FREQ,
925	DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
926
927	intel_update_cdclk(display);
928	}
929
930	static int skl_calc_cdclk(int min_cdclk, int vco)
931	{
932	if (vco == 8640000) {
933	if (min_cdclk > 540000)
934	return 617143;
935	else if (min_cdclk > 432000)
936	return 540000;
937	else if (min_cdclk > 308571)
938	return 432000;
939	else
940	return 308571;
941	} else {
942	if (min_cdclk > 540000)
943	return 675000;
944	else if (min_cdclk > 450000)
945	return 540000;
946	else if (min_cdclk > 337500)
947	return 450000;
948	else
949	return 337500;
950	}
951	}
952
953	static u8 skl_calc_voltage_level(int cdclk)
954	{
955	if (cdclk > 540000)
956	return 3;
957	else if (cdclk > 450000)
958	return 2;
959	else if (cdclk > 337500)
960	return 1;
961	else
962	return 0;
963	}
964
965	static void skl_dpll0_update(struct intel_display *display,
966	struct intel_cdclk_config *cdclk_config)
967	{
968	u32 val;
969
970	cdclk_config->ref = 24000;
971	cdclk_config->vco = 0;
972
973	val = intel_de_read(display, LCPLL1_CTL);
974	if ((val & LCPLL_PLL_ENABLE) == 0)
975	return;
976
977	if (drm_WARN_ON(display->drm, (val & LCPLL_PLL_LOCK) == 0))
978	return;
979
980	val = intel_de_read(display, DPLL_CTRL1);
981
982	if (drm_WARN_ON(display->drm,
983	(val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
984	DPLL_CTRL1_SSC(SKL_DPLL0) |
985	DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
986	DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
987	return;
988
989	switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
990	case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
991	case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
992	case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
993	case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
994	cdclk_config->vco = 8100000;
995	break;
996	case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
997	case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
998	cdclk_config->vco = 8640000;
999	break;
1000	default:
1001	MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
1002	break;
1003	}
1004	}
1005
1006	static void skl_get_cdclk(struct intel_display *display,
1007	struct intel_cdclk_config *cdclk_config)
1008	{
1009	u32 cdctl;
1010
1011	skl_dpll0_update(display, cdclk_config);
1012
1013	cdclk_config->cdclk = cdclk_config->bypass = cdclk_config->ref;
1014
1015	if (cdclk_config->vco == 0)
1016	goto out;
1017
1018	cdctl = intel_de_read(display, CDCLK_CTL);
1019
1020	if (cdclk_config->vco == 8640000) {
1021	switch (cdctl & CDCLK_FREQ_SEL_MASK) {
1022	case CDCLK_FREQ_450_432:
1023	cdclk_config->cdclk = 432000;
1024	break;
1025	case CDCLK_FREQ_337_308:
1026	cdclk_config->cdclk = 308571;
1027	break;
1028	case CDCLK_FREQ_540:
1029	cdclk_config->cdclk = 540000;
1030	break;
1031	case CDCLK_FREQ_675_617:
1032	cdclk_config->cdclk = 617143;
1033	break;
1034	default:
1035	MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
1036	break;
1037	}
1038	} else {
1039	switch (cdctl & CDCLK_FREQ_SEL_MASK) {
1040	case CDCLK_FREQ_450_432:
1041	cdclk_config->cdclk = 450000;
1042	break;
1043	case CDCLK_FREQ_337_308:
1044	cdclk_config->cdclk = 337500;
1045	break;
1046	case CDCLK_FREQ_540:
1047	cdclk_config->cdclk = 540000;
1048	break;
1049	case CDCLK_FREQ_675_617:
1050	cdclk_config->cdclk = 675000;
1051	break;
1052	default:
1053	MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
1054	break;
1055	}
1056	}
1057
1058	out:
1059	/*
1060	* Can't read this out :( Let's assume it's
1061	* at least what the CDCLK frequency requires.
1062	*/
1063	cdclk_config->voltage_level =
1064	skl_calc_voltage_level(cdclk: cdclk_config->cdclk);
1065	}
1066
1067	/* convert from kHz to .1 fixpoint MHz with -1MHz offset */
1068	static int skl_cdclk_decimal(int cdclk)
1069	{
1070	return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
1071	}
1072
1073	static void skl_set_preferred_cdclk_vco(struct intel_display *display, int vco)
1074	{
1075	bool changed = display->cdclk.skl_preferred_vco_freq != vco;
1076
1077	display->cdclk.skl_preferred_vco_freq = vco;
1078
1079	if (changed)
1080	intel_update_max_cdclk(display);
1081	}
1082
1083	static u32 skl_dpll0_link_rate(struct intel_display *display, int vco)
1084	{
1085	drm_WARN_ON(display->drm, vco != 8100000 && vco != 8640000);
1086
1087	/*
1088	* We always enable DPLL0 with the lowest link rate possible, but still
1089	* taking into account the VCO required to operate the eDP panel at the
1090	* desired frequency. The usual DP link rates operate with a VCO of
1091	* 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
1092	* The modeset code is responsible for the selection of the exact link
1093	* rate later on, with the constraint of choosing a frequency that
1094	* works with vco.
1095	*/
1096	if (vco == 8640000)
1097	return DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0);
1098	else
1099	return DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0);
1100	}
1101
1102	static void skl_dpll0_enable(struct intel_display *display, int vco)
1103	{
1104	intel_de_rmw(display, DPLL_CTRL1,
1105	DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
1106	DPLL_CTRL1_SSC(SKL_DPLL0) |
1107	DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0),
1108	DPLL_CTRL1_OVERRIDE(SKL_DPLL0) |
1109	skl_dpll0_link_rate(display, vco));
1110	intel_de_posting_read(display, DPLL_CTRL1);
1111
1112	intel_de_rmw(display, LCPLL1_CTL,
1113	clear: 0, LCPLL_PLL_ENABLE);
1114
1115	if (intel_de_wait_for_set_ms(display, LCPLL1_CTL, LCPLL_PLL_LOCK, timeout_ms: 5))
1116	drm_err(display->drm, "DPLL0 not locked\n");
1117
1118	display->cdclk.hw.vco = vco;
1119
1120	/* We'll want to keep using the current vco from now on. */
1121	skl_set_preferred_cdclk_vco(display, vco);
1122	}
1123
1124	static void skl_dpll0_disable(struct intel_display *display)
1125	{
1126	intel_de_rmw(display, LCPLL1_CTL,
1127	LCPLL_PLL_ENABLE, set: 0);
1128
1129	if (intel_de_wait_for_clear_ms(display, LCPLL1_CTL, LCPLL_PLL_LOCK, timeout_ms: 1))
1130	drm_err(display->drm, "Couldn't disable DPLL0\n");
1131
1132	display->cdclk.hw.vco = 0;
1133	}
1134
1135	static u32 skl_cdclk_freq_sel(struct intel_display *display,
1136	int cdclk, int vco)
1137	{
1138	switch (cdclk) {
1139	default:
1140	drm_WARN_ON(display->drm,
1141	cdclk != display->cdclk.hw.bypass);
1142	drm_WARN_ON(display->drm, vco != 0);
1143	fallthrough;
1144	case 308571:
1145	case 337500:
1146	return CDCLK_FREQ_337_308;
1147	case 450000:
1148	case 432000:
1149	return CDCLK_FREQ_450_432;
1150	case 540000:
1151	return CDCLK_FREQ_540;
1152	case 617143:
1153	case 675000:
1154	return CDCLK_FREQ_675_617;
1155	}
1156	}
1157
1158	static void skl_set_cdclk(struct intel_display *display,
1159	const struct intel_cdclk_config *cdclk_config,
1160	enum pipe pipe)
1161	{
1162	int cdclk = cdclk_config->cdclk;
1163	int vco = cdclk_config->vco;
1164	u32 freq_select, cdclk_ctl;
1165	int ret;
1166
1167	/*
1168	* Based on WA#1183 CDCLK rates 308 and 617MHz CDCLK rates are
1169	* unsupported on SKL. In theory this should never happen since only
1170	* the eDP1.4 2.16 and 4.32Gbps rates require it, but eDP1.4 is not
1171	* supported on SKL either, see the above WA. WARN whenever trying to
1172	* use the corresponding VCO freq as that always leads to using the
1173	* minimum 308MHz CDCLK.
1174	*/
1175	drm_WARN_ON_ONCE(display->drm,
1176	display->platform.skylake && vco == 8640000);
1177
1178	ret = intel_pcode_request(drm: display->drm, SKL_PCODE_CDCLK_CONTROL,
1179	SKL_CDCLK_PREPARE_FOR_CHANGE,
1180	SKL_CDCLK_READY_FOR_CHANGE,
1181	SKL_CDCLK_READY_FOR_CHANGE, timeout_base_ms: 3);
1182	if (ret) {
1183	drm_err(display->drm,
1184	"Failed to inform PCU about cdclk change (%d)\n", ret);
1185	return;
1186	}
1187
1188	freq_select = skl_cdclk_freq_sel(display, cdclk, vco);
1189
1190	if (display->cdclk.hw.vco != 0 &&
1191	display->cdclk.hw.vco != vco)
1192	skl_dpll0_disable(display);
1193
1194	cdclk_ctl = intel_de_read(display, CDCLK_CTL);
1195
1196	if (display->cdclk.hw.vco != vco) {
1197	/* Wa Display #1183: skl,kbl,cfl */
1198	cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
1199	cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
1200	intel_de_write(display, CDCLK_CTL, val: cdclk_ctl);
1201	}
1202
1203	/* Wa Display #1183: skl,kbl,cfl */
1204	cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE;
1205	intel_de_write(display, CDCLK_CTL, val: cdclk_ctl);
1206	intel_de_posting_read(display, CDCLK_CTL);
1207
1208	if (display->cdclk.hw.vco != vco)
1209	skl_dpll0_enable(display, vco);
1210
1211	/* Wa Display #1183: skl,kbl,cfl */
1212	cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
1213	intel_de_write(display, CDCLK_CTL, val: cdclk_ctl);
1214
1215	cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
1216	intel_de_write(display, CDCLK_CTL, val: cdclk_ctl);
1217
1218	/* Wa Display #1183: skl,kbl,cfl */
1219	cdclk_ctl &= ~CDCLK_DIVMUX_CD_OVERRIDE;
1220	intel_de_write(display, CDCLK_CTL, val: cdclk_ctl);
1221	intel_de_posting_read(display, CDCLK_CTL);
1222
1223	/* inform PCU of the change */
1224	intel_pcode_write(display->drm, SKL_PCODE_CDCLK_CONTROL,
1225	cdclk_config->voltage_level);
1226
1227	intel_update_cdclk(display);
1228	}
1229
1230	static void skl_sanitize_cdclk(struct intel_display *display)
1231	{
1232	u32 cdctl, expected;
1233
1234	/*
1235	* check if the pre-os initialized the display
1236	* There is SWF18 scratchpad register defined which is set by the
1237	* pre-os which can be used by the OS drivers to check the status
1238	*/
1239	if ((intel_de_read(display, SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
1240	goto sanitize;
1241
1242	intel_update_cdclk(display);
1243	intel_cdclk_dump_config(display, cdclk_config: &display->cdclk.hw, context: "Current CDCLK");
1244
1245	/* Is PLL enabled and locked ? */
1246	if (display->cdclk.hw.vco == 0 ||
1247	display->cdclk.hw.cdclk == display->cdclk.hw.bypass)
1248	goto sanitize;
1249
1250	/* DPLL okay; verify the cdclock
1251	*
1252	* Noticed in some instances that the freq selection is correct but
1253	* decimal part is programmed wrong from BIOS where pre-os does not
1254	* enable display. Verify the same as well.
1255	*/
1256	cdctl = intel_de_read(display, CDCLK_CTL);
1257	expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
1258	skl_cdclk_decimal(cdclk: display->cdclk.hw.cdclk);
1259	if (cdctl == expected)
1260	/* All well; nothing to sanitize */
1261	return;
1262
1263	sanitize:
1264	drm_dbg_kms(display->drm, "Sanitizing cdclk programmed by pre-os\n");
1265
1266	/* force cdclk programming */
1267	display->cdclk.hw.cdclk = 0;
1268	/* force full PLL disable + enable */
1269	display->cdclk.hw.vco = ~0;
1270	}
1271
1272	static void skl_cdclk_init_hw(struct intel_display *display)
1273	{
1274	struct intel_cdclk_config cdclk_config;
1275
1276	skl_sanitize_cdclk(display);
1277
1278	if (display->cdclk.hw.cdclk != 0 &&
1279	display->cdclk.hw.vco != 0) {
1280	/*
1281	* Use the current vco as our initial
1282	* guess as to what the preferred vco is.
1283	*/
1284	if (display->cdclk.skl_preferred_vco_freq == 0)
1285	skl_set_preferred_cdclk_vco(display,
1286	vco: display->cdclk.hw.vco);
1287	return;
1288	}
1289
1290	cdclk_config = display->cdclk.hw;
1291
1292	cdclk_config.vco = display->cdclk.skl_preferred_vco_freq;
1293	if (cdclk_config.vco == 0)
1294	cdclk_config.vco = 8100000;
1295	cdclk_config.cdclk = skl_calc_cdclk(min_cdclk: 0, vco: cdclk_config.vco);
1296	cdclk_config.voltage_level = skl_calc_voltage_level(cdclk: cdclk_config.cdclk);
1297
1298	skl_set_cdclk(display, cdclk_config: &cdclk_config, pipe: INVALID_PIPE);
1299	}
1300
1301	static void skl_cdclk_uninit_hw(struct intel_display *display)
1302	{
1303	struct intel_cdclk_config cdclk_config = display->cdclk.hw;
1304
1305	cdclk_config.cdclk = cdclk_config.bypass;
1306	cdclk_config.vco = 0;
1307	cdclk_config.voltage_level = skl_calc_voltage_level(cdclk: cdclk_config.cdclk);
1308
1309	skl_set_cdclk(display, cdclk_config: &cdclk_config, pipe: INVALID_PIPE);
1310	}
1311
1312	struct intel_cdclk_vals {
1313	u32 cdclk;
1314	u16 refclk;
1315	u16 waveform;
1316	u8 ratio;
1317	};
1318
1319	static const struct intel_cdclk_vals bxt_cdclk_table[] = {
1320	{ .refclk = 19200, .cdclk = 144000, .ratio = 60 },
1321	{ .refclk = 19200, .cdclk = 288000, .ratio = 60 },
1322	{ .refclk = 19200, .cdclk = 384000, .ratio = 60 },
1323	{ .refclk = 19200, .cdclk = 576000, .ratio = 60 },
1324	{ .refclk = 19200, .cdclk = 624000, .ratio = 65 },
1325	{}
1326	};
1327
1328	static const struct intel_cdclk_vals glk_cdclk_table[] = {
1329	{ .refclk = 19200, .cdclk = 79200, .ratio = 33 },
1330	{ .refclk = 19200, .cdclk = 158400, .ratio = 33 },
1331	{ .refclk = 19200, .cdclk = 316800, .ratio = 33 },
1332	{}
1333	};
1334
1335	static const struct intel_cdclk_vals icl_cdclk_table[] = {
1336	{ .refclk = 19200, .cdclk = 172800, .ratio = 18 },
1337	{ .refclk = 19200, .cdclk = 192000, .ratio = 20 },
1338	{ .refclk = 19200, .cdclk = 307200, .ratio = 32 },
1339	{ .refclk = 19200, .cdclk = 326400, .ratio = 68 },
1340	{ .refclk = 19200, .cdclk = 556800, .ratio = 58 },
1341	{ .refclk = 19200, .cdclk = 652800, .ratio = 68 },
1342
1343	{ .refclk = 24000, .cdclk = 180000, .ratio = 15 },
1344	{ .refclk = 24000, .cdclk = 192000, .ratio = 16 },
1345	{ .refclk = 24000, .cdclk = 312000, .ratio = 26 },
1346	{ .refclk = 24000, .cdclk = 324000, .ratio = 54 },
1347	{ .refclk = 24000, .cdclk = 552000, .ratio = 46 },
1348	{ .refclk = 24000, .cdclk = 648000, .ratio = 54 },
1349
1350	{ .refclk = 38400, .cdclk = 172800, .ratio = 9 },
1351	{ .refclk = 38400, .cdclk = 192000, .ratio = 10 },
1352	{ .refclk = 38400, .cdclk = 307200, .ratio = 16 },
1353	{ .refclk = 38400, .cdclk = 326400, .ratio = 34 },
1354	{ .refclk = 38400, .cdclk = 556800, .ratio = 29 },
1355	{ .refclk = 38400, .cdclk = 652800, .ratio = 34 },
1356	{}
1357	};
1358
1359	static const struct intel_cdclk_vals rkl_cdclk_table[] = {
1360	{ .refclk = 19200, .cdclk = 172800, .ratio = 36 },
1361	{ .refclk = 19200, .cdclk = 192000, .ratio = 40 },
1362	{ .refclk = 19200, .cdclk = 307200, .ratio = 64 },
1363	{ .refclk = 19200, .cdclk = 326400, .ratio = 136 },
1364	{ .refclk = 19200, .cdclk = 556800, .ratio = 116 },
1365	{ .refclk = 19200, .cdclk = 652800, .ratio = 136 },
1366
1367	{ .refclk = 24000, .cdclk = 180000, .ratio = 30 },
1368	{ .refclk = 24000, .cdclk = 192000, .ratio = 32 },
1369	{ .refclk = 24000, .cdclk = 312000, .ratio = 52 },
1370	{ .refclk = 24000, .cdclk = 324000, .ratio = 108 },
1371	{ .refclk = 24000, .cdclk = 552000, .ratio = 92 },
1372	{ .refclk = 24000, .cdclk = 648000, .ratio = 108 },
1373
1374	{ .refclk = 38400, .cdclk = 172800, .ratio = 18 },
1375	{ .refclk = 38400, .cdclk = 192000, .ratio = 20 },
1376	{ .refclk = 38400, .cdclk = 307200, .ratio = 32 },
1377	{ .refclk = 38400, .cdclk = 326400, .ratio = 68 },
1378	{ .refclk = 38400, .cdclk = 556800, .ratio = 58 },
1379	{ .refclk = 38400, .cdclk = 652800, .ratio = 68 },
1380	{}
1381	};
1382
1383	static const struct intel_cdclk_vals adlp_a_step_cdclk_table[] = {
1384	{ .refclk = 19200, .cdclk = 307200, .ratio = 32 },
1385	{ .refclk = 19200, .cdclk = 556800, .ratio = 58 },
1386	{ .refclk = 19200, .cdclk = 652800, .ratio = 68 },
1387
1388	{ .refclk = 24000, .cdclk = 312000, .ratio = 26 },
1389	{ .refclk = 24000, .cdclk = 552000, .ratio = 46 },
1390	{ .refclk = 24400, .cdclk = 648000, .ratio = 54 },
1391
1392	{ .refclk = 38400, .cdclk = 307200, .ratio = 16 },
1393	{ .refclk = 38400, .cdclk = 556800, .ratio = 29 },
1394	{ .refclk = 38400, .cdclk = 652800, .ratio = 34 },
1395	{}
1396	};
1397
1398	static const struct intel_cdclk_vals adlp_cdclk_table[] = {
1399	{ .refclk = 19200, .cdclk = 172800, .ratio = 27 },
1400	{ .refclk = 19200, .cdclk = 192000, .ratio = 20 },
1401	{ .refclk = 19200, .cdclk = 307200, .ratio = 32 },
1402	{ .refclk = 19200, .cdclk = 556800, .ratio = 58 },
1403	{ .refclk = 19200, .cdclk = 652800, .ratio = 68 },
1404
1405	{ .refclk = 24000, .cdclk = 176000, .ratio = 22 },
1406	{ .refclk = 24000, .cdclk = 192000, .ratio = 16 },
1407	{ .refclk = 24000, .cdclk = 312000, .ratio = 26 },
1408	{ .refclk = 24000, .cdclk = 552000, .ratio = 46 },
1409	{ .refclk = 24000, .cdclk = 648000, .ratio = 54 },
1410
1411	{ .refclk = 38400, .cdclk = 179200, .ratio = 14 },
1412	{ .refclk = 38400, .cdclk = 192000, .ratio = 10 },
1413	{ .refclk = 38400, .cdclk = 307200, .ratio = 16 },
1414	{ .refclk = 38400, .cdclk = 556800, .ratio = 29 },
1415	{ .refclk = 38400, .cdclk = 652800, .ratio = 34 },
1416	{}
1417	};
1418
1419	static const struct intel_cdclk_vals rplu_cdclk_table[] = {
1420	{ .refclk = 19200, .cdclk = 172800, .ratio = 27 },
1421	{ .refclk = 19200, .cdclk = 192000, .ratio = 20 },
1422	{ .refclk = 19200, .cdclk = 307200, .ratio = 32 },
1423	{ .refclk = 19200, .cdclk = 480000, .ratio = 50 },
1424	{ .refclk = 19200, .cdclk = 556800, .ratio = 58 },
1425	{ .refclk = 19200, .cdclk = 652800, .ratio = 68 },
1426
1427	{ .refclk = 24000, .cdclk = 176000, .ratio = 22 },
1428	{ .refclk = 24000, .cdclk = 192000, .ratio = 16 },
1429	{ .refclk = 24000, .cdclk = 312000, .ratio = 26 },
1430	{ .refclk = 24000, .cdclk = 480000, .ratio = 40 },
1431	{ .refclk = 24000, .cdclk = 552000, .ratio = 46 },
1432	{ .refclk = 24000, .cdclk = 648000, .ratio = 54 },
1433
1434	{ .refclk = 38400, .cdclk = 179200, .ratio = 14 },
1435	{ .refclk = 38400, .cdclk = 192000, .ratio = 10 },
1436	{ .refclk = 38400, .cdclk = 307200, .ratio = 16 },
1437	{ .refclk = 38400, .cdclk = 480000, .ratio = 25 },
1438	{ .refclk = 38400, .cdclk = 556800, .ratio = 29 },
1439	{ .refclk = 38400, .cdclk = 652800, .ratio = 34 },
1440	{}
1441	};
1442
1443	static const struct intel_cdclk_vals dg2_cdclk_table[] = {
1444	{ .refclk = 38400, .cdclk = 163200, .ratio = 34, .waveform = 0x8888 },
1445	{ .refclk = 38400, .cdclk = 204000, .ratio = 34, .waveform = 0x9248 },
1446	{ .refclk = 38400, .cdclk = 244800, .ratio = 34, .waveform = 0xa4a4 },
1447	{ .refclk = 38400, .cdclk = 285600, .ratio = 34, .waveform = 0xa54a },
1448	{ .refclk = 38400, .cdclk = 326400, .ratio = 34, .waveform = 0xaaaa },
1449	{ .refclk = 38400, .cdclk = 367200, .ratio = 34, .waveform = 0xad5a },
1450	{ .refclk = 38400, .cdclk = 408000, .ratio = 34, .waveform = 0xb6b6 },
1451	{ .refclk = 38400, .cdclk = 448800, .ratio = 34, .waveform = 0xdbb6 },
1452	{ .refclk = 38400, .cdclk = 489600, .ratio = 34, .waveform = 0xeeee },
1453	{ .refclk = 38400, .cdclk = 530400, .ratio = 34, .waveform = 0xf7de },
1454	{ .refclk = 38400, .cdclk = 571200, .ratio = 34, .waveform = 0xfefe },
1455	{ .refclk = 38400, .cdclk = 612000, .ratio = 34, .waveform = 0xfffe },
1456	{ .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
1457	{}
1458	};
1459
1460	static const struct intel_cdclk_vals mtl_cdclk_table[] = {
1461	{ .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a },
1462	{ .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 },
1463	{ .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0x0000 },
1464	{ .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0x0000 },
1465	{ .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0x0000 },
1466	{ .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0x0000 },
1467	{}
1468	};
1469
1470	static const struct intel_cdclk_vals xe2lpd_cdclk_table[] = {
1471	{ .refclk = 38400, .cdclk = 153600, .ratio = 16, .waveform = 0xaaaa },
1472	{ .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a },
1473	{ .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 },
1474	{ .refclk = 38400, .cdclk = 211200, .ratio = 16, .waveform = 0xdbb6 },
1475	{ .refclk = 38400, .cdclk = 230400, .ratio = 16, .waveform = 0xeeee },
1476	{ .refclk = 38400, .cdclk = 249600, .ratio = 16, .waveform = 0xf7de },
1477	{ .refclk = 38400, .cdclk = 268800, .ratio = 16, .waveform = 0xfefe },
1478	{ .refclk = 38400, .cdclk = 288000, .ratio = 16, .waveform = 0xfffe },
1479	{ .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0xffff },
1480	{ .refclk = 38400, .cdclk = 330000, .ratio = 25, .waveform = 0xdbb6 },
1481	{ .refclk = 38400, .cdclk = 360000, .ratio = 25, .waveform = 0xeeee },
1482	{ .refclk = 38400, .cdclk = 390000, .ratio = 25, .waveform = 0xf7de },
1483	{ .refclk = 38400, .cdclk = 420000, .ratio = 25, .waveform = 0xfefe },
1484	{ .refclk = 38400, .cdclk = 450000, .ratio = 25, .waveform = 0xfffe },
1485	{ .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0xffff },
1486	{ .refclk = 38400, .cdclk = 487200, .ratio = 29, .waveform = 0xfefe },
1487	{ .refclk = 38400, .cdclk = 522000, .ratio = 29, .waveform = 0xfffe },
1488	{ .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0xffff },
1489	{ .refclk = 38400, .cdclk = 571200, .ratio = 34, .waveform = 0xfefe },
1490	{ .refclk = 38400, .cdclk = 612000, .ratio = 34, .waveform = 0xfffe },
1491	{ .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
1492	{}
1493	};
1494
1495	/*
1496	* Xe2_HPD always uses the minimal cdclk table from Wa_15015413771
1497	*/
1498	static const struct intel_cdclk_vals xe2hpd_cdclk_table[] = {
1499	{ .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
1500	{}
1501	};
1502
1503	static const struct intel_cdclk_vals xe3lpd_cdclk_table[] = {
1504	{ .refclk = 38400, .cdclk = 153600, .ratio = 16, .waveform = 0xaaaa },
1505	{ .refclk = 38400, .cdclk = 172800, .ratio = 16, .waveform = 0xad5a },
1506	{ .refclk = 38400, .cdclk = 192000, .ratio = 16, .waveform = 0xb6b6 },
1507	{ .refclk = 38400, .cdclk = 211200, .ratio = 16, .waveform = 0xdbb6 },
1508	{ .refclk = 38400, .cdclk = 230400, .ratio = 16, .waveform = 0xeeee },
1509	{ .refclk = 38400, .cdclk = 249600, .ratio = 16, .waveform = 0xf7de },
1510	{ .refclk = 38400, .cdclk = 268800, .ratio = 16, .waveform = 0xfefe },
1511	{ .refclk = 38400, .cdclk = 288000, .ratio = 16, .waveform = 0xfffe },
1512	{ .refclk = 38400, .cdclk = 307200, .ratio = 16, .waveform = 0xffff },
1513	{ .refclk = 38400, .cdclk = 326400, .ratio = 17, .waveform = 0xffff },
1514	{ .refclk = 38400, .cdclk = 345600, .ratio = 18, .waveform = 0xffff },
1515	{ .refclk = 38400, .cdclk = 364800, .ratio = 19, .waveform = 0xffff },
1516	{ .refclk = 38400, .cdclk = 384000, .ratio = 20, .waveform = 0xffff },
1517	{ .refclk = 38400, .cdclk = 403200, .ratio = 21, .waveform = 0xffff },
1518	{ .refclk = 38400, .cdclk = 422400, .ratio = 22, .waveform = 0xffff },
1519	{ .refclk = 38400, .cdclk = 441600, .ratio = 23, .waveform = 0xffff },
1520	{ .refclk = 38400, .cdclk = 460800, .ratio = 24, .waveform = 0xffff },
1521	{ .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0xffff },
1522	{ .refclk = 38400, .cdclk = 499200, .ratio = 26, .waveform = 0xffff },
1523	{ .refclk = 38400, .cdclk = 518400, .ratio = 27, .waveform = 0xffff },
1524	{ .refclk = 38400, .cdclk = 537600, .ratio = 28, .waveform = 0xffff },
1525	{ .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0xffff },
1526	{ .refclk = 38400, .cdclk = 576000, .ratio = 30, .waveform = 0xffff },
1527	{ .refclk = 38400, .cdclk = 595200, .ratio = 31, .waveform = 0xffff },
1528	{ .refclk = 38400, .cdclk = 614400, .ratio = 32, .waveform = 0xffff },
1529	{ .refclk = 38400, .cdclk = 633600, .ratio = 33, .waveform = 0xffff },
1530	{ .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
1531	{ .refclk = 38400, .cdclk = 672000, .ratio = 35, .waveform = 0xffff },
1532	{ .refclk = 38400, .cdclk = 691200, .ratio = 36, .waveform = 0xffff },
1533	{}
1534	};
1535
1536	static const struct intel_cdclk_vals xe3p_lpd_cdclk_table[] = {
1537	{ .refclk = 38400, .cdclk = 151200, .ratio = 21, .waveform = 0xa4a4 },
1538	{ .refclk = 38400, .cdclk = 176400, .ratio = 21, .waveform = 0xaa54 },
1539	{ .refclk = 38400, .cdclk = 201600, .ratio = 21, .waveform = 0xaaaa },
1540	{ .refclk = 38400, .cdclk = 226800, .ratio = 21, .waveform = 0xad5a },
1541	{ .refclk = 38400, .cdclk = 252000, .ratio = 21, .waveform = 0xb6b6 },
1542	{ .refclk = 38400, .cdclk = 277200, .ratio = 21, .waveform = 0xdbb6 },
1543	{ .refclk = 38400, .cdclk = 302400, .ratio = 21, .waveform = 0xeeee },
1544	{ .refclk = 38400, .cdclk = 327600, .ratio = 21, .waveform = 0xf7de },
1545	{ .refclk = 38400, .cdclk = 352800, .ratio = 21, .waveform = 0xfefe },
1546	{ .refclk = 38400, .cdclk = 378000, .ratio = 21, .waveform = 0xfffe },
1547	{ .refclk = 38400, .cdclk = 403200, .ratio = 21, .waveform = 0xffff },
1548	{ .refclk = 38400, .cdclk = 422400, .ratio = 22, .waveform = 0xffff },
1549	{ .refclk = 38400, .cdclk = 441600, .ratio = 23, .waveform = 0xffff },
1550	{ .refclk = 38400, .cdclk = 460800, .ratio = 24, .waveform = 0xffff },
1551	{ .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0xffff },
1552	{ .refclk = 38400, .cdclk = 499200, .ratio = 26, .waveform = 0xffff },
1553	{ .refclk = 38400, .cdclk = 518400, .ratio = 27, .waveform = 0xffff },
1554	{ .refclk = 38400, .cdclk = 537600, .ratio = 28, .waveform = 0xffff },
1555	{ .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0xffff },
1556	{ .refclk = 38400, .cdclk = 576000, .ratio = 30, .waveform = 0xffff },
1557	{ .refclk = 38400, .cdclk = 595200, .ratio = 31, .waveform = 0xffff },
1558	{ .refclk = 38400, .cdclk = 614400, .ratio = 32, .waveform = 0xffff },
1559	{ .refclk = 38400, .cdclk = 633600, .ratio = 33, .waveform = 0xffff },
1560	{ .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
1561	{ .refclk = 38400, .cdclk = 672000, .ratio = 35, .waveform = 0xffff },
1562	{ .refclk = 38400, .cdclk = 691200, .ratio = 36, .waveform = 0xffff },
1563	{ .refclk = 38400, .cdclk = 710400, .ratio = 37, .waveform = 0xffff },
1564	{ .refclk = 38400, .cdclk = 729600, .ratio = 38, .waveform = 0xffff },
1565	{ .refclk = 38400, .cdclk = 748800, .ratio = 39, .waveform = 0xffff },
1566	{ .refclk = 38400, .cdclk = 768000, .ratio = 40, .waveform = 0xffff },
1567	{ .refclk = 38400, .cdclk = 787200, .ratio = 41, .waveform = 0xffff },
1568	{}
1569	};
1570
1571	static const int cdclk_squash_len = 16;
1572
1573	static int cdclk_squash_divider(u16 waveform)
1574	{
1575	return hweight16(waveform ?: 0xffff);
1576	}
1577
1578	static int cdclk_divider(int cdclk, int vco, u16 waveform)
1579	{
1580	/* 2 * cd2x divider */
1581	return DIV_ROUND_CLOSEST(vco * cdclk_squash_divider(waveform),
1582	cdclk * cdclk_squash_len);
1583	}
1584
1585	static int bxt_calc_cdclk(struct intel_display *display, int min_cdclk)
1586	{
1587	const struct intel_cdclk_vals *table = display->cdclk.table;
1588	int i;
1589
1590	for (i = 0; table[i].refclk; i++)
1591	if (table[i].refclk == display->cdclk.hw.ref &&
1592	table[i].cdclk >= min_cdclk)
1593	return table[i].cdclk;
1594
1595	drm_WARN(display->drm, 1,
1596	"Cannot satisfy minimum cdclk %d with refclk %u\n",
1597	min_cdclk, display->cdclk.hw.ref);
1598	return display->cdclk.max_cdclk_freq;
1599	}
1600
1601	static int bxt_calc_cdclk_pll_vco(struct intel_display *display, int cdclk)
1602	{
1603	const struct intel_cdclk_vals *table = display->cdclk.table;
1604	int i;
1605
1606	if (cdclk == display->cdclk.hw.bypass)
1607	return 0;
1608
1609	for (i = 0; table[i].refclk; i++)
1610	if (table[i].refclk == display->cdclk.hw.ref &&
1611	table[i].cdclk == cdclk)
1612	return display->cdclk.hw.ref * table[i].ratio;
1613
1614	drm_WARN(display->drm, 1, "cdclk %d not valid for refclk %u\n",
1615	cdclk, display->cdclk.hw.ref);
1616	return 0;
1617	}
1618
1619	static u8 bxt_calc_voltage_level(int cdclk)
1620	{
1621	return DIV_ROUND_UP(cdclk, 25000);
1622	}
1623
1624	static u8 calc_voltage_level(int cdclk, int num_voltage_levels,
1625	const int voltage_level_max_cdclk[])
1626	{
1627	int voltage_level;
1628
1629	for (voltage_level = 0; voltage_level < num_voltage_levels; voltage_level++) {
1630	if (cdclk <= voltage_level_max_cdclk[voltage_level])
1631	return voltage_level;
1632	}
1633
1634	MISSING_CASE(cdclk);
1635	return num_voltage_levels - 1;
1636	}
1637
1638	static u8 icl_calc_voltage_level(int cdclk)
1639	{
1640	static const int icl_voltage_level_max_cdclk[] = {
1641	[0] = 312000,
1642	[1] = 556800,
1643	[2] = 652800,
1644	};
1645
1646	return calc_voltage_level(cdclk,
1647	ARRAY_SIZE(icl_voltage_level_max_cdclk),
1648	voltage_level_max_cdclk: icl_voltage_level_max_cdclk);
1649	}
1650
1651	static u8 ehl_calc_voltage_level(int cdclk)
1652	{
1653	static const int ehl_voltage_level_max_cdclk[] = {
1654	[0] = 180000,
1655	[1] = 312000,
1656	[2] = 326400,
1657	/*
1658	* Bspec lists the limit as 556.8 MHz, but some JSL
1659	* development boards (at least) boot with 652.8 MHz
1660	*/
1661	[3] = 652800,
1662	};
1663
1664	return calc_voltage_level(cdclk,
1665	ARRAY_SIZE(ehl_voltage_level_max_cdclk),
1666	voltage_level_max_cdclk: ehl_voltage_level_max_cdclk);
1667	}
1668
1669	static u8 tgl_calc_voltage_level(int cdclk)
1670	{
1671	static const int tgl_voltage_level_max_cdclk[] = {
1672	[0] = 312000,
1673	[1] = 326400,
1674	[2] = 556800,
1675	[3] = 652800,
1676	};
1677
1678	return calc_voltage_level(cdclk,
1679	ARRAY_SIZE(tgl_voltage_level_max_cdclk),
1680	voltage_level_max_cdclk: tgl_voltage_level_max_cdclk);
1681	}
1682
1683	static u8 rplu_calc_voltage_level(int cdclk)
1684	{
1685	static const int rplu_voltage_level_max_cdclk[] = {
1686	[0] = 312000,
1687	[1] = 480000,
1688	[2] = 556800,
1689	[3] = 652800,
1690	};
1691
1692	return calc_voltage_level(cdclk,
1693	ARRAY_SIZE(rplu_voltage_level_max_cdclk),
1694	voltage_level_max_cdclk: rplu_voltage_level_max_cdclk);
1695	}
1696
1697	static u8 xe3lpd_calc_voltage_level(int cdclk)
1698	{
1699	/*
1700	* Starting with xe3lpd power controller does not need the voltage
1701	* index when doing the modeset update. This function is best left
1702	* defined but returning 0 to the mask.
1703	*/
1704	return 0;
1705	}
1706
1707	static void icl_readout_refclk(struct intel_display *display,
1708	struct intel_cdclk_config *cdclk_config)
1709	{
1710	u32 dssm = intel_de_read(display, SKL_DSSM) & ICL_DSSM_CDCLK_PLL_REFCLK_MASK;
1711
1712	switch (dssm) {
1713	default:
1714	MISSING_CASE(dssm);
1715	fallthrough;
1716	case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz:
1717	cdclk_config->ref = 24000;
1718	break;
1719	case ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz:
1720	cdclk_config->ref = 19200;
1721	break;
1722	case ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz:
1723	cdclk_config->ref = 38400;
1724	break;
1725	}
1726	}
1727
1728	static void bxt_de_pll_readout(struct intel_display *display,
1729	struct intel_cdclk_config *cdclk_config)
1730	{
1731	u32 val, ratio;
1732
1733	if (display->platform.dg2)
1734	cdclk_config->ref = 38400;
1735	else if (DISPLAY_VER(display) >= 11)
1736	icl_readout_refclk(display, cdclk_config);
1737	else
1738	cdclk_config->ref = 19200;
1739
1740	val = intel_de_read(display, BXT_DE_PLL_ENABLE);
1741	if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 ||
1742	(val & BXT_DE_PLL_LOCK) == 0) {
1743	/*
1744	* CDCLK PLL is disabled, the VCO/ratio doesn't matter, but
1745	* setting it to zero is a way to signal that.
1746	*/
1747	cdclk_config->vco = 0;
1748	return;
1749	}
1750
1751	/*
1752	* DISPLAY_VER >= 11 have the ratio directly in the PLL enable register,
1753	* gen9lp had it in a separate PLL control register.
1754	*/
1755	if (DISPLAY_VER(display) >= 11)
1756	ratio = val & ICL_CDCLK_PLL_RATIO_MASK;
1757	else
1758	ratio = intel_de_read(display, BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
1759
1760	cdclk_config->vco = ratio * cdclk_config->ref;
1761	}
1762
1763	static void bxt_get_cdclk(struct intel_display *display,
1764	struct intel_cdclk_config *cdclk_config)
1765	{
1766	u32 squash_ctl = 0;
1767	u32 divider;
1768	int div;
1769
1770	bxt_de_pll_readout(display, cdclk_config);
1771
1772	if (DISPLAY_VER(display) >= 12)
1773	cdclk_config->bypass = cdclk_config->ref / 2;
1774	else if (DISPLAY_VER(display) >= 11)
1775	cdclk_config->bypass = 50000;
1776	else
1777	cdclk_config->bypass = cdclk_config->ref;
1778
1779	if (cdclk_config->vco == 0) {
1780	cdclk_config->cdclk = cdclk_config->bypass;
1781	goto out;
1782	}
1783
1784	divider = intel_de_read(display, CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
1785
1786	switch (divider) {
1787	case BXT_CDCLK_CD2X_DIV_SEL_1:
1788	div = 2;
1789	break;
1790	case BXT_CDCLK_CD2X_DIV_SEL_1_5:
1791	div = 3;
1792	break;
1793	case BXT_CDCLK_CD2X_DIV_SEL_2:
1794	div = 4;
1795	break;
1796	case BXT_CDCLK_CD2X_DIV_SEL_4:
1797	div = 8;
1798	break;
1799	default:
1800	MISSING_CASE(divider);
1801	return;
1802	}
1803
1804	if (HAS_CDCLK_SQUASH(display))
1805	squash_ctl = intel_de_read(display, CDCLK_SQUASH_CTL);
1806
1807	if (squash_ctl & CDCLK_SQUASH_ENABLE) {
1808	u16 waveform;
1809	int size;
1810
1811	size = REG_FIELD_GET(CDCLK_SQUASH_WINDOW_SIZE_MASK, squash_ctl) + 1;
1812	waveform = REG_FIELD_GET(CDCLK_SQUASH_WAVEFORM_MASK, squash_ctl) >> (16 - size);
1813
1814	cdclk_config->cdclk = DIV_ROUND_CLOSEST(hweight16(waveform) *
1815	cdclk_config->vco, size * div);
1816	} else {
1817	cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, div);
1818	}
1819
1820	out:
1821	if (DISPLAY_VER(display) >= 20)
1822	cdclk_config->joined_mbus = intel_de_read(display, MBUS_CTL) & MBUS_JOIN;
1823	/*
1824	* Can't read this out :( Let's assume it's
1825	* at least what the CDCLK frequency requires.
1826	*/
1827	cdclk_config->voltage_level =
1828	intel_cdclk_calc_voltage_level(display, cdclk: cdclk_config->cdclk);
1829	}
1830
1831	static void bxt_de_pll_disable(struct intel_display *display)
1832	{
1833	intel_de_write(display, BXT_DE_PLL_ENABLE, val: 0);
1834
1835	/* Timeout 200us */
1836	if (intel_de_wait_for_clear_ms(display,
1837	BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, timeout_ms: 1))
1838	drm_err(display->drm, "timeout waiting for DE PLL unlock\n");
1839
1840	display->cdclk.hw.vco = 0;
1841	}
1842
1843	static void bxt_de_pll_enable(struct intel_display *display, int vco)
1844	{
1845	int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref);
1846
1847	intel_de_rmw(display, BXT_DE_PLL_CTL,
1848	BXT_DE_PLL_RATIO_MASK, BXT_DE_PLL_RATIO(ratio));
1849
1850	intel_de_write(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
1851
1852	/* Timeout 200us */
1853	if (intel_de_wait_for_set_ms(display,
1854	BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, timeout_ms: 1))
1855	drm_err(display->drm, "timeout waiting for DE PLL lock\n");
1856
1857	display->cdclk.hw.vco = vco;
1858	}
1859
1860	static void icl_cdclk_pll_disable(struct intel_display *display)
1861	{
1862	intel_de_rmw(display, BXT_DE_PLL_ENABLE,
1863	BXT_DE_PLL_PLL_ENABLE, set: 0);
1864
1865	/* Timeout 200us */
1866	if (intel_de_wait_for_clear_ms(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, timeout_ms: 1))
1867	drm_err(display->drm, "timeout waiting for CDCLK PLL unlock\n");
1868
1869	display->cdclk.hw.vco = 0;
1870	}
1871
1872	static void icl_cdclk_pll_enable(struct intel_display *display, int vco)
1873	{
1874	int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref);
1875	u32 val;
1876
1877	val = ICL_CDCLK_PLL_RATIO(ratio);
1878	intel_de_write(display, BXT_DE_PLL_ENABLE, val);
1879
1880	val |= BXT_DE_PLL_PLL_ENABLE;
1881	intel_de_write(display, BXT_DE_PLL_ENABLE, val);
1882
1883	/* Timeout 200us */
1884	if (intel_de_wait_for_set_ms(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, timeout_ms: 1))
1885	drm_err(display->drm, "timeout waiting for CDCLK PLL lock\n");
1886
1887	display->cdclk.hw.vco = vco;
1888	}
1889
1890	static void adlp_cdclk_pll_crawl(struct intel_display *display, int vco)
1891	{
1892	int ratio = DIV_ROUND_CLOSEST(vco, display->cdclk.hw.ref);
1893	u32 val;
1894
1895	/* Write PLL ratio without disabling */
1896	val = ICL_CDCLK_PLL_RATIO(ratio) | BXT_DE_PLL_PLL_ENABLE;
1897	intel_de_write(display, BXT_DE_PLL_ENABLE, val);
1898
1899	/* Submit freq change request */
1900	val |= BXT_DE_PLL_FREQ_REQ;
1901	intel_de_write(display, BXT_DE_PLL_ENABLE, val);
1902
1903	/* Timeout 200us */
1904	if (intel_de_wait_for_set_ms(display, BXT_DE_PLL_ENABLE,
1905	BXT_DE_PLL_LOCK | BXT_DE_PLL_FREQ_REQ_ACK, timeout_ms: 1))
1906	drm_err(display->drm, "timeout waiting for FREQ change request ack\n");
1907
1908	val &= ~BXT_DE_PLL_FREQ_REQ;
1909	intel_de_write(display, BXT_DE_PLL_ENABLE, val);
1910
1911	display->cdclk.hw.vco = vco;
1912	}
1913
1914	static u32 bxt_cdclk_cd2x_pipe(struct intel_display *display, enum pipe pipe)
1915	{
1916	if (DISPLAY_VER(display) >= 12) {
1917	if (pipe == INVALID_PIPE)
1918	return TGL_CDCLK_CD2X_PIPE_NONE;
1919	else
1920	return TGL_CDCLK_CD2X_PIPE(pipe);
1921	} else if (DISPLAY_VER(display) >= 11) {
1922	if (pipe == INVALID_PIPE)
1923	return ICL_CDCLK_CD2X_PIPE_NONE;
1924	else
1925	return ICL_CDCLK_CD2X_PIPE(pipe);
1926	} else {
1927	if (pipe == INVALID_PIPE)
1928	return BXT_CDCLK_CD2X_PIPE_NONE;
1929	else
1930	return BXT_CDCLK_CD2X_PIPE(pipe);
1931	}
1932	}
1933
1934	static u32 bxt_cdclk_cd2x_div_sel(struct intel_display *display,
1935	int cdclk, int vco, u16 waveform)
1936	{
1937	/* cdclk = vco / 2 / div{1,1.5,2,4} */
1938	switch (cdclk_divider(cdclk, vco, waveform)) {
1939	default:
1940	drm_WARN_ON(display->drm,
1941	cdclk != display->cdclk.hw.bypass);
1942	drm_WARN_ON(display->drm, vco != 0);
1943	fallthrough;
1944	case 2:
1945	return BXT_CDCLK_CD2X_DIV_SEL_1;
1946	case 3:
1947	return BXT_CDCLK_CD2X_DIV_SEL_1_5;
1948	case 4:
1949	return BXT_CDCLK_CD2X_DIV_SEL_2;
1950	case 8:
1951	return BXT_CDCLK_CD2X_DIV_SEL_4;
1952	}
1953	}
1954
1955	static u16 cdclk_squash_waveform(struct intel_display *display,
1956	int cdclk)
1957	{
1958	const struct intel_cdclk_vals *table = display->cdclk.table;
1959	int i;
1960
1961	if (cdclk == display->cdclk.hw.bypass)
1962	return 0;
1963
1964	for (i = 0; table[i].refclk; i++)
1965	if (table[i].refclk == display->cdclk.hw.ref &&
1966	table[i].cdclk == cdclk)
1967	return table[i].waveform;
1968
1969	drm_WARN(display->drm, 1, "cdclk %d not valid for refclk %u\n",
1970	cdclk, display->cdclk.hw.ref);
1971
1972	return 0xffff;
1973	}
1974
1975	static void icl_cdclk_pll_update(struct intel_display *display, int vco)
1976	{
1977	if (display->cdclk.hw.vco != 0 &&
1978	display->cdclk.hw.vco != vco)
1979	icl_cdclk_pll_disable(display);
1980
1981	if (display->cdclk.hw.vco != vco)
1982	icl_cdclk_pll_enable(display, vco);
1983	}
1984
1985	static void bxt_cdclk_pll_update(struct intel_display *display, int vco)
1986	{
1987	if (display->cdclk.hw.vco != 0 &&
1988	display->cdclk.hw.vco != vco)
1989	bxt_de_pll_disable(display);
1990
1991	if (display->cdclk.hw.vco != vco)
1992	bxt_de_pll_enable(display, vco);
1993	}
1994
1995	static void dg2_cdclk_squash_program(struct intel_display *display,
1996	u16 waveform)
1997	{
1998	u32 squash_ctl = 0;
1999
2000	if (waveform)
2001	squash_ctl = CDCLK_SQUASH_ENABLE |
2002	CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform;
2003
2004	intel_de_write(display, CDCLK_SQUASH_CTL, val: squash_ctl);
2005	}
2006
2007	static bool cdclk_pll_is_unknown(unsigned int vco)
2008	{
2009	/*
2010	* Ensure driver does not take the crawl path for the
2011	* case when the vco is set to ~0 in the
2012	* sanitize path.
2013	*/
2014	return vco == ~0;
2015	}
2016
2017	static bool mdclk_source_is_cdclk_pll(struct intel_display *display)
2018	{
2019	return DISPLAY_VER(display) >= 20;
2020	}
2021
2022	static u32 xe2lpd_mdclk_source_sel(struct intel_display *display)
2023	{
2024	if (mdclk_source_is_cdclk_pll(display))
2025	return MDCLK_SOURCE_SEL_CDCLK_PLL;
2026
2027	return MDCLK_SOURCE_SEL_CD2XCLK;
2028	}
2029
2030	int intel_mdclk_cdclk_ratio(struct intel_display *display,
2031	const struct intel_cdclk_config *cdclk_config)
2032	{
2033	if (mdclk_source_is_cdclk_pll(display))
2034	return DIV_ROUND_UP(cdclk_config->vco, cdclk_config->cdclk);
2035
2036	/* Otherwise, source for MDCLK is CD2XCLK. */
2037	return 2;
2038	}
2039
2040	static void xe2lpd_mdclk_cdclk_ratio_program(struct intel_display *display,
2041	const struct intel_cdclk_config *cdclk_config)
2042	{
2043	intel_dbuf_mdclk_cdclk_ratio_update(display,
2044	ratio: intel_mdclk_cdclk_ratio(display, cdclk_config),
2045	joined_mbus: cdclk_config->joined_mbus);
2046	}
2047
2048	static bool cdclk_compute_crawl_and_squash_midpoint(struct intel_display *display,
2049	const struct intel_cdclk_config *old_cdclk_config,
2050	const struct intel_cdclk_config *new_cdclk_config,
2051	struct intel_cdclk_config *mid_cdclk_config)
2052	{
2053	u16 old_waveform, new_waveform, mid_waveform;
2054	int old_div, new_div, mid_div;
2055
2056	/* Return if PLL is in an unknown state, force a complete disable and re-enable. */
2057	if (cdclk_pll_is_unknown(vco: old_cdclk_config->vco))
2058	return false;
2059
2060	/* Return if both Squash and Crawl are not present */
2061	if (!HAS_CDCLK_CRAWL(display) || !HAS_CDCLK_SQUASH(display))
2062	return false;
2063
2064	old_waveform = cdclk_squash_waveform(display, cdclk: old_cdclk_config->cdclk);
2065	new_waveform = cdclk_squash_waveform(display, cdclk: new_cdclk_config->cdclk);
2066
2067	/* Return if Squash only or Crawl only is the desired action */
2068	if (old_cdclk_config->vco == 0 || new_cdclk_config->vco == 0 ||
2069	old_cdclk_config->vco == new_cdclk_config->vco ||
2070	old_waveform == new_waveform)
2071	return false;
2072
2073	old_div = cdclk_divider(cdclk: old_cdclk_config->cdclk,
2074	vco: old_cdclk_config->vco, waveform: old_waveform);
2075	new_div = cdclk_divider(cdclk: new_cdclk_config->cdclk,
2076	vco: new_cdclk_config->vco, waveform: new_waveform);
2077
2078	/*
2079	* Should not happen currently. We might need more midpoint
2080	* transitions if we need to also change the cd2x divider.
2081	*/
2082	if (drm_WARN_ON(display->drm, old_div != new_div))
2083	return false;
2084
2085	*mid_cdclk_config = *new_cdclk_config;
2086
2087	/*
2088	* Populate the mid_cdclk_config accordingly.
2089	* - If moving to a higher cdclk, the desired action is squashing.
2090	* The mid cdclk config should have the new (squash) waveform.
2091	* - If moving to a lower cdclk, the desired action is crawling.
2092	* The mid cdclk config should have the new vco.
2093	*/
2094
2095	if (cdclk_squash_divider(waveform: new_waveform) > cdclk_squash_divider(waveform: old_waveform)) {
2096	mid_cdclk_config->vco = old_cdclk_config->vco;
2097	mid_div = old_div;
2098	mid_waveform = new_waveform;
2099	} else {
2100	mid_cdclk_config->vco = new_cdclk_config->vco;
2101	mid_div = new_div;
2102	mid_waveform = old_waveform;
2103	}
2104
2105	mid_cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_squash_divider(mid_waveform) *
2106	mid_cdclk_config->vco,
2107	cdclk_squash_len * mid_div);
2108
2109	/* make sure the mid clock came out sane */
2110
2111	drm_WARN_ON(display->drm, mid_cdclk_config->cdclk <
2112	min(old_cdclk_config->cdclk, new_cdclk_config->cdclk));
2113	drm_WARN_ON(display->drm, mid_cdclk_config->cdclk >
2114	display->cdclk.max_cdclk_freq);
2115	drm_WARN_ON(display->drm, cdclk_squash_waveform(display, mid_cdclk_config->cdclk) !=
2116	mid_waveform);
2117
2118	return true;
2119	}
2120
2121	static bool pll_enable_wa_needed(struct intel_display *display)
2122	{
2123	return (DISPLAY_VERx100(display) == 2000 ||
2124	DISPLAY_VERx100(display) == 1400 ||
2125	display->platform.dg2) &&
2126	display->cdclk.hw.vco > 0;
2127	}
2128
2129	static u32 bxt_cdclk_ctl(struct intel_display *display,
2130	const struct intel_cdclk_config *cdclk_config,
2131	enum pipe pipe)
2132	{
2133	int cdclk = cdclk_config->cdclk;
2134	int vco = cdclk_config->vco;
2135	u16 waveform;
2136	u32 val;
2137
2138	waveform = cdclk_squash_waveform(display, cdclk);
2139
2140	val = bxt_cdclk_cd2x_div_sel(display, cdclk, vco, waveform) |
2141	bxt_cdclk_cd2x_pipe(display, pipe);
2142
2143	/*
2144	* Disable SSA Precharge when CD clock frequency < 500 MHz,
2145	* enable otherwise.
2146	*/
2147	if ((display->platform.geminilake || display->platform.broxton) &&
2148	cdclk >= 500000)
2149	val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
2150
2151	if (DISPLAY_VER(display) >= 20)
2152	val |= xe2lpd_mdclk_source_sel(display);
2153	else
2154	val |= skl_cdclk_decimal(cdclk);
2155
2156	return val;
2157	}
2158
2159	static void _bxt_set_cdclk(struct intel_display *display,
2160	const struct intel_cdclk_config *cdclk_config,
2161	enum pipe pipe)
2162	{
2163	int cdclk = cdclk_config->cdclk;
2164	int vco = cdclk_config->vco;
2165
2166	if (HAS_CDCLK_CRAWL(display) && display->cdclk.hw.vco > 0 && vco > 0 &&
2167	!cdclk_pll_is_unknown(vco: display->cdclk.hw.vco)) {
2168	if (display->cdclk.hw.vco != vco)
2169	adlp_cdclk_pll_crawl(display, vco);
2170	} else if (DISPLAY_VER(display) >= 11) {
2171	/* wa_15010685871: dg2, mtl */
2172	if (pll_enable_wa_needed(display))
2173	dg2_cdclk_squash_program(display, waveform: 0);
2174
2175	icl_cdclk_pll_update(display, vco);
2176	} else {
2177	bxt_cdclk_pll_update(display, vco);
2178	}
2179
2180	if (HAS_CDCLK_SQUASH(display)) {
2181	u16 waveform = cdclk_squash_waveform(display, cdclk);
2182
2183	dg2_cdclk_squash_program(display, waveform);
2184	}
2185
2186	intel_de_write(display, CDCLK_CTL, val: bxt_cdclk_ctl(display, cdclk_config, pipe));
2187
2188	if (pipe != INVALID_PIPE)
2189	intel_crtc_wait_for_next_vblank(crtc: intel_crtc_for_pipe(display, pipe));
2190	}
2191
2192	static void bxt_set_cdclk(struct intel_display *display,
2193	const struct intel_cdclk_config *cdclk_config,
2194	enum pipe pipe)
2195	{
2196	struct intel_cdclk_config mid_cdclk_config;
2197	int cdclk = cdclk_config->cdclk;
2198	int ret = 0;
2199
2200	/*
2201	* Inform power controller of upcoming frequency change.
2202	* Display versions 14 and beyond do not follow the PUnit
2203	* mailbox communication, skip
2204	* this step.
2205	*/
2206	if (DISPLAY_VER(display) >= 14 || display->platform.dg2)
2207	; /* NOOP */
2208	else if (DISPLAY_VER(display) >= 11)
2209	ret = intel_pcode_request(drm: display->drm, SKL_PCODE_CDCLK_CONTROL,
2210	SKL_CDCLK_PREPARE_FOR_CHANGE,
2211	SKL_CDCLK_READY_FOR_CHANGE,
2212	SKL_CDCLK_READY_FOR_CHANGE, timeout_base_ms: 3);
2213	else
2214	/*
2215	* BSpec requires us to wait up to 150usec, but that leads to
2216	* timeouts; the 2ms used here is based on experiment.
2217	*/
2218	ret = intel_pcode_write_timeout(drm: display->drm,
2219	HSW_PCODE_DE_WRITE_FREQ_REQ,
2220	val: 0x80000000, timeout_ms: 2);
2221
2222	if (ret) {
2223	drm_err(display->drm,
2224	"Failed to inform PCU about cdclk change (err %d, freq %d)\n",
2225	ret, cdclk);
2226	return;
2227	}
2228
2229	if (DISPLAY_VER(display) >= 20 && cdclk < display->cdclk.hw.cdclk)
2230	xe2lpd_mdclk_cdclk_ratio_program(display, cdclk_config);
2231
2232	if (cdclk_compute_crawl_and_squash_midpoint(display, old_cdclk_config: &display->cdclk.hw,
2233	new_cdclk_config: cdclk_config, mid_cdclk_config: &mid_cdclk_config)) {
2234	_bxt_set_cdclk(display, cdclk_config: &mid_cdclk_config, pipe);
2235	_bxt_set_cdclk(display, cdclk_config, pipe);
2236	} else {
2237	_bxt_set_cdclk(display, cdclk_config, pipe);
2238	}
2239
2240	if (DISPLAY_VER(display) >= 20 && cdclk > display->cdclk.hw.cdclk)
2241	xe2lpd_mdclk_cdclk_ratio_program(display, cdclk_config);
2242
2243	if (DISPLAY_VER(display) >= 14)
2244	/*
2245	* NOOP - No Pcode communication needed for
2246	* Display versions 14 and beyond
2247	*/;
2248	else if (DISPLAY_VER(display) >= 11 && !display->platform.dg2)
2249	ret = intel_pcode_write(display->drm, SKL_PCODE_CDCLK_CONTROL,
2250	cdclk_config->voltage_level);
2251	if (DISPLAY_VER(display) < 11) {
2252	/*
2253	* The timeout isn't specified, the 2ms used here is based on
2254	* experiment.
2255	* FIXME: Waiting for the request completion could be delayed
2256	* until the next PCODE request based on BSpec.
2257	*/
2258	ret = intel_pcode_write_timeout(drm: display->drm,
2259	HSW_PCODE_DE_WRITE_FREQ_REQ,
2260	val: cdclk_config->voltage_level, timeout_ms: 2);
2261	}
2262	if (ret) {
2263	drm_err(display->drm,
2264	"PCode CDCLK freq set failed, (err %d, freq %d)\n",
2265	ret, cdclk);
2266	return;
2267	}
2268
2269	intel_update_cdclk(display);
2270
2271	if (DISPLAY_VER(display) >= 11)
2272	/*
2273	* Can't read out the voltage level :(
2274	* Let's just assume everything is as expected.
2275	*/
2276	display->cdclk.hw.voltage_level = cdclk_config->voltage_level;
2277	}
2278
2279	static void bxt_sanitize_cdclk(struct intel_display *display)
2280	{
2281	u32 cdctl, expected;
2282	int cdclk, vco;
2283
2284	intel_update_cdclk(display);
2285	intel_cdclk_dump_config(display, cdclk_config: &display->cdclk.hw, context: "Current CDCLK");
2286
2287	if (display->cdclk.hw.vco == 0 ||
2288	display->cdclk.hw.cdclk == display->cdclk.hw.bypass)
2289	goto sanitize;
2290
2291	/* Make sure this is a legal cdclk value for the platform */
2292	cdclk = bxt_calc_cdclk(display, min_cdclk: display->cdclk.hw.cdclk);
2293	if (cdclk != display->cdclk.hw.cdclk)
2294	goto sanitize;
2295
2296	/* Make sure the VCO is correct for the cdclk */
2297	vco = bxt_calc_cdclk_pll_vco(display, cdclk);
2298	if (vco != display->cdclk.hw.vco)
2299	goto sanitize;
2300
2301	/*
2302	* Some BIOS versions leave an incorrect decimal frequency value and
2303	* set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
2304	* so sanitize this register.
2305	*/
2306	cdctl = intel_de_read(display, CDCLK_CTL);
2307	expected = bxt_cdclk_ctl(display, cdclk_config: &display->cdclk.hw, pipe: INVALID_PIPE);
2308
2309	/*
2310	* Let's ignore the pipe field, since BIOS could have configured the
2311	* dividers both syncing to an active pipe, or asynchronously
2312	* (PIPE_NONE).
2313	*/
2314	cdctl &= ~bxt_cdclk_cd2x_pipe(display, pipe: INVALID_PIPE);
2315	expected &= ~bxt_cdclk_cd2x_pipe(display, pipe: INVALID_PIPE);
2316
2317	if (cdctl == expected)
2318	/* All well; nothing to sanitize */
2319	return;
2320
2321	sanitize:
2322	drm_dbg_kms(display->drm, "Sanitizing cdclk programmed by pre-os\n");
2323
2324	/* force cdclk programming */
2325	display->cdclk.hw.cdclk = 0;
2326
2327	/* force full PLL disable + enable */
2328	display->cdclk.hw.vco = ~0;
2329	}
2330
2331	static void bxt_cdclk_init_hw(struct intel_display *display)
2332	{
2333	struct intel_cdclk_config cdclk_config;
2334
2335	bxt_sanitize_cdclk(display);
2336
2337	if (display->cdclk.hw.cdclk != 0 &&
2338	display->cdclk.hw.vco != 0)
2339	return;
2340
2341	cdclk_config = display->cdclk.hw;
2342
2343	/*
2344	* FIXME:
2345	* - The initial CDCLK needs to be read from VBT.
2346	* Need to make this change after VBT has changes for BXT.
2347	*/
2348	cdclk_config.cdclk = bxt_calc_cdclk(display, min_cdclk: 0);
2349	cdclk_config.vco = bxt_calc_cdclk_pll_vco(display, cdclk: cdclk_config.cdclk);
2350	cdclk_config.voltage_level =
2351	intel_cdclk_calc_voltage_level(display, cdclk: cdclk_config.cdclk);
2352
2353	bxt_set_cdclk(display, cdclk_config: &cdclk_config, pipe: INVALID_PIPE);
2354	}
2355
2356	static void bxt_cdclk_uninit_hw(struct intel_display *display)
2357	{
2358	struct intel_cdclk_config cdclk_config = display->cdclk.hw;
2359
2360	cdclk_config.cdclk = cdclk_config.bypass;
2361	cdclk_config.vco = 0;
2362	cdclk_config.voltage_level =
2363	intel_cdclk_calc_voltage_level(display, cdclk: cdclk_config.cdclk);
2364
2365	bxt_set_cdclk(display, cdclk_config: &cdclk_config, pipe: INVALID_PIPE);
2366	}
2367
2368	/**
2369	* intel_cdclk_init_hw - Initialize CDCLK hardware
2370	* @display: display instance
2371	*
2372	* Initialize CDCLK. This consists mainly of initializing display->cdclk.hw and
2373	* sanitizing the state of the hardware if needed. This is generally done only
2374	* during the display core initialization sequence, after which the DMC will
2375	* take care of turning CDCLK off/on as needed.
2376	*/
2377	void intel_cdclk_init_hw(struct intel_display *display)
2378	{
2379	if (DISPLAY_VER(display) >= 10 || display->platform.broxton)
2380	bxt_cdclk_init_hw(display);
2381	else if (DISPLAY_VER(display) == 9)
2382	skl_cdclk_init_hw(display);
2383	}
2384
2385	/**
2386	* intel_cdclk_uninit_hw - Uninitialize CDCLK hardware
2387	* @display: display instance
2388	*
2389	* Uninitialize CDCLK. This is done only during the display core
2390	* uninitialization sequence.
2391	*/
2392	void intel_cdclk_uninit_hw(struct intel_display *display)
2393	{
2394	if (DISPLAY_VER(display) >= 10 || display->platform.broxton)
2395	bxt_cdclk_uninit_hw(display);
2396	else if (DISPLAY_VER(display) == 9)
2397	skl_cdclk_uninit_hw(display);
2398	}
2399
2400	static bool intel_cdclk_can_crawl_and_squash(struct intel_display *display,
2401	const struct intel_cdclk_config *a,
2402	const struct intel_cdclk_config *b)
2403	{
2404	u16 old_waveform;
2405	u16 new_waveform;
2406
2407	drm_WARN_ON(display->drm, cdclk_pll_is_unknown(a->vco));
2408
2409	if (a->vco == 0 || b->vco == 0)
2410	return false;
2411
2412	if (!HAS_CDCLK_CRAWL(display) || !HAS_CDCLK_SQUASH(display))
2413	return false;
2414
2415	old_waveform = cdclk_squash_waveform(display, cdclk: a->cdclk);
2416	new_waveform = cdclk_squash_waveform(display, cdclk: b->cdclk);
2417
2418	return a->vco != b->vco &&
2419	old_waveform != new_waveform;
2420	}
2421
2422	static bool intel_cdclk_can_crawl(struct intel_display *display,
2423	const struct intel_cdclk_config *a,
2424	const struct intel_cdclk_config *b)
2425	{
2426	int a_div, b_div;
2427
2428	if (!HAS_CDCLK_CRAWL(display))
2429	return false;
2430
2431	/*
2432	* The vco and cd2x divider will change independently
2433	* from each, so we disallow cd2x change when crawling.
2434	*/
2435	a_div = DIV_ROUND_CLOSEST(a->vco, a->cdclk);
2436	b_div = DIV_ROUND_CLOSEST(b->vco, b->cdclk);
2437
2438	return a->vco != 0 && b->vco != 0 &&
2439	a->vco != b->vco &&
2440	a_div == b_div &&
2441	a->ref == b->ref;
2442	}
2443
2444	static bool intel_cdclk_can_squash(struct intel_display *display,
2445	const struct intel_cdclk_config *a,
2446	const struct intel_cdclk_config *b)
2447	{
2448	/*
2449	* FIXME should store a bit more state in intel_cdclk_config
2450	* to differentiate squasher vs. cd2x divider properly. For
2451	* the moment all platforms with squasher use a fixed cd2x
2452	* divider.
2453	*/
2454	if (!HAS_CDCLK_SQUASH(display))
2455	return false;
2456
2457	return a->cdclk != b->cdclk &&
2458	a->vco != 0 &&
2459	a->vco == b->vco &&
2460	a->ref == b->ref;
2461	}
2462
2463	/**
2464	* intel_cdclk_clock_changed - Check whether the clock changed
2465	* @a: first CDCLK configuration
2466	* @b: second CDCLK configuration
2467	*
2468	* Returns:
2469	* True if CDCLK changed in a way that requires re-programming and
2470	* False otherwise.
2471	*/
2472	bool intel_cdclk_clock_changed(const struct intel_cdclk_config *a,
2473	const struct intel_cdclk_config *b)
2474	{
2475	return a->cdclk != b->cdclk ||
2476	a->vco != b->vco ||
2477	a->ref != b->ref;
2478	}
2479
2480	/**
2481	* intel_cdclk_can_cd2x_update - Determine if changing between the two CDCLK
2482	* configurations requires only a cd2x divider update
2483	* @display: display instance
2484	* @a: first CDCLK configuration
2485	* @b: second CDCLK configuration
2486	*
2487	* Returns:
2488	* True if changing between the two CDCLK configurations
2489	* can be done with just a cd2x divider update, false if not.
2490	*/
2491	static bool intel_cdclk_can_cd2x_update(struct intel_display *display,
2492	const struct intel_cdclk_config *a,
2493	const struct intel_cdclk_config *b)
2494	{
2495	/* Older hw doesn't have the capability */
2496	if (DISPLAY_VER(display) < 10 && !display->platform.broxton)
2497	return false;
2498
2499	/*
2500	* FIXME should store a bit more state in intel_cdclk_config
2501	* to differentiate squasher vs. cd2x divider properly. For
2502	* the moment all platforms with squasher use a fixed cd2x
2503	* divider.
2504	*/
2505	if (HAS_CDCLK_SQUASH(display))
2506	return false;
2507
2508	return a->cdclk != b->cdclk &&
2509	a->vco != 0 &&
2510	a->vco == b->vco &&
2511	a->ref == b->ref;
2512	}
2513
2514	/**
2515	* intel_cdclk_changed - Determine if two CDCLK configurations are different
2516	* @a: first CDCLK configuration
2517	* @b: second CDCLK configuration
2518	*
2519	* Returns:
2520	* True if the CDCLK configurations don't match, false if they do.
2521	*/
2522	static bool intel_cdclk_changed(const struct intel_cdclk_config *a,
2523	const struct intel_cdclk_config *b)
2524	{
2525	return intel_cdclk_clock_changed(a, b) ||
2526	a->voltage_level != b->voltage_level;
2527	}
2528
2529	void intel_cdclk_dump_config(struct intel_display *display,
2530	const struct intel_cdclk_config *cdclk_config,
2531	const char *context)
2532	{
2533	drm_dbg_kms(display->drm, "%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n",
2534	context, cdclk_config->cdclk, cdclk_config->vco,
2535	cdclk_config->ref, cdclk_config->bypass,
2536	cdclk_config->voltage_level);
2537	}
2538
2539	static void intel_pcode_notify(struct intel_display *display,
2540	u8 voltage_level,
2541	u8 active_pipe_count,
2542	u16 cdclk,
2543	bool cdclk_update_valid,
2544	bool pipe_count_update_valid)
2545	{
2546	int ret;
2547	u32 update_mask = 0;
2548
2549	if (!display->platform.dg2)
2550	return;
2551
2552	update_mask = DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, active_pipe_count, voltage_level);
2553
2554	if (cdclk_update_valid)
2555	update_mask |= DISPLAY_TO_PCODE_CDCLK_VALID;
2556
2557	if (pipe_count_update_valid)
2558	update_mask |= DISPLAY_TO_PCODE_PIPE_COUNT_VALID;
2559
2560	ret = intel_pcode_request(drm: display->drm, SKL_PCODE_CDCLK_CONTROL,
2561	SKL_CDCLK_PREPARE_FOR_CHANGE |
2562	update_mask,
2563	SKL_CDCLK_READY_FOR_CHANGE,
2564	SKL_CDCLK_READY_FOR_CHANGE, timeout_base_ms: 3);
2565	if (ret)
2566	drm_err(display->drm,
2567	"Failed to inform PCU about display config (err %d)\n",
2568	ret);
2569	}
2570
2571	static void intel_set_cdclk(struct intel_display *display,
2572	const struct intel_cdclk_config *cdclk_config,
2573	enum pipe pipe, const char *context)
2574	{
2575	struct intel_encoder *encoder;
2576
2577	if (!intel_cdclk_changed(a: &display->cdclk.hw, b: cdclk_config))
2578	return;
2579
2580	if (drm_WARN_ON_ONCE(display->drm, !display->funcs.cdclk->set_cdclk))
2581	return;
2582
2583	intel_cdclk_dump_config(display, cdclk_config, context);
2584
2585	for_each_intel_encoder_with_psr(display->drm, encoder) {
2586	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2587
2588	intel_psr_pause(intel_dp);
2589	}
2590
2591	intel_audio_cdclk_change_pre(display);
2592
2593	/*
2594	* Lock aux/gmbus while we change cdclk in case those
2595	* functions use cdclk. Not all platforms/ports do,
2596	* but we'll lock them all for simplicity.
2597	*/
2598	mutex_lock(&display->gmbus.mutex);
2599	for_each_intel_dp(display->drm, encoder) {
2600	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2601
2602	mutex_lock_nest_lock(&intel_dp->aux.hw_mutex,
2603	&display->gmbus.mutex);
2604	}
2605
2606	intel_cdclk_set_cdclk(display, cdclk_config, pipe);
2607
2608	for_each_intel_dp(display->drm, encoder) {
2609	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2610
2611	mutex_unlock(lock: &intel_dp->aux.hw_mutex);
2612	}
2613	mutex_unlock(lock: &display->gmbus.mutex);
2614
2615	for_each_intel_encoder_with_psr(display->drm, encoder) {
2616	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2617
2618	intel_psr_resume(intel_dp);
2619	}
2620
2621	intel_audio_cdclk_change_post(display);
2622
2623	if (drm_WARN(display->drm,
2624	intel_cdclk_changed(&display->cdclk.hw, cdclk_config),
2625	"cdclk state doesn't match!\n")) {
2626	intel_cdclk_dump_config(display, cdclk_config: &display->cdclk.hw, context: "[hw state]");
2627	intel_cdclk_dump_config(display, cdclk_config, context: "[sw state]");
2628	}
2629	}
2630
2631	static bool dg2_power_well_count(struct intel_display *display,
2632	const struct intel_cdclk_state *cdclk_state)
2633	{
2634	return display->platform.dg2 ? hweight8(cdclk_state->active_pipes) : 0;
2635	}
2636
2637	static void intel_cdclk_pcode_pre_notify(struct intel_atomic_state *state)
2638	{
2639	struct intel_display *display = to_intel_display(state);
2640	const struct intel_cdclk_state *old_cdclk_state =
2641	intel_atomic_get_old_cdclk_state(state);
2642	const struct intel_cdclk_state *new_cdclk_state =
2643	intel_atomic_get_new_cdclk_state(state);
2644	unsigned int cdclk = 0; u8 voltage_level, num_active_pipes = 0;
2645	bool change_cdclk, update_pipe_count;
2646
2647	if (!intel_cdclk_changed(a: &old_cdclk_state->actual,
2648	b: &new_cdclk_state->actual) &&
2649	dg2_power_well_count(display, cdclk_state: old_cdclk_state) ==
2650	dg2_power_well_count(display, cdclk_state: new_cdclk_state))
2651	return;
2652
2653	/* According to "Sequence Before Frequency Change", voltage level set to 0x3 */
2654	voltage_level = DISPLAY_TO_PCODE_VOLTAGE_MAX;
2655
2656	change_cdclk = new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk;
2657	update_pipe_count = dg2_power_well_count(display, cdclk_state: new_cdclk_state) >
2658	dg2_power_well_count(display, cdclk_state: old_cdclk_state);
2659
2660	/*
2661	* According to "Sequence Before Frequency Change",
2662	* if CDCLK is increasing, set bits 25:16 to upcoming CDCLK,
2663	* if CDCLK is decreasing or not changing, set bits 25:16 to current CDCLK,
2664	* which basically means we choose the maximum of old and new CDCLK, if we know both
2665	*/
2666	if (change_cdclk)
2667	cdclk = max(new_cdclk_state->actual.cdclk, old_cdclk_state->actual.cdclk);
2668
2669	/*
2670	* According to "Sequence For Pipe Count Change",
2671	* if pipe count is increasing, set bits 25:16 to upcoming pipe count
2672	* (power well is enabled)
2673	* no action if it is decreasing, before the change
2674	*/
2675	if (update_pipe_count)
2676	num_active_pipes = dg2_power_well_count(display, cdclk_state: new_cdclk_state);
2677
2678	intel_pcode_notify(display, voltage_level, active_pipe_count: num_active_pipes, cdclk,
2679	cdclk_update_valid: change_cdclk, pipe_count_update_valid: update_pipe_count);
2680	}
2681
2682	static void intel_cdclk_pcode_post_notify(struct intel_atomic_state *state)
2683	{
2684	struct intel_display *display = to_intel_display(state);
2685	const struct intel_cdclk_state *new_cdclk_state =
2686	intel_atomic_get_new_cdclk_state(state);
2687	const struct intel_cdclk_state *old_cdclk_state =
2688	intel_atomic_get_old_cdclk_state(state);
2689	unsigned int cdclk = 0; u8 voltage_level, num_active_pipes = 0;
2690	bool update_cdclk, update_pipe_count;
2691
2692	/* According to "Sequence After Frequency Change", set voltage to used level */
2693	voltage_level = new_cdclk_state->actual.voltage_level;
2694
2695	update_cdclk = new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk;
2696	update_pipe_count = dg2_power_well_count(display, cdclk_state: new_cdclk_state) <
2697	dg2_power_well_count(display, cdclk_state: old_cdclk_state);
2698
2699	/*
2700	* According to "Sequence After Frequency Change",
2701	* set bits 25:16 to current CDCLK
2702	*/
2703	if (update_cdclk)
2704	cdclk = new_cdclk_state->actual.cdclk;
2705
2706	/*
2707	* According to "Sequence For Pipe Count Change",
2708	* if pipe count is decreasing, set bits 25:16 to current pipe count,
2709	* after the change(power well is disabled)
2710	* no action if it is increasing, after the change
2711	*/
2712	if (update_pipe_count)
2713	num_active_pipes = dg2_power_well_count(display, cdclk_state: new_cdclk_state);
2714
2715	intel_pcode_notify(display, voltage_level, active_pipe_count: num_active_pipes, cdclk,
2716	cdclk_update_valid: update_cdclk, pipe_count_update_valid: update_pipe_count);
2717	}
2718
2719	bool intel_cdclk_is_decreasing_later(struct intel_atomic_state *state)
2720	{
2721	const struct intel_cdclk_state *old_cdclk_state =
2722	intel_atomic_get_old_cdclk_state(state);
2723	const struct intel_cdclk_state *new_cdclk_state =
2724	intel_atomic_get_new_cdclk_state(state);
2725
2726	return new_cdclk_state && !new_cdclk_state->disable_pipes &&
2727	new_cdclk_state->actual.cdclk < old_cdclk_state->actual.cdclk;
2728	}
2729
2730	/**
2731	* intel_set_cdclk_pre_plane_update - Push the CDCLK state to the hardware
2732	* @state: intel atomic state
2733	*
2734	* Program the hardware before updating the HW plane state based on the
2735	* new CDCLK state, if necessary.
2736	*/
2737	void
2738	intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state)
2739	{
2740	struct intel_display *display = to_intel_display(state);
2741	const struct intel_cdclk_state *old_cdclk_state =
2742	intel_atomic_get_old_cdclk_state(state);
2743	const struct intel_cdclk_state *new_cdclk_state =
2744	intel_atomic_get_new_cdclk_state(state);
2745	struct intel_cdclk_config cdclk_config;
2746	enum pipe pipe;
2747
2748	if (!new_cdclk_state)
2749	return;
2750
2751	if (!intel_cdclk_changed(a: &old_cdclk_state->actual,
2752	b: &new_cdclk_state->actual))
2753	return;
2754
2755	if (display->platform.dg2)
2756	intel_cdclk_pcode_pre_notify(state);
2757
2758	if (new_cdclk_state->disable_pipes) {
2759	cdclk_config = new_cdclk_state->actual;
2760	pipe = INVALID_PIPE;
2761	} else {
2762	if (new_cdclk_state->actual.cdclk >= old_cdclk_state->actual.cdclk) {
2763	cdclk_config = new_cdclk_state->actual;
2764	pipe = new_cdclk_state->pipe;
2765	} else {
2766	cdclk_config = old_cdclk_state->actual;
2767	pipe = INVALID_PIPE;
2768	}
2769
2770	cdclk_config.voltage_level = max(new_cdclk_state->actual.voltage_level,
2771	old_cdclk_state->actual.voltage_level);
2772	}
2773
2774	/*
2775	* mbus joining will be changed later by
2776	* intel_dbuf_mbus_{pre,post}_ddb_update()
2777	*/
2778	cdclk_config.joined_mbus = old_cdclk_state->actual.joined_mbus;
2779
2780	drm_WARN_ON(display->drm, !new_cdclk_state->base.changed);
2781
2782	intel_set_cdclk(display, cdclk_config: &cdclk_config, pipe,
2783	context: "Pre changing CDCLK to");
2784	}
2785
2786	/**
2787	* intel_set_cdclk_post_plane_update - Push the CDCLK state to the hardware
2788	* @state: intel atomic state
2789	*
2790	* Program the hardware after updating the HW plane state based on the
2791	* new CDCLK state, if necessary.
2792	*/
2793	void
2794	intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)
2795	{
2796	struct intel_display *display = to_intel_display(state);
2797	const struct intel_cdclk_state *old_cdclk_state =
2798	intel_atomic_get_old_cdclk_state(state);
2799	const struct intel_cdclk_state *new_cdclk_state =
2800	intel_atomic_get_new_cdclk_state(state);
2801	enum pipe pipe;
2802
2803	if (!new_cdclk_state)
2804	return;
2805
2806	if (!intel_cdclk_changed(a: &old_cdclk_state->actual,
2807	b: &new_cdclk_state->actual))
2808	return;
2809
2810	if (display->platform.dg2)
2811	intel_cdclk_pcode_post_notify(state);
2812
2813	if (!new_cdclk_state->disable_pipes &&
2814	new_cdclk_state->actual.cdclk < old_cdclk_state->actual.cdclk)
2815	pipe = new_cdclk_state->pipe;
2816	else
2817	pipe = INVALID_PIPE;
2818
2819	drm_WARN_ON(display->drm, !new_cdclk_state->base.changed);
2820
2821	intel_set_cdclk(display, cdclk_config: &new_cdclk_state->actual, pipe,
2822	context: "Post changing CDCLK to");
2823	}
2824
2825	/* pixels per CDCLK */
2826	static int intel_cdclk_ppc(struct intel_display *display, bool double_wide)
2827	{
2828	return DISPLAY_VER(display) >= 10 || double_wide ? 2 : 1;
2829	}
2830
2831	/* max pixel rate as % of CDCLK (not accounting for PPC) */
2832	static int intel_cdclk_guardband(struct intel_display *display)
2833	{
2834	if (DISPLAY_VER(display) >= 9 ||
2835	display->platform.broadwell || display->platform.haswell)
2836	return 100;
2837	else if (display->platform.cherryview)
2838	return 95;
2839	else
2840	return 90;
2841	}
2842
2843	static int _intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state, int pixel_rate)
2844	{
2845	struct intel_display *display = to_intel_display(crtc_state);
2846	int ppc = intel_cdclk_ppc(display, double_wide: crtc_state->double_wide);
2847	int guardband = intel_cdclk_guardband(display);
2848
2849	return DIV_ROUND_UP(pixel_rate * 100, guardband * ppc);
2850	}
2851
2852	static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
2853	{
2854	return _intel_pixel_rate_to_cdclk(crtc_state, pixel_rate: crtc_state->pixel_rate);
2855	}
2856
2857	static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state)
2858	{
2859	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2860	struct intel_display *display = to_intel_display(crtc);
2861	struct intel_plane *plane;
2862	int min_cdclk = 0;
2863
2864	for_each_intel_plane_on_crtc(display->drm, crtc, plane)
2865	min_cdclk = max(min_cdclk, crtc_state->plane_min_cdclk[plane->id]);
2866
2867	return min_cdclk;
2868	}
2869
2870	int intel_crtc_min_cdclk(const struct intel_crtc_state *crtc_state)
2871	{
2872	int min_cdclk;
2873
2874	if (!crtc_state->hw.enable)
2875	return 0;
2876
2877	min_cdclk = intel_pixel_rate_to_cdclk(crtc_state);
2878	min_cdclk = max(min_cdclk, intel_crtc_bw_min_cdclk(crtc_state));
2879	min_cdclk = max(min_cdclk, intel_fbc_min_cdclk(crtc_state));
2880	min_cdclk = max(min_cdclk, hsw_ips_min_cdclk(crtc_state));
2881	min_cdclk = max(min_cdclk, intel_audio_min_cdclk(crtc_state));
2882	min_cdclk = max(min_cdclk, vlv_dsi_min_cdclk(crtc_state));
2883	min_cdclk = max(min_cdclk, intel_planes_min_cdclk(crtc_state));
2884	min_cdclk = max(min_cdclk, intel_vdsc_min_cdclk(crtc_state));
2885
2886	return min_cdclk;
2887	}
2888
2889	static int intel_cdclk_update_crtc_min_cdclk(struct intel_atomic_state *state,
2890	struct intel_crtc *crtc,
2891	int old_min_cdclk, int new_min_cdclk,
2892	bool *need_cdclk_calc)
2893	{
2894	struct intel_display *display = to_intel_display(state);
2895	struct intel_cdclk_state *cdclk_state;
2896	bool allow_cdclk_decrease = intel_any_crtc_needs_modeset(state);
2897	int ret;
2898
2899	if (new_min_cdclk == old_min_cdclk)
2900	return 0;
2901
2902	if (!allow_cdclk_decrease && new_min_cdclk < old_min_cdclk)
2903	return 0;
2904
2905	cdclk_state = intel_atomic_get_cdclk_state(state);
2906	if (IS_ERR(ptr: cdclk_state))
2907	return PTR_ERR(ptr: cdclk_state);
2908
2909	old_min_cdclk = cdclk_state->min_cdclk[crtc->pipe];
2910
2911	if (new_min_cdclk == old_min_cdclk)
2912	return 0;
2913
2914	if (!allow_cdclk_decrease && new_min_cdclk < old_min_cdclk)
2915	return 0;
2916
2917	cdclk_state->min_cdclk[crtc->pipe] = new_min_cdclk;
2918
2919	ret = intel_atomic_lock_global_state(obj_state: &cdclk_state->base);
2920	if (ret)
2921	return ret;
2922
2923	*need_cdclk_calc = true;
2924
2925	drm_dbg_kms(display->drm,
2926	"[CRTC:%d:%s] min cdclk: %d kHz -> %d kHz\n",
2927	crtc->base.base.id, crtc->base.name,
2928	old_min_cdclk, new_min_cdclk);
2929
2930	return 0;
2931	}
2932
2933	int intel_cdclk_update_dbuf_bw_min_cdclk(struct intel_atomic_state *state,
2934	int old_min_cdclk, int new_min_cdclk,
2935	bool *need_cdclk_calc)
2936	{
2937	struct intel_display *display = to_intel_display(state);
2938	struct intel_cdclk_state *cdclk_state;
2939	bool allow_cdclk_decrease = intel_any_crtc_needs_modeset(state);
2940	int ret;
2941
2942	if (new_min_cdclk == old_min_cdclk)
2943	return 0;
2944
2945	if (!allow_cdclk_decrease && new_min_cdclk < old_min_cdclk)
2946	return 0;
2947
2948	cdclk_state = intel_atomic_get_cdclk_state(state);
2949	if (IS_ERR(ptr: cdclk_state))
2950	return PTR_ERR(ptr: cdclk_state);
2951
2952	old_min_cdclk = cdclk_state->dbuf_bw_min_cdclk;
2953
2954	if (new_min_cdclk == old_min_cdclk)
2955	return 0;
2956
2957	if (!allow_cdclk_decrease && new_min_cdclk < old_min_cdclk)
2958	return 0;
2959
2960	cdclk_state->dbuf_bw_min_cdclk = new_min_cdclk;
2961
2962	ret = intel_atomic_lock_global_state(obj_state: &cdclk_state->base);
2963	if (ret)
2964	return ret;
2965
2966	*need_cdclk_calc = true;
2967
2968	drm_dbg_kms(display->drm,
2969	"dbuf bandwidth min cdclk: %d kHz -> %d kHz\n",
2970	old_min_cdclk, new_min_cdclk);
2971
2972	return 0;
2973	}
2974
2975	static bool glk_cdclk_audio_wa_needed(struct intel_display *display,
2976	const struct intel_cdclk_state *cdclk_state)
2977	{
2978	return display->platform.geminilake &&
2979	cdclk_state->enabled_pipes &&
2980	!is_power_of_2(n: cdclk_state->enabled_pipes);
2981	}
2982
2983	static int intel_compute_min_cdclk(struct intel_atomic_state *state)
2984	{
2985	struct intel_display *display = to_intel_display(state);
2986	struct intel_cdclk_state *cdclk_state =
2987	intel_atomic_get_new_cdclk_state(state);
2988	enum pipe pipe;
2989	int min_cdclk;
2990
2991	min_cdclk = cdclk_state->force_min_cdclk;
2992	min_cdclk = max(min_cdclk, cdclk_state->dbuf_bw_min_cdclk);
2993	for_each_pipe(display, pipe)
2994	min_cdclk = max(min_cdclk, cdclk_state->min_cdclk[pipe]);
2995
2996	/*
2997	* Avoid glk_force_audio_cdclk() causing excessive screen
2998	* blinking when multiple pipes are active by making sure
2999	* CDCLK frequency is always high enough for audio. With a
3000	* single active pipe we can always change CDCLK frequency
3001	* by changing the cd2x divider (see glk_cdclk_table[]) and
3002	* thus a full modeset won't be needed then.
3003	*/
3004	if (glk_cdclk_audio_wa_needed(display, cdclk_state))
3005	min_cdclk = max(min_cdclk, 2 * 96000);
3006
3007	if (min_cdclk > display->cdclk.max_cdclk_freq) {
3008	drm_dbg_kms(display->drm,
3009	"required cdclk (%d kHz) exceeds max (%d kHz)\n",
3010	min_cdclk, display->cdclk.max_cdclk_freq);
3011	return -EINVAL;
3012	}
3013
3014	return min_cdclk;
3015	}
3016
3017	/*
3018	* Account for port clock min voltage level requirements.
3019	* This only really does something on DISPLA_VER >= 11 but can be
3020	* called on earlier platforms as well.
3021	*
3022	* Note that this functions assumes that 0 is
3023	* the lowest voltage value, and higher values
3024	* correspond to increasingly higher voltages.
3025	*
3026	* Should that relationship no longer hold on
3027	* future platforms this code will need to be
3028	* adjusted.
3029	*/
3030	static int bxt_compute_min_voltage_level(struct intel_atomic_state *state)
3031	{
3032	struct intel_display *display = to_intel_display(state);
3033	struct intel_cdclk_state *cdclk_state =
3034	intel_atomic_get_new_cdclk_state(state);
3035	struct intel_crtc *crtc;
3036	struct intel_crtc_state *crtc_state;
3037	u8 min_voltage_level;
3038	int i;
3039	enum pipe pipe;
3040
3041	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
3042	int ret;
3043
3044	if (crtc_state->hw.enable)
3045	min_voltage_level = crtc_state->min_voltage_level;
3046	else
3047	min_voltage_level = 0;
3048
3049	if (cdclk_state->min_voltage_level[crtc->pipe] == min_voltage_level)
3050	continue;
3051
3052	cdclk_state->min_voltage_level[crtc->pipe] = min_voltage_level;
3053
3054	ret = intel_atomic_lock_global_state(obj_state: &cdclk_state->base);
3055	if (ret)
3056	return ret;
3057	}
3058
3059	min_voltage_level = 0;
3060	for_each_pipe(display, pipe)
3061	min_voltage_level = max(min_voltage_level,
3062	cdclk_state->min_voltage_level[pipe]);
3063
3064	return min_voltage_level;
3065	}
3066
3067	static int vlv_modeset_calc_cdclk(struct intel_atomic_state *state)
3068	{
3069	struct intel_display *display = to_intel_display(state);
3070	struct intel_cdclk_state *cdclk_state =
3071	intel_atomic_get_new_cdclk_state(state);
3072	int min_cdclk, cdclk;
3073
3074	min_cdclk = intel_compute_min_cdclk(state);
3075	if (min_cdclk < 0)
3076	return min_cdclk;
3077
3078	cdclk = vlv_calc_cdclk(display, min_cdclk);
3079
3080	cdclk_state->logical.cdclk = cdclk;
3081	cdclk_state->logical.voltage_level =
3082	vlv_calc_voltage_level(display, cdclk);
3083
3084	if (!cdclk_state->active_pipes) {
3085	cdclk = vlv_calc_cdclk(display, min_cdclk: cdclk_state->force_min_cdclk);
3086
3087	cdclk_state->actual.cdclk = cdclk;
3088	cdclk_state->actual.voltage_level =
3089	vlv_calc_voltage_level(display, cdclk);
3090	} else {
3091	cdclk_state->actual = cdclk_state->logical;
3092	}
3093
3094	return 0;
3095	}
3096
3097	static int bdw_modeset_calc_cdclk(struct intel_atomic_state *state)
3098	{
3099	struct intel_cdclk_state *cdclk_state =
3100	intel_atomic_get_new_cdclk_state(state);
3101	int min_cdclk, cdclk;
3102
3103	min_cdclk = intel_compute_min_cdclk(state);
3104	if (min_cdclk < 0)
3105	return min_cdclk;
3106
3107	cdclk = bdw_calc_cdclk(min_cdclk);
3108
3109	cdclk_state->logical.cdclk = cdclk;
3110	cdclk_state->logical.voltage_level =
3111	bdw_calc_voltage_level(cdclk);
3112
3113	if (!cdclk_state->active_pipes) {
3114	cdclk = bdw_calc_cdclk(min_cdclk: cdclk_state->force_min_cdclk);
3115
3116	cdclk_state->actual.cdclk = cdclk;
3117	cdclk_state->actual.voltage_level =
3118	bdw_calc_voltage_level(cdclk);
3119	} else {
3120	cdclk_state->actual = cdclk_state->logical;
3121	}
3122
3123	return 0;
3124	}
3125
3126	static int skl_dpll0_vco(struct intel_atomic_state *state)
3127	{
3128	struct intel_display *display = to_intel_display(state);
3129	struct intel_cdclk_state *cdclk_state =
3130	intel_atomic_get_new_cdclk_state(state);
3131	struct intel_crtc *crtc;
3132	struct intel_crtc_state *crtc_state;
3133	int vco, i;
3134
3135	vco = cdclk_state->logical.vco;
3136	if (!vco)
3137	vco = display->cdclk.skl_preferred_vco_freq;
3138
3139	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
3140	if (!crtc_state->hw.enable)
3141	continue;
3142
3143	if (!intel_crtc_has_type(crtc_state, type: INTEL_OUTPUT_EDP))
3144	continue;
3145
3146	/*
3147	* DPLL0 VCO may need to be adjusted to get the correct
3148	* clock for eDP. This will affect cdclk as well.
3149	*/
3150	switch (crtc_state->port_clock / 2) {
3151	case 108000:
3152	case 216000:
3153	vco = 8640000;
3154	break;
3155	default:
3156	vco = 8100000;
3157	break;
3158	}
3159	}
3160
3161	return vco;
3162	}
3163
3164	static int skl_modeset_calc_cdclk(struct intel_atomic_state *state)
3165	{
3166	struct intel_cdclk_state *cdclk_state =
3167	intel_atomic_get_new_cdclk_state(state);
3168	int min_cdclk, cdclk, vco;
3169
3170	min_cdclk = intel_compute_min_cdclk(state);
3171	if (min_cdclk < 0)
3172	return min_cdclk;
3173
3174	vco = skl_dpll0_vco(state);
3175
3176	cdclk = skl_calc_cdclk(min_cdclk, vco);
3177
3178	cdclk_state->logical.vco = vco;
3179	cdclk_state->logical.cdclk = cdclk;
3180	cdclk_state->logical.voltage_level =
3181	skl_calc_voltage_level(cdclk);
3182
3183	if (!cdclk_state->active_pipes) {
3184	cdclk = skl_calc_cdclk(min_cdclk: cdclk_state->force_min_cdclk, vco);
3185
3186	cdclk_state->actual.vco = vco;
3187	cdclk_state->actual.cdclk = cdclk;
3188	cdclk_state->actual.voltage_level =
3189	skl_calc_voltage_level(cdclk);
3190	} else {
3191	cdclk_state->actual = cdclk_state->logical;
3192	}
3193
3194	return 0;
3195	}
3196
3197	static int bxt_modeset_calc_cdclk(struct intel_atomic_state *state)
3198	{
3199	struct intel_display *display = to_intel_display(state);
3200	struct intel_cdclk_state *cdclk_state =
3201	intel_atomic_get_new_cdclk_state(state);
3202	int min_cdclk, min_voltage_level, cdclk, vco;
3203
3204	min_cdclk = intel_compute_min_cdclk(state);
3205	if (min_cdclk < 0)
3206	return min_cdclk;
3207
3208	min_voltage_level = bxt_compute_min_voltage_level(state);
3209	if (min_voltage_level < 0)
3210	return min_voltage_level;
3211
3212	cdclk = bxt_calc_cdclk(display, min_cdclk);
3213	vco = bxt_calc_cdclk_pll_vco(display, cdclk);
3214
3215	cdclk_state->logical.vco = vco;
3216	cdclk_state->logical.cdclk = cdclk;
3217	cdclk_state->logical.voltage_level =
3218	max_t(int, min_voltage_level,
3219	intel_cdclk_calc_voltage_level(display, cdclk));
3220
3221	if (!cdclk_state->active_pipes) {
3222	cdclk = bxt_calc_cdclk(display, min_cdclk: cdclk_state->force_min_cdclk);
3223	vco = bxt_calc_cdclk_pll_vco(display, cdclk);
3224
3225	cdclk_state->actual.vco = vco;
3226	cdclk_state->actual.cdclk = cdclk;
3227	cdclk_state->actual.voltage_level =
3228	intel_cdclk_calc_voltage_level(display, cdclk);
3229	} else {
3230	cdclk_state->actual = cdclk_state->logical;
3231	}
3232
3233	return 0;
3234	}
3235
3236	static int fixed_modeset_calc_cdclk(struct intel_atomic_state *state)
3237	{
3238	int min_cdclk;
3239
3240	/*
3241	* We can't change the cdclk frequency, but we still want to
3242	* check that the required minimum frequency doesn't exceed
3243	* the actual cdclk frequency.
3244	*/
3245	min_cdclk = intel_compute_min_cdclk(state);
3246	if (min_cdclk < 0)
3247	return min_cdclk;
3248
3249	return 0;
3250	}
3251
3252	static struct intel_global_state *intel_cdclk_duplicate_state(struct intel_global_obj *obj)
3253	{
3254	struct intel_cdclk_state *cdclk_state;
3255
3256	cdclk_state = kmemdup(obj->state, sizeof(*cdclk_state), GFP_KERNEL);
3257	if (!cdclk_state)
3258	return NULL;
3259
3260	cdclk_state->pipe = INVALID_PIPE;
3261	cdclk_state->disable_pipes = false;
3262
3263	return &cdclk_state->base;
3264	}
3265
3266	static void intel_cdclk_destroy_state(struct intel_global_obj *obj,
3267	struct intel_global_state *state)
3268	{
3269	kfree(objp: state);
3270	}
3271
3272	static const struct intel_global_state_funcs intel_cdclk_funcs = {
3273	.atomic_duplicate_state = intel_cdclk_duplicate_state,
3274	.atomic_destroy_state = intel_cdclk_destroy_state,
3275	};
3276
3277	struct intel_cdclk_state *
3278	intel_atomic_get_cdclk_state(struct intel_atomic_state *state)
3279	{
3280	struct intel_display *display = to_intel_display(state);
3281	struct intel_global_state *cdclk_state;
3282
3283	cdclk_state = intel_atomic_get_global_obj_state(state, obj: &display->cdclk.obj);
3284	if (IS_ERR(ptr: cdclk_state))
3285	return ERR_CAST(ptr: cdclk_state);
3286
3287	return to_intel_cdclk_state(cdclk_state);
3288	}
3289
3290	static int intel_cdclk_modeset_checks(struct intel_atomic_state *state,
3291	bool *need_cdclk_calc)
3292	{
3293	struct intel_display *display = to_intel_display(state);
3294	const struct intel_cdclk_state *old_cdclk_state;
3295	struct intel_cdclk_state *new_cdclk_state;
3296	int ret;
3297
3298	if (!intel_any_crtc_enable_changed(state) &&
3299	!intel_any_crtc_active_changed(state))
3300	return 0;
3301
3302	new_cdclk_state = intel_atomic_get_cdclk_state(state);
3303	if (IS_ERR(ptr: new_cdclk_state))
3304	return PTR_ERR(ptr: new_cdclk_state);
3305
3306	old_cdclk_state = intel_atomic_get_old_cdclk_state(state);
3307
3308	new_cdclk_state->enabled_pipes =
3309	intel_calc_enabled_pipes(state, enabled_pipes: old_cdclk_state->enabled_pipes);
3310
3311	new_cdclk_state->active_pipes =
3312	intel_calc_active_pipes(state, active_pipes: old_cdclk_state->active_pipes);
3313
3314	ret = intel_atomic_lock_global_state(obj_state: &new_cdclk_state->base);
3315	if (ret)
3316	return ret;
3317
3318	if (!old_cdclk_state->active_pipes != !new_cdclk_state->active_pipes)
3319	*need_cdclk_calc = true;
3320
3321	if (glk_cdclk_audio_wa_needed(display, cdclk_state: old_cdclk_state) !=
3322	glk_cdclk_audio_wa_needed(display, cdclk_state: new_cdclk_state))
3323	*need_cdclk_calc = true;
3324
3325	if (dg2_power_well_count(display, cdclk_state: old_cdclk_state) !=
3326	dg2_power_well_count(display, cdclk_state: new_cdclk_state))
3327	*need_cdclk_calc = true;
3328
3329	return 0;
3330	}
3331
3332	static int intel_crtcs_calc_min_cdclk(struct intel_atomic_state *state,
3333	bool *need_cdclk_calc)
3334	{
3335	const struct intel_crtc_state *old_crtc_state;
3336	const struct intel_crtc_state *new_crtc_state;
3337	struct intel_crtc *crtc;
3338	int i, ret;
3339
3340	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
3341	new_crtc_state, i) {
3342	ret = intel_cdclk_update_crtc_min_cdclk(state, crtc,
3343	old_min_cdclk: old_crtc_state->min_cdclk,
3344	new_min_cdclk: new_crtc_state->min_cdclk,
3345	need_cdclk_calc);
3346	if (ret)
3347	return ret;
3348	}
3349
3350	return 0;
3351	}
3352
3353	int intel_cdclk_state_set_joined_mbus(struct intel_atomic_state *state, bool joined_mbus)
3354	{
3355	struct intel_cdclk_state *cdclk_state;
3356
3357	cdclk_state = intel_atomic_get_cdclk_state(state);
3358	if (IS_ERR(ptr: cdclk_state))
3359	return PTR_ERR(ptr: cdclk_state);
3360
3361	cdclk_state->actual.joined_mbus = joined_mbus;
3362	cdclk_state->logical.joined_mbus = joined_mbus;
3363
3364	return intel_atomic_lock_global_state(obj_state: &cdclk_state->base);
3365	}
3366
3367	int intel_cdclk_init(struct intel_display *display)
3368	{
3369	struct intel_cdclk_state *cdclk_state;
3370
3371	cdclk_state = kzalloc(sizeof(*cdclk_state), GFP_KERNEL);
3372	if (!cdclk_state)
3373	return -ENOMEM;
3374
3375	intel_atomic_global_obj_init(display, obj: &display->cdclk.obj,
3376	state: &cdclk_state->base, funcs: &intel_cdclk_funcs);
3377
3378	return 0;
3379	}
3380
3381	static bool intel_cdclk_need_serialize(struct intel_display *display,
3382	const struct intel_cdclk_state *old_cdclk_state,
3383	const struct intel_cdclk_state *new_cdclk_state)
3384	{
3385	/*
3386	* We need to poke hw for DG2, because we notify PCode if
3387	* pipe power well count changes.
3388	*/
3389	return intel_cdclk_changed(a: &old_cdclk_state->actual,
3390	b: &new_cdclk_state->actual) ||
3391	dg2_power_well_count(display, cdclk_state: old_cdclk_state) !=
3392	dg2_power_well_count(display, cdclk_state: new_cdclk_state);
3393	}
3394
3395	static int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
3396	{
3397	struct intel_display *display = to_intel_display(state);
3398	const struct intel_cdclk_state *old_cdclk_state;
3399	struct intel_cdclk_state *new_cdclk_state;
3400	enum pipe pipe = INVALID_PIPE;
3401	int ret;
3402
3403	new_cdclk_state = intel_atomic_get_cdclk_state(state);
3404	if (IS_ERR(ptr: new_cdclk_state))
3405	return PTR_ERR(ptr: new_cdclk_state);
3406
3407	old_cdclk_state = intel_atomic_get_old_cdclk_state(state);
3408
3409	ret = intel_cdclk_modeset_calc_cdclk(state);
3410	if (ret)
3411	return ret;
3412
3413	if (intel_cdclk_need_serialize(display, old_cdclk_state, new_cdclk_state)) {
3414	/*
3415	* Also serialize commits across all crtcs
3416	* if the actual hw needs to be poked.
3417	*/
3418	ret = intel_atomic_serialize_global_state(obj_state: &new_cdclk_state->base);
3419	if (ret)
3420	return ret;
3421	} else if (intel_cdclk_changed(a: &old_cdclk_state->logical,
3422	b: &new_cdclk_state->logical)) {
3423	ret = intel_atomic_lock_global_state(obj_state: &new_cdclk_state->base);
3424	if (ret)
3425	return ret;
3426	} else {
3427	return 0;
3428	}
3429
3430	if (is_power_of_2(n: new_cdclk_state->active_pipes) &&
3431	intel_cdclk_can_cd2x_update(display,
3432	a: &old_cdclk_state->actual,
3433	b: &new_cdclk_state->actual)) {
3434	struct intel_crtc *crtc;
3435	struct intel_crtc_state *crtc_state;
3436
3437	pipe = ilog2(new_cdclk_state->active_pipes);
3438	crtc = intel_crtc_for_pipe(display, pipe);
3439
3440	crtc_state = intel_atomic_get_crtc_state(state: &state->base, crtc);
3441	if (IS_ERR(ptr: crtc_state))
3442	return PTR_ERR(ptr: crtc_state);
3443
3444	if (intel_crtc_needs_modeset(crtc_state))
3445	pipe = INVALID_PIPE;
3446	}
3447
3448	if (intel_cdclk_can_crawl_and_squash(display,
3449	a: &old_cdclk_state->actual,
3450	b: &new_cdclk_state->actual)) {
3451	drm_dbg_kms(display->drm,
3452	"Can change cdclk via crawling and squashing\n");
3453	} else if (intel_cdclk_can_squash(display,
3454	a: &old_cdclk_state->actual,
3455	b: &new_cdclk_state->actual)) {
3456	drm_dbg_kms(display->drm,
3457	"Can change cdclk via squashing\n");
3458	} else if (intel_cdclk_can_crawl(display,
3459	a: &old_cdclk_state->actual,
3460	b: &new_cdclk_state->actual)) {
3461	drm_dbg_kms(display->drm,
3462	"Can change cdclk via crawling\n");
3463	} else if (pipe != INVALID_PIPE) {
3464	new_cdclk_state->pipe = pipe;
3465
3466	drm_dbg_kms(display->drm,
3467	"Can change cdclk cd2x divider with pipe %c active\n",
3468	pipe_name(pipe));
3469	} else if (intel_cdclk_clock_changed(a: &old_cdclk_state->actual,
3470	b: &new_cdclk_state->actual)) {
3471	/* All pipes must be switched off while we change the cdclk. */
3472	ret = intel_modeset_all_pipes_late(state, reason: "CDCLK change");
3473	if (ret)
3474	return ret;
3475
3476	new_cdclk_state->disable_pipes = true;
3477
3478	drm_dbg_kms(display->drm,
3479	"Modeset required for cdclk change\n");
3480	}
3481
3482	if (intel_mdclk_cdclk_ratio(display, cdclk_config: &old_cdclk_state->actual) !=
3483	intel_mdclk_cdclk_ratio(display, cdclk_config: &new_cdclk_state->actual)) {
3484	int ratio = intel_mdclk_cdclk_ratio(display, cdclk_config: &new_cdclk_state->actual);
3485
3486	ret = intel_dbuf_state_set_mdclk_cdclk_ratio(state, ratio);
3487	if (ret)
3488	return ret;
3489	}
3490
3491	drm_dbg_kms(display->drm,
3492	"New cdclk calculated to be logical %u kHz, actual %u kHz\n",
3493	new_cdclk_state->logical.cdclk,
3494	new_cdclk_state->actual.cdclk);
3495	drm_dbg_kms(display->drm,
3496	"New voltage level calculated to be logical %u, actual %u\n",
3497	new_cdclk_state->logical.voltage_level,
3498	new_cdclk_state->actual.voltage_level);
3499
3500	return 0;
3501	}
3502
3503	int intel_cdclk_atomic_check(struct intel_atomic_state *state)
3504	{
3505	const struct intel_cdclk_state *old_cdclk_state;
3506	struct intel_cdclk_state *new_cdclk_state;
3507	bool need_cdclk_calc = false;
3508	int ret;
3509
3510	ret = intel_cdclk_modeset_checks(state, need_cdclk_calc: &need_cdclk_calc);
3511	if (ret)
3512	return ret;
3513
3514	ret = intel_crtcs_calc_min_cdclk(state, need_cdclk_calc: &need_cdclk_calc);
3515	if (ret)
3516	return ret;
3517
3518	ret = intel_dbuf_bw_calc_min_cdclk(state, need_cdclk_calc: &need_cdclk_calc);
3519	if (ret)
3520	return ret;
3521
3522	old_cdclk_state = intel_atomic_get_old_cdclk_state(state);
3523	new_cdclk_state = intel_atomic_get_new_cdclk_state(state);
3524
3525	if (new_cdclk_state &&
3526	old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk) {
3527	ret = intel_atomic_lock_global_state(obj_state: &new_cdclk_state->base);
3528	if (ret)
3529	return ret;
3530
3531	need_cdclk_calc = true;
3532	}
3533
3534	if (need_cdclk_calc) {
3535	ret = intel_modeset_calc_cdclk(state);
3536	if (ret)
3537	return ret;
3538	}
3539
3540	return 0;
3541	}
3542
3543	void intel_cdclk_update_hw_state(struct intel_display *display)
3544	{
3545	const struct intel_dbuf_bw_state *dbuf_bw_state =
3546	to_intel_dbuf_bw_state(obj_state: display->dbuf_bw.obj.state);
3547	struct intel_cdclk_state *cdclk_state =
3548	to_intel_cdclk_state(display->cdclk.obj.state);
3549	struct intel_crtc *crtc;
3550
3551	cdclk_state->enabled_pipes = 0;
3552	cdclk_state->active_pipes = 0;
3553
3554	for_each_intel_crtc(display->drm, crtc) {
3555	const struct intel_crtc_state *crtc_state =
3556	to_intel_crtc_state(crtc->base.state);
3557	enum pipe pipe = crtc->pipe;
3558
3559	if (crtc_state->hw.enable)
3560	cdclk_state->enabled_pipes |= BIT(pipe);
3561	if (crtc_state->hw.active)
3562	cdclk_state->active_pipes |= BIT(pipe);
3563
3564	cdclk_state->min_cdclk[pipe] = crtc_state->min_cdclk;
3565	cdclk_state->min_voltage_level[pipe] = crtc_state->min_voltage_level;
3566	}
3567
3568	cdclk_state->dbuf_bw_min_cdclk = intel_dbuf_bw_min_cdclk(display, dbuf_bw_state);
3569	}
3570
3571	void intel_cdclk_crtc_disable_noatomic(struct intel_crtc *crtc)
3572	{
3573	struct intel_display *display = to_intel_display(crtc);
3574
3575	intel_cdclk_update_hw_state(display);
3576	}
3577
3578	static int intel_compute_max_dotclk(struct intel_display *display)
3579	{
3580	int ppc = intel_cdclk_ppc(display, HAS_DOUBLE_WIDE(display));
3581	int guardband = intel_cdclk_guardband(display);
3582	int max_cdclk_freq = display->cdclk.max_cdclk_freq;
3583
3584	return ppc * max_cdclk_freq * guardband / 100;
3585	}
3586
3587	/**
3588	* intel_update_max_cdclk - Determine the maximum support CDCLK frequency
3589	* @display: display instance
3590	*
3591	* Determine the maximum CDCLK frequency the platform supports, and also
3592	* derive the maximum dot clock frequency the maximum CDCLK frequency
3593	* allows.
3594	*/
3595	void intel_update_max_cdclk(struct intel_display *display)
3596	{
3597	if (DISPLAY_VER(display) >= 35) {
3598	display->cdclk.max_cdclk_freq = 787200;
3599	} else if (DISPLAY_VERx100(display) >= 3002) {
3600	display->cdclk.max_cdclk_freq = 480000;
3601	} else if (DISPLAY_VER(display) >= 30) {
3602	display->cdclk.max_cdclk_freq = 691200;
3603	} else if (display->platform.jasperlake || display->platform.elkhartlake) {
3604	if (display->cdclk.hw.ref == 24000)
3605	display->cdclk.max_cdclk_freq = 552000;
3606	else
3607	display->cdclk.max_cdclk_freq = 556800;
3608	} else if (DISPLAY_VER(display) >= 11) {
3609	if (display->cdclk.hw.ref == 24000)
3610	display->cdclk.max_cdclk_freq = 648000;
3611	else
3612	display->cdclk.max_cdclk_freq = 652800;
3613	} else if (display->platform.geminilake) {
3614	display->cdclk.max_cdclk_freq = 316800;
3615	} else if (display->platform.broxton) {
3616	display->cdclk.max_cdclk_freq = 624000;
3617	} else if (DISPLAY_VER(display) == 9) {
3618	u32 limit = intel_de_read(display, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
3619	int max_cdclk, vco;
3620
3621	vco = display->cdclk.skl_preferred_vco_freq;
3622	drm_WARN_ON(display->drm, vco != 8100000 && vco != 8640000);
3623
3624	/*
3625	* Use the lower (vco 8640) cdclk values as a
3626	* first guess. skl_calc_cdclk() will correct it
3627	* if the preferred vco is 8100 instead.
3628	*/
3629	if (limit == SKL_DFSM_CDCLK_LIMIT_675)
3630	max_cdclk = 617143;
3631	else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
3632	max_cdclk = 540000;
3633	else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
3634	max_cdclk = 432000;
3635	else
3636	max_cdclk = 308571;
3637
3638	display->cdclk.max_cdclk_freq = skl_calc_cdclk(min_cdclk: max_cdclk, vco);
3639	} else if (display->platform.broadwell) {
3640	/*
3641	* FIXME with extra cooling we can allow
3642	* 540 MHz for ULX and 675 Mhz for ULT.
3643	* How can we know if extra cooling is
3644	* available? PCI ID, VTB, something else?
3645	*/
3646	if (intel_de_read(display, FUSE_STRAP) & HSW_CDCLK_LIMIT)
3647	display->cdclk.max_cdclk_freq = 450000;
3648	else if (display->platform.broadwell_ulx)
3649	display->cdclk.max_cdclk_freq = 450000;
3650	else if (display->platform.broadwell_ult)
3651	display->cdclk.max_cdclk_freq = 540000;
3652	else
3653	display->cdclk.max_cdclk_freq = 675000;
3654	} else if (display->platform.cherryview) {
3655	display->cdclk.max_cdclk_freq = 320000;
3656	} else if (display->platform.valleyview) {
3657	display->cdclk.max_cdclk_freq = 400000;
3658	} else {
3659	/* otherwise assume cdclk is fixed */
3660	display->cdclk.max_cdclk_freq = display->cdclk.hw.cdclk;
3661	}
3662
3663	display->cdclk.max_dotclk_freq = intel_compute_max_dotclk(display);
3664
3665	drm_dbg(display->drm, "Max CD clock rate: %d kHz\n",
3666	display->cdclk.max_cdclk_freq);
3667
3668	drm_dbg(display->drm, "Max dotclock rate: %d kHz\n",
3669	display->cdclk.max_dotclk_freq);
3670	}
3671
3672	/**
3673	* intel_update_cdclk - Determine the current CDCLK frequency
3674	* @display: display instance
3675	*
3676	* Determine the current CDCLK frequency.
3677	*/
3678	void intel_update_cdclk(struct intel_display *display)
3679	{
3680	intel_cdclk_get_cdclk(display, cdclk_config: &display->cdclk.hw);
3681
3682	/*
3683	* 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
3684	* Programmng [sic] note: bit[9:2] should be programmed to the number
3685	* of cdclk that generates 4MHz reference clock freq which is used to
3686	* generate GMBus clock. This will vary with the cdclk freq.
3687	*/
3688	if (display->platform.valleyview || display->platform.cherryview)
3689	intel_de_write(display, GMBUSFREQ_VLV,
3690	DIV_ROUND_UP(display->cdclk.hw.cdclk, 1000));
3691	}
3692
3693	static int dg1_rawclk(struct intel_display *display)
3694	{
3695	/*
3696	* DG1 always uses a 38.4 MHz rawclk. The bspec tells us
3697	* "Program Numerator=2, Denominator=4, Divider=37 decimal."
3698	*/
3699	intel_de_write(display, PCH_RAWCLK_FREQ,
3700	CNP_RAWCLK_DEN(4) | CNP_RAWCLK_DIV(37) | ICP_RAWCLK_NUM(2));
3701
3702	return 38400;
3703	}
3704
3705	static int cnp_rawclk(struct intel_display *display)
3706	{
3707	int divider, fraction;
3708	u32 rawclk;
3709
3710	if (intel_de_read(display, SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) {
3711	/* 24 MHz */
3712	divider = 24000;
3713	fraction = 0;
3714	} else {
3715	/* 19.2 MHz */
3716	divider = 19000;
3717	fraction = 200;
3718	}
3719
3720	rawclk = CNP_RAWCLK_DIV(divider / 1000);
3721	if (fraction) {
3722	int numerator = 1;
3723
3724	rawclk |= CNP_RAWCLK_DEN(DIV_ROUND_CLOSEST(numerator * 1000,
3725	fraction) - 1);
3726	if (INTEL_PCH_TYPE(display) >= PCH_ICP)
3727	rawclk |= ICP_RAWCLK_NUM(numerator);
3728	}
3729
3730	intel_de_write(display, PCH_RAWCLK_FREQ, val: rawclk);
3731	return divider + fraction;
3732	}
3733
3734	static int pch_rawclk(struct intel_display *display)
3735	{
3736	return (intel_de_read(display, PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
3737	}
3738
3739	static int i9xx_hrawclk(struct intel_display *display)
3740	{
3741	struct drm_i915_private *i915 = to_i915(dev: display->drm);
3742
3743	/* hrawclock is 1/4 the FSB frequency */
3744	return DIV_ROUND_CLOSEST(intel_fsb_freq(i915), 4);
3745	}
3746
3747	/**
3748	* intel_read_rawclk - Determine the current RAWCLK frequency
3749	* @display: display instance
3750	*
3751	* Determine the current RAWCLK frequency. RAWCLK is a fixed
3752	* frequency clock so this needs to done only once.
3753	*/
3754	u32 intel_read_rawclk(struct intel_display *display)
3755	{
3756	u32 freq;
3757
3758	if (INTEL_PCH_TYPE(display) >= PCH_MTL)
3759	/*
3760	* MTL always uses a 38.4 MHz rawclk. The bspec tells us
3761	* "RAWCLK_FREQ defaults to the values for 38.4 and does
3762	* not need to be programmed."
3763	*/
3764	freq = 38400;
3765	else if (INTEL_PCH_TYPE(display) >= PCH_DG1)
3766	freq = dg1_rawclk(display);
3767	else if (INTEL_PCH_TYPE(display) >= PCH_CNP)
3768	freq = cnp_rawclk(display);
3769	else if (HAS_PCH_SPLIT(display))
3770	freq = pch_rawclk(display);
3771	else if (display->platform.valleyview || display->platform.cherryview)
3772	freq = vlv_clock_get_hrawclk(drm: display->drm);
3773	else if (DISPLAY_VER(display) >= 3)
3774	freq = i9xx_hrawclk(display);
3775	else
3776	/* no rawclk on other platforms, or no need to know it */
3777	return 0;
3778
3779	return freq;
3780	}
3781
3782	static int i915_cdclk_info_show(struct seq_file *m, void *unused)
3783	{
3784	struct intel_display *display = m->private;
3785
3786	seq_printf(m, fmt: "Current CD clock frequency: %d kHz\n", display->cdclk.hw.cdclk);
3787	seq_printf(m, fmt: "Max CD clock frequency: %d kHz\n", display->cdclk.max_cdclk_freq);
3788	seq_printf(m, fmt: "Max pixel clock frequency: %d kHz\n", display->cdclk.max_dotclk_freq);
3789
3790	return 0;
3791	}
3792
3793	DEFINE_SHOW_ATTRIBUTE(i915_cdclk_info);
3794
3795	void intel_cdclk_debugfs_register(struct intel_display *display)
3796	{
3797	debugfs_create_file("i915_cdclk_info", 0444, display->drm->debugfs_root,
3798	display, &i915_cdclk_info_fops);
3799	}
3800
3801	static const struct intel_cdclk_funcs xe3lpd_cdclk_funcs = {
3802	.get_cdclk = bxt_get_cdclk,
3803	.set_cdclk = bxt_set_cdclk,
3804	.modeset_calc_cdclk = bxt_modeset_calc_cdclk,
3805	.calc_voltage_level = xe3lpd_calc_voltage_level,
3806	};
3807
3808	static const struct intel_cdclk_funcs rplu_cdclk_funcs = {
3809	.get_cdclk = bxt_get_cdclk,
3810	.set_cdclk = bxt_set_cdclk,
3811	.modeset_calc_cdclk = bxt_modeset_calc_cdclk,
3812	.calc_voltage_level = rplu_calc_voltage_level,
3813	};
3814
3815	static const struct intel_cdclk_funcs tgl_cdclk_funcs = {
3816	.get_cdclk = bxt_get_cdclk,
3817	.set_cdclk = bxt_set_cdclk,
3818	.modeset_calc_cdclk = bxt_modeset_calc_cdclk,
3819	.calc_voltage_level = tgl_calc_voltage_level,
3820	};
3821
3822	static const struct intel_cdclk_funcs ehl_cdclk_funcs = {
3823	.get_cdclk = bxt_get_cdclk,
3824	.set_cdclk = bxt_set_cdclk,
3825	.modeset_calc_cdclk = bxt_modeset_calc_cdclk,
3826	.calc_voltage_level = ehl_calc_voltage_level,
3827	};
3828
3829	static const struct intel_cdclk_funcs icl_cdclk_funcs = {
3830	.get_cdclk = bxt_get_cdclk,
3831	.set_cdclk = bxt_set_cdclk,
3832	.modeset_calc_cdclk = bxt_modeset_calc_cdclk,
3833	.calc_voltage_level = icl_calc_voltage_level,
3834	};
3835
3836	static const struct intel_cdclk_funcs bxt_cdclk_funcs = {
3837	.get_cdclk = bxt_get_cdclk,
3838	.set_cdclk = bxt_set_cdclk,
3839	.modeset_calc_cdclk = bxt_modeset_calc_cdclk,
3840	.calc_voltage_level = bxt_calc_voltage_level,
3841	};
3842
3843	static const struct intel_cdclk_funcs skl_cdclk_funcs = {
3844	.get_cdclk = skl_get_cdclk,
3845	.set_cdclk = skl_set_cdclk,
3846	.modeset_calc_cdclk = skl_modeset_calc_cdclk,
3847	};
3848
3849	static const struct intel_cdclk_funcs bdw_cdclk_funcs = {
3850	.get_cdclk = bdw_get_cdclk,
3851	.set_cdclk = bdw_set_cdclk,
3852	.modeset_calc_cdclk = bdw_modeset_calc_cdclk,
3853	};
3854
3855	static const struct intel_cdclk_funcs chv_cdclk_funcs = {
3856	.get_cdclk = vlv_get_cdclk,
3857	.set_cdclk = chv_set_cdclk,
3858	.modeset_calc_cdclk = vlv_modeset_calc_cdclk,
3859	};
3860
3861	static const struct intel_cdclk_funcs vlv_cdclk_funcs = {
3862	.get_cdclk = vlv_get_cdclk,
3863	.set_cdclk = vlv_set_cdclk,
3864	.modeset_calc_cdclk = vlv_modeset_calc_cdclk,
3865	};
3866
3867	static const struct intel_cdclk_funcs hsw_cdclk_funcs = {
3868	.get_cdclk = hsw_get_cdclk,
3869	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3870	};
3871
3872	/* SNB, IVB, 965G, 945G */
3873	static const struct intel_cdclk_funcs fixed_400mhz_cdclk_funcs = {
3874	.get_cdclk = fixed_400mhz_get_cdclk,
3875	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3876	};
3877
3878	static const struct intel_cdclk_funcs ilk_cdclk_funcs = {
3879	.get_cdclk = fixed_450mhz_get_cdclk,
3880	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3881	};
3882
3883	static const struct intel_cdclk_funcs gm45_cdclk_funcs = {
3884	.get_cdclk = gm45_get_cdclk,
3885	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3886	};
3887
3888	/* G45 uses G33 */
3889
3890	static const struct intel_cdclk_funcs i965gm_cdclk_funcs = {
3891	.get_cdclk = i965gm_get_cdclk,
3892	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3893	};
3894
3895	/* i965G uses fixed 400 */
3896
3897	static const struct intel_cdclk_funcs pnv_cdclk_funcs = {
3898	.get_cdclk = pnv_get_cdclk,
3899	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3900	};
3901
3902	static const struct intel_cdclk_funcs g33_cdclk_funcs = {
3903	.get_cdclk = g33_get_cdclk,
3904	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3905	};
3906
3907	static const struct intel_cdclk_funcs i945gm_cdclk_funcs = {
3908	.get_cdclk = i945gm_get_cdclk,
3909	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3910	};
3911
3912	/* i945G uses fixed 400 */
3913
3914	static const struct intel_cdclk_funcs i915gm_cdclk_funcs = {
3915	.get_cdclk = i915gm_get_cdclk,
3916	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3917	};
3918
3919	static const struct intel_cdclk_funcs i915g_cdclk_funcs = {
3920	.get_cdclk = fixed_333mhz_get_cdclk,
3921	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3922	};
3923
3924	static const struct intel_cdclk_funcs i865g_cdclk_funcs = {
3925	.get_cdclk = fixed_266mhz_get_cdclk,
3926	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3927	};
3928
3929	static const struct intel_cdclk_funcs i85x_cdclk_funcs = {
3930	.get_cdclk = i85x_get_cdclk,
3931	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3932	};
3933
3934	static const struct intel_cdclk_funcs i845g_cdclk_funcs = {
3935	.get_cdclk = fixed_200mhz_get_cdclk,
3936	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3937	};
3938
3939	static const struct intel_cdclk_funcs i830_cdclk_funcs = {
3940	.get_cdclk = fixed_133mhz_get_cdclk,
3941	.modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3942	};
3943
3944	/**
3945	* intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks
3946	* @display: display instance
3947	*/
3948	void intel_init_cdclk_hooks(struct intel_display *display)
3949	{
3950	if (DISPLAY_VER(display) >= 35) {
3951	display->funcs.cdclk = &xe3lpd_cdclk_funcs;
3952	display->cdclk.table = xe3p_lpd_cdclk_table;
3953	} else if (DISPLAY_VER(display) >= 30) {
3954	display->funcs.cdclk = &xe3lpd_cdclk_funcs;
3955	display->cdclk.table = xe3lpd_cdclk_table;
3956	} else if (DISPLAY_VER(display) >= 20) {
3957	display->funcs.cdclk = &rplu_cdclk_funcs;
3958	display->cdclk.table = xe2lpd_cdclk_table;
3959	} else if (DISPLAY_VERx100(display) >= 1401) {
3960	display->funcs.cdclk = &rplu_cdclk_funcs;
3961	display->cdclk.table = xe2hpd_cdclk_table;
3962	} else if (DISPLAY_VER(display) >= 14) {
3963	display->funcs.cdclk = &rplu_cdclk_funcs;
3964	display->cdclk.table = mtl_cdclk_table;
3965	} else if (display->platform.dg2) {
3966	display->funcs.cdclk = &tgl_cdclk_funcs;
3967	display->cdclk.table = dg2_cdclk_table;
3968	} else if (display->platform.alderlake_p) {
3969	/* Wa_22011320316:adl-p[a0] */
3970	if (display->platform.alderlake_p && IS_DISPLAY_STEP(display, STEP_A0, STEP_B0)) {
3971	display->cdclk.table = adlp_a_step_cdclk_table;
3972	display->funcs.cdclk = &tgl_cdclk_funcs;
3973	} else if (display->platform.alderlake_p_raptorlake_u) {
3974	display->cdclk.table = rplu_cdclk_table;
3975	display->funcs.cdclk = &rplu_cdclk_funcs;
3976	} else {
3977	display->cdclk.table = adlp_cdclk_table;
3978	display->funcs.cdclk = &tgl_cdclk_funcs;
3979	}
3980	} else if (display->platform.rocketlake) {
3981	display->funcs.cdclk = &tgl_cdclk_funcs;
3982	display->cdclk.table = rkl_cdclk_table;
3983	} else if (DISPLAY_VER(display) >= 12) {
3984	display->funcs.cdclk = &tgl_cdclk_funcs;
3985	display->cdclk.table = icl_cdclk_table;
3986	} else if (display->platform.jasperlake || display->platform.elkhartlake) {
3987	display->funcs.cdclk = &ehl_cdclk_funcs;
3988	display->cdclk.table = icl_cdclk_table;
3989	} else if (DISPLAY_VER(display) >= 11) {
3990	display->funcs.cdclk = &icl_cdclk_funcs;
3991	display->cdclk.table = icl_cdclk_table;
3992	} else if (display->platform.geminilake || display->platform.broxton) {
3993	display->funcs.cdclk = &bxt_cdclk_funcs;
3994	if (display->platform.geminilake)
3995	display->cdclk.table = glk_cdclk_table;
3996	else
3997	display->cdclk.table = bxt_cdclk_table;
3998	} else if (DISPLAY_VER(display) == 9) {
3999	display->funcs.cdclk = &skl_cdclk_funcs;
4000	} else if (display->platform.broadwell) {
4001	display->funcs.cdclk = &bdw_cdclk_funcs;
4002	} else if (display->platform.haswell) {
4003	display->funcs.cdclk = &hsw_cdclk_funcs;
4004	} else if (display->platform.cherryview) {
4005	display->funcs.cdclk = &chv_cdclk_funcs;
4006	} else if (display->platform.valleyview) {
4007	display->funcs.cdclk = &vlv_cdclk_funcs;
4008	} else if (display->platform.sandybridge || display->platform.ivybridge) {
4009	display->funcs.cdclk = &fixed_400mhz_cdclk_funcs;
4010	} else if (display->platform.ironlake) {
4011	display->funcs.cdclk = &ilk_cdclk_funcs;
4012	} else if (display->platform.gm45) {
4013	display->funcs.cdclk = &gm45_cdclk_funcs;
4014	} else if (display->platform.g45) {
4015	display->funcs.cdclk = &g33_cdclk_funcs;
4016	} else if (display->platform.i965gm) {
4017	display->funcs.cdclk = &i965gm_cdclk_funcs;
4018	} else if (display->platform.i965g) {
4019	display->funcs.cdclk = &fixed_400mhz_cdclk_funcs;
4020	} else if (display->platform.pineview) {
4021	display->funcs.cdclk = &pnv_cdclk_funcs;
4022	} else if (display->platform.g33) {
4023	display->funcs.cdclk = &g33_cdclk_funcs;
4024	} else if (display->platform.i945gm) {
4025	display->funcs.cdclk = &i945gm_cdclk_funcs;
4026	} else if (display->platform.i945g) {
4027	display->funcs.cdclk = &fixed_400mhz_cdclk_funcs;
4028	} else if (display->platform.i915gm) {
4029	display->funcs.cdclk = &i915gm_cdclk_funcs;
4030	} else if (display->platform.i915g) {
4031	display->funcs.cdclk = &i915g_cdclk_funcs;
4032	} else if (display->platform.i865g) {
4033	display->funcs.cdclk = &i865g_cdclk_funcs;
4034	} else if (display->platform.i85x) {
4035	display->funcs.cdclk = &i85x_cdclk_funcs;
4036	} else if (display->platform.i845g) {
4037	display->funcs.cdclk = &i845g_cdclk_funcs;
4038	} else if (display->platform.i830) {
4039	display->funcs.cdclk = &i830_cdclk_funcs;
4040	}
4041
4042	if (drm_WARN(display->drm, !display->funcs.cdclk,
4043	"Unknown platform. Assuming i830\n"))
4044	display->funcs.cdclk = &i830_cdclk_funcs;
4045	}
4046
4047	int intel_cdclk_logical(const struct intel_cdclk_state *cdclk_state)
4048	{
4049	return cdclk_state->logical.cdclk;
4050	}
4051
4052	int intel_cdclk_actual(const struct intel_cdclk_state *cdclk_state)
4053	{
4054	return cdclk_state->actual.cdclk;
4055	}
4056
4057	int intel_cdclk_actual_voltage_level(const struct intel_cdclk_state *cdclk_state)
4058	{
4059	return cdclk_state->actual.voltage_level;
4060	}
4061
4062	int intel_cdclk_min_cdclk(const struct intel_cdclk_state *cdclk_state, enum pipe pipe)
4063	{
4064	return cdclk_state->min_cdclk[pipe];
4065	}
4066
4067	bool intel_cdclk_pmdemand_needs_update(struct intel_atomic_state *state)
4068	{
4069	const struct intel_cdclk_state *new_cdclk_state, *old_cdclk_state;
4070
4071	new_cdclk_state = intel_atomic_get_new_cdclk_state(state);
4072	old_cdclk_state = intel_atomic_get_old_cdclk_state(state);
4073
4074	if (new_cdclk_state &&
4075	(new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk ||
4076	new_cdclk_state->actual.voltage_level != old_cdclk_state->actual.voltage_level))
4077	return true;
4078
4079	return false;
4080	}
4081
4082	void intel_cdclk_force_min_cdclk(struct intel_cdclk_state *cdclk_state, int force_min_cdclk)
4083	{
4084	cdclk_state->force_min_cdclk = force_min_cdclk;
4085	}
4086
4087	void intel_cdclk_read_hw(struct intel_display *display)
4088	{
4089	struct intel_cdclk_state *cdclk_state;
4090
4091	cdclk_state = to_intel_cdclk_state(display->cdclk.obj.state);
4092
4093	intel_update_cdclk(display);
4094	intel_cdclk_dump_config(display, cdclk_config: &display->cdclk.hw, context: "Current CDCLK");
4095	cdclk_state->actual = display->cdclk.hw;
4096	cdclk_state->logical = display->cdclk.hw;
4097	}
4098
4099	static int calc_cdclk(const struct intel_crtc_state *crtc_state, int min_cdclk)
4100	{
4101	struct intel_display *display = to_intel_display(crtc_state);
4102
4103	if (DISPLAY_VER(display) >= 10 || display->platform.broxton) {
4104	return bxt_calc_cdclk(display, min_cdclk);
4105	} else if (DISPLAY_VER(display) == 9) {
4106	int vco;
4107
4108	vco = display->cdclk.skl_preferred_vco_freq;
4109	if (vco == 0)
4110	vco = 8100000;
4111
4112	return skl_calc_cdclk(min_cdclk, vco);
4113	} else if (display->platform.broadwell) {
4114	return bdw_calc_cdclk(min_cdclk);
4115	} else if (display->platform.cherryview || display->platform.valleyview) {
4116	return vlv_calc_cdclk(display, min_cdclk);
4117	} else {
4118	return display->cdclk.max_cdclk_freq;
4119	}
4120	}
4121
4122	static unsigned int _intel_cdclk_prefill_adj(const struct intel_crtc_state *crtc_state,
4123	int clock, int min_cdclk)
4124	{
4125	struct intel_display *display = to_intel_display(crtc_state);
4126	int ppc = intel_cdclk_ppc(display, double_wide: crtc_state->double_wide);
4127	int cdclk = calc_cdclk(crtc_state, min_cdclk);
4128
4129	return min(0x10000, DIV_ROUND_UP_ULL((u64)clock << 16, ppc * cdclk));
4130	}
4131
4132	unsigned int intel_cdclk_prefill_adjustment(const struct intel_crtc_state *crtc_state)
4133	{
4134	/* FIXME use the actual min_cdclk for the pipe here */
4135	return intel_cdclk_prefill_adjustment_worst(crtc_state);
4136	}
4137
4138	unsigned int intel_cdclk_prefill_adjustment_worst(const struct intel_crtc_state *crtc_state)
4139	{
4140	int clock = crtc_state->hw.pipe_mode.crtc_clock;
4141	int min_cdclk;
4142
4143	/*
4144	* FIXME could perhaps consider a few more of the factors
4145	* that go the per-crtc min_cdclk. Namely anything that
4146	* only changes during full modesets.
4147	*
4148	* FIXME this assumes 1:1 scaling, but the other _worst() stuff
4149	* assumes max downscaling, so the final result will be
4150	* unrealistically bad. Figure out where the actual maximum value
4151	* lies and use that to compute a more realistic worst case
4152	* estimate...
4153	*/
4154	min_cdclk = _intel_pixel_rate_to_cdclk(crtc_state, pixel_rate: clock);
4155
4156	return _intel_cdclk_prefill_adj(crtc_state, clock, min_cdclk);
4157	}
4158
4159	int intel_cdclk_min_cdclk_for_prefill(const struct intel_crtc_state *crtc_state,
4160	unsigned int prefill_lines_unadjusted,
4161	unsigned int prefill_lines_available)
4162	{
4163	struct intel_display *display = to_intel_display(crtc_state);
4164	const struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
4165	int ppc = intel_cdclk_ppc(display, double_wide: crtc_state->double_wide);
4166
4167	return DIV_ROUND_UP_ULL(mul_u32_u32(pipe_mode->crtc_clock, prefill_lines_unadjusted),
4168	ppc * prefill_lines_available);
4169	}
4170