1/*
2 * Copyright © 2009 Keith Packard
3 *
4 * Permission to use, copy, modify, distribute, and sell this software and its
5 * documentation for any purpose is hereby granted without fee, provided that
6 * the above copyright notice appear in all copies and that both that copyright
7 * notice and this permission notice appear in supporting documentation, and
8 * that the name of the copyright holders not be used in advertising or
9 * publicity pertaining to distribution of the software without specific,
10 * written prior permission. The copyright holders make no representations
11 * about the suitability of this software for any purpose. It is provided "as
12 * is" without express or implied warranty.
13 *
14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
20 * OF THIS SOFTWARE.
21 */
22
23#include <linux/backlight.h>
24#include <linux/delay.h>
25#include <linux/dynamic_debug.h>
26#include <linux/errno.h>
27#include <linux/export.h>
28#include <linux/i2c.h>
29#include <linux/init.h>
30#include <linux/iopoll.h>
31#include <linux/kernel.h>
32#include <linux/minmax.h>
33#include <linux/module.h>
34#include <linux/sched.h>
35#include <linux/seq_file.h>
36#include <linux/string_helpers.h>
37
38#include <drm/display/drm_dp_helper.h>
39#include <drm/display/drm_dp_mst_helper.h>
40#include <drm/drm_edid.h>
41#include <drm/drm_fixed.h>
42#include <drm/drm_print.h>
43#include <drm/drm_vblank.h>
44#include <drm/drm_panel.h>
45
46#include "drm_dp_helper_internal.h"
47
48DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0,
49 "DRM_UT_CORE",
50 "DRM_UT_DRIVER",
51 "DRM_UT_KMS",
52 "DRM_UT_PRIME",
53 "DRM_UT_ATOMIC",
54 "DRM_UT_VBL",
55 "DRM_UT_STATE",
56 "DRM_UT_LEASE",
57 "DRM_UT_DP",
58 "DRM_UT_DRMRES");
59
60struct dp_aux_backlight {
61 struct backlight_device *base;
62 struct drm_dp_aux *aux;
63 struct drm_edp_backlight_info info;
64 bool enabled;
65};
66
67/**
68 * DOC: dp helpers
69 *
70 * These functions contain some common logic and helpers at various abstraction
71 * levels to deal with Display Port sink devices and related things like DP aux
72 * channel transfers, EDID reading over DP aux channels, decoding certain DPCD
73 * blocks, ...
74 */
75
76/* Helpers for DP link training */
77static u8 dp_link_status(const u8 link_status[DP_LINK_STATUS_SIZE], int r)
78{
79 return link_status[r - DP_LANE0_1_STATUS];
80}
81
82static u8 dp_get_lane_status(const u8 link_status[DP_LINK_STATUS_SIZE],
83 int lane)
84{
85 int i = DP_LANE0_1_STATUS + (lane >> 1);
86 int s = (lane & 1) * 4;
87 u8 l = dp_link_status(link_status, r: i);
88
89 return (l >> s) & 0xf;
90}
91
92bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
93 int lane_count)
94{
95 u8 lane_align;
96 u8 lane_status;
97 int lane;
98
99 lane_align = dp_link_status(link_status,
100 DP_LANE_ALIGN_STATUS_UPDATED);
101 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
102 return false;
103 for (lane = 0; lane < lane_count; lane++) {
104 lane_status = dp_get_lane_status(link_status, lane);
105 if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS)
106 return false;
107 }
108 return true;
109}
110EXPORT_SYMBOL(drm_dp_channel_eq_ok);
111
112bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
113 int lane_count)
114{
115 int lane;
116 u8 lane_status;
117
118 for (lane = 0; lane < lane_count; lane++) {
119 lane_status = dp_get_lane_status(link_status, lane);
120 if ((lane_status & DP_LANE_CR_DONE) == 0)
121 return false;
122 }
123 return true;
124}
125EXPORT_SYMBOL(drm_dp_clock_recovery_ok);
126
127bool drm_dp_post_lt_adj_req_in_progress(const u8 link_status[DP_LINK_STATUS_SIZE])
128{
129 u8 lane_align = dp_link_status(link_status, DP_LANE_ALIGN_STATUS_UPDATED);
130
131 return lane_align & DP_POST_LT_ADJ_REQ_IN_PROGRESS;
132}
133EXPORT_SYMBOL(drm_dp_post_lt_adj_req_in_progress);
134
135u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],
136 int lane)
137{
138 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
139 int s = ((lane & 1) ?
140 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
141 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
142 u8 l = dp_link_status(link_status, r: i);
143
144 return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
145}
146EXPORT_SYMBOL(drm_dp_get_adjust_request_voltage);
147
148u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],
149 int lane)
150{
151 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
152 int s = ((lane & 1) ?
153 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
154 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
155 u8 l = dp_link_status(link_status, r: i);
156
157 return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
158}
159EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis);
160
161/* DP 2.0 128b/132b */
162u8 drm_dp_get_adjust_tx_ffe_preset(const u8 link_status[DP_LINK_STATUS_SIZE],
163 int lane)
164{
165 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
166 int s = ((lane & 1) ?
167 DP_ADJUST_TX_FFE_PRESET_LANE1_SHIFT :
168 DP_ADJUST_TX_FFE_PRESET_LANE0_SHIFT);
169 u8 l = dp_link_status(link_status, r: i);
170
171 return (l >> s) & 0xf;
172}
173EXPORT_SYMBOL(drm_dp_get_adjust_tx_ffe_preset);
174
175/* DP 2.0 errata for 128b/132b */
176bool drm_dp_128b132b_lane_channel_eq_done(const u8 link_status[DP_LINK_STATUS_SIZE],
177 int lane_count)
178{
179 u8 lane_align, lane_status;
180 int lane;
181
182 lane_align = dp_link_status(link_status, DP_LANE_ALIGN_STATUS_UPDATED);
183 if (!(lane_align & DP_INTERLANE_ALIGN_DONE))
184 return false;
185
186 for (lane = 0; lane < lane_count; lane++) {
187 lane_status = dp_get_lane_status(link_status, lane);
188 if (!(lane_status & DP_LANE_CHANNEL_EQ_DONE))
189 return false;
190 }
191 return true;
192}
193EXPORT_SYMBOL(drm_dp_128b132b_lane_channel_eq_done);
194
195/* DP 2.0 errata for 128b/132b */
196bool drm_dp_128b132b_lane_symbol_locked(const u8 link_status[DP_LINK_STATUS_SIZE],
197 int lane_count)
198{
199 u8 lane_status;
200 int lane;
201
202 for (lane = 0; lane < lane_count; lane++) {
203 lane_status = dp_get_lane_status(link_status, lane);
204 if (!(lane_status & DP_LANE_SYMBOL_LOCKED))
205 return false;
206 }
207 return true;
208}
209EXPORT_SYMBOL(drm_dp_128b132b_lane_symbol_locked);
210
211/* DP 2.0 errata for 128b/132b */
212bool drm_dp_128b132b_eq_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE])
213{
214 u8 status = dp_link_status(link_status, DP_LANE_ALIGN_STATUS_UPDATED);
215
216 return status & DP_128B132B_DPRX_EQ_INTERLANE_ALIGN_DONE;
217}
218EXPORT_SYMBOL(drm_dp_128b132b_eq_interlane_align_done);
219
220/* DP 2.0 errata for 128b/132b */
221bool drm_dp_128b132b_cds_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE])
222{
223 u8 status = dp_link_status(link_status, DP_LANE_ALIGN_STATUS_UPDATED);
224
225 return status & DP_128B132B_DPRX_CDS_INTERLANE_ALIGN_DONE;
226}
227EXPORT_SYMBOL(drm_dp_128b132b_cds_interlane_align_done);
228
229/* DP 2.0 errata for 128b/132b */
230bool drm_dp_128b132b_link_training_failed(const u8 link_status[DP_LINK_STATUS_SIZE])
231{
232 u8 status = dp_link_status(link_status, DP_LANE_ALIGN_STATUS_UPDATED);
233
234 return status & DP_128B132B_LT_FAILED;
235}
236EXPORT_SYMBOL(drm_dp_128b132b_link_training_failed);
237
238static int __8b10b_clock_recovery_delay_us(const struct drm_dp_aux *aux, u8 rd_interval)
239{
240 if (rd_interval > 4)
241 drm_dbg_kms(aux->drm_dev, "%s: invalid AUX interval 0x%02x (max 4)\n",
242 aux->name, rd_interval);
243
244 if (rd_interval == 0)
245 return 100;
246
247 return rd_interval * 4 * USEC_PER_MSEC;
248}
249
250static int __8b10b_channel_eq_delay_us(const struct drm_dp_aux *aux, u8 rd_interval)
251{
252 if (rd_interval > 4)
253 drm_dbg_kms(aux->drm_dev, "%s: invalid AUX interval 0x%02x (max 4)\n",
254 aux->name, rd_interval);
255
256 if (rd_interval == 0)
257 return 400;
258
259 return rd_interval * 4 * USEC_PER_MSEC;
260}
261
262static int __128b132b_channel_eq_delay_us(const struct drm_dp_aux *aux, u8 rd_interval)
263{
264 switch (rd_interval) {
265 default:
266 drm_dbg_kms(aux->drm_dev, "%s: invalid AUX interval 0x%02x\n",
267 aux->name, rd_interval);
268 fallthrough;
269 case DP_128B132B_TRAINING_AUX_RD_INTERVAL_400_US:
270 return 400;
271 case DP_128B132B_TRAINING_AUX_RD_INTERVAL_4_MS:
272 return 4000;
273 case DP_128B132B_TRAINING_AUX_RD_INTERVAL_8_MS:
274 return 8000;
275 case DP_128B132B_TRAINING_AUX_RD_INTERVAL_12_MS:
276 return 12000;
277 case DP_128B132B_TRAINING_AUX_RD_INTERVAL_16_MS:
278 return 16000;
279 case DP_128B132B_TRAINING_AUX_RD_INTERVAL_32_MS:
280 return 32000;
281 case DP_128B132B_TRAINING_AUX_RD_INTERVAL_64_MS:
282 return 64000;
283 }
284}
285
286/*
287 * The link training delays are different for:
288 *
289 * - Clock recovery vs. channel equalization
290 * - DPRX vs. LTTPR
291 * - 128b/132b vs. 8b/10b
292 * - DPCD rev 1.3 vs. later
293 *
294 * Get the correct delay in us, reading DPCD if necessary.
295 */
296static int __read_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
297 enum drm_dp_phy dp_phy, bool uhbr, bool cr)
298{
299 int (*parse)(const struct drm_dp_aux *aux, u8 rd_interval);
300 unsigned int offset;
301 u8 rd_interval, mask;
302
303 if (dp_phy == DP_PHY_DPRX) {
304 if (uhbr) {
305 if (cr)
306 return 100;
307
308 offset = DP_128B132B_TRAINING_AUX_RD_INTERVAL;
309 mask = DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK;
310 parse = __128b132b_channel_eq_delay_us;
311 } else {
312 if (cr && dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)
313 return 100;
314
315 offset = DP_TRAINING_AUX_RD_INTERVAL;
316 mask = DP_TRAINING_AUX_RD_MASK;
317 if (cr)
318 parse = __8b10b_clock_recovery_delay_us;
319 else
320 parse = __8b10b_channel_eq_delay_us;
321 }
322 } else {
323 if (uhbr) {
324 offset = DP_128B132B_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy);
325 mask = DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK;
326 parse = __128b132b_channel_eq_delay_us;
327 } else {
328 if (cr)
329 return 100;
330
331 offset = DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy);
332 mask = DP_TRAINING_AUX_RD_MASK;
333 parse = __8b10b_channel_eq_delay_us;
334 }
335 }
336
337 if (offset < DP_RECEIVER_CAP_SIZE) {
338 rd_interval = dpcd[offset];
339 } else {
340 if (drm_dp_dpcd_read_byte(aux, offset, valuep: &rd_interval) < 0) {
341 drm_dbg_kms(aux->drm_dev, "%s: failed rd interval read\n",
342 aux->name);
343 /* arbitrary default delay */
344 return 400;
345 }
346 }
347
348 return parse(aux, rd_interval & mask);
349}
350
351int drm_dp_read_clock_recovery_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
352 enum drm_dp_phy dp_phy, bool uhbr)
353{
354 return __read_delay(aux, dpcd, dp_phy, uhbr, cr: true);
355}
356EXPORT_SYMBOL(drm_dp_read_clock_recovery_delay);
357
358int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
359 enum drm_dp_phy dp_phy, bool uhbr)
360{
361 return __read_delay(aux, dpcd, dp_phy, uhbr, cr: false);
362}
363EXPORT_SYMBOL(drm_dp_read_channel_eq_delay);
364
365/* Per DP 2.0 Errata */
366int drm_dp_128b132b_read_aux_rd_interval(struct drm_dp_aux *aux)
367{
368 int unit;
369 u8 val;
370
371 if (drm_dp_dpcd_read_byte(aux, DP_128B132B_TRAINING_AUX_RD_INTERVAL, valuep: &val) < 0) {
372 drm_err(aux->drm_dev, "%s: failed rd interval read\n",
373 aux->name);
374 /* default to max */
375 val = DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK;
376 }
377
378 unit = (val & DP_128B132B_TRAINING_AUX_RD_INTERVAL_1MS_UNIT) ? 1 : 2;
379 val &= DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK;
380
381 return (val + 1) * unit * 1000;
382}
383EXPORT_SYMBOL(drm_dp_128b132b_read_aux_rd_interval);
384
385void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux,
386 const u8 dpcd[DP_RECEIVER_CAP_SIZE])
387{
388 u8 rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
389 DP_TRAINING_AUX_RD_MASK;
390 int delay_us;
391
392 if (dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)
393 delay_us = 100;
394 else
395 delay_us = __8b10b_clock_recovery_delay_us(aux, rd_interval);
396
397 usleep_range(min: delay_us, max: delay_us * 2);
398}
399EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay);
400
401static void __drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux,
402 u8 rd_interval)
403{
404 int delay_us = __8b10b_channel_eq_delay_us(aux, rd_interval);
405
406 usleep_range(min: delay_us, max: delay_us * 2);
407}
408
409void drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux,
410 const u8 dpcd[DP_RECEIVER_CAP_SIZE])
411{
412 __drm_dp_link_train_channel_eq_delay(aux,
413 rd_interval: dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
414 DP_TRAINING_AUX_RD_MASK);
415}
416EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay);
417
418/**
419 * drm_dp_phy_name() - Get the name of the given DP PHY
420 * @dp_phy: The DP PHY identifier
421 *
422 * Given the @dp_phy, get a user friendly name of the DP PHY, either "DPRX" or
423 * "LTTPR <N>", or "<INVALID DP PHY>" on errors. The returned string is always
424 * non-NULL and valid.
425 *
426 * Returns: Name of the DP PHY.
427 */
428const char *drm_dp_phy_name(enum drm_dp_phy dp_phy)
429{
430 static const char * const phy_names[] = {
431 [DP_PHY_DPRX] = "DPRX",
432 [DP_PHY_LTTPR1] = "LTTPR 1",
433 [DP_PHY_LTTPR2] = "LTTPR 2",
434 [DP_PHY_LTTPR3] = "LTTPR 3",
435 [DP_PHY_LTTPR4] = "LTTPR 4",
436 [DP_PHY_LTTPR5] = "LTTPR 5",
437 [DP_PHY_LTTPR6] = "LTTPR 6",
438 [DP_PHY_LTTPR7] = "LTTPR 7",
439 [DP_PHY_LTTPR8] = "LTTPR 8",
440 };
441
442 if (dp_phy < 0 || dp_phy >= ARRAY_SIZE(phy_names) ||
443 WARN_ON(!phy_names[dp_phy]))
444 return "<INVALID DP PHY>";
445
446 return phy_names[dp_phy];
447}
448EXPORT_SYMBOL(drm_dp_phy_name);
449
450void drm_dp_lttpr_link_train_clock_recovery_delay(void)
451{
452 usleep_range(min: 100, max: 200);
453}
454EXPORT_SYMBOL(drm_dp_lttpr_link_train_clock_recovery_delay);
455
456static u8 dp_lttpr_phy_cap(const u8 phy_cap[DP_LTTPR_PHY_CAP_SIZE], int r)
457{
458 return phy_cap[r - DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1];
459}
460
461void drm_dp_lttpr_link_train_channel_eq_delay(const struct drm_dp_aux *aux,
462 const u8 phy_cap[DP_LTTPR_PHY_CAP_SIZE])
463{
464 u8 interval = dp_lttpr_phy_cap(phy_cap,
465 DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1) &
466 DP_TRAINING_AUX_RD_MASK;
467
468 __drm_dp_link_train_channel_eq_delay(aux, rd_interval: interval);
469}
470EXPORT_SYMBOL(drm_dp_lttpr_link_train_channel_eq_delay);
471
472/**
473 * drm_dp_lttpr_wake_timeout_setup() - Grant extended time for sink to wake up
474 * @aux: The DP AUX channel to use
475 * @transparent_mode: This is true if lttpr is in transparent mode
476 *
477 * This function checks if the sink needs any extended wake time, if it does
478 * it grants this request. Post this setup the source device can keep trying
479 * the Aux transaction till the granted wake timeout.
480 * If this function is not called all Aux transactions are expected to take
481 * a default of 1ms before they throw an error.
482 */
483void drm_dp_lttpr_wake_timeout_setup(struct drm_dp_aux *aux, bool transparent_mode)
484{
485 u8 val = 1;
486 int ret;
487
488 if (transparent_mode) {
489 static const u8 timeout_mapping[] = {
490 [DP_DPRX_SLEEP_WAKE_TIMEOUT_PERIOD_1_MS] = 1,
491 [DP_DPRX_SLEEP_WAKE_TIMEOUT_PERIOD_20_MS] = 20,
492 [DP_DPRX_SLEEP_WAKE_TIMEOUT_PERIOD_40_MS] = 40,
493 [DP_DPRX_SLEEP_WAKE_TIMEOUT_PERIOD_60_MS] = 60,
494 [DP_DPRX_SLEEP_WAKE_TIMEOUT_PERIOD_80_MS] = 80,
495 [DP_DPRX_SLEEP_WAKE_TIMEOUT_PERIOD_100_MS] = 100,
496 };
497
498 ret = drm_dp_dpcd_readb(aux, DP_EXTENDED_DPRX_SLEEP_WAKE_TIMEOUT_REQUEST, valuep: &val);
499 if (ret != 1) {
500 drm_dbg_kms(aux->drm_dev,
501 "Failed to read Extended sleep wake timeout request\n");
502 return;
503 }
504
505 val = (val < sizeof(timeout_mapping) && timeout_mapping[val]) ?
506 timeout_mapping[val] : 1;
507
508 if (val > 1)
509 drm_dp_dpcd_writeb(aux,
510 DP_EXTENDED_DPRX_SLEEP_WAKE_TIMEOUT_GRANT,
511 DP_DPRX_SLEEP_WAKE_TIMEOUT_PERIOD_GRANTED);
512 } else {
513 ret = drm_dp_dpcd_readb(aux, DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT, valuep: &val);
514 if (ret != 1) {
515 drm_dbg_kms(aux->drm_dev,
516 "Failed to read Extended sleep wake timeout request\n");
517 return;
518 }
519
520 val = (val & DP_EXTENDED_WAKE_TIMEOUT_REQUEST_MASK) ?
521 (val & DP_EXTENDED_WAKE_TIMEOUT_REQUEST_MASK) * 10 : 1;
522
523 if (val > 1)
524 drm_dp_dpcd_writeb(aux, DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT,
525 DP_EXTENDED_WAKE_TIMEOUT_GRANT);
526 }
527}
528EXPORT_SYMBOL(drm_dp_lttpr_wake_timeout_setup);
529
530u8 drm_dp_link_rate_to_bw_code(int link_rate)
531{
532 switch (link_rate) {
533 case 1000000:
534 return DP_LINK_BW_10;
535 case 1350000:
536 return DP_LINK_BW_13_5;
537 case 2000000:
538 return DP_LINK_BW_20;
539 default:
540 /* Spec says link_bw = link_rate / 0.27Gbps */
541 return link_rate / 27000;
542 }
543}
544EXPORT_SYMBOL(drm_dp_link_rate_to_bw_code);
545
546int drm_dp_bw_code_to_link_rate(u8 link_bw)
547{
548 switch (link_bw) {
549 case DP_LINK_BW_10:
550 return 1000000;
551 case DP_LINK_BW_13_5:
552 return 1350000;
553 case DP_LINK_BW_20:
554 return 2000000;
555 default:
556 /* Spec says link_rate = link_bw * 0.27Gbps */
557 return link_bw * 27000;
558 }
559}
560EXPORT_SYMBOL(drm_dp_bw_code_to_link_rate);
561
562#define AUX_RETRY_INTERVAL 500 /* us */
563
564static inline void
565drm_dp_dump_access(const struct drm_dp_aux *aux,
566 u8 request, uint offset, void *buffer, int ret)
567{
568 const char *arrow = request == DP_AUX_NATIVE_READ ? "->" : "<-";
569
570 if (ret > 0)
571 drm_dbg_dp(aux->drm_dev, "%s: 0x%05x AUX %s (ret=%3d) %*ph\n",
572 aux->name, offset, arrow, ret, min(ret, 20), buffer);
573 else
574 drm_dbg_dp(aux->drm_dev, "%s: 0x%05x AUX %s (ret=%3d)\n",
575 aux->name, offset, arrow, ret);
576}
577
578/**
579 * DOC: dp helpers
580 *
581 * The DisplayPort AUX channel is an abstraction to allow generic, driver-
582 * independent access to AUX functionality. Drivers can take advantage of
583 * this by filling in the fields of the drm_dp_aux structure.
584 *
585 * Transactions are described using a hardware-independent drm_dp_aux_msg
586 * structure, which is passed into a driver's .transfer() implementation.
587 * Both native and I2C-over-AUX transactions are supported.
588 */
589
590static int drm_dp_dpcd_access(struct drm_dp_aux *aux, u8 request,
591 unsigned int offset, void *buffer, size_t size)
592{
593 struct drm_dp_aux_msg msg;
594 unsigned int retry, native_reply;
595 int err = 0, ret = 0;
596
597 memset(&msg, 0, sizeof(msg));
598 msg.address = offset;
599 msg.request = request;
600 msg.buffer = buffer;
601 msg.size = size;
602
603 mutex_lock(&aux->hw_mutex);
604
605 /*
606 * If the device attached to the aux bus is powered down then there's
607 * no reason to attempt a transfer. Error out immediately.
608 */
609 if (aux->powered_down) {
610 ret = -EBUSY;
611 goto unlock;
612 }
613
614 /*
615 * The specification doesn't give any recommendation on how often to
616 * retry native transactions. We used to retry 7 times like for
617 * aux i2c transactions but real world devices this wasn't
618 * sufficient, bump to 32 which makes Dell 4k monitors happier.
619 */
620 for (retry = 0; retry < 32; retry++) {
621 if (ret != 0 && ret != -ETIMEDOUT) {
622 usleep_range(AUX_RETRY_INTERVAL,
623 AUX_RETRY_INTERVAL + 100);
624 }
625
626 ret = aux->transfer(aux, &msg);
627 if (ret >= 0) {
628 native_reply = msg.reply & DP_AUX_NATIVE_REPLY_MASK;
629 if (native_reply == DP_AUX_NATIVE_REPLY_ACK) {
630 if (ret == size)
631 goto unlock;
632
633 ret = -EPROTO;
634 } else
635 ret = -EIO;
636 }
637
638 /*
639 * We want the error we return to be the error we received on
640 * the first transaction, since we may get a different error the
641 * next time we retry
642 */
643 if (!err)
644 err = ret;
645 }
646
647 drm_dbg_kms(aux->drm_dev, "%s: Too many retries, giving up. First error: %d\n",
648 aux->name, err);
649 ret = err;
650
651unlock:
652 mutex_unlock(lock: &aux->hw_mutex);
653 return ret;
654}
655
656/**
657 * drm_dp_dpcd_probe() - probe a given DPCD address with a 1-byte read access
658 * @aux: DisplayPort AUX channel (SST)
659 * @offset: address of the register to probe
660 *
661 * Probe the provided DPCD address by reading 1 byte from it. The function can
662 * be used to trigger some side-effect the read access has, like waking up the
663 * sink, without the need for the read-out value.
664 *
665 * Returns 0 if the read access suceeded, or a negative error code on failure.
666 */
667int drm_dp_dpcd_probe(struct drm_dp_aux *aux, unsigned int offset)
668{
669 u8 buffer;
670 int ret;
671
672 ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, offset, buffer: &buffer, size: 1);
673 WARN_ON(ret == 0);
674
675 drm_dp_dump_access(aux, DP_AUX_NATIVE_READ, offset, buffer: &buffer, ret);
676
677 return ret < 0 ? ret : 0;
678}
679EXPORT_SYMBOL(drm_dp_dpcd_probe);
680
681/**
682 * drm_dp_dpcd_set_powered() - Set whether the DP device is powered
683 * @aux: DisplayPort AUX channel; for convenience it's OK to pass NULL here
684 * and the function will be a no-op.
685 * @powered: true if powered; false if not
686 *
687 * If the endpoint device on the DP AUX bus is known to be powered down
688 * then this function can be called to make future transfers fail immediately
689 * instead of needing to time out.
690 *
691 * If this function is never called then a device defaults to being powered.
692 */
693void drm_dp_dpcd_set_powered(struct drm_dp_aux *aux, bool powered)
694{
695 if (!aux)
696 return;
697
698 mutex_lock(&aux->hw_mutex);
699 aux->powered_down = !powered;
700 mutex_unlock(lock: &aux->hw_mutex);
701}
702EXPORT_SYMBOL(drm_dp_dpcd_set_powered);
703
704/**
705 * drm_dp_dpcd_set_probe() - Set whether a probing before DPCD access is done
706 * @aux: DisplayPort AUX channel
707 * @enable: Enable the probing if required
708 */
709void drm_dp_dpcd_set_probe(struct drm_dp_aux *aux, bool enable)
710{
711 WRITE_ONCE(aux->dpcd_probe_disabled, !enable);
712}
713EXPORT_SYMBOL(drm_dp_dpcd_set_probe);
714
715static bool dpcd_access_needs_probe(struct drm_dp_aux *aux)
716{
717 /*
718 * HP ZR24w corrupts the first DPCD access after entering power save
719 * mode. Eg. on a read, the entire buffer will be filled with the same
720 * byte. Do a throw away read to avoid corrupting anything we care
721 * about. Afterwards things will work correctly until the monitor
722 * gets woken up and subsequently re-enters power save mode.
723 *
724 * The user pressing any button on the monitor is enough to wake it
725 * up, so there is no particularly good place to do the workaround.
726 * We just have to do it before any DPCD access and hope that the
727 * monitor doesn't power down exactly after the throw away read.
728 */
729 return !aux->is_remote && !READ_ONCE(aux->dpcd_probe_disabled);
730}
731
732/**
733 * drm_dp_dpcd_read() - read a series of bytes from the DPCD
734 * @aux: DisplayPort AUX channel (SST or MST)
735 * @offset: address of the (first) register to read
736 * @buffer: buffer to store the register values
737 * @size: number of bytes in @buffer
738 *
739 * Returns the number of bytes transferred on success, or a negative error
740 * code on failure. -EIO is returned if the request was NAKed by the sink or
741 * if the retry count was exceeded. If not all bytes were transferred, this
742 * function returns -EPROTO. Errors from the underlying AUX channel transfer
743 * function, with the exception of -EBUSY (which causes the transaction to
744 * be retried), are propagated to the caller.
745 *
746 * In most of the cases you want to use drm_dp_dpcd_read_data() instead.
747 */
748ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset,
749 void *buffer, size_t size)
750{
751 int ret;
752
753 if (dpcd_access_needs_probe(aux)) {
754 ret = drm_dp_dpcd_probe(aux, DP_TRAINING_PATTERN_SET);
755 if (ret < 0)
756 return ret;
757 }
758
759 if (aux->is_remote)
760 ret = drm_dp_mst_dpcd_read(aux, offset, buffer, size);
761 else
762 ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, offset,
763 buffer, size);
764
765 drm_dp_dump_access(aux, DP_AUX_NATIVE_READ, offset, buffer, ret);
766 return ret;
767}
768EXPORT_SYMBOL(drm_dp_dpcd_read);
769
770/**
771 * drm_dp_dpcd_write() - write a series of bytes to the DPCD
772 * @aux: DisplayPort AUX channel (SST or MST)
773 * @offset: address of the (first) register to write
774 * @buffer: buffer containing the values to write
775 * @size: number of bytes in @buffer
776 *
777 * Returns the number of bytes transferred on success, or a negative error
778 * code on failure. -EIO is returned if the request was NAKed by the sink or
779 * if the retry count was exceeded. If not all bytes were transferred, this
780 * function returns -EPROTO. Errors from the underlying AUX channel transfer
781 * function, with the exception of -EBUSY (which causes the transaction to
782 * be retried), are propagated to the caller.
783 *
784 * In most of the cases you want to use drm_dp_dpcd_write_data() instead.
785 */
786ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset,
787 void *buffer, size_t size)
788{
789 int ret;
790
791 if (aux->is_remote)
792 ret = drm_dp_mst_dpcd_write(aux, offset, buffer, size);
793 else
794 ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_WRITE, offset,
795 buffer, size);
796
797 drm_dp_dump_access(aux, DP_AUX_NATIVE_WRITE, offset, buffer, ret);
798 return ret;
799}
800EXPORT_SYMBOL(drm_dp_dpcd_write);
801
802/**
803 * drm_dp_dpcd_read_link_status() - read DPCD link status (bytes 0x202-0x207)
804 * @aux: DisplayPort AUX channel
805 * @status: buffer to store the link status in (must be at least 6 bytes)
806 *
807 * Returns a negative error code on failure or 0 on success.
808 */
809int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
810 u8 status[DP_LINK_STATUS_SIZE])
811{
812 return drm_dp_dpcd_read_data(aux, DP_LANE0_1_STATUS, buffer: status,
813 DP_LINK_STATUS_SIZE);
814}
815EXPORT_SYMBOL(drm_dp_dpcd_read_link_status);
816
817/**
818 * drm_dp_dpcd_read_phy_link_status - get the link status information for a DP PHY
819 * @aux: DisplayPort AUX channel
820 * @dp_phy: the DP PHY to get the link status for
821 * @link_status: buffer to return the status in
822 *
823 * Fetch the AUX DPCD registers for the DPRX or an LTTPR PHY link status. The
824 * layout of the returned @link_status matches the DPCD register layout of the
825 * DPRX PHY link status.
826 *
827 * Returns 0 if the information was read successfully or a negative error code
828 * on failure.
829 */
830int drm_dp_dpcd_read_phy_link_status(struct drm_dp_aux *aux,
831 enum drm_dp_phy dp_phy,
832 u8 link_status[DP_LINK_STATUS_SIZE])
833{
834 int ret;
835
836 if (dp_phy == DP_PHY_DPRX)
837 return drm_dp_dpcd_read_data(aux,
838 DP_LANE0_1_STATUS,
839 buffer: link_status,
840 DP_LINK_STATUS_SIZE);
841
842 ret = drm_dp_dpcd_read_data(aux,
843 DP_LANE0_1_STATUS_PHY_REPEATER(dp_phy),
844 buffer: link_status,
845 DP_LINK_STATUS_SIZE - 1);
846
847 if (ret < 0)
848 return ret;
849
850 /* Convert the LTTPR to the sink PHY link status layout */
851 memmove(&link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS + 1],
852 &link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS],
853 DP_LINK_STATUS_SIZE - (DP_SINK_STATUS - DP_LANE0_1_STATUS) - 1);
854 link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS] = 0;
855
856 return 0;
857}
858EXPORT_SYMBOL(drm_dp_dpcd_read_phy_link_status);
859
860/**
861 * drm_dp_link_power_up() - power up a DisplayPort link
862 * @aux: DisplayPort AUX channel
863 * @revision: DPCD revision supported on the link
864 *
865 * Returns 0 on success or a negative error code on failure.
866 */
867int drm_dp_link_power_up(struct drm_dp_aux *aux, unsigned char revision)
868{
869 u8 value;
870 int err;
871
872 /* DP_SET_POWER register is only available on DPCD v1.1 and later */
873 if (revision < DP_DPCD_REV_11)
874 return 0;
875
876 err = drm_dp_dpcd_readb(aux, DP_SET_POWER, valuep: &value);
877 if (err < 0)
878 return err;
879
880 value &= ~DP_SET_POWER_MASK;
881 value |= DP_SET_POWER_D0;
882
883 err = drm_dp_dpcd_writeb(aux, DP_SET_POWER, value);
884 if (err < 0)
885 return err;
886
887 /*
888 * According to the DP 1.1 specification, a "Sink Device must exit the
889 * power saving state within 1 ms" (Section 2.5.3.1, Table 5-52, "Sink
890 * Control Field" (register 0x600).
891 */
892 usleep_range(min: 1000, max: 2000);
893
894 return 0;
895}
896EXPORT_SYMBOL(drm_dp_link_power_up);
897
898/**
899 * drm_dp_link_power_down() - power down a DisplayPort link
900 * @aux: DisplayPort AUX channel
901 * @revision: DPCD revision supported on the link
902 *
903 * Returns 0 on success or a negative error code on failure.
904 */
905int drm_dp_link_power_down(struct drm_dp_aux *aux, unsigned char revision)
906{
907 u8 value;
908 int err;
909
910 /* DP_SET_POWER register is only available on DPCD v1.1 and later */
911 if (revision < DP_DPCD_REV_11)
912 return 0;
913
914 err = drm_dp_dpcd_readb(aux, DP_SET_POWER, valuep: &value);
915 if (err < 0)
916 return err;
917
918 value &= ~DP_SET_POWER_MASK;
919 value |= DP_SET_POWER_D3;
920
921 err = drm_dp_dpcd_writeb(aux, DP_SET_POWER, value);
922 if (err < 0)
923 return err;
924
925 return 0;
926}
927EXPORT_SYMBOL(drm_dp_link_power_down);
928
929static int read_payload_update_status(struct drm_dp_aux *aux)
930{
931 int ret;
932 u8 status;
933
934 ret = drm_dp_dpcd_read_byte(aux, DP_PAYLOAD_TABLE_UPDATE_STATUS, valuep: &status);
935 if (ret < 0)
936 return ret;
937
938 return status;
939}
940
941/**
942 * drm_dp_dpcd_write_payload() - Write Virtual Channel information to payload table
943 * @aux: DisplayPort AUX channel
944 * @vcpid: Virtual Channel Payload ID
945 * @start_time_slot: Starting time slot
946 * @time_slot_count: Time slot count
947 *
948 * Write the Virtual Channel payload allocation table, checking the payload
949 * update status and retrying as necessary.
950 *
951 * Returns:
952 * 0 on success, negative error otherwise
953 */
954int drm_dp_dpcd_write_payload(struct drm_dp_aux *aux,
955 int vcpid, u8 start_time_slot, u8 time_slot_count)
956{
957 u8 payload_alloc[3], status;
958 int ret;
959 int retries = 0;
960
961 drm_dp_dpcd_write_byte(aux, DP_PAYLOAD_TABLE_UPDATE_STATUS,
962 DP_PAYLOAD_TABLE_UPDATED);
963
964 payload_alloc[0] = vcpid;
965 payload_alloc[1] = start_time_slot;
966 payload_alloc[2] = time_slot_count;
967
968 ret = drm_dp_dpcd_write_data(aux, DP_PAYLOAD_ALLOCATE_SET, buffer: payload_alloc, size: 3);
969 if (ret < 0) {
970 drm_dbg_kms(aux->drm_dev, "failed to write payload allocation %d\n", ret);
971 goto fail;
972 }
973
974retry:
975 ret = drm_dp_dpcd_read_byte(aux, DP_PAYLOAD_TABLE_UPDATE_STATUS, valuep: &status);
976 if (ret < 0) {
977 drm_dbg_kms(aux->drm_dev, "failed to read payload table status %d\n", ret);
978 goto fail;
979 }
980
981 if (!(status & DP_PAYLOAD_TABLE_UPDATED)) {
982 retries++;
983 if (retries < 20) {
984 usleep_range(min: 10000, max: 20000);
985 goto retry;
986 }
987 drm_dbg_kms(aux->drm_dev, "status not set after read payload table status %d\n",
988 status);
989 ret = -EINVAL;
990 goto fail;
991 }
992 ret = 0;
993fail:
994 return ret;
995}
996EXPORT_SYMBOL(drm_dp_dpcd_write_payload);
997
998/**
999 * drm_dp_dpcd_clear_payload() - Clear the entire VC Payload ID table
1000 * @aux: DisplayPort AUX channel
1001 *
1002 * Clear the entire VC Payload ID table.
1003 *
1004 * Returns: 0 on success, negative error code on errors.
1005 */
1006int drm_dp_dpcd_clear_payload(struct drm_dp_aux *aux)
1007{
1008 return drm_dp_dpcd_write_payload(aux, 0, 0, 0x3f);
1009}
1010EXPORT_SYMBOL(drm_dp_dpcd_clear_payload);
1011
1012/**
1013 * drm_dp_dpcd_poll_act_handled() - Poll for ACT handled status
1014 * @aux: DisplayPort AUX channel
1015 * @timeout_ms: Timeout in ms
1016 *
1017 * Try waiting for the sink to finish updating its payload table by polling for
1018 * the ACT handled bit of DP_PAYLOAD_TABLE_UPDATE_STATUS for up to @timeout_ms
1019 * milliseconds, defaulting to 3000 ms if 0.
1020 *
1021 * Returns:
1022 * 0 if the ACT was handled in time, negative error code on failure.
1023 */
1024int drm_dp_dpcd_poll_act_handled(struct drm_dp_aux *aux, int timeout_ms)
1025{
1026 int ret, status;
1027
1028 /* default to 3 seconds, this is arbitrary */
1029 timeout_ms = timeout_ms ?: 3000;
1030
1031 ret = readx_poll_timeout(read_payload_update_status, aux, status,
1032 status & DP_PAYLOAD_ACT_HANDLED || status < 0,
1033 200, timeout_ms * USEC_PER_MSEC);
1034 if (ret < 0 && status >= 0) {
1035 drm_err(aux->drm_dev, "Failed to get ACT after %d ms, last status: %02x\n",
1036 timeout_ms, status);
1037 return -EINVAL;
1038 } else if (status < 0) {
1039 /*
1040 * Failure here isn't unexpected - the hub may have
1041 * just been unplugged
1042 */
1043 drm_dbg_kms(aux->drm_dev, "Failed to read payload table status: %d\n", status);
1044 return status;
1045 }
1046
1047 return 0;
1048}
1049EXPORT_SYMBOL(drm_dp_dpcd_poll_act_handled);
1050
1051static bool is_edid_digital_input_dp(const struct drm_edid *drm_edid)
1052{
1053 /* FIXME: get rid of drm_edid_raw() */
1054 const struct edid *edid = drm_edid_raw(drm_edid);
1055
1056 return edid && edid->revision >= 4 &&
1057 edid->input & DRM_EDID_INPUT_DIGITAL &&
1058 (edid->input & DRM_EDID_DIGITAL_TYPE_MASK) == DRM_EDID_DIGITAL_TYPE_DP;
1059}
1060
1061/**
1062 * drm_dp_downstream_is_type() - is the downstream facing port of certain type?
1063 * @dpcd: DisplayPort configuration data
1064 * @port_cap: port capabilities
1065 * @type: port type to be checked. Can be:
1066 * %DP_DS_PORT_TYPE_DP, %DP_DS_PORT_TYPE_VGA, %DP_DS_PORT_TYPE_DVI,
1067 * %DP_DS_PORT_TYPE_HDMI, %DP_DS_PORT_TYPE_NON_EDID,
1068 * %DP_DS_PORT_TYPE_DP_DUALMODE or %DP_DS_PORT_TYPE_WIRELESS.
1069 *
1070 * Caveat: Only works with DPCD 1.1+ port caps.
1071 *
1072 * Returns: whether the downstream facing port matches the type.
1073 */
1074bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1075 const u8 port_cap[4], u8 type)
1076{
1077 return drm_dp_is_branch(dpcd) &&
1078 dpcd[DP_DPCD_REV] >= 0x11 &&
1079 (port_cap[0] & DP_DS_PORT_TYPE_MASK) == type;
1080}
1081EXPORT_SYMBOL(drm_dp_downstream_is_type);
1082
1083/**
1084 * drm_dp_downstream_is_tmds() - is the downstream facing port TMDS?
1085 * @dpcd: DisplayPort configuration data
1086 * @port_cap: port capabilities
1087 * @drm_edid: EDID
1088 *
1089 * Returns: whether the downstream facing port is TMDS (HDMI/DVI).
1090 */
1091bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1092 const u8 port_cap[4],
1093 const struct drm_edid *drm_edid)
1094{
1095 if (dpcd[DP_DPCD_REV] < 0x11) {
1096 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) {
1097 case DP_DWN_STRM_PORT_TYPE_TMDS:
1098 return true;
1099 default:
1100 return false;
1101 }
1102 }
1103
1104 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
1105 case DP_DS_PORT_TYPE_DP_DUALMODE:
1106 if (is_edid_digital_input_dp(drm_edid))
1107 return false;
1108 fallthrough;
1109 case DP_DS_PORT_TYPE_DVI:
1110 case DP_DS_PORT_TYPE_HDMI:
1111 return true;
1112 default:
1113 return false;
1114 }
1115}
1116EXPORT_SYMBOL(drm_dp_downstream_is_tmds);
1117
1118/**
1119 * drm_dp_send_real_edid_checksum() - send back real edid checksum value
1120 * @aux: DisplayPort AUX channel
1121 * @real_edid_checksum: real edid checksum for the last block
1122 *
1123 * Returns:
1124 * True on success
1125 */
1126bool drm_dp_send_real_edid_checksum(struct drm_dp_aux *aux,
1127 u8 real_edid_checksum)
1128{
1129 u8 link_edid_read = 0, auto_test_req = 0, test_resp = 0;
1130
1131 if (drm_dp_dpcd_read_byte(aux, DP_DEVICE_SERVICE_IRQ_VECTOR,
1132 valuep: &auto_test_req) < 0) {
1133 drm_err(aux->drm_dev, "%s: DPCD failed read at register 0x%x\n",
1134 aux->name, DP_DEVICE_SERVICE_IRQ_VECTOR);
1135 return false;
1136 }
1137 auto_test_req &= DP_AUTOMATED_TEST_REQUEST;
1138
1139 if (drm_dp_dpcd_read_byte(aux, DP_TEST_REQUEST, valuep: &link_edid_read) < 0) {
1140 drm_err(aux->drm_dev, "%s: DPCD failed read at register 0x%x\n",
1141 aux->name, DP_TEST_REQUEST);
1142 return false;
1143 }
1144 link_edid_read &= DP_TEST_LINK_EDID_READ;
1145
1146 if (!auto_test_req || !link_edid_read) {
1147 drm_dbg_kms(aux->drm_dev, "%s: Source DUT does not support TEST_EDID_READ\n",
1148 aux->name);
1149 return false;
1150 }
1151
1152 if (drm_dp_dpcd_write_byte(aux, DP_DEVICE_SERVICE_IRQ_VECTOR,
1153 value: auto_test_req) < 0) {
1154 drm_err(aux->drm_dev, "%s: DPCD failed write at register 0x%x\n",
1155 aux->name, DP_DEVICE_SERVICE_IRQ_VECTOR);
1156 return false;
1157 }
1158
1159 /* send back checksum for the last edid extension block data */
1160 if (drm_dp_dpcd_write_byte(aux, DP_TEST_EDID_CHECKSUM,
1161 value: real_edid_checksum) < 0) {
1162 drm_err(aux->drm_dev, "%s: DPCD failed write at register 0x%x\n",
1163 aux->name, DP_TEST_EDID_CHECKSUM);
1164 return false;
1165 }
1166
1167 test_resp |= DP_TEST_EDID_CHECKSUM_WRITE;
1168 if (drm_dp_dpcd_write_byte(aux, DP_TEST_RESPONSE, value: test_resp) < 0) {
1169 drm_err(aux->drm_dev, "%s: DPCD failed write at register 0x%x\n",
1170 aux->name, DP_TEST_RESPONSE);
1171 return false;
1172 }
1173
1174 return true;
1175}
1176EXPORT_SYMBOL(drm_dp_send_real_edid_checksum);
1177
1178static u8 drm_dp_downstream_port_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1179{
1180 u8 port_count = dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_PORT_COUNT_MASK;
1181
1182 if (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE && port_count > 4)
1183 port_count = 4;
1184
1185 return port_count;
1186}
1187
1188static int drm_dp_read_extended_dpcd_caps(struct drm_dp_aux *aux,
1189 u8 dpcd[DP_RECEIVER_CAP_SIZE])
1190{
1191 u8 dpcd_ext[DP_RECEIVER_CAP_SIZE];
1192 int ret;
1193
1194 /*
1195 * Prior to DP1.3 the bit represented by
1196 * DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT was reserved.
1197 * If it is set DP_DPCD_REV at 0000h could be at a value less than
1198 * the true capability of the panel. The only way to check is to
1199 * then compare 0000h and 2200h.
1200 */
1201 if (!(dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
1202 DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT))
1203 return 0;
1204
1205 ret = drm_dp_dpcd_read_data(aux, DP_DP13_DPCD_REV, buffer: &dpcd_ext,
1206 size: sizeof(dpcd_ext));
1207 if (ret < 0)
1208 return ret;
1209
1210 if (dpcd[DP_DPCD_REV] > dpcd_ext[DP_DPCD_REV]) {
1211 drm_dbg_kms(aux->drm_dev,
1212 "%s: Extended DPCD rev less than base DPCD rev (%d > %d)\n",
1213 aux->name, dpcd[DP_DPCD_REV], dpcd_ext[DP_DPCD_REV]);
1214 return 0;
1215 }
1216
1217 if (!memcmp(p: dpcd, q: dpcd_ext, size: sizeof(dpcd_ext)))
1218 return 0;
1219
1220 drm_dbg_kms(aux->drm_dev, "%s: Base DPCD: %*ph\n", aux->name, DP_RECEIVER_CAP_SIZE, dpcd);
1221
1222 memcpy(dpcd, dpcd_ext, sizeof(dpcd_ext));
1223
1224 return 0;
1225}
1226
1227/**
1228 * drm_dp_read_dpcd_caps() - read DPCD caps and extended DPCD caps if
1229 * available
1230 * @aux: DisplayPort AUX channel
1231 * @dpcd: Buffer to store the resulting DPCD in
1232 *
1233 * Attempts to read the base DPCD caps for @aux. Additionally, this function
1234 * checks for and reads the extended DPRX caps (%DP_DP13_DPCD_REV) if
1235 * present.
1236 *
1237 * Returns: %0 if the DPCD was read successfully, negative error code
1238 * otherwise.
1239 */
1240int drm_dp_read_dpcd_caps(struct drm_dp_aux *aux,
1241 u8 dpcd[DP_RECEIVER_CAP_SIZE])
1242{
1243 int ret;
1244
1245 ret = drm_dp_dpcd_read_data(aux, DP_DPCD_REV, buffer: dpcd, DP_RECEIVER_CAP_SIZE);
1246 if (ret < 0)
1247 return ret;
1248 if (dpcd[DP_DPCD_REV] == 0)
1249 return -EIO;
1250
1251 ret = drm_dp_read_extended_dpcd_caps(aux, dpcd);
1252 if (ret < 0)
1253 return ret;
1254
1255 drm_dbg_kms(aux->drm_dev, "%s: DPCD: %*ph\n", aux->name, DP_RECEIVER_CAP_SIZE, dpcd);
1256
1257 return ret;
1258}
1259EXPORT_SYMBOL(drm_dp_read_dpcd_caps);
1260
1261/**
1262 * drm_dp_read_downstream_info() - read DPCD downstream port info if available
1263 * @aux: DisplayPort AUX channel
1264 * @dpcd: A cached copy of the port's DPCD
1265 * @downstream_ports: buffer to store the downstream port info in
1266 *
1267 * See also:
1268 * drm_dp_downstream_max_clock()
1269 * drm_dp_downstream_max_bpc()
1270 *
1271 * Returns: 0 if either the downstream port info was read successfully or
1272 * there was no downstream info to read, or a negative error code otherwise.
1273 */
1274int drm_dp_read_downstream_info(struct drm_dp_aux *aux,
1275 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1276 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS])
1277{
1278 int ret;
1279 u8 len;
1280
1281 memset(downstream_ports, 0, DP_MAX_DOWNSTREAM_PORTS);
1282
1283 /* No downstream info to read */
1284 if (!drm_dp_is_branch(dpcd) || dpcd[DP_DPCD_REV] == DP_DPCD_REV_10)
1285 return 0;
1286
1287 /* Some branches advertise having 0 downstream ports, despite also advertising they have a
1288 * downstream port present. The DP spec isn't clear on if this is allowed or not, but since
1289 * some branches do it we need to handle it regardless.
1290 */
1291 len = drm_dp_downstream_port_count(dpcd);
1292 if (!len)
1293 return 0;
1294
1295 if (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE)
1296 len *= 4;
1297
1298 ret = drm_dp_dpcd_read_data(aux, DP_DOWNSTREAM_PORT_0, buffer: downstream_ports, size: len);
1299 if (ret < 0)
1300 return ret;
1301
1302 drm_dbg_kms(aux->drm_dev, "%s: DPCD DFP: %*ph\n", aux->name, len, downstream_ports);
1303
1304 return 0;
1305}
1306EXPORT_SYMBOL(drm_dp_read_downstream_info);
1307
1308/**
1309 * drm_dp_downstream_max_dotclock() - extract downstream facing port max dot clock
1310 * @dpcd: DisplayPort configuration data
1311 * @port_cap: port capabilities
1312 *
1313 * Returns: Downstream facing port max dot clock in kHz on success,
1314 * or 0 if max clock not defined
1315 */
1316int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1317 const u8 port_cap[4])
1318{
1319 if (!drm_dp_is_branch(dpcd))
1320 return 0;
1321
1322 if (dpcd[DP_DPCD_REV] < 0x11)
1323 return 0;
1324
1325 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
1326 case DP_DS_PORT_TYPE_VGA:
1327 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
1328 return 0;
1329 return port_cap[1] * 8000;
1330 default:
1331 return 0;
1332 }
1333}
1334EXPORT_SYMBOL(drm_dp_downstream_max_dotclock);
1335
1336/**
1337 * drm_dp_downstream_max_tmds_clock() - extract downstream facing port max TMDS clock
1338 * @dpcd: DisplayPort configuration data
1339 * @port_cap: port capabilities
1340 * @drm_edid: EDID
1341 *
1342 * Returns: HDMI/DVI downstream facing port max TMDS clock in kHz on success,
1343 * or 0 if max TMDS clock not defined
1344 */
1345int drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1346 const u8 port_cap[4],
1347 const struct drm_edid *drm_edid)
1348{
1349 if (!drm_dp_is_branch(dpcd))
1350 return 0;
1351
1352 if (dpcd[DP_DPCD_REV] < 0x11) {
1353 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) {
1354 case DP_DWN_STRM_PORT_TYPE_TMDS:
1355 return 165000;
1356 default:
1357 return 0;
1358 }
1359 }
1360
1361 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
1362 case DP_DS_PORT_TYPE_DP_DUALMODE:
1363 if (is_edid_digital_input_dp(drm_edid))
1364 return 0;
1365 /*
1366 * It's left up to the driver to check the
1367 * DP dual mode adapter's max TMDS clock.
1368 *
1369 * Unfortunately it looks like branch devices
1370 * may not fordward that the DP dual mode i2c
1371 * access so we just usually get i2c nak :(
1372 */
1373 fallthrough;
1374 case DP_DS_PORT_TYPE_HDMI:
1375 /*
1376 * We should perhaps assume 165 MHz when detailed cap
1377 * info is not available. But looks like many typical
1378 * branch devices fall into that category and so we'd
1379 * probably end up with users complaining that they can't
1380 * get high resolution modes with their favorite dongle.
1381 *
1382 * So let's limit to 300 MHz instead since DPCD 1.4
1383 * HDMI 2.0 DFPs are required to have the detailed cap
1384 * info. So it's more likely we're dealing with a HDMI 1.4
1385 * compatible* device here.
1386 */
1387 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
1388 return 300000;
1389 return port_cap[1] * 2500;
1390 case DP_DS_PORT_TYPE_DVI:
1391 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
1392 return 165000;
1393 /* FIXME what to do about DVI dual link? */
1394 return port_cap[1] * 2500;
1395 default:
1396 return 0;
1397 }
1398}
1399EXPORT_SYMBOL(drm_dp_downstream_max_tmds_clock);
1400
1401/**
1402 * drm_dp_downstream_min_tmds_clock() - extract downstream facing port min TMDS clock
1403 * @dpcd: DisplayPort configuration data
1404 * @port_cap: port capabilities
1405 * @drm_edid: EDID
1406 *
1407 * Returns: HDMI/DVI downstream facing port min TMDS clock in kHz on success,
1408 * or 0 if max TMDS clock not defined
1409 */
1410int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1411 const u8 port_cap[4],
1412 const struct drm_edid *drm_edid)
1413{
1414 if (!drm_dp_is_branch(dpcd))
1415 return 0;
1416
1417 if (dpcd[DP_DPCD_REV] < 0x11) {
1418 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) {
1419 case DP_DWN_STRM_PORT_TYPE_TMDS:
1420 return 25000;
1421 default:
1422 return 0;
1423 }
1424 }
1425
1426 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
1427 case DP_DS_PORT_TYPE_DP_DUALMODE:
1428 if (is_edid_digital_input_dp(drm_edid))
1429 return 0;
1430 fallthrough;
1431 case DP_DS_PORT_TYPE_DVI:
1432 case DP_DS_PORT_TYPE_HDMI:
1433 /*
1434 * Unclear whether the protocol converter could
1435 * utilize pixel replication. Assume it won't.
1436 */
1437 return 25000;
1438 default:
1439 return 0;
1440 }
1441}
1442EXPORT_SYMBOL(drm_dp_downstream_min_tmds_clock);
1443
1444/**
1445 * drm_dp_downstream_max_bpc() - extract downstream facing port max
1446 * bits per component
1447 * @dpcd: DisplayPort configuration data
1448 * @port_cap: downstream facing port capabilities
1449 * @drm_edid: EDID
1450 *
1451 * Returns: Max bpc on success or 0 if max bpc not defined
1452 */
1453int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1454 const u8 port_cap[4],
1455 const struct drm_edid *drm_edid)
1456{
1457 if (!drm_dp_is_branch(dpcd))
1458 return 0;
1459
1460 if (dpcd[DP_DPCD_REV] < 0x11) {
1461 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) {
1462 case DP_DWN_STRM_PORT_TYPE_DP:
1463 return 0;
1464 default:
1465 return 8;
1466 }
1467 }
1468
1469 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
1470 case DP_DS_PORT_TYPE_DP:
1471 return 0;
1472 case DP_DS_PORT_TYPE_DP_DUALMODE:
1473 if (is_edid_digital_input_dp(drm_edid))
1474 return 0;
1475 fallthrough;
1476 case DP_DS_PORT_TYPE_HDMI:
1477 case DP_DS_PORT_TYPE_DVI:
1478 case DP_DS_PORT_TYPE_VGA:
1479 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
1480 return 8;
1481
1482 switch (port_cap[2] & DP_DS_MAX_BPC_MASK) {
1483 case DP_DS_8BPC:
1484 return 8;
1485 case DP_DS_10BPC:
1486 return 10;
1487 case DP_DS_12BPC:
1488 return 12;
1489 case DP_DS_16BPC:
1490 return 16;
1491 default:
1492 return 8;
1493 }
1494 break;
1495 default:
1496 return 8;
1497 }
1498}
1499EXPORT_SYMBOL(drm_dp_downstream_max_bpc);
1500
1501/**
1502 * drm_dp_downstream_420_passthrough() - determine downstream facing port
1503 * YCbCr 4:2:0 pass-through capability
1504 * @dpcd: DisplayPort configuration data
1505 * @port_cap: downstream facing port capabilities
1506 *
1507 * Returns: whether the downstream facing port can pass through YCbCr 4:2:0
1508 */
1509bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1510 const u8 port_cap[4])
1511{
1512 if (!drm_dp_is_branch(dpcd))
1513 return false;
1514
1515 if (dpcd[DP_DPCD_REV] < 0x13)
1516 return false;
1517
1518 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
1519 case DP_DS_PORT_TYPE_DP:
1520 return true;
1521 case DP_DS_PORT_TYPE_HDMI:
1522 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
1523 return false;
1524
1525 return port_cap[3] & DP_DS_HDMI_YCBCR420_PASS_THROUGH;
1526 default:
1527 return false;
1528 }
1529}
1530EXPORT_SYMBOL(drm_dp_downstream_420_passthrough);
1531
1532/**
1533 * drm_dp_downstream_444_to_420_conversion() - determine downstream facing port
1534 * YCbCr 4:4:4->4:2:0 conversion capability
1535 * @dpcd: DisplayPort configuration data
1536 * @port_cap: downstream facing port capabilities
1537 *
1538 * Returns: whether the downstream facing port can convert YCbCr 4:4:4 to 4:2:0
1539 */
1540bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1541 const u8 port_cap[4])
1542{
1543 if (!drm_dp_is_branch(dpcd))
1544 return false;
1545
1546 if (dpcd[DP_DPCD_REV] < 0x13)
1547 return false;
1548
1549 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
1550 case DP_DS_PORT_TYPE_HDMI:
1551 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
1552 return false;
1553
1554 return port_cap[3] & DP_DS_HDMI_YCBCR444_TO_420_CONV;
1555 default:
1556 return false;
1557 }
1558}
1559EXPORT_SYMBOL(drm_dp_downstream_444_to_420_conversion);
1560
1561/**
1562 * drm_dp_downstream_rgb_to_ycbcr_conversion() - determine downstream facing port
1563 * RGB->YCbCr conversion capability
1564 * @dpcd: DisplayPort configuration data
1565 * @port_cap: downstream facing port capabilities
1566 * @color_spc: Colorspace for which conversion cap is sought
1567 *
1568 * Returns: whether the downstream facing port can convert RGB->YCbCr for a given
1569 * colorspace.
1570 */
1571bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1572 const u8 port_cap[4],
1573 u8 color_spc)
1574{
1575 if (!drm_dp_is_branch(dpcd))
1576 return false;
1577
1578 if (dpcd[DP_DPCD_REV] < 0x13)
1579 return false;
1580
1581 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
1582 case DP_DS_PORT_TYPE_HDMI:
1583 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
1584 return false;
1585
1586 return port_cap[3] & color_spc;
1587 default:
1588 return false;
1589 }
1590}
1591EXPORT_SYMBOL(drm_dp_downstream_rgb_to_ycbcr_conversion);
1592
1593/**
1594 * drm_dp_downstream_mode() - return a mode for downstream facing port
1595 * @dev: DRM device
1596 * @dpcd: DisplayPort configuration data
1597 * @port_cap: port capabilities
1598 *
1599 * Provides a suitable mode for downstream facing ports without EDID.
1600 *
1601 * Returns: A new drm_display_mode on success or NULL on failure
1602 */
1603struct drm_display_mode *
1604drm_dp_downstream_mode(struct drm_device *dev,
1605 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1606 const u8 port_cap[4])
1607
1608{
1609 u8 vic;
1610
1611 if (!drm_dp_is_branch(dpcd))
1612 return NULL;
1613
1614 if (dpcd[DP_DPCD_REV] < 0x11)
1615 return NULL;
1616
1617 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
1618 case DP_DS_PORT_TYPE_NON_EDID:
1619 switch (port_cap[0] & DP_DS_NON_EDID_MASK) {
1620 case DP_DS_NON_EDID_720x480i_60:
1621 vic = 6;
1622 break;
1623 case DP_DS_NON_EDID_720x480i_50:
1624 vic = 21;
1625 break;
1626 case DP_DS_NON_EDID_1920x1080i_60:
1627 vic = 5;
1628 break;
1629 case DP_DS_NON_EDID_1920x1080i_50:
1630 vic = 20;
1631 break;
1632 case DP_DS_NON_EDID_1280x720_60:
1633 vic = 4;
1634 break;
1635 case DP_DS_NON_EDID_1280x720_50:
1636 vic = 19;
1637 break;
1638 default:
1639 return NULL;
1640 }
1641 return drm_display_mode_from_cea_vic(dev, video_code: vic);
1642 default:
1643 return NULL;
1644 }
1645}
1646EXPORT_SYMBOL(drm_dp_downstream_mode);
1647
1648/**
1649 * drm_dp_downstream_id() - identify branch device
1650 * @aux: DisplayPort AUX channel
1651 * @id: DisplayPort branch device id
1652 *
1653 * Returns branch device id on success or NULL on failure
1654 */
1655int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6])
1656{
1657 return drm_dp_dpcd_read_data(aux, DP_BRANCH_ID, buffer: id, size: 6);
1658}
1659EXPORT_SYMBOL(drm_dp_downstream_id);
1660
1661/**
1662 * drm_dp_downstream_debug() - debug DP branch devices
1663 * @m: pointer for debugfs file
1664 * @dpcd: DisplayPort configuration data
1665 * @port_cap: port capabilities
1666 * @drm_edid: EDID
1667 * @aux: DisplayPort AUX channel
1668 *
1669 */
1670void drm_dp_downstream_debug(struct seq_file *m,
1671 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1672 const u8 port_cap[4],
1673 const struct drm_edid *drm_edid,
1674 struct drm_dp_aux *aux)
1675{
1676 bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
1677 DP_DETAILED_CAP_INFO_AVAILABLE;
1678 int clk;
1679 int bpc;
1680 char id[7];
1681 int len;
1682 uint8_t rev[2];
1683 int type = port_cap[0] & DP_DS_PORT_TYPE_MASK;
1684 bool branch_device = drm_dp_is_branch(dpcd);
1685
1686 seq_printf(m, fmt: "\tDP branch device present: %s\n",
1687 str_yes_no(v: branch_device));
1688
1689 if (!branch_device)
1690 return;
1691
1692 switch (type) {
1693 case DP_DS_PORT_TYPE_DP:
1694 seq_puts(m, s: "\t\tType: DisplayPort\n");
1695 break;
1696 case DP_DS_PORT_TYPE_VGA:
1697 seq_puts(m, s: "\t\tType: VGA\n");
1698 break;
1699 case DP_DS_PORT_TYPE_DVI:
1700 seq_puts(m, s: "\t\tType: DVI\n");
1701 break;
1702 case DP_DS_PORT_TYPE_HDMI:
1703 seq_puts(m, s: "\t\tType: HDMI\n");
1704 break;
1705 case DP_DS_PORT_TYPE_NON_EDID:
1706 seq_puts(m, s: "\t\tType: others without EDID support\n");
1707 break;
1708 case DP_DS_PORT_TYPE_DP_DUALMODE:
1709 seq_puts(m, s: "\t\tType: DP++\n");
1710 break;
1711 case DP_DS_PORT_TYPE_WIRELESS:
1712 seq_puts(m, s: "\t\tType: Wireless\n");
1713 break;
1714 default:
1715 seq_puts(m, s: "\t\tType: N/A\n");
1716 }
1717
1718 memset(id, 0, sizeof(id));
1719 drm_dp_downstream_id(aux, id);
1720 seq_printf(m, fmt: "\t\tID: %s\n", id);
1721
1722 len = drm_dp_dpcd_read_data(aux, DP_BRANCH_HW_REV, buffer: &rev[0], size: 1);
1723 if (!len)
1724 seq_printf(m, fmt: "\t\tHW: %d.%d\n",
1725 (rev[0] & 0xf0) >> 4, rev[0] & 0xf);
1726
1727 len = drm_dp_dpcd_read_data(aux, DP_BRANCH_SW_REV, buffer: rev, size: 2);
1728 if (!len)
1729 seq_printf(m, fmt: "\t\tSW: %d.%d\n", rev[0], rev[1]);
1730
1731 if (detailed_cap_info) {
1732 clk = drm_dp_downstream_max_dotclock(dpcd, port_cap);
1733 if (clk > 0)
1734 seq_printf(m, fmt: "\t\tMax dot clock: %d kHz\n", clk);
1735
1736 clk = drm_dp_downstream_max_tmds_clock(dpcd, port_cap, drm_edid);
1737 if (clk > 0)
1738 seq_printf(m, fmt: "\t\tMax TMDS clock: %d kHz\n", clk);
1739
1740 clk = drm_dp_downstream_min_tmds_clock(dpcd, port_cap, drm_edid);
1741 if (clk > 0)
1742 seq_printf(m, fmt: "\t\tMin TMDS clock: %d kHz\n", clk);
1743
1744 bpc = drm_dp_downstream_max_bpc(dpcd, port_cap, drm_edid);
1745
1746 if (bpc > 0)
1747 seq_printf(m, fmt: "\t\tMax bpc: %d\n", bpc);
1748 }
1749}
1750EXPORT_SYMBOL(drm_dp_downstream_debug);
1751
1752/**
1753 * drm_dp_subconnector_type() - get DP branch device type
1754 * @dpcd: DisplayPort configuration data
1755 * @port_cap: port capabilities
1756 */
1757enum drm_mode_subconnector
1758drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1759 const u8 port_cap[4])
1760{
1761 int type;
1762 if (!drm_dp_is_branch(dpcd))
1763 return DRM_MODE_SUBCONNECTOR_Native;
1764 /* DP 1.0 approach */
1765 if (dpcd[DP_DPCD_REV] == DP_DPCD_REV_10) {
1766 type = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
1767 DP_DWN_STRM_PORT_TYPE_MASK;
1768
1769 switch (type) {
1770 case DP_DWN_STRM_PORT_TYPE_TMDS:
1771 /* Can be HDMI or DVI-D, DVI-D is a safer option */
1772 return DRM_MODE_SUBCONNECTOR_DVID;
1773 case DP_DWN_STRM_PORT_TYPE_ANALOG:
1774 /* Can be VGA or DVI-A, VGA is more popular */
1775 return DRM_MODE_SUBCONNECTOR_VGA;
1776 case DP_DWN_STRM_PORT_TYPE_DP:
1777 return DRM_MODE_SUBCONNECTOR_DisplayPort;
1778 case DP_DWN_STRM_PORT_TYPE_OTHER:
1779 default:
1780 return DRM_MODE_SUBCONNECTOR_Unknown;
1781 }
1782 }
1783 type = port_cap[0] & DP_DS_PORT_TYPE_MASK;
1784
1785 switch (type) {
1786 case DP_DS_PORT_TYPE_DP:
1787 case DP_DS_PORT_TYPE_DP_DUALMODE:
1788 return DRM_MODE_SUBCONNECTOR_DisplayPort;
1789 case DP_DS_PORT_TYPE_VGA:
1790 return DRM_MODE_SUBCONNECTOR_VGA;
1791 case DP_DS_PORT_TYPE_DVI:
1792 return DRM_MODE_SUBCONNECTOR_DVID;
1793 case DP_DS_PORT_TYPE_HDMI:
1794 return DRM_MODE_SUBCONNECTOR_HDMIA;
1795 case DP_DS_PORT_TYPE_WIRELESS:
1796 return DRM_MODE_SUBCONNECTOR_Wireless;
1797 case DP_DS_PORT_TYPE_NON_EDID:
1798 default:
1799 return DRM_MODE_SUBCONNECTOR_Unknown;
1800 }
1801}
1802EXPORT_SYMBOL(drm_dp_subconnector_type);
1803
1804/**
1805 * drm_dp_set_subconnector_property - set subconnector for DP connector
1806 * @connector: connector to set property on
1807 * @status: connector status
1808 * @dpcd: DisplayPort configuration data
1809 * @port_cap: port capabilities
1810 *
1811 * Called by a driver on every detect event.
1812 */
1813void drm_dp_set_subconnector_property(struct drm_connector *connector,
1814 enum drm_connector_status status,
1815 const u8 *dpcd,
1816 const u8 port_cap[4])
1817{
1818 enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
1819
1820 if (status == connector_status_connected)
1821 subconnector = drm_dp_subconnector_type(dpcd, port_cap);
1822 drm_object_property_set_value(obj: &connector->base,
1823 property: connector->dev->mode_config.dp_subconnector_property,
1824 val: subconnector);
1825}
1826EXPORT_SYMBOL(drm_dp_set_subconnector_property);
1827
1828/**
1829 * drm_dp_read_sink_count_cap() - Check whether a given connector has a valid sink
1830 * count
1831 * @connector: The DRM connector to check
1832 * @dpcd: A cached copy of the connector's DPCD RX capabilities
1833 * @desc: A cached copy of the connector's DP descriptor
1834 *
1835 * See also: drm_dp_read_sink_count()
1836 *
1837 * Returns: %True if the (e)DP connector has a valid sink count that should
1838 * be probed, %false otherwise.
1839 */
1840bool drm_dp_read_sink_count_cap(struct drm_connector *connector,
1841 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1842 const struct drm_dp_desc *desc)
1843{
1844 /* Some eDP panels don't set a valid value for the sink count */
1845 return connector->connector_type != DRM_MODE_CONNECTOR_eDP &&
1846 dpcd[DP_DPCD_REV] >= DP_DPCD_REV_11 &&
1847 dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT &&
1848 !drm_dp_has_quirk(desc, quirk: DP_DPCD_QUIRK_NO_SINK_COUNT);
1849}
1850EXPORT_SYMBOL(drm_dp_read_sink_count_cap);
1851
1852/**
1853 * drm_dp_read_sink_count() - Retrieve the sink count for a given sink
1854 * @aux: The DP AUX channel to use
1855 *
1856 * See also: drm_dp_read_sink_count_cap()
1857 *
1858 * Returns: The current sink count reported by @aux, or a negative error code
1859 * otherwise.
1860 */
1861int drm_dp_read_sink_count(struct drm_dp_aux *aux)
1862{
1863 u8 count;
1864 int ret;
1865
1866 ret = drm_dp_dpcd_read_byte(aux, DP_SINK_COUNT, valuep: &count);
1867 if (ret < 0)
1868 return ret;
1869
1870 return DP_GET_SINK_COUNT(count);
1871}
1872EXPORT_SYMBOL(drm_dp_read_sink_count);
1873
1874/*
1875 * I2C-over-AUX implementation
1876 */
1877
1878static u32 drm_dp_i2c_functionality(struct i2c_adapter *adapter)
1879{
1880 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
1881 I2C_FUNC_SMBUS_READ_BLOCK_DATA |
1882 I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
1883 I2C_FUNC_10BIT_ADDR;
1884}
1885
1886static void drm_dp_i2c_msg_write_status_update(struct drm_dp_aux_msg *msg)
1887{
1888 /*
1889 * In case of i2c defer or short i2c ack reply to a write,
1890 * we need to switch to WRITE_STATUS_UPDATE to drain the
1891 * rest of the message
1892 */
1893 if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_I2C_WRITE) {
1894 msg->request &= DP_AUX_I2C_MOT;
1895 msg->request |= DP_AUX_I2C_WRITE_STATUS_UPDATE;
1896 }
1897}
1898
1899#define AUX_PRECHARGE_LEN 10 /* 10 to 16 */
1900#define AUX_SYNC_LEN (16 + 4) /* preamble + AUX_SYNC_END */
1901#define AUX_STOP_LEN 4
1902#define AUX_CMD_LEN 4
1903#define AUX_ADDRESS_LEN 20
1904#define AUX_REPLY_PAD_LEN 4
1905#define AUX_LENGTH_LEN 8
1906
1907/*
1908 * Calculate the duration of the AUX request/reply in usec. Gives the
1909 * "best" case estimate, ie. successful while as short as possible.
1910 */
1911static int drm_dp_aux_req_duration(const struct drm_dp_aux_msg *msg)
1912{
1913 int len = AUX_PRECHARGE_LEN + AUX_SYNC_LEN + AUX_STOP_LEN +
1914 AUX_CMD_LEN + AUX_ADDRESS_LEN + AUX_LENGTH_LEN;
1915
1916 if ((msg->request & DP_AUX_I2C_READ) == 0)
1917 len += msg->size * 8;
1918
1919 return len;
1920}
1921
1922static int drm_dp_aux_reply_duration(const struct drm_dp_aux_msg *msg)
1923{
1924 int len = AUX_PRECHARGE_LEN + AUX_SYNC_LEN + AUX_STOP_LEN +
1925 AUX_CMD_LEN + AUX_REPLY_PAD_LEN;
1926
1927 /*
1928 * For read we expect what was asked. For writes there will
1929 * be 0 or 1 data bytes. Assume 0 for the "best" case.
1930 */
1931 if (msg->request & DP_AUX_I2C_READ)
1932 len += msg->size * 8;
1933
1934 return len;
1935}
1936
1937#define I2C_START_LEN 1
1938#define I2C_STOP_LEN 1
1939#define I2C_ADDR_LEN 9 /* ADDRESS + R/W + ACK/NACK */
1940#define I2C_DATA_LEN 9 /* DATA + ACK/NACK */
1941
1942/*
1943 * Calculate the length of the i2c transfer in usec, assuming
1944 * the i2c bus speed is as specified. Gives the "worst"
1945 * case estimate, ie. successful while as long as possible.
1946 * Doesn't account the "MOT" bit, and instead assumes each
1947 * message includes a START, ADDRESS and STOP. Neither does it
1948 * account for additional random variables such as clock stretching.
1949 */
1950static int drm_dp_i2c_msg_duration(const struct drm_dp_aux_msg *msg,
1951 int i2c_speed_khz)
1952{
1953 /* AUX bitrate is 1MHz, i2c bitrate as specified */
1954 return DIV_ROUND_UP((I2C_START_LEN + I2C_ADDR_LEN +
1955 msg->size * I2C_DATA_LEN +
1956 I2C_STOP_LEN) * 1000, i2c_speed_khz);
1957}
1958
1959/*
1960 * Determine how many retries should be attempted to successfully transfer
1961 * the specified message, based on the estimated durations of the
1962 * i2c and AUX transfers.
1963 */
1964static int drm_dp_i2c_retry_count(const struct drm_dp_aux_msg *msg,
1965 int i2c_speed_khz)
1966{
1967 int aux_time_us = drm_dp_aux_req_duration(msg) +
1968 drm_dp_aux_reply_duration(msg);
1969 int i2c_time_us = drm_dp_i2c_msg_duration(msg, i2c_speed_khz);
1970
1971 return DIV_ROUND_UP(i2c_time_us, aux_time_us + AUX_RETRY_INTERVAL);
1972}
1973
1974/*
1975 * FIXME currently assumes 10 kHz as some real world devices seem
1976 * to require it. We should query/set the speed via DPCD if supported.
1977 */
1978static int dp_aux_i2c_speed_khz __read_mostly = 10;
1979module_param_unsafe(dp_aux_i2c_speed_khz, int, 0644);
1980MODULE_PARM_DESC(dp_aux_i2c_speed_khz,
1981 "Assumed speed of the i2c bus in kHz, (1-400, default 10)");
1982
1983/*
1984 * Transfer a single I2C-over-AUX message and handle various error conditions,
1985 * retrying the transaction as appropriate. It is assumed that the
1986 * &drm_dp_aux.transfer function does not modify anything in the msg other than the
1987 * reply field.
1988 *
1989 * Returns bytes transferred on success, or a negative error code on failure.
1990 */
1991static int drm_dp_i2c_do_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1992{
1993 unsigned int retry, defer_i2c;
1994 int ret;
1995 /*
1996 * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device
1997 * is required to retry at least seven times upon receiving AUX_DEFER
1998 * before giving up the AUX transaction.
1999 *
2000 * We also try to account for the i2c bus speed.
2001 */
2002 int max_retries = max(7, drm_dp_i2c_retry_count(msg, dp_aux_i2c_speed_khz));
2003
2004 for (retry = 0, defer_i2c = 0; retry < (max_retries + defer_i2c); retry++) {
2005 ret = aux->transfer(aux, msg);
2006 if (ret < 0) {
2007 if (ret == -EBUSY)
2008 continue;
2009
2010 /*
2011 * While timeouts can be errors, they're usually normal
2012 * behavior (for instance, when a driver tries to
2013 * communicate with a non-existent DisplayPort device).
2014 * Avoid spamming the kernel log with timeout errors.
2015 */
2016 if (ret == -ETIMEDOUT)
2017 drm_dbg_kms_ratelimited(aux->drm_dev, "%s: transaction timed out\n",
2018 aux->name);
2019 else
2020 drm_dbg_kms(aux->drm_dev, "%s: transaction failed: %d\n",
2021 aux->name, ret);
2022 return ret;
2023 }
2024
2025
2026 switch (msg->reply & DP_AUX_NATIVE_REPLY_MASK) {
2027 case DP_AUX_NATIVE_REPLY_ACK:
2028 /*
2029 * For I2C-over-AUX transactions this isn't enough, we
2030 * need to check for the I2C ACK reply.
2031 */
2032 break;
2033
2034 case DP_AUX_NATIVE_REPLY_NACK:
2035 drm_dbg_kms(aux->drm_dev, "%s: native nack (result=%d, size=%zu)\n",
2036 aux->name, ret, msg->size);
2037 return -EREMOTEIO;
2038
2039 case DP_AUX_NATIVE_REPLY_DEFER:
2040 drm_dbg_kms(aux->drm_dev, "%s: native defer\n", aux->name);
2041 /*
2042 * We could check for I2C bit rate capabilities and if
2043 * available adjust this interval. We could also be
2044 * more careful with DP-to-legacy adapters where a
2045 * long legacy cable may force very low I2C bit rates.
2046 *
2047 * For now just defer for long enough to hopefully be
2048 * safe for all use-cases.
2049 */
2050 usleep_range(AUX_RETRY_INTERVAL, AUX_RETRY_INTERVAL + 100);
2051 continue;
2052
2053 default:
2054 drm_err(aux->drm_dev, "%s: invalid native reply %#04x\n",
2055 aux->name, msg->reply);
2056 return -EREMOTEIO;
2057 }
2058
2059 switch (msg->reply & DP_AUX_I2C_REPLY_MASK) {
2060 case DP_AUX_I2C_REPLY_ACK:
2061 /*
2062 * Both native ACK and I2C ACK replies received. We
2063 * can assume the transfer was successful.
2064 */
2065 if (ret != msg->size)
2066 drm_dp_i2c_msg_write_status_update(msg);
2067 return ret;
2068
2069 case DP_AUX_I2C_REPLY_NACK:
2070 drm_dbg_kms(aux->drm_dev, "%s: I2C nack (result=%d, size=%zu)\n",
2071 aux->name, ret, msg->size);
2072 aux->i2c_nack_count++;
2073 return -EREMOTEIO;
2074
2075 case DP_AUX_I2C_REPLY_DEFER:
2076 drm_dbg_kms(aux->drm_dev, "%s: I2C defer\n", aux->name);
2077 /* DP Compliance Test 4.2.2.5 Requirement:
2078 * Must have at least 7 retries for I2C defers on the
2079 * transaction to pass this test
2080 */
2081 aux->i2c_defer_count++;
2082 if (defer_i2c < 7)
2083 defer_i2c++;
2084 usleep_range(AUX_RETRY_INTERVAL, AUX_RETRY_INTERVAL + 100);
2085 drm_dp_i2c_msg_write_status_update(msg);
2086
2087 continue;
2088
2089 default:
2090 drm_err(aux->drm_dev, "%s: invalid I2C reply %#04x\n",
2091 aux->name, msg->reply);
2092 return -EREMOTEIO;
2093 }
2094 }
2095
2096 drm_dbg_kms(aux->drm_dev, "%s: Too many retries, giving up\n", aux->name);
2097 return -EREMOTEIO;
2098}
2099
2100static void drm_dp_i2c_msg_set_request(struct drm_dp_aux_msg *msg,
2101 const struct i2c_msg *i2c_msg)
2102{
2103 msg->request = (i2c_msg->flags & I2C_M_RD) ?
2104 DP_AUX_I2C_READ : DP_AUX_I2C_WRITE;
2105 if (!(i2c_msg->flags & I2C_M_STOP))
2106 msg->request |= DP_AUX_I2C_MOT;
2107}
2108
2109/*
2110 * Keep retrying drm_dp_i2c_do_msg until all data has been transferred.
2111 *
2112 * Returns an error code on failure, or a recommended transfer size on success.
2113 */
2114static int drm_dp_i2c_drain_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *orig_msg)
2115{
2116 int err, ret = orig_msg->size;
2117 struct drm_dp_aux_msg msg = *orig_msg;
2118
2119 while (msg.size > 0) {
2120 err = drm_dp_i2c_do_msg(aux, msg: &msg);
2121 if (err <= 0)
2122 return err == 0 ? -EPROTO : err;
2123
2124 if (err < msg.size && err < ret) {
2125 drm_dbg_kms(aux->drm_dev,
2126 "%s: Partial I2C reply: requested %zu bytes got %d bytes\n",
2127 aux->name, msg.size, err);
2128 ret = err;
2129 }
2130
2131 msg.size -= err;
2132 msg.buffer += err;
2133 }
2134
2135 return ret;
2136}
2137
2138/*
2139 * Bizlink designed DP->DVI-D Dual Link adapters require the I2C over AUX
2140 * packets to be as large as possible. If not, the I2C transactions never
2141 * succeed. Hence the default is maximum.
2142 */
2143static int dp_aux_i2c_transfer_size __read_mostly = DP_AUX_MAX_PAYLOAD_BYTES;
2144module_param_unsafe(dp_aux_i2c_transfer_size, int, 0644);
2145MODULE_PARM_DESC(dp_aux_i2c_transfer_size,
2146 "Number of bytes to transfer in a single I2C over DP AUX CH message, (1-16, default 16)");
2147
2148static int drm_dp_i2c_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs,
2149 int num)
2150{
2151 struct drm_dp_aux *aux = adapter->algo_data;
2152 unsigned int i, j;
2153 unsigned transfer_size;
2154 struct drm_dp_aux_msg msg;
2155 int err = 0;
2156
2157 if (aux->powered_down)
2158 return -EBUSY;
2159
2160 dp_aux_i2c_transfer_size = clamp(dp_aux_i2c_transfer_size, 1, DP_AUX_MAX_PAYLOAD_BYTES);
2161
2162 memset(&msg, 0, sizeof(msg));
2163
2164 for (i = 0; i < num; i++) {
2165 msg.address = msgs[i].addr;
2166
2167 if (!aux->no_zero_sized) {
2168 drm_dp_i2c_msg_set_request(msg: &msg, i2c_msg: &msgs[i]);
2169 /* Send a bare address packet to start the transaction.
2170 * Zero sized messages specify an address only (bare
2171 * address) transaction.
2172 */
2173 msg.buffer = NULL;
2174 msg.size = 0;
2175 err = drm_dp_i2c_do_msg(aux, msg: &msg);
2176 }
2177
2178 /*
2179 * Reset msg.request in case in case it got
2180 * changed into a WRITE_STATUS_UPDATE.
2181 */
2182 drm_dp_i2c_msg_set_request(msg: &msg, i2c_msg: &msgs[i]);
2183
2184 if (err < 0)
2185 break;
2186 /* We want each transaction to be as large as possible, but
2187 * we'll go to smaller sizes if the hardware gives us a
2188 * short reply.
2189 */
2190 transfer_size = dp_aux_i2c_transfer_size;
2191 for (j = 0; j < msgs[i].len; j += msg.size) {
2192 msg.buffer = msgs[i].buf + j;
2193 msg.size = min(transfer_size, msgs[i].len - j);
2194
2195 if (j + msg.size == msgs[i].len && aux->no_zero_sized)
2196 msg.request &= ~DP_AUX_I2C_MOT;
2197 err = drm_dp_i2c_drain_msg(aux, orig_msg: &msg);
2198
2199 /*
2200 * Reset msg.request in case in case it got
2201 * changed into a WRITE_STATUS_UPDATE.
2202 */
2203 drm_dp_i2c_msg_set_request(msg: &msg, i2c_msg: &msgs[i]);
2204
2205 if (err < 0)
2206 break;
2207 transfer_size = err;
2208 }
2209 if (err < 0)
2210 break;
2211 }
2212 if (err >= 0)
2213 err = num;
2214
2215 if (!aux->no_zero_sized) {
2216 /* Send a bare address packet to close out the transaction.
2217 * Zero sized messages specify an address only (bare
2218 * address) transaction.
2219 */
2220 msg.request &= ~DP_AUX_I2C_MOT;
2221 msg.buffer = NULL;
2222 msg.size = 0;
2223 (void)drm_dp_i2c_do_msg(aux, msg: &msg);
2224 }
2225 return err;
2226}
2227
2228static const struct i2c_algorithm drm_dp_i2c_algo = {
2229 .functionality = drm_dp_i2c_functionality,
2230 .master_xfer = drm_dp_i2c_xfer,
2231};
2232
2233static struct drm_dp_aux *i2c_to_aux(struct i2c_adapter *i2c)
2234{
2235 return container_of(i2c, struct drm_dp_aux, ddc);
2236}
2237
2238static void lock_bus(struct i2c_adapter *i2c, unsigned int flags)
2239{
2240 mutex_lock(&i2c_to_aux(i2c)->hw_mutex);
2241}
2242
2243static int trylock_bus(struct i2c_adapter *i2c, unsigned int flags)
2244{
2245 return mutex_trylock(&i2c_to_aux(i2c)->hw_mutex);
2246}
2247
2248static void unlock_bus(struct i2c_adapter *i2c, unsigned int flags)
2249{
2250 mutex_unlock(lock: &i2c_to_aux(i2c)->hw_mutex);
2251}
2252
2253static const struct i2c_lock_operations drm_dp_i2c_lock_ops = {
2254 .lock_bus = lock_bus,
2255 .trylock_bus = trylock_bus,
2256 .unlock_bus = unlock_bus,
2257};
2258
2259static int drm_dp_aux_get_crc(struct drm_dp_aux *aux, u8 *crc)
2260{
2261 u8 buf, count;
2262 int ret;
2263
2264 ret = drm_dp_dpcd_read_byte(aux, DP_TEST_SINK, valuep: &buf);
2265 if (ret < 0)
2266 return ret;
2267
2268 WARN_ON(!(buf & DP_TEST_SINK_START));
2269
2270 ret = drm_dp_dpcd_read_byte(aux, DP_TEST_SINK_MISC, valuep: &buf);
2271 if (ret < 0)
2272 return ret;
2273
2274 count = buf & DP_TEST_COUNT_MASK;
2275 if (count == aux->crc_count)
2276 return -EAGAIN; /* No CRC yet */
2277
2278 aux->crc_count = count;
2279
2280 /*
2281 * At DP_TEST_CRC_R_CR, there's 6 bytes containing CRC data, 2 bytes
2282 * per component (RGB or CrYCb).
2283 */
2284 return drm_dp_dpcd_read_data(aux, DP_TEST_CRC_R_CR, buffer: crc, size: 6);
2285}
2286
2287static void drm_dp_aux_crc_work(struct work_struct *work)
2288{
2289 struct drm_dp_aux *aux = container_of(work, struct drm_dp_aux,
2290 crc_work);
2291 struct drm_crtc *crtc;
2292 u8 crc_bytes[6];
2293 uint32_t crcs[3];
2294 int ret;
2295
2296 if (WARN_ON(!aux->crtc))
2297 return;
2298
2299 crtc = aux->crtc;
2300 while (crtc->crc.opened) {
2301 drm_crtc_wait_one_vblank(crtc);
2302 if (!crtc->crc.opened)
2303 break;
2304
2305 ret = drm_dp_aux_get_crc(aux, crc: crc_bytes);
2306 if (ret == -EAGAIN) {
2307 usleep_range(min: 1000, max: 2000);
2308 ret = drm_dp_aux_get_crc(aux, crc: crc_bytes);
2309 }
2310
2311 if (ret == -EAGAIN) {
2312 drm_dbg_kms(aux->drm_dev, "%s: Get CRC failed after retrying: %d\n",
2313 aux->name, ret);
2314 continue;
2315 } else if (ret) {
2316 drm_dbg_kms(aux->drm_dev, "%s: Failed to get a CRC: %d\n", aux->name, ret);
2317 continue;
2318 }
2319
2320 crcs[0] = crc_bytes[0] | crc_bytes[1] << 8;
2321 crcs[1] = crc_bytes[2] | crc_bytes[3] << 8;
2322 crcs[2] = crc_bytes[4] | crc_bytes[5] << 8;
2323 drm_crtc_add_crc_entry(crtc, has_frame: false, frame: 0, crcs);
2324 }
2325}
2326
2327/**
2328 * drm_dp_remote_aux_init() - minimally initialise a remote aux channel
2329 * @aux: DisplayPort AUX channel
2330 *
2331 * Used for remote aux channel in general. Merely initialize the crc work
2332 * struct.
2333 */
2334void drm_dp_remote_aux_init(struct drm_dp_aux *aux)
2335{
2336 INIT_WORK(&aux->crc_work, drm_dp_aux_crc_work);
2337}
2338EXPORT_SYMBOL(drm_dp_remote_aux_init);
2339
2340/**
2341 * drm_dp_aux_init() - minimally initialise an aux channel
2342 * @aux: DisplayPort AUX channel
2343 *
2344 * If you need to use the drm_dp_aux's i2c adapter prior to registering it with
2345 * the outside world, call drm_dp_aux_init() first. For drivers which are
2346 * grandparents to their AUX adapters (e.g. the AUX adapter is parented by a
2347 * &drm_connector), you must still call drm_dp_aux_register() once the connector
2348 * has been registered to allow userspace access to the auxiliary DP channel.
2349 * Likewise, for such drivers you should also assign &drm_dp_aux.drm_dev as
2350 * early as possible so that the &drm_device that corresponds to the AUX adapter
2351 * may be mentioned in debugging output from the DRM DP helpers.
2352 *
2353 * For devices which use a separate platform device for their AUX adapters, this
2354 * may be called as early as required by the driver.
2355 *
2356 */
2357void drm_dp_aux_init(struct drm_dp_aux *aux)
2358{
2359 mutex_init(&aux->hw_mutex);
2360 mutex_init(&aux->cec.lock);
2361 INIT_WORK(&aux->crc_work, drm_dp_aux_crc_work);
2362
2363 aux->ddc.algo = &drm_dp_i2c_algo;
2364 aux->ddc.algo_data = aux;
2365 aux->ddc.retries = 3;
2366
2367 aux->ddc.lock_ops = &drm_dp_i2c_lock_ops;
2368}
2369EXPORT_SYMBOL(drm_dp_aux_init);
2370
2371/**
2372 * drm_dp_aux_register() - initialise and register aux channel
2373 * @aux: DisplayPort AUX channel
2374 *
2375 * Automatically calls drm_dp_aux_init() if this hasn't been done yet. This
2376 * should only be called once the parent of @aux, &drm_dp_aux.dev, is
2377 * initialized. For devices which are grandparents of their AUX channels,
2378 * &drm_dp_aux.dev will typically be the &drm_connector &device which
2379 * corresponds to @aux. For these devices, it's advised to call
2380 * drm_dp_aux_register() in &drm_connector_funcs.late_register, and likewise to
2381 * call drm_dp_aux_unregister() in &drm_connector_funcs.early_unregister.
2382 * Functions which don't follow this will likely Oops when
2383 * %CONFIG_DRM_DISPLAY_DP_AUX_CHARDEV is enabled.
2384 *
2385 * For devices where the AUX channel is a device that exists independently of
2386 * the &drm_device that uses it, such as SoCs and bridge devices, it is
2387 * recommended to call drm_dp_aux_register() after a &drm_device has been
2388 * assigned to &drm_dp_aux.drm_dev, and likewise to call
2389 * drm_dp_aux_unregister() once the &drm_device should no longer be associated
2390 * with the AUX channel (e.g. on bridge detach).
2391 *
2392 * Drivers which need to use the aux channel before either of the two points
2393 * mentioned above need to call drm_dp_aux_init() in order to use the AUX
2394 * channel before registration.
2395 *
2396 * Returns 0 on success or a negative error code on failure.
2397 */
2398int drm_dp_aux_register(struct drm_dp_aux *aux)
2399{
2400 int ret;
2401
2402 WARN_ON_ONCE(!aux->drm_dev);
2403
2404 if (!aux->ddc.algo)
2405 drm_dp_aux_init(aux);
2406
2407 aux->ddc.owner = THIS_MODULE;
2408 aux->ddc.dev.parent = aux->dev;
2409
2410 strscpy(aux->ddc.name, aux->name ? aux->name : dev_name(aux->dev),
2411 sizeof(aux->ddc.name));
2412
2413 ret = drm_dp_aux_register_devnode(aux);
2414 if (ret)
2415 return ret;
2416
2417 ret = i2c_add_adapter(adap: &aux->ddc);
2418 if (ret) {
2419 drm_dp_aux_unregister_devnode(aux);
2420 return ret;
2421 }
2422
2423 return 0;
2424}
2425EXPORT_SYMBOL(drm_dp_aux_register);
2426
2427/**
2428 * drm_dp_aux_unregister() - unregister an AUX adapter
2429 * @aux: DisplayPort AUX channel
2430 */
2431void drm_dp_aux_unregister(struct drm_dp_aux *aux)
2432{
2433 drm_dp_aux_unregister_devnode(aux);
2434 i2c_del_adapter(adap: &aux->ddc);
2435}
2436EXPORT_SYMBOL(drm_dp_aux_unregister);
2437
2438#define PSR_SETUP_TIME(x) [DP_PSR_SETUP_TIME_ ## x >> DP_PSR_SETUP_TIME_SHIFT] = (x)
2439
2440/**
2441 * drm_dp_psr_setup_time() - PSR setup in time usec
2442 * @psr_cap: PSR capabilities from DPCD
2443 *
2444 * Returns:
2445 * PSR setup time for the panel in microseconds, negative
2446 * error code on failure.
2447 */
2448int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE])
2449{
2450 static const u16 psr_setup_time_us[] = {
2451 PSR_SETUP_TIME(330),
2452 PSR_SETUP_TIME(275),
2453 PSR_SETUP_TIME(220),
2454 PSR_SETUP_TIME(165),
2455 PSR_SETUP_TIME(110),
2456 PSR_SETUP_TIME(55),
2457 PSR_SETUP_TIME(0),
2458 };
2459 int i;
2460
2461 i = (psr_cap[1] & DP_PSR_SETUP_TIME_MASK) >> DP_PSR_SETUP_TIME_SHIFT;
2462 if (i >= ARRAY_SIZE(psr_setup_time_us))
2463 return -EINVAL;
2464
2465 return psr_setup_time_us[i];
2466}
2467EXPORT_SYMBOL(drm_dp_psr_setup_time);
2468
2469#undef PSR_SETUP_TIME
2470
2471/**
2472 * drm_dp_start_crc() - start capture of frame CRCs
2473 * @aux: DisplayPort AUX channel
2474 * @crtc: CRTC displaying the frames whose CRCs are to be captured
2475 *
2476 * Returns 0 on success or a negative error code on failure.
2477 */
2478int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc)
2479{
2480 u8 buf;
2481 int ret;
2482
2483 ret = drm_dp_dpcd_read_byte(aux, DP_TEST_SINK, valuep: &buf);
2484 if (ret < 0)
2485 return ret;
2486
2487 ret = drm_dp_dpcd_write_byte(aux, DP_TEST_SINK, value: buf | DP_TEST_SINK_START);
2488 if (ret < 0)
2489 return ret;
2490
2491 aux->crc_count = 0;
2492 aux->crtc = crtc;
2493 schedule_work(work: &aux->crc_work);
2494
2495 return 0;
2496}
2497EXPORT_SYMBOL(drm_dp_start_crc);
2498
2499/**
2500 * drm_dp_stop_crc() - stop capture of frame CRCs
2501 * @aux: DisplayPort AUX channel
2502 *
2503 * Returns 0 on success or a negative error code on failure.
2504 */
2505int drm_dp_stop_crc(struct drm_dp_aux *aux)
2506{
2507 u8 buf;
2508 int ret;
2509
2510 ret = drm_dp_dpcd_read_byte(aux, DP_TEST_SINK, valuep: &buf);
2511 if (ret < 0)
2512 return ret;
2513
2514 ret = drm_dp_dpcd_write_byte(aux, DP_TEST_SINK, value: buf & ~DP_TEST_SINK_START);
2515 if (ret < 0)
2516 return ret;
2517
2518 flush_work(work: &aux->crc_work);
2519 aux->crtc = NULL;
2520
2521 return 0;
2522}
2523EXPORT_SYMBOL(drm_dp_stop_crc);
2524
2525struct dpcd_quirk {
2526 u8 oui[3];
2527 u8 device_id[6];
2528 bool is_branch;
2529 u32 quirks;
2530};
2531
2532#define OUI(first, second, third) { (first), (second), (third) }
2533#define DEVICE_ID(first, second, third, fourth, fifth, sixth) \
2534 { (first), (second), (third), (fourth), (fifth), (sixth) }
2535
2536#define DEVICE_ID_ANY DEVICE_ID(0, 0, 0, 0, 0, 0)
2537
2538static const struct dpcd_quirk dpcd_quirk_list[] = {
2539 /* Analogix 7737 needs reduced M and N at HBR2 link rates */
2540 { OUI(0x00, 0x22, 0xb9), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_CONSTANT_N) },
2541 /* LG LP140WF6-SPM1 eDP panel */
2542 { OUI(0x00, 0x22, 0xb9), DEVICE_ID('s', 'i', 'v', 'a', 'r', 'T'), false, BIT(DP_DPCD_QUIRK_CONSTANT_N) },
2543 /* Apple panels need some additional handling to support PSR */
2544 { OUI(0x00, 0x10, 0xfa), DEVICE_ID_ANY, false, BIT(DP_DPCD_QUIRK_NO_PSR) },
2545 /* CH7511 seems to leave SINK_COUNT zeroed */
2546 { OUI(0x00, 0x00, 0x00), DEVICE_ID('C', 'H', '7', '5', '1', '1'), false, BIT(DP_DPCD_QUIRK_NO_SINK_COUNT) },
2547 /* Synaptics DP1.4 MST hubs can support DSC without virtual DPCD */
2548 { OUI(0x90, 0xCC, 0x24), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD) },
2549 /* Synaptics DP1.4 MST hubs require DSC for some modes on which it applies HBLANK expansion. */
2550 { OUI(0x90, 0xCC, 0x24), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC) },
2551 /* MediaTek panels (at least in U3224KBA) require DSC for modes with a short HBLANK on UHBR links. */
2552 { OUI(0x00, 0x0C, 0xE7), DEVICE_ID_ANY, false, BIT(DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC) },
2553 /* Apple MacBookPro 2017 15 inch eDP Retina panel reports too low DP_MAX_LINK_RATE */
2554 { OUI(0x00, 0x10, 0xfa), DEVICE_ID(101, 68, 21, 101, 98, 97), false, BIT(DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS) },
2555 /* Synaptics Panamera supports only a compressed bpp of 12 above 50% of its max DSC pixel throughput */
2556 { OUI(0x90, 0xCC, 0x24), DEVICE_ID('S', 'Y', 'N', 'A', 0x53, 0x22), true, BIT(DP_DPCD_QUIRK_DSC_THROUGHPUT_BPP_LIMIT) },
2557 { OUI(0x90, 0xCC, 0x24), DEVICE_ID('S', 'Y', 'N', 'A', 0x53, 0x31), true, BIT(DP_DPCD_QUIRK_DSC_THROUGHPUT_BPP_LIMIT) },
2558 { OUI(0x90, 0xCC, 0x24), DEVICE_ID('S', 'Y', 'N', 'A', 0x53, 0x33), true, BIT(DP_DPCD_QUIRK_DSC_THROUGHPUT_BPP_LIMIT) },
2559};
2560
2561#undef OUI
2562
2563/*
2564 * Get a bit mask of DPCD quirks for the sink/branch device identified by
2565 * ident. The quirk data is shared but it's up to the drivers to act on the
2566 * data.
2567 *
2568 * For now, only the OUI (first three bytes) is used, but this may be extended
2569 * to device identification string and hardware/firmware revisions later.
2570 */
2571static u32
2572drm_dp_get_quirks(const struct drm_dp_dpcd_ident *ident, bool is_branch)
2573{
2574 const struct dpcd_quirk *quirk;
2575 u32 quirks = 0;
2576 int i;
2577 u8 any_device[] = DEVICE_ID_ANY;
2578
2579 for (i = 0; i < ARRAY_SIZE(dpcd_quirk_list); i++) {
2580 quirk = &dpcd_quirk_list[i];
2581
2582 if (quirk->is_branch != is_branch)
2583 continue;
2584
2585 if (memcmp(p: quirk->oui, q: ident->oui, size: sizeof(ident->oui)) != 0)
2586 continue;
2587
2588 if (memcmp(p: quirk->device_id, q: any_device, size: sizeof(any_device)) != 0 &&
2589 memcmp(p: quirk->device_id, q: ident->device_id, size: sizeof(ident->device_id)) != 0)
2590 continue;
2591
2592 quirks |= quirk->quirks;
2593 }
2594
2595 return quirks;
2596}
2597
2598#undef DEVICE_ID_ANY
2599#undef DEVICE_ID
2600
2601static int drm_dp_read_ident(struct drm_dp_aux *aux, unsigned int offset,
2602 struct drm_dp_dpcd_ident *ident)
2603{
2604 return drm_dp_dpcd_read_data(aux, offset, buffer: ident, size: sizeof(*ident));
2605}
2606
2607static void drm_dp_dump_desc(struct drm_dp_aux *aux,
2608 const char *device_name, const struct drm_dp_desc *desc)
2609{
2610 const struct drm_dp_dpcd_ident *ident = &desc->ident;
2611
2612 drm_dbg_kms(aux->drm_dev,
2613 "%s: %s: OUI %*phD dev-ID %*pE HW-rev %d.%d SW-rev %d.%d quirks 0x%04x\n",
2614 aux->name, device_name,
2615 (int)sizeof(ident->oui), ident->oui,
2616 (int)strnlen(ident->device_id, sizeof(ident->device_id)), ident->device_id,
2617 ident->hw_rev >> 4, ident->hw_rev & 0xf,
2618 ident->sw_major_rev, ident->sw_minor_rev,
2619 desc->quirks);
2620}
2621
2622/**
2623 * drm_dp_read_desc - read sink/branch descriptor from DPCD
2624 * @aux: DisplayPort AUX channel
2625 * @desc: Device descriptor to fill from DPCD
2626 * @is_branch: true for branch devices, false for sink devices
2627 *
2628 * Read DPCD 0x400 (sink) or 0x500 (branch) into @desc. Also debug log the
2629 * identification.
2630 *
2631 * Returns 0 on success or a negative error code on failure.
2632 */
2633int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc,
2634 bool is_branch)
2635{
2636 struct drm_dp_dpcd_ident *ident = &desc->ident;
2637 unsigned int offset = is_branch ? DP_BRANCH_OUI : DP_SINK_OUI;
2638 int ret;
2639
2640 ret = drm_dp_read_ident(aux, offset, ident);
2641 if (ret < 0)
2642 return ret;
2643
2644 desc->quirks = drm_dp_get_quirks(ident, is_branch);
2645
2646 drm_dp_dump_desc(aux, device_name: is_branch ? "DP branch" : "DP sink", desc);
2647
2648 return 0;
2649}
2650EXPORT_SYMBOL(drm_dp_read_desc);
2651
2652/**
2653 * drm_dp_dump_lttpr_desc - read and dump the DPCD descriptor for an LTTPR PHY
2654 * @aux: DisplayPort AUX channel
2655 * @dp_phy: LTTPR PHY instance
2656 *
2657 * Read the DPCD LTTPR PHY descriptor for @dp_phy and print a debug message
2658 * with its details to dmesg.
2659 *
2660 * Returns 0 on success or a negative error code on failure.
2661 */
2662int drm_dp_dump_lttpr_desc(struct drm_dp_aux *aux, enum drm_dp_phy dp_phy)
2663{
2664 struct drm_dp_desc desc = {};
2665 int ret;
2666
2667 if (drm_WARN_ON(aux->drm_dev, dp_phy < DP_PHY_LTTPR1 || dp_phy > DP_MAX_LTTPR_COUNT))
2668 return -EINVAL;
2669
2670 ret = drm_dp_read_ident(aux, DP_OUI_PHY_REPEATER(dp_phy), ident: &desc.ident);
2671 if (ret < 0)
2672 return ret;
2673
2674 drm_dp_dump_desc(aux, device_name: drm_dp_phy_name(dp_phy), desc: &desc);
2675
2676 return 0;
2677}
2678EXPORT_SYMBOL(drm_dp_dump_lttpr_desc);
2679
2680/**
2681 * drm_dp_dsc_sink_bpp_incr() - Get bits per pixel increment
2682 * @dsc_dpcd: DSC capabilities from DPCD
2683 *
2684 * Returns the bpp precision supported by the DP sink.
2685 */
2686u8 drm_dp_dsc_sink_bpp_incr(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
2687{
2688 u8 bpp_increment_dpcd = dsc_dpcd[DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT];
2689
2690 switch (bpp_increment_dpcd & DP_DSC_BITS_PER_PIXEL_MASK) {
2691 case DP_DSC_BITS_PER_PIXEL_1_16:
2692 return 16;
2693 case DP_DSC_BITS_PER_PIXEL_1_8:
2694 return 8;
2695 case DP_DSC_BITS_PER_PIXEL_1_4:
2696 return 4;
2697 case DP_DSC_BITS_PER_PIXEL_1_2:
2698 return 2;
2699 case DP_DSC_BITS_PER_PIXEL_1_1:
2700 return 1;
2701 }
2702
2703 return 0;
2704}
2705EXPORT_SYMBOL(drm_dp_dsc_sink_bpp_incr);
2706
2707/**
2708 * drm_dp_dsc_sink_max_slice_count() - Get the max slice count
2709 * supported by the DSC sink.
2710 * @dsc_dpcd: DSC capabilities from DPCD
2711 * @is_edp: true if its eDP, false for DP
2712 *
2713 * Read the slice capabilities DPCD register from DSC sink to get
2714 * the maximum slice count supported. This is used to populate
2715 * the DSC parameters in the &struct drm_dsc_config by the driver.
2716 * Driver creates an infoframe using these parameters to populate
2717 * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC
2718 * infoframe using the helper function drm_dsc_pps_infoframe_pack()
2719 *
2720 * Returns:
2721 * Maximum slice count supported by DSC sink or 0 its invalid
2722 */
2723u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
2724 bool is_edp)
2725{
2726 u8 slice_cap1 = dsc_dpcd[DP_DSC_SLICE_CAP_1 - DP_DSC_SUPPORT];
2727
2728 if (is_edp) {
2729 /* For eDP, register DSC_SLICE_CAPABILITIES_1 gives slice count */
2730 if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK)
2731 return 4;
2732 if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK)
2733 return 2;
2734 if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK)
2735 return 1;
2736 } else {
2737 /* For DP, use values from DSC_SLICE_CAP_1 and DSC_SLICE_CAP2 */
2738 u8 slice_cap2 = dsc_dpcd[DP_DSC_SLICE_CAP_2 - DP_DSC_SUPPORT];
2739
2740 if (slice_cap2 & DP_DSC_24_PER_DP_DSC_SINK)
2741 return 24;
2742 if (slice_cap2 & DP_DSC_20_PER_DP_DSC_SINK)
2743 return 20;
2744 if (slice_cap2 & DP_DSC_16_PER_DP_DSC_SINK)
2745 return 16;
2746 if (slice_cap1 & DP_DSC_12_PER_DP_DSC_SINK)
2747 return 12;
2748 if (slice_cap1 & DP_DSC_10_PER_DP_DSC_SINK)
2749 return 10;
2750 if (slice_cap1 & DP_DSC_8_PER_DP_DSC_SINK)
2751 return 8;
2752 if (slice_cap1 & DP_DSC_6_PER_DP_DSC_SINK)
2753 return 6;
2754 if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK)
2755 return 4;
2756 if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK)
2757 return 2;
2758 if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK)
2759 return 1;
2760 }
2761
2762 return 0;
2763}
2764EXPORT_SYMBOL(drm_dp_dsc_sink_max_slice_count);
2765
2766/**
2767 * drm_dp_dsc_sink_line_buf_depth() - Get the line buffer depth in bits
2768 * @dsc_dpcd: DSC capabilities from DPCD
2769 *
2770 * Read the DSC DPCD register to parse the line buffer depth in bits which is
2771 * number of bits of precision within the decoder line buffer supported by
2772 * the DSC sink. This is used to populate the DSC parameters in the
2773 * &struct drm_dsc_config by the driver.
2774 * Driver creates an infoframe using these parameters to populate
2775 * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC
2776 * infoframe using the helper function drm_dsc_pps_infoframe_pack()
2777 *
2778 * Returns:
2779 * Line buffer depth supported by DSC panel or 0 its invalid
2780 */
2781u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
2782{
2783 u8 line_buf_depth = dsc_dpcd[DP_DSC_LINE_BUF_BIT_DEPTH - DP_DSC_SUPPORT];
2784
2785 switch (line_buf_depth & DP_DSC_LINE_BUF_BIT_DEPTH_MASK) {
2786 case DP_DSC_LINE_BUF_BIT_DEPTH_9:
2787 return 9;
2788 case DP_DSC_LINE_BUF_BIT_DEPTH_10:
2789 return 10;
2790 case DP_DSC_LINE_BUF_BIT_DEPTH_11:
2791 return 11;
2792 case DP_DSC_LINE_BUF_BIT_DEPTH_12:
2793 return 12;
2794 case DP_DSC_LINE_BUF_BIT_DEPTH_13:
2795 return 13;
2796 case DP_DSC_LINE_BUF_BIT_DEPTH_14:
2797 return 14;
2798 case DP_DSC_LINE_BUF_BIT_DEPTH_15:
2799 return 15;
2800 case DP_DSC_LINE_BUF_BIT_DEPTH_16:
2801 return 16;
2802 case DP_DSC_LINE_BUF_BIT_DEPTH_8:
2803 return 8;
2804 }
2805
2806 return 0;
2807}
2808EXPORT_SYMBOL(drm_dp_dsc_sink_line_buf_depth);
2809
2810/**
2811 * drm_dp_dsc_sink_supported_input_bpcs() - Get all the input bits per component
2812 * values supported by the DSC sink.
2813 * @dsc_dpcd: DSC capabilities from DPCD
2814 * @dsc_bpc: An array to be filled by this helper with supported
2815 * input bpcs.
2816 *
2817 * Read the DSC DPCD from the sink device to parse the supported bits per
2818 * component values. This is used to populate the DSC parameters
2819 * in the &struct drm_dsc_config by the driver.
2820 * Driver creates an infoframe using these parameters to populate
2821 * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC
2822 * infoframe using the helper function drm_dsc_pps_infoframe_pack()
2823 *
2824 * Returns:
2825 * Number of input BPC values parsed from the DPCD
2826 */
2827int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
2828 u8 dsc_bpc[3])
2829{
2830 int num_bpc = 0;
2831 u8 color_depth = dsc_dpcd[DP_DSC_DEC_COLOR_DEPTH_CAP - DP_DSC_SUPPORT];
2832
2833 if (!drm_dp_sink_supports_dsc(dsc_dpcd))
2834 return 0;
2835
2836 if (color_depth & DP_DSC_12_BPC)
2837 dsc_bpc[num_bpc++] = 12;
2838 if (color_depth & DP_DSC_10_BPC)
2839 dsc_bpc[num_bpc++] = 10;
2840
2841 /* A DP DSC Sink device shall support 8 bpc. */
2842 dsc_bpc[num_bpc++] = 8;
2843
2844 return num_bpc;
2845}
2846EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
2847
2848/*
2849 * See DP Standard v2.1a 2.8.4 Minimum Slices/Display, Table 2-159 and
2850 * Appendix L.1 Derivation of Slice Count Requirements.
2851 */
2852static int dsc_sink_min_slice_throughput(int peak_pixel_rate)
2853{
2854 if (peak_pixel_rate >= 4800000)
2855 return 600000;
2856 else if (peak_pixel_rate >= 2700000)
2857 return 400000;
2858 else
2859 return 340000;
2860}
2861
2862/**
2863 * drm_dp_dsc_sink_max_slice_throughput() - Get a DSC sink's maximum pixel throughput per slice
2864 * @dsc_dpcd: DSC sink's capabilities from DPCD
2865 * @peak_pixel_rate: Cumulative peak pixel rate in kHz
2866 * @is_rgb_yuv444: The mode is either RGB or YUV444
2867 *
2868 * Return the DSC sink device's maximum pixel throughput per slice, based on
2869 * the device's @dsc_dpcd capabilities, the @peak_pixel_rate of the transferred
2870 * stream(s) and whether the output format @is_rgb_yuv444 or yuv422/yuv420.
2871 *
2872 * Note that @peak_pixel_rate is the total pixel rate transferred to the same
2873 * DSC/display sink. For instance to calculate a tile's slice count of an MST
2874 * multi-tiled display sink (not considering here the required
2875 * rounding/alignment of slice count)::
2876 *
2877 * @peak_pixel_rate = tile_pixel_rate * tile_count
2878 * total_slice_count = @peak_pixel_rate / drm_dp_dsc_sink_max_slice_throughput(@peak_pixel_rate)
2879 * tile_slice_count = total_slice_count / tile_count
2880 *
2881 * Returns:
2882 * The maximum pixel throughput per slice supported by the DSC sink device
2883 * in kPixels/sec.
2884 */
2885int drm_dp_dsc_sink_max_slice_throughput(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
2886 int peak_pixel_rate, bool is_rgb_yuv444)
2887{
2888 int throughput;
2889 int delta = 0;
2890 int base;
2891
2892 throughput = dsc_dpcd[DP_DSC_PEAK_THROUGHPUT - DP_DSC_SUPPORT];
2893
2894 if (is_rgb_yuv444) {
2895 throughput = (throughput & DP_DSC_THROUGHPUT_MODE_0_MASK) >>
2896 DP_DSC_THROUGHPUT_MODE_0_SHIFT;
2897
2898 delta = ((dsc_dpcd[DP_DSC_RC_BUF_BLK_SIZE - DP_DSC_SUPPORT]) &
2899 DP_DSC_THROUGHPUT_MODE_0_DELTA_MASK) >>
2900 DP_DSC_THROUGHPUT_MODE_0_DELTA_SHIFT; /* in units of 2 MPixels/sec */
2901 delta *= 2000;
2902 } else {
2903 throughput = (throughput & DP_DSC_THROUGHPUT_MODE_1_MASK) >>
2904 DP_DSC_THROUGHPUT_MODE_1_SHIFT;
2905 }
2906
2907 switch (throughput) {
2908 case 0:
2909 return dsc_sink_min_slice_throughput(peak_pixel_rate);
2910 case 1:
2911 base = 340000;
2912 break;
2913 case 2 ... 14:
2914 base = 400000 + 50000 * (throughput - 2);
2915 break;
2916 case 15:
2917 base = 170000;
2918 break;
2919 }
2920
2921 return base + delta;
2922}
2923EXPORT_SYMBOL(drm_dp_dsc_sink_max_slice_throughput);
2924
2925static u8 dsc_branch_dpcd_cap(const u8 dpcd[DP_DSC_BRANCH_CAP_SIZE], int reg)
2926{
2927 return dpcd[reg - DP_DSC_BRANCH_OVERALL_THROUGHPUT_0];
2928}
2929
2930/**
2931 * drm_dp_dsc_branch_max_overall_throughput() - Branch device's max overall DSC pixel throughput
2932 * @dsc_branch_dpcd: DSC branch capabilities from DPCD
2933 * @is_rgb_yuv444: The mode is either RGB or YUV444
2934 *
2935 * Return the branch device's maximum overall DSC pixel throughput, based on
2936 * the device's DPCD DSC branch capabilities, and whether the output
2937 * format @is_rgb_yuv444 or yuv422/yuv420.
2938 *
2939 * Returns:
2940 * - 0: The maximum overall throughput capability is not indicated by
2941 * the device separately and it must be determined from the per-slice
2942 * max throughput (see @drm_dp_dsc_branch_slice_max_throughput())
2943 * and the maximum slice count supported by the device.
2944 * - > 0: The maximum overall DSC pixel throughput supported by the branch
2945 * device in kPixels/sec.
2946 */
2947int drm_dp_dsc_branch_max_overall_throughput(const u8 dsc_branch_dpcd[DP_DSC_BRANCH_CAP_SIZE],
2948 bool is_rgb_yuv444)
2949{
2950 int throughput;
2951
2952 if (is_rgb_yuv444)
2953 throughput = dsc_branch_dpcd_cap(dpcd: dsc_branch_dpcd,
2954 DP_DSC_BRANCH_OVERALL_THROUGHPUT_0);
2955 else
2956 throughput = dsc_branch_dpcd_cap(dpcd: dsc_branch_dpcd,
2957 DP_DSC_BRANCH_OVERALL_THROUGHPUT_1);
2958
2959 switch (throughput) {
2960 case 0:
2961 return 0;
2962 case 1:
2963 return 680000;
2964 default:
2965 return 600000 + 50000 * throughput;
2966 }
2967}
2968EXPORT_SYMBOL(drm_dp_dsc_branch_max_overall_throughput);
2969
2970/**
2971 * drm_dp_dsc_branch_max_line_width() - Branch device's max DSC line width
2972 * @dsc_branch_dpcd: DSC branch capabilities from DPCD
2973 *
2974 * Return the branch device's maximum overall DSC line width, based on
2975 * the device's @dsc_branch_dpcd capabilities.
2976 *
2977 * Returns:
2978 * - 0: The maximum line width is not indicated by the device
2979 * separately and it must be determined from the maximum
2980 * slice count and slice-width supported by the device.
2981 * - %-EINVAL: The device indicates an invalid maximum line width
2982 * (< 5120 pixels).
2983 * - >= 5120: The maximum line width in pixels.
2984 */
2985int drm_dp_dsc_branch_max_line_width(const u8 dsc_branch_dpcd[DP_DSC_BRANCH_CAP_SIZE])
2986{
2987 int line_width = dsc_branch_dpcd_cap(dpcd: dsc_branch_dpcd, DP_DSC_BRANCH_MAX_LINE_WIDTH);
2988
2989 switch (line_width) {
2990 case 0:
2991 return 0;
2992 case 1 ... 15:
2993 return -EINVAL;
2994 default:
2995 return line_width * 320;
2996 }
2997}
2998EXPORT_SYMBOL(drm_dp_dsc_branch_max_line_width);
2999
3000static int drm_dp_read_lttpr_regs(struct drm_dp_aux *aux,
3001 const u8 dpcd[DP_RECEIVER_CAP_SIZE], int address,
3002 u8 *buf, int buf_size)
3003{
3004 /*
3005 * At least the DELL P2715Q monitor with a DPCD_REV < 0x14 returns
3006 * corrupted values when reading from the 0xF0000- range with a block
3007 * size bigger than 1.
3008 */
3009 int block_size = dpcd[DP_DPCD_REV] < 0x14 ? 1 : buf_size;
3010 int offset;
3011 int ret;
3012
3013 for (offset = 0; offset < buf_size; offset += block_size) {
3014 ret = drm_dp_dpcd_read_data(aux,
3015 offset: address + offset,
3016 buffer: &buf[offset], size: block_size);
3017 if (ret < 0)
3018 return ret;
3019 }
3020
3021 return 0;
3022}
3023
3024/**
3025 * drm_dp_read_lttpr_common_caps - read the LTTPR common capabilities
3026 * @aux: DisplayPort AUX channel
3027 * @dpcd: DisplayPort configuration data
3028 * @caps: buffer to return the capability info in
3029 *
3030 * Read capabilities common to all LTTPRs.
3031 *
3032 * Returns 0 on success or a negative error code on failure.
3033 */
3034int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux,
3035 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
3036 u8 caps[DP_LTTPR_COMMON_CAP_SIZE])
3037{
3038 return drm_dp_read_lttpr_regs(aux, dpcd,
3039 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
3040 buf: caps, DP_LTTPR_COMMON_CAP_SIZE);
3041}
3042EXPORT_SYMBOL(drm_dp_read_lttpr_common_caps);
3043
3044/**
3045 * drm_dp_read_lttpr_phy_caps - read the capabilities for a given LTTPR PHY
3046 * @aux: DisplayPort AUX channel
3047 * @dpcd: DisplayPort configuration data
3048 * @dp_phy: LTTPR PHY to read the capabilities for
3049 * @caps: buffer to return the capability info in
3050 *
3051 * Read the capabilities for the given LTTPR PHY.
3052 *
3053 * Returns 0 on success or a negative error code on failure.
3054 */
3055int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux,
3056 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
3057 enum drm_dp_phy dp_phy,
3058 u8 caps[DP_LTTPR_PHY_CAP_SIZE])
3059{
3060 return drm_dp_read_lttpr_regs(aux, dpcd,
3061 DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy),
3062 buf: caps, DP_LTTPR_PHY_CAP_SIZE);
3063}
3064EXPORT_SYMBOL(drm_dp_read_lttpr_phy_caps);
3065
3066static u8 dp_lttpr_common_cap(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE], int r)
3067{
3068 return caps[r - DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
3069}
3070
3071/**
3072 * drm_dp_lttpr_count - get the number of detected LTTPRs
3073 * @caps: LTTPR common capabilities
3074 *
3075 * Get the number of detected LTTPRs from the LTTPR common capabilities info.
3076 *
3077 * Returns:
3078 * -ERANGE if more than supported number (8) of LTTPRs are detected
3079 * -EINVAL if the DP_PHY_REPEATER_CNT register contains an invalid value
3080 * otherwise the number of detected LTTPRs
3081 */
3082int drm_dp_lttpr_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE])
3083{
3084 u8 count = dp_lttpr_common_cap(caps, DP_PHY_REPEATER_CNT);
3085
3086 switch (hweight8(count)) {
3087 case 0:
3088 return 0;
3089 case 1:
3090 return 8 - ilog2(count);
3091 case 8:
3092 return -ERANGE;
3093 default:
3094 return -EINVAL;
3095 }
3096}
3097EXPORT_SYMBOL(drm_dp_lttpr_count);
3098
3099/**
3100 * drm_dp_lttpr_max_link_rate - get the maximum link rate supported by all LTTPRs
3101 * @caps: LTTPR common capabilities
3102 *
3103 * Returns the maximum link rate supported by all detected LTTPRs.
3104 */
3105int drm_dp_lttpr_max_link_rate(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE])
3106{
3107 u8 rate = dp_lttpr_common_cap(caps, DP_MAX_LINK_RATE_PHY_REPEATER);
3108
3109 return drm_dp_bw_code_to_link_rate(rate);
3110}
3111EXPORT_SYMBOL(drm_dp_lttpr_max_link_rate);
3112
3113/**
3114 * drm_dp_lttpr_set_transparent_mode() - set the LTTPR in transparent mode
3115 * @aux: DisplayPort AUX channel
3116 * @enable: Enable or disable transparent mode
3117 *
3118 * Returns: 0 on success or a negative error code on failure.
3119 */
3120int drm_dp_lttpr_set_transparent_mode(struct drm_dp_aux *aux, bool enable)
3121{
3122 u8 val = enable ? DP_PHY_REPEATER_MODE_TRANSPARENT :
3123 DP_PHY_REPEATER_MODE_NON_TRANSPARENT;
3124 int ret = drm_dp_dpcd_writeb(aux, DP_PHY_REPEATER_MODE, value: val);
3125
3126 if (ret < 0)
3127 return ret;
3128
3129 return (ret == 1) ? 0 : -EIO;
3130}
3131EXPORT_SYMBOL(drm_dp_lttpr_set_transparent_mode);
3132
3133/**
3134 * drm_dp_lttpr_init() - init LTTPR transparency mode according to DP standard
3135 * @aux: DisplayPort AUX channel
3136 * @lttpr_count: Number of LTTPRs. Between 0 and 8, according to DP standard.
3137 * Negative error code for any non-valid number.
3138 * See drm_dp_lttpr_count().
3139 *
3140 * Returns: 0 on success or a negative error code on failure.
3141 */
3142int drm_dp_lttpr_init(struct drm_dp_aux *aux, int lttpr_count)
3143{
3144 int ret;
3145
3146 if (!lttpr_count)
3147 return 0;
3148
3149 /*
3150 * See DP Standard v2.0 3.6.6.1 about the explicit disabling of
3151 * non-transparent mode and the disable->enable non-transparent mode
3152 * sequence.
3153 */
3154 ret = drm_dp_lttpr_set_transparent_mode(aux, true);
3155 if (ret)
3156 return ret;
3157
3158 if (lttpr_count < 0)
3159 return -ENODEV;
3160
3161 if (drm_dp_lttpr_set_transparent_mode(aux, false)) {
3162 /*
3163 * Roll-back to transparent mode if setting non-transparent
3164 * mode has failed
3165 */
3166 drm_dp_lttpr_set_transparent_mode(aux, true);
3167 return -EINVAL;
3168 }
3169
3170 return 0;
3171}
3172EXPORT_SYMBOL(drm_dp_lttpr_init);
3173
3174/**
3175 * drm_dp_lttpr_max_lane_count - get the maximum lane count supported by all LTTPRs
3176 * @caps: LTTPR common capabilities
3177 *
3178 * Returns the maximum lane count supported by all detected LTTPRs.
3179 */
3180int drm_dp_lttpr_max_lane_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE])
3181{
3182 u8 max_lanes = dp_lttpr_common_cap(caps, DP_MAX_LANE_COUNT_PHY_REPEATER);
3183
3184 return max_lanes & DP_MAX_LANE_COUNT_MASK;
3185}
3186EXPORT_SYMBOL(drm_dp_lttpr_max_lane_count);
3187
3188/**
3189 * drm_dp_lttpr_voltage_swing_level_3_supported - check for LTTPR vswing3 support
3190 * @caps: LTTPR PHY capabilities
3191 *
3192 * Returns true if the @caps for an LTTPR TX PHY indicate support for
3193 * voltage swing level 3.
3194 */
3195bool
3196drm_dp_lttpr_voltage_swing_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE])
3197{
3198 u8 txcap = dp_lttpr_phy_cap(phy_cap: caps, DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1);
3199
3200 return txcap & DP_VOLTAGE_SWING_LEVEL_3_SUPPORTED;
3201}
3202EXPORT_SYMBOL(drm_dp_lttpr_voltage_swing_level_3_supported);
3203
3204/**
3205 * drm_dp_lttpr_pre_emphasis_level_3_supported - check for LTTPR preemph3 support
3206 * @caps: LTTPR PHY capabilities
3207 *
3208 * Returns true if the @caps for an LTTPR TX PHY indicate support for
3209 * pre-emphasis level 3.
3210 */
3211bool
3212drm_dp_lttpr_pre_emphasis_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE])
3213{
3214 u8 txcap = dp_lttpr_phy_cap(phy_cap: caps, DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1);
3215
3216 return txcap & DP_PRE_EMPHASIS_LEVEL_3_SUPPORTED;
3217}
3218EXPORT_SYMBOL(drm_dp_lttpr_pre_emphasis_level_3_supported);
3219
3220/**
3221 * drm_dp_get_phy_test_pattern() - get the requested pattern from the sink.
3222 * @aux: DisplayPort AUX channel
3223 * @data: DP phy compliance test parameters.
3224 *
3225 * Returns 0 on success or a negative error code on failure.
3226 */
3227int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
3228 struct drm_dp_phy_test_params *data)
3229{
3230 int err;
3231 u8 rate, lanes;
3232
3233 err = drm_dp_dpcd_read_byte(aux, DP_TEST_LINK_RATE, valuep: &rate);
3234 if (err < 0)
3235 return err;
3236 data->link_rate = drm_dp_bw_code_to_link_rate(rate);
3237
3238 err = drm_dp_dpcd_read_byte(aux, DP_TEST_LANE_COUNT, valuep: &lanes);
3239 if (err < 0)
3240 return err;
3241 data->num_lanes = lanes & DP_MAX_LANE_COUNT_MASK;
3242
3243 if (lanes & DP_ENHANCED_FRAME_CAP)
3244 data->enhanced_frame_cap = true;
3245
3246 err = drm_dp_dpcd_read_byte(aux, DP_PHY_TEST_PATTERN, valuep: &data->phy_pattern);
3247 if (err < 0)
3248 return err;
3249
3250 switch (data->phy_pattern) {
3251 case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
3252 err = drm_dp_dpcd_read_data(aux, DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
3253 buffer: &data->custom80, size: sizeof(data->custom80));
3254 if (err < 0)
3255 return err;
3256
3257 break;
3258 case DP_PHY_TEST_PATTERN_CP2520:
3259 err = drm_dp_dpcd_read_data(aux, DP_TEST_HBR2_SCRAMBLER_RESET,
3260 buffer: &data->hbr2_reset,
3261 size: sizeof(data->hbr2_reset));
3262 if (err < 0)
3263 return err;
3264 }
3265
3266 return 0;
3267}
3268EXPORT_SYMBOL(drm_dp_get_phy_test_pattern);
3269
3270/**
3271 * drm_dp_set_phy_test_pattern() - set the pattern to the sink.
3272 * @aux: DisplayPort AUX channel
3273 * @data: DP phy compliance test parameters.
3274 * @dp_rev: DP revision to use for compliance testing
3275 *
3276 * Returns 0 on success or a negative error code on failure.
3277 */
3278int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
3279 struct drm_dp_phy_test_params *data, u8 dp_rev)
3280{
3281 int err, i;
3282 u8 test_pattern;
3283
3284 test_pattern = data->phy_pattern;
3285 if (dp_rev < 0x12) {
3286 test_pattern = (test_pattern << 2) &
3287 DP_LINK_QUAL_PATTERN_11_MASK;
3288 err = drm_dp_dpcd_write_byte(aux, DP_TRAINING_PATTERN_SET,
3289 value: test_pattern);
3290 if (err < 0)
3291 return err;
3292 } else {
3293 for (i = 0; i < data->num_lanes; i++) {
3294 err = drm_dp_dpcd_write_byte(aux,
3295 DP_LINK_QUAL_LANE0_SET + i,
3296 value: test_pattern);
3297 if (err < 0)
3298 return err;
3299 }
3300 }
3301
3302 return 0;
3303}
3304EXPORT_SYMBOL(drm_dp_set_phy_test_pattern);
3305
3306static const char *dp_pixelformat_get_name(enum dp_pixelformat pixelformat)
3307{
3308 if (pixelformat < 0 || pixelformat > DP_PIXELFORMAT_RESERVED)
3309 return "Invalid";
3310
3311 switch (pixelformat) {
3312 case DP_PIXELFORMAT_RGB:
3313 return "RGB";
3314 case DP_PIXELFORMAT_YUV444:
3315 return "YUV444";
3316 case DP_PIXELFORMAT_YUV422:
3317 return "YUV422";
3318 case DP_PIXELFORMAT_YUV420:
3319 return "YUV420";
3320 case DP_PIXELFORMAT_Y_ONLY:
3321 return "Y_ONLY";
3322 case DP_PIXELFORMAT_RAW:
3323 return "RAW";
3324 default:
3325 return "Reserved";
3326 }
3327}
3328
3329static const char *dp_colorimetry_get_name(enum dp_pixelformat pixelformat,
3330 enum dp_colorimetry colorimetry)
3331{
3332 if (pixelformat < 0 || pixelformat > DP_PIXELFORMAT_RESERVED)
3333 return "Invalid";
3334
3335 switch (colorimetry) {
3336 case DP_COLORIMETRY_DEFAULT:
3337 switch (pixelformat) {
3338 case DP_PIXELFORMAT_RGB:
3339 return "sRGB";
3340 case DP_PIXELFORMAT_YUV444:
3341 case DP_PIXELFORMAT_YUV422:
3342 case DP_PIXELFORMAT_YUV420:
3343 return "BT.601";
3344 case DP_PIXELFORMAT_Y_ONLY:
3345 return "DICOM PS3.14";
3346 case DP_PIXELFORMAT_RAW:
3347 return "Custom Color Profile";
3348 default:
3349 return "Reserved";
3350 }
3351 case DP_COLORIMETRY_RGB_WIDE_FIXED: /* and DP_COLORIMETRY_BT709_YCC */
3352 switch (pixelformat) {
3353 case DP_PIXELFORMAT_RGB:
3354 return "Wide Fixed";
3355 case DP_PIXELFORMAT_YUV444:
3356 case DP_PIXELFORMAT_YUV422:
3357 case DP_PIXELFORMAT_YUV420:
3358 return "BT.709";
3359 default:
3360 return "Reserved";
3361 }
3362 case DP_COLORIMETRY_RGB_WIDE_FLOAT: /* and DP_COLORIMETRY_XVYCC_601 */
3363 switch (pixelformat) {
3364 case DP_PIXELFORMAT_RGB:
3365 return "Wide Float";
3366 case DP_PIXELFORMAT_YUV444:
3367 case DP_PIXELFORMAT_YUV422:
3368 case DP_PIXELFORMAT_YUV420:
3369 return "xvYCC 601";
3370 default:
3371 return "Reserved";
3372 }
3373 case DP_COLORIMETRY_OPRGB: /* and DP_COLORIMETRY_XVYCC_709 */
3374 switch (pixelformat) {
3375 case DP_PIXELFORMAT_RGB:
3376 return "OpRGB";
3377 case DP_PIXELFORMAT_YUV444:
3378 case DP_PIXELFORMAT_YUV422:
3379 case DP_PIXELFORMAT_YUV420:
3380 return "xvYCC 709";
3381 default:
3382 return "Reserved";
3383 }
3384 case DP_COLORIMETRY_DCI_P3_RGB: /* and DP_COLORIMETRY_SYCC_601 */
3385 switch (pixelformat) {
3386 case DP_PIXELFORMAT_RGB:
3387 return "DCI-P3";
3388 case DP_PIXELFORMAT_YUV444:
3389 case DP_PIXELFORMAT_YUV422:
3390 case DP_PIXELFORMAT_YUV420:
3391 return "sYCC 601";
3392 default:
3393 return "Reserved";
3394 }
3395 case DP_COLORIMETRY_RGB_CUSTOM: /* and DP_COLORIMETRY_OPYCC_601 */
3396 switch (pixelformat) {
3397 case DP_PIXELFORMAT_RGB:
3398 return "Custom Profile";
3399 case DP_PIXELFORMAT_YUV444:
3400 case DP_PIXELFORMAT_YUV422:
3401 case DP_PIXELFORMAT_YUV420:
3402 return "OpYCC 601";
3403 default:
3404 return "Reserved";
3405 }
3406 case DP_COLORIMETRY_BT2020_RGB: /* and DP_COLORIMETRY_BT2020_CYCC */
3407 switch (pixelformat) {
3408 case DP_PIXELFORMAT_RGB:
3409 return "BT.2020 RGB";
3410 case DP_PIXELFORMAT_YUV444:
3411 case DP_PIXELFORMAT_YUV422:
3412 case DP_PIXELFORMAT_YUV420:
3413 return "BT.2020 CYCC";
3414 default:
3415 return "Reserved";
3416 }
3417 case DP_COLORIMETRY_BT2020_YCC:
3418 switch (pixelformat) {
3419 case DP_PIXELFORMAT_YUV444:
3420 case DP_PIXELFORMAT_YUV422:
3421 case DP_PIXELFORMAT_YUV420:
3422 return "BT.2020 YCC";
3423 default:
3424 return "Reserved";
3425 }
3426 default:
3427 return "Invalid";
3428 }
3429}
3430
3431static const char *dp_dynamic_range_get_name(enum dp_dynamic_range dynamic_range)
3432{
3433 switch (dynamic_range) {
3434 case DP_DYNAMIC_RANGE_VESA:
3435 return "VESA range";
3436 case DP_DYNAMIC_RANGE_CTA:
3437 return "CTA range";
3438 default:
3439 return "Invalid";
3440 }
3441}
3442
3443static const char *dp_content_type_get_name(enum dp_content_type content_type)
3444{
3445 switch (content_type) {
3446 case DP_CONTENT_TYPE_NOT_DEFINED:
3447 return "Not defined";
3448 case DP_CONTENT_TYPE_GRAPHICS:
3449 return "Graphics";
3450 case DP_CONTENT_TYPE_PHOTO:
3451 return "Photo";
3452 case DP_CONTENT_TYPE_VIDEO:
3453 return "Video";
3454 case DP_CONTENT_TYPE_GAME:
3455 return "Game";
3456 default:
3457 return "Reserved";
3458 }
3459}
3460
3461void drm_dp_vsc_sdp_log(struct drm_printer *p, const struct drm_dp_vsc_sdp *vsc)
3462{
3463 drm_printf(p, f: "DP SDP: VSC, revision %u, length %u\n",
3464 vsc->revision, vsc->length);
3465 drm_printf(p, f: " pixelformat: %s\n",
3466 dp_pixelformat_get_name(pixelformat: vsc->pixelformat));
3467 drm_printf(p, f: " colorimetry: %s\n",
3468 dp_colorimetry_get_name(pixelformat: vsc->pixelformat, colorimetry: vsc->colorimetry));
3469 drm_printf(p, f: " bpc: %u\n", vsc->bpc);
3470 drm_printf(p, f: " dynamic range: %s\n",
3471 dp_dynamic_range_get_name(dynamic_range: vsc->dynamic_range));
3472 drm_printf(p, f: " content type: %s\n",
3473 dp_content_type_get_name(content_type: vsc->content_type));
3474}
3475EXPORT_SYMBOL(drm_dp_vsc_sdp_log);
3476
3477void drm_dp_as_sdp_log(struct drm_printer *p, const struct drm_dp_as_sdp *as_sdp)
3478{
3479 drm_printf(p, f: "DP SDP: AS_SDP, revision %u, length %u\n",
3480 as_sdp->revision, as_sdp->length);
3481 drm_printf(p, f: " vtotal: %d\n", as_sdp->vtotal);
3482 drm_printf(p, f: " target_rr: %d\n", as_sdp->target_rr);
3483 drm_printf(p, f: " duration_incr_ms: %d\n", as_sdp->duration_incr_ms);
3484 drm_printf(p, f: " duration_decr_ms: %d\n", as_sdp->duration_decr_ms);
3485 drm_printf(p, f: " operation_mode: %d\n", as_sdp->mode);
3486}
3487EXPORT_SYMBOL(drm_dp_as_sdp_log);
3488
3489/**
3490 * drm_dp_as_sdp_supported() - check if adaptive sync sdp is supported
3491 * @aux: DisplayPort AUX channel
3492 * @dpcd: DisplayPort configuration data
3493 *
3494 * Returns true if adaptive sync sdp is supported, else returns false
3495 */
3496bool drm_dp_as_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE])
3497{
3498 u8 rx_feature;
3499
3500 if (dpcd[DP_DPCD_REV] < DP_DPCD_REV_13)
3501 return false;
3502
3503 if (drm_dp_dpcd_read_byte(aux, DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1,
3504 valuep: &rx_feature) < 0) {
3505 drm_dbg_dp(aux->drm_dev,
3506 "Failed to read DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1\n");
3507 return false;
3508 }
3509
3510 return (rx_feature & DP_ADAPTIVE_SYNC_SDP_SUPPORTED);
3511}
3512EXPORT_SYMBOL(drm_dp_as_sdp_supported);
3513
3514/**
3515 * drm_dp_vsc_sdp_supported() - check if vsc sdp is supported
3516 * @aux: DisplayPort AUX channel
3517 * @dpcd: DisplayPort configuration data
3518 *
3519 * Returns true if vsc sdp is supported, else returns false
3520 */
3521bool drm_dp_vsc_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE])
3522{
3523 u8 rx_feature;
3524
3525 if (dpcd[DP_DPCD_REV] < DP_DPCD_REV_13)
3526 return false;
3527
3528 if (drm_dp_dpcd_read_byte(aux, DP_DPRX_FEATURE_ENUMERATION_LIST, valuep: &rx_feature) < 0) {
3529 drm_dbg_dp(aux->drm_dev, "failed to read DP_DPRX_FEATURE_ENUMERATION_LIST\n");
3530 return false;
3531 }
3532
3533 return (rx_feature & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED);
3534}
3535EXPORT_SYMBOL(drm_dp_vsc_sdp_supported);
3536
3537/**
3538 * drm_dp_vsc_sdp_pack() - pack a given vsc sdp into generic dp_sdp
3539 * @vsc: vsc sdp initialized according to its purpose as defined in
3540 * table 2-118 - table 2-120 in DP 1.4a specification
3541 * @sdp: valid handle to the generic dp_sdp which will be packed
3542 *
3543 * Returns length of sdp on success and error code on failure
3544 */
3545ssize_t drm_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
3546 struct dp_sdp *sdp)
3547{
3548 size_t length = sizeof(struct dp_sdp);
3549
3550 memset(sdp, 0, sizeof(struct dp_sdp));
3551
3552 /*
3553 * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
3554 * VSC SDP Header Bytes
3555 */
3556 sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
3557 sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */
3558 sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
3559 sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
3560
3561 if (vsc->revision == 0x6) {
3562 sdp->db[0] = 1;
3563 sdp->db[3] = 1;
3564 }
3565
3566 /*
3567 * Revision 0x5 and revision 0x7 supports Pixel Encoding/Colorimetry
3568 * Format as per DP 1.4a spec and DP 2.0 respectively.
3569 */
3570 if (!(vsc->revision == 0x5 || vsc->revision == 0x7))
3571 goto out;
3572
3573 /* VSC SDP Payload for DB16 through DB18 */
3574 /* Pixel Encoding and Colorimetry Formats */
3575 sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */
3576 sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
3577
3578 switch (vsc->bpc) {
3579 case 6:
3580 /* 6bpc: 0x0 */
3581 break;
3582 case 8:
3583 sdp->db[17] = 0x1; /* DB17[3:0] */
3584 break;
3585 case 10:
3586 sdp->db[17] = 0x2;
3587 break;
3588 case 12:
3589 sdp->db[17] = 0x3;
3590 break;
3591 case 16:
3592 sdp->db[17] = 0x4;
3593 break;
3594 default:
3595 WARN(1, "Missing case %d\n", vsc->bpc);
3596 return -EINVAL;
3597 }
3598
3599 /* Dynamic Range and Component Bit Depth */
3600 if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
3601 sdp->db[17] |= 0x80; /* DB17[7] */
3602
3603 /* Content Type */
3604 sdp->db[18] = vsc->content_type & 0x7;
3605
3606out:
3607 return length;
3608}
3609EXPORT_SYMBOL(drm_dp_vsc_sdp_pack);
3610
3611/**
3612 * drm_dp_get_pcon_max_frl_bw() - maximum frl supported by PCON
3613 * @dpcd: DisplayPort configuration data
3614 * @port_cap: port capabilities
3615 *
3616 * Returns maximum frl bandwidth supported by PCON in GBPS,
3617 * returns 0 if not supported.
3618 */
3619int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
3620 const u8 port_cap[4])
3621{
3622 int bw;
3623 u8 buf;
3624
3625 buf = port_cap[2];
3626 bw = buf & DP_PCON_MAX_FRL_BW;
3627
3628 switch (bw) {
3629 case DP_PCON_MAX_9GBPS:
3630 return 9;
3631 case DP_PCON_MAX_18GBPS:
3632 return 18;
3633 case DP_PCON_MAX_24GBPS:
3634 return 24;
3635 case DP_PCON_MAX_32GBPS:
3636 return 32;
3637 case DP_PCON_MAX_40GBPS:
3638 return 40;
3639 case DP_PCON_MAX_48GBPS:
3640 return 48;
3641 case DP_PCON_MAX_0GBPS:
3642 default:
3643 return 0;
3644 }
3645
3646 return 0;
3647}
3648EXPORT_SYMBOL(drm_dp_get_pcon_max_frl_bw);
3649
3650/**
3651 * drm_dp_pcon_frl_prepare() - Prepare PCON for FRL.
3652 * @aux: DisplayPort AUX channel
3653 * @enable_frl_ready_hpd: Configure DP_PCON_ENABLE_HPD_READY.
3654 *
3655 * Returns 0 if success, else returns negative error code.
3656 */
3657int drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool enable_frl_ready_hpd)
3658{
3659 u8 buf = DP_PCON_ENABLE_SOURCE_CTL_MODE |
3660 DP_PCON_ENABLE_LINK_FRL_MODE;
3661
3662 if (enable_frl_ready_hpd)
3663 buf |= DP_PCON_ENABLE_HPD_READY;
3664
3665 return drm_dp_dpcd_write_byte(aux, DP_PCON_HDMI_LINK_CONFIG_1, value: buf);
3666}
3667EXPORT_SYMBOL(drm_dp_pcon_frl_prepare);
3668
3669/**
3670 * drm_dp_pcon_is_frl_ready() - Is PCON ready for FRL
3671 * @aux: DisplayPort AUX channel
3672 *
3673 * Returns true if success, else returns false.
3674 */
3675bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux *aux)
3676{
3677 int ret;
3678 u8 buf;
3679
3680 ret = drm_dp_dpcd_read_byte(aux, DP_PCON_HDMI_TX_LINK_STATUS, valuep: &buf);
3681 if (ret < 0)
3682 return false;
3683
3684 if (buf & DP_PCON_FRL_READY)
3685 return true;
3686
3687 return false;
3688}
3689EXPORT_SYMBOL(drm_dp_pcon_is_frl_ready);
3690
3691/**
3692 * drm_dp_pcon_frl_configure_1() - Set HDMI LINK Configuration-Step1
3693 * @aux: DisplayPort AUX channel
3694 * @max_frl_gbps: maximum frl bw to be configured between PCON and HDMI sink
3695 * @frl_mode: FRL Training mode, it can be either Concurrent or Sequential.
3696 * In Concurrent Mode, the FRL link bring up can be done along with
3697 * DP Link training. In Sequential mode, the FRL link bring up is done prior to
3698 * the DP Link training.
3699 *
3700 * Returns 0 if success, else returns negative error code.
3701 */
3702
3703int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps,
3704 u8 frl_mode)
3705{
3706 int ret;
3707 u8 buf;
3708
3709 ret = drm_dp_dpcd_read_byte(aux, DP_PCON_HDMI_LINK_CONFIG_1, valuep: &buf);
3710 if (ret < 0)
3711 return ret;
3712
3713 if (frl_mode == DP_PCON_ENABLE_CONCURRENT_LINK)
3714 buf |= DP_PCON_ENABLE_CONCURRENT_LINK;
3715 else
3716 buf &= ~DP_PCON_ENABLE_CONCURRENT_LINK;
3717
3718 switch (max_frl_gbps) {
3719 case 9:
3720 buf |= DP_PCON_ENABLE_MAX_BW_9GBPS;
3721 break;
3722 case 18:
3723 buf |= DP_PCON_ENABLE_MAX_BW_18GBPS;
3724 break;
3725 case 24:
3726 buf |= DP_PCON_ENABLE_MAX_BW_24GBPS;
3727 break;
3728 case 32:
3729 buf |= DP_PCON_ENABLE_MAX_BW_32GBPS;
3730 break;
3731 case 40:
3732 buf |= DP_PCON_ENABLE_MAX_BW_40GBPS;
3733 break;
3734 case 48:
3735 buf |= DP_PCON_ENABLE_MAX_BW_48GBPS;
3736 break;
3737 case 0:
3738 buf |= DP_PCON_ENABLE_MAX_BW_0GBPS;
3739 break;
3740 default:
3741 return -EINVAL;
3742 }
3743
3744 return drm_dp_dpcd_write_byte(aux, DP_PCON_HDMI_LINK_CONFIG_1, value: buf);
3745}
3746EXPORT_SYMBOL(drm_dp_pcon_frl_configure_1);
3747
3748/**
3749 * drm_dp_pcon_frl_configure_2() - Set HDMI Link configuration Step-2
3750 * @aux: DisplayPort AUX channel
3751 * @max_frl_mask : Max FRL BW to be tried by the PCON with HDMI Sink
3752 * @frl_type : FRL training type, can be Extended, or Normal.
3753 * In Normal FRL training, the PCON tries each frl bw from the max_frl_mask
3754 * starting from min, and stops when link training is successful. In Extended
3755 * FRL training, all frl bw selected in the mask are trained by the PCON.
3756 *
3757 * Returns 0 if success, else returns negative error code.
3758 */
3759int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask,
3760 u8 frl_type)
3761{
3762 int ret;
3763 u8 buf = max_frl_mask;
3764
3765 if (frl_type == DP_PCON_FRL_LINK_TRAIN_EXTENDED)
3766 buf |= DP_PCON_FRL_LINK_TRAIN_EXTENDED;
3767 else
3768 buf &= ~DP_PCON_FRL_LINK_TRAIN_EXTENDED;
3769
3770 return drm_dp_dpcd_write_byte(aux, DP_PCON_HDMI_LINK_CONFIG_2, value: buf);
3771 if (ret < 0)
3772 return ret;
3773
3774 return 0;
3775}
3776EXPORT_SYMBOL(drm_dp_pcon_frl_configure_2);
3777
3778/**
3779 * drm_dp_pcon_reset_frl_config() - Re-Set HDMI Link configuration.
3780 * @aux: DisplayPort AUX channel
3781 *
3782 * Returns 0 if success, else returns negative error code.
3783 */
3784int drm_dp_pcon_reset_frl_config(struct drm_dp_aux *aux)
3785{
3786 return drm_dp_dpcd_write_byte(aux, DP_PCON_HDMI_LINK_CONFIG_1, value: 0x0);
3787}
3788EXPORT_SYMBOL(drm_dp_pcon_reset_frl_config);
3789
3790/**
3791 * drm_dp_pcon_frl_enable() - Enable HDMI link through FRL
3792 * @aux: DisplayPort AUX channel
3793 *
3794 * Returns 0 if success, else returns negative error code.
3795 */
3796int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux)
3797{
3798 int ret;
3799 u8 buf = 0;
3800
3801 ret = drm_dp_dpcd_read_byte(aux, DP_PCON_HDMI_LINK_CONFIG_1, valuep: &buf);
3802 if (ret < 0)
3803 return ret;
3804 if (!(buf & DP_PCON_ENABLE_SOURCE_CTL_MODE)) {
3805 drm_dbg_kms(aux->drm_dev, "%s: PCON in Autonomous mode, can't enable FRL\n",
3806 aux->name);
3807 return -EINVAL;
3808 }
3809 buf |= DP_PCON_ENABLE_HDMI_LINK;
3810 return drm_dp_dpcd_write_byte(aux, DP_PCON_HDMI_LINK_CONFIG_1, value: buf);
3811}
3812EXPORT_SYMBOL(drm_dp_pcon_frl_enable);
3813
3814/**
3815 * drm_dp_pcon_hdmi_link_active() - check if the PCON HDMI LINK status is active.
3816 * @aux: DisplayPort AUX channel
3817 *
3818 * Returns true if link is active else returns false.
3819 */
3820bool drm_dp_pcon_hdmi_link_active(struct drm_dp_aux *aux)
3821{
3822 u8 buf;
3823 int ret;
3824
3825 ret = drm_dp_dpcd_read_byte(aux, DP_PCON_HDMI_TX_LINK_STATUS, valuep: &buf);
3826 if (ret < 0)
3827 return false;
3828
3829 return buf & DP_PCON_HDMI_TX_LINK_ACTIVE;
3830}
3831EXPORT_SYMBOL(drm_dp_pcon_hdmi_link_active);
3832
3833/**
3834 * drm_dp_pcon_hdmi_link_mode() - get the PCON HDMI LINK MODE
3835 * @aux: DisplayPort AUX channel
3836 * @frl_trained_mask: pointer to store bitmask of the trained bw configuration.
3837 * Valid only if the MODE returned is FRL. For Normal Link training mode
3838 * only 1 of the bits will be set, but in case of Extended mode, more than
3839 * one bits can be set.
3840 *
3841 * Returns the link mode : TMDS or FRL on success, else returns negative error
3842 * code.
3843 */
3844int drm_dp_pcon_hdmi_link_mode(struct drm_dp_aux *aux, u8 *frl_trained_mask)
3845{
3846 u8 buf;
3847 int mode;
3848 int ret;
3849
3850 ret = drm_dp_dpcd_read_byte(aux, DP_PCON_HDMI_POST_FRL_STATUS, valuep: &buf);
3851 if (ret < 0)
3852 return ret;
3853
3854 mode = buf & DP_PCON_HDMI_LINK_MODE;
3855
3856 if (frl_trained_mask && DP_PCON_HDMI_MODE_FRL == mode)
3857 *frl_trained_mask = (buf & DP_PCON_HDMI_FRL_TRAINED_BW) >> 1;
3858
3859 return mode;
3860}
3861EXPORT_SYMBOL(drm_dp_pcon_hdmi_link_mode);
3862
3863/**
3864 * drm_dp_pcon_hdmi_frl_link_error_count() - print the error count per lane
3865 * during link failure between PCON and HDMI sink
3866 * @aux: DisplayPort AUX channel
3867 * @connector: DRM connector
3868 * code.
3869 **/
3870
3871void drm_dp_pcon_hdmi_frl_link_error_count(struct drm_dp_aux *aux,
3872 struct drm_connector *connector)
3873{
3874 u8 buf, error_count;
3875 int i, num_error;
3876 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3877
3878 for (i = 0; i < hdmi->max_lanes; i++) {
3879 if (drm_dp_dpcd_read_byte(aux, DP_PCON_HDMI_ERROR_STATUS_LN0 + i, valuep: &buf) < 0)
3880 return;
3881
3882 error_count = buf & DP_PCON_HDMI_ERROR_COUNT_MASK;
3883 switch (error_count) {
3884 case DP_PCON_HDMI_ERROR_COUNT_HUNDRED_PLUS:
3885 num_error = 100;
3886 break;
3887 case DP_PCON_HDMI_ERROR_COUNT_TEN_PLUS:
3888 num_error = 10;
3889 break;
3890 case DP_PCON_HDMI_ERROR_COUNT_THREE_PLUS:
3891 num_error = 3;
3892 break;
3893 default:
3894 num_error = 0;
3895 }
3896
3897 drm_err(aux->drm_dev, "%s: More than %d errors since the last read for lane %d",
3898 aux->name, num_error, i);
3899 }
3900}
3901EXPORT_SYMBOL(drm_dp_pcon_hdmi_frl_link_error_count);
3902
3903/*
3904 * drm_dp_pcon_enc_is_dsc_1_2 - Does PCON Encoder supports DSC 1.2
3905 * @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder
3906 *
3907 * Returns true is PCON encoder is DSC 1.2 else returns false.
3908 */
3909bool drm_dp_pcon_enc_is_dsc_1_2(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE])
3910{
3911 u8 buf;
3912 u8 major_v, minor_v;
3913
3914 buf = pcon_dsc_dpcd[DP_PCON_DSC_VERSION - DP_PCON_DSC_ENCODER];
3915 major_v = (buf & DP_PCON_DSC_MAJOR_MASK) >> DP_PCON_DSC_MAJOR_SHIFT;
3916 minor_v = (buf & DP_PCON_DSC_MINOR_MASK) >> DP_PCON_DSC_MINOR_SHIFT;
3917
3918 if (major_v == 1 && minor_v == 2)
3919 return true;
3920
3921 return false;
3922}
3923EXPORT_SYMBOL(drm_dp_pcon_enc_is_dsc_1_2);
3924
3925/*
3926 * drm_dp_pcon_dsc_max_slices - Get max slices supported by PCON DSC Encoder
3927 * @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder
3928 *
3929 * Returns maximum no. of slices supported by the PCON DSC Encoder.
3930 */
3931int drm_dp_pcon_dsc_max_slices(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE])
3932{
3933 u8 slice_cap1, slice_cap2;
3934
3935 slice_cap1 = pcon_dsc_dpcd[DP_PCON_DSC_SLICE_CAP_1 - DP_PCON_DSC_ENCODER];
3936 slice_cap2 = pcon_dsc_dpcd[DP_PCON_DSC_SLICE_CAP_2 - DP_PCON_DSC_ENCODER];
3937
3938 if (slice_cap2 & DP_PCON_DSC_24_PER_DSC_ENC)
3939 return 24;
3940 if (slice_cap2 & DP_PCON_DSC_20_PER_DSC_ENC)
3941 return 20;
3942 if (slice_cap2 & DP_PCON_DSC_16_PER_DSC_ENC)
3943 return 16;
3944 if (slice_cap1 & DP_PCON_DSC_12_PER_DSC_ENC)
3945 return 12;
3946 if (slice_cap1 & DP_PCON_DSC_10_PER_DSC_ENC)
3947 return 10;
3948 if (slice_cap1 & DP_PCON_DSC_8_PER_DSC_ENC)
3949 return 8;
3950 if (slice_cap1 & DP_PCON_DSC_6_PER_DSC_ENC)
3951 return 6;
3952 if (slice_cap1 & DP_PCON_DSC_4_PER_DSC_ENC)
3953 return 4;
3954 if (slice_cap1 & DP_PCON_DSC_2_PER_DSC_ENC)
3955 return 2;
3956 if (slice_cap1 & DP_PCON_DSC_1_PER_DSC_ENC)
3957 return 1;
3958
3959 return 0;
3960}
3961EXPORT_SYMBOL(drm_dp_pcon_dsc_max_slices);
3962
3963/*
3964 * drm_dp_pcon_dsc_max_slice_width() - Get max slice width for Pcon DSC encoder
3965 * @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder
3966 *
3967 * Returns maximum width of the slices in pixel width i.e. no. of pixels x 320.
3968 */
3969int drm_dp_pcon_dsc_max_slice_width(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE])
3970{
3971 u8 buf;
3972
3973 buf = pcon_dsc_dpcd[DP_PCON_DSC_MAX_SLICE_WIDTH - DP_PCON_DSC_ENCODER];
3974
3975 return buf * DP_DSC_SLICE_WIDTH_MULTIPLIER;
3976}
3977EXPORT_SYMBOL(drm_dp_pcon_dsc_max_slice_width);
3978
3979/*
3980 * drm_dp_pcon_dsc_bpp_incr() - Get bits per pixel increment for PCON DSC encoder
3981 * @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder
3982 *
3983 * Returns the bpp precision supported by the PCON encoder.
3984 */
3985int drm_dp_pcon_dsc_bpp_incr(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE])
3986{
3987 u8 buf;
3988
3989 buf = pcon_dsc_dpcd[DP_PCON_DSC_BPP_INCR - DP_PCON_DSC_ENCODER];
3990
3991 switch (buf & DP_PCON_DSC_BPP_INCR_MASK) {
3992 case DP_PCON_DSC_ONE_16TH_BPP:
3993 return 16;
3994 case DP_PCON_DSC_ONE_8TH_BPP:
3995 return 8;
3996 case DP_PCON_DSC_ONE_4TH_BPP:
3997 return 4;
3998 case DP_PCON_DSC_ONE_HALF_BPP:
3999 return 2;
4000 case DP_PCON_DSC_ONE_BPP:
4001 return 1;
4002 }
4003
4004 return 0;
4005}
4006EXPORT_SYMBOL(drm_dp_pcon_dsc_bpp_incr);
4007
4008static
4009int drm_dp_pcon_configure_dsc_enc(struct drm_dp_aux *aux, u8 pps_buf_config)
4010{
4011 u8 buf;
4012 int ret;
4013
4014 ret = drm_dp_dpcd_read_byte(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, valuep: &buf);
4015 if (ret < 0)
4016 return ret;
4017
4018 buf |= DP_PCON_ENABLE_DSC_ENCODER;
4019
4020 if (pps_buf_config <= DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER) {
4021 buf &= ~DP_PCON_ENCODER_PPS_OVERRIDE_MASK;
4022 buf |= pps_buf_config << 2;
4023 }
4024
4025 return drm_dp_dpcd_write_byte(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, value: buf);
4026}
4027
4028/**
4029 * drm_dp_pcon_pps_default() - Let PCON fill the default pps parameters
4030 * for DSC1.2 between PCON & HDMI2.1 sink
4031 * @aux: DisplayPort AUX channel
4032 *
4033 * Returns 0 on success, else returns negative error code.
4034 */
4035int drm_dp_pcon_pps_default(struct drm_dp_aux *aux)
4036{
4037 return drm_dp_pcon_configure_dsc_enc(aux, DP_PCON_ENC_PPS_OVERRIDE_DISABLED);
4038}
4039EXPORT_SYMBOL(drm_dp_pcon_pps_default);
4040
4041/**
4042 * drm_dp_pcon_pps_override_buf() - Configure PPS encoder override buffer for
4043 * HDMI sink
4044 * @aux: DisplayPort AUX channel
4045 * @pps_buf: 128 bytes to be written into PPS buffer for HDMI sink by PCON.
4046 *
4047 * Returns 0 on success, else returns negative error code.
4048 */
4049int drm_dp_pcon_pps_override_buf(struct drm_dp_aux *aux, u8 pps_buf[128])
4050{
4051 int ret;
4052
4053 ret = drm_dp_dpcd_write_data(aux, DP_PCON_HDMI_PPS_OVERRIDE_BASE, buffer: &pps_buf, size: 128);
4054 if (ret < 0)
4055 return ret;
4056
4057 return drm_dp_pcon_configure_dsc_enc(aux, DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER);
4058}
4059EXPORT_SYMBOL(drm_dp_pcon_pps_override_buf);
4060
4061/*
4062 * drm_dp_pcon_pps_override_param() - Write PPS parameters to DSC encoder
4063 * override registers
4064 * @aux: DisplayPort AUX channel
4065 * @pps_param: 3 Parameters (2 Bytes each) : Slice Width, Slice Height,
4066 * bits_per_pixel.
4067 *
4068 * Returns 0 on success, else returns negative error code.
4069 */
4070int drm_dp_pcon_pps_override_param(struct drm_dp_aux *aux, u8 pps_param[6])
4071{
4072 int ret;
4073
4074 ret = drm_dp_dpcd_write_data(aux, DP_PCON_HDMI_PPS_OVRD_SLICE_HEIGHT, buffer: &pps_param[0], size: 2);
4075 if (ret < 0)
4076 return ret;
4077 ret = drm_dp_dpcd_write_data(aux, DP_PCON_HDMI_PPS_OVRD_SLICE_WIDTH, buffer: &pps_param[2], size: 2);
4078 if (ret < 0)
4079 return ret;
4080 ret = drm_dp_dpcd_write_data(aux, DP_PCON_HDMI_PPS_OVRD_BPP, buffer: &pps_param[4], size: 2);
4081 if (ret < 0)
4082 return ret;
4083
4084 return drm_dp_pcon_configure_dsc_enc(aux, DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER);
4085}
4086EXPORT_SYMBOL(drm_dp_pcon_pps_override_param);
4087
4088/*
4089 * drm_dp_pcon_convert_rgb_to_ycbcr() - Configure the PCon to convert RGB to Ycbcr
4090 * @aux: displayPort AUX channel
4091 * @color_spc: Color-space/s for which conversion is to be enabled, 0 for disable.
4092 *
4093 * Returns 0 on success, else returns negative error code.
4094 */
4095int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc)
4096{
4097 int ret;
4098 u8 buf;
4099
4100 ret = drm_dp_dpcd_read_byte(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, valuep: &buf);
4101 if (ret < 0)
4102 return ret;
4103
4104 if (color_spc & DP_CONVERSION_RGB_YCBCR_MASK)
4105 buf |= (color_spc & DP_CONVERSION_RGB_YCBCR_MASK);
4106 else
4107 buf &= ~DP_CONVERSION_RGB_YCBCR_MASK;
4108
4109 return drm_dp_dpcd_write_byte(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, value: buf);
4110}
4111EXPORT_SYMBOL(drm_dp_pcon_convert_rgb_to_ycbcr);
4112
4113/**
4114 * drm_edp_backlight_set_level() - Set the backlight level of an eDP panel via AUX
4115 * @aux: The DP AUX channel to use
4116 * @bl: Backlight capability info from drm_edp_backlight_init()
4117 * @level: The brightness level to set
4118 *
4119 * Sets the brightness level of an eDP panel's backlight. Note that the panel's backlight must
4120 * already have been enabled by the driver by calling drm_edp_backlight_enable().
4121 *
4122 * Returns: %0 on success, negative error code on failure
4123 */
4124int drm_edp_backlight_set_level(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
4125 u32 level)
4126{
4127 int ret;
4128 unsigned int offset = DP_EDP_BACKLIGHT_BRIGHTNESS_MSB;
4129 u8 buf[3] = { 0 };
4130 size_t len = 2;
4131
4132 /* The panel uses the PWM for controlling brightness levels */
4133 if (!(bl->aux_set || bl->luminance_set))
4134 return 0;
4135
4136 if (bl->luminance_set) {
4137 level = level * 1000;
4138 level &= 0xffffff;
4139 buf[0] = (level & 0x0000ff);
4140 buf[1] = (level & 0x00ff00) >> 8;
4141 buf[2] = (level & 0xff0000) >> 16;
4142 offset = DP_EDP_PANEL_TARGET_LUMINANCE_VALUE;
4143 len = 3;
4144 } else if (bl->lsb_reg_used) {
4145 buf[0] = (level & 0xff00) >> 8;
4146 buf[1] = (level & 0x00ff);
4147 } else {
4148 buf[0] = level;
4149 }
4150
4151 ret = drm_dp_dpcd_write_data(aux, offset, buffer: buf, size: len);
4152 if (ret < 0) {
4153 drm_err(aux->drm_dev,
4154 "%s: Failed to write aux backlight level: %d\n",
4155 aux->name, ret);
4156 return ret;
4157 }
4158
4159 return 0;
4160}
4161EXPORT_SYMBOL(drm_edp_backlight_set_level);
4162
4163static int
4164drm_edp_backlight_set_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
4165 bool enable)
4166{
4167 int ret;
4168 u8 buf;
4169
4170 /* This panel uses the EDP_BL_PWR GPIO for enablement */
4171 if (!bl->aux_enable)
4172 return 0;
4173
4174 ret = drm_dp_dpcd_read_byte(aux, DP_EDP_DISPLAY_CONTROL_REGISTER, valuep: &buf);
4175 if (ret < 0) {
4176 drm_err(aux->drm_dev, "%s: Failed to read eDP display control register: %d\n",
4177 aux->name, ret);
4178 return ret;
4179 }
4180 if (enable)
4181 buf |= DP_EDP_BACKLIGHT_ENABLE;
4182 else
4183 buf &= ~DP_EDP_BACKLIGHT_ENABLE;
4184
4185 ret = drm_dp_dpcd_write_byte(aux, DP_EDP_DISPLAY_CONTROL_REGISTER, value: buf);
4186 if (ret < 0) {
4187 drm_err(aux->drm_dev, "%s: Failed to write eDP display control register: %d\n",
4188 aux->name, ret);
4189 return ret;
4190 }
4191
4192 return 0;
4193}
4194
4195/**
4196 * drm_edp_backlight_enable() - Enable an eDP panel's backlight using DPCD
4197 * @aux: The DP AUX channel to use
4198 * @bl: Backlight capability info from drm_edp_backlight_init()
4199 * @level: The initial backlight level to set via AUX, if there is one
4200 *
4201 * This function handles enabling DPCD backlight controls on a panel over DPCD, while additionally
4202 * restoring any important backlight state such as the given backlight level, the brightness byte
4203 * count, backlight frequency, etc.
4204 *
4205 * Note that certain panels do not support being enabled or disabled via DPCD, but instead require
4206 * that the driver handle enabling/disabling the panel through implementation-specific means using
4207 * the EDP_BL_PWR GPIO. For such panels, &drm_edp_backlight_info.aux_enable will be set to %false,
4208 * this function becomes a no-op, and the driver is expected to handle powering the panel on using
4209 * the EDP_BL_PWR GPIO.
4210 *
4211 * Returns: %0 on success, negative error code on failure.
4212 */
4213int drm_edp_backlight_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
4214 const u32 level)
4215{
4216 int ret;
4217 u8 dpcd_buf;
4218
4219 if (bl->aux_set)
4220 dpcd_buf = DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD;
4221 else
4222 dpcd_buf = DP_EDP_BACKLIGHT_CONTROL_MODE_PWM;
4223
4224 if (bl->luminance_set)
4225 dpcd_buf |= DP_EDP_PANEL_LUMINANCE_CONTROL_ENABLE;
4226
4227 if (bl->pwmgen_bit_count) {
4228 ret = drm_dp_dpcd_write_byte(aux, DP_EDP_PWMGEN_BIT_COUNT, value: bl->pwmgen_bit_count);
4229 if (ret < 0)
4230 drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux pwmgen bit count: %d\n",
4231 aux->name, ret);
4232 }
4233
4234 if (bl->pwm_freq_pre_divider) {
4235 ret = drm_dp_dpcd_write_byte(aux, DP_EDP_BACKLIGHT_FREQ_SET,
4236 value: bl->pwm_freq_pre_divider);
4237 if (ret < 0)
4238 drm_dbg_kms(aux->drm_dev,
4239 "%s: Failed to write aux backlight frequency: %d\n",
4240 aux->name, ret);
4241 else
4242 dpcd_buf |= DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE;
4243 }
4244
4245 ret = drm_dp_dpcd_write_byte(aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, value: dpcd_buf);
4246 if (ret < 0) {
4247 drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux backlight mode: %d\n",
4248 aux->name, ret);
4249 return ret < 0 ? ret : -EIO;
4250 }
4251
4252 ret = drm_edp_backlight_set_level(aux, bl, level);
4253 if (ret < 0)
4254 return ret;
4255 ret = drm_edp_backlight_set_enable(aux, bl, enable: true);
4256 if (ret < 0)
4257 return ret;
4258
4259 return 0;
4260}
4261EXPORT_SYMBOL(drm_edp_backlight_enable);
4262
4263/**
4264 * drm_edp_backlight_disable() - Disable an eDP backlight using DPCD, if supported
4265 * @aux: The DP AUX channel to use
4266 * @bl: Backlight capability info from drm_edp_backlight_init()
4267 *
4268 * This function handles disabling DPCD backlight controls on a panel over AUX.
4269 *
4270 * Note that certain panels do not support being enabled or disabled via DPCD, but instead require
4271 * that the driver handle enabling/disabling the panel through implementation-specific means using
4272 * the EDP_BL_PWR GPIO. For such panels, &drm_edp_backlight_info.aux_enable will be set to %false,
4273 * this function becomes a no-op, and the driver is expected to handle powering the panel off using
4274 * the EDP_BL_PWR GPIO.
4275 *
4276 * Returns: %0 on success or no-op, negative error code on failure.
4277 */
4278int drm_edp_backlight_disable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl)
4279{
4280 int ret;
4281
4282 ret = drm_edp_backlight_set_enable(aux, bl, enable: false);
4283 if (ret < 0)
4284 return ret;
4285
4286 return 0;
4287}
4288EXPORT_SYMBOL(drm_edp_backlight_disable);
4289
4290static inline int
4291drm_edp_backlight_probe_max(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
4292 u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE])
4293{
4294 int fxp, fxp_min, fxp_max, fxp_actual, f = 1;
4295 int ret;
4296 u8 pn, pn_min, pn_max, bit_count;
4297
4298 if (!bl->aux_set)
4299 return 0;
4300
4301 ret = drm_dp_dpcd_read_byte(aux, DP_EDP_PWMGEN_BIT_COUNT, valuep: &bit_count);
4302 if (ret < 0) {
4303 drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap: %d\n",
4304 aux->name, ret);
4305 return -ENODEV;
4306 }
4307
4308 bit_count &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
4309
4310 ret = drm_dp_dpcd_read_byte(aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN, valuep: &pn_min);
4311 if (ret < 0) {
4312 drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap min: %d\n",
4313 aux->name, ret);
4314 return -ENODEV;
4315 }
4316 pn_min &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
4317
4318 ret = drm_dp_dpcd_read_byte(aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX, valuep: &pn_max);
4319 if (ret < 0) {
4320 drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap max: %d\n",
4321 aux->name, ret);
4322 return -ENODEV;
4323 }
4324 pn_max &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
4325
4326 if (unlikely(pn_min > pn_max)) {
4327 drm_dbg_kms(aux->drm_dev, "%s: Invalid pwmgen bit count cap min/max returned: %d %d\n",
4328 aux->name, pn_min, pn_max);
4329 return -EINVAL;
4330 }
4331
4332 /*
4333 * Per VESA eDP Spec v1.4b, section 3.3.10.2:
4334 * If DP_EDP_PWMGEN_BIT_COUNT is less than DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN,
4335 * the sink must use the MIN value as the effective PWM bit count.
4336 * Clamp the reported value to the [MIN, MAX] capability range to ensure
4337 * correct brightness scaling on compliant eDP panels.
4338 * Only enable this logic if the [MIN, MAX] range is valid in regard to Spec.
4339 */
4340 pn = bit_count;
4341 if (bit_count < pn_min)
4342 pn = clamp(bit_count, pn_min, pn_max);
4343
4344 bl->max = (1 << pn) - 1;
4345 if (!driver_pwm_freq_hz) {
4346 if (pn != bit_count)
4347 goto bit_count_write_back;
4348
4349 return 0;
4350 }
4351
4352 /*
4353 * Set PWM Frequency divider to match desired frequency provided by the driver.
4354 * The PWM Frequency is calculated as 27Mhz / (F x P).
4355 * - Where F = PWM Frequency Pre-Divider value programmed by field 7:0 of the
4356 * EDP_BACKLIGHT_FREQ_SET register (DPCD Address 00728h)
4357 * - Where P = 2^Pn, where Pn is the value programmed by field 4:0 of the
4358 * EDP_PWMGEN_BIT_COUNT register (DPCD Address 00724h)
4359 */
4360
4361 /* Find desired value of (F x P)
4362 * Note that, if F x P is out of supported range, the maximum value or minimum value will
4363 * applied automatically. So no need to check that.
4364 */
4365 fxp = DIV_ROUND_CLOSEST(1000 * DP_EDP_BACKLIGHT_FREQ_BASE_KHZ, driver_pwm_freq_hz);
4366
4367 /* Use highest possible value of Pn for more granularity of brightness adjustment while
4368 * satisfying the conditions below.
4369 * - Pn is in the range of Pn_min and Pn_max
4370 * - F is in the range of 1 and 255
4371 * - FxP is within 25% of desired value.
4372 * Note: 25% is arbitrary value and may need some tweak.
4373 */
4374 /* Ensure frequency is within 25% of desired value */
4375 fxp_min = DIV_ROUND_CLOSEST(fxp * 3, 4);
4376 fxp_max = DIV_ROUND_CLOSEST(fxp * 5, 4);
4377 if (fxp_min < (1 << pn_min) || (255 << pn_max) < fxp_max) {
4378 drm_dbg_kms(aux->drm_dev,
4379 "%s: Driver defined backlight frequency (%d) out of range\n",
4380 aux->name, driver_pwm_freq_hz);
4381 return 0;
4382 }
4383
4384 for (pn = pn_max; pn >= pn_min; pn--) {
4385 f = clamp(DIV_ROUND_CLOSEST(fxp, 1 << pn), 1, 255);
4386 fxp_actual = f << pn;
4387 if (fxp_min <= fxp_actual && fxp_actual <= fxp_max)
4388 break;
4389 }
4390
4391bit_count_write_back:
4392 ret = drm_dp_dpcd_write_byte(aux, DP_EDP_PWMGEN_BIT_COUNT, value: pn);
4393 if (ret < 0) {
4394 drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux pwmgen bit count: %d\n",
4395 aux->name, ret);
4396 return 0;
4397 }
4398
4399 if (!driver_pwm_freq_hz)
4400 return 0;
4401
4402 bl->pwmgen_bit_count = pn;
4403 bl->max = (1 << pn) - 1;
4404
4405 if (edp_dpcd[2] & DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP) {
4406 bl->pwm_freq_pre_divider = f;
4407 drm_dbg_kms(aux->drm_dev, "%s: Using backlight frequency from driver (%dHz)\n",
4408 aux->name, driver_pwm_freq_hz);
4409 }
4410
4411 return 0;
4412}
4413
4414static inline int
4415drm_edp_backlight_probe_state(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
4416 u8 *current_mode)
4417{
4418 int ret;
4419 u8 buf[3];
4420 u8 mode_reg;
4421
4422 ret = drm_dp_dpcd_read_byte(aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, valuep: &mode_reg);
4423 if (ret < 0) {
4424 drm_dbg_kms(aux->drm_dev, "%s: Failed to read backlight mode: %d\n",
4425 aux->name, ret);
4426 return ret < 0 ? ret : -EIO;
4427 }
4428
4429 *current_mode = (mode_reg & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK);
4430 if (!bl->aux_set)
4431 return 0;
4432
4433 if (*current_mode == DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD) {
4434 int size = 1 + bl->lsb_reg_used;
4435
4436 if (bl->luminance_set) {
4437 ret = drm_dp_dpcd_read_data(aux, DP_EDP_PANEL_TARGET_LUMINANCE_VALUE,
4438 buffer: buf, size: sizeof(buf));
4439 if (ret < 0) {
4440 drm_dbg_kms(aux->drm_dev,
4441 "%s: Failed to read backlight level: %d\n",
4442 aux->name, ret);
4443 return ret;
4444 }
4445
4446 /*
4447 * Incase luminance is set we want to send the value back in nits but
4448 * since DP_EDP_PANEL_TARGET_LUMINANCE stores values in millinits we
4449 * need to divide by 1000.
4450 */
4451 return (buf[0] | buf[1] << 8 | buf[2] << 16) / 1000;
4452 } else {
4453 ret = drm_dp_dpcd_read_data(aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB,
4454 buffer: buf, size);
4455 if (ret < 0) {
4456 drm_dbg_kms(aux->drm_dev,
4457 "%s: Failed to read backlight level: %d\n",
4458 aux->name, ret);
4459 return ret;
4460 }
4461
4462 if (bl->lsb_reg_used)
4463 return (buf[0] << 8) | buf[1];
4464 else
4465 return buf[0];
4466 }
4467 }
4468
4469 /*
4470 * If we're not in DPCD control mode yet, the programmed brightness value is meaningless and
4471 * the driver should assume max brightness
4472 */
4473 return bl->max;
4474}
4475
4476/**
4477 * drm_edp_backlight_init() - Probe a display panel's TCON using the standard VESA eDP backlight
4478 * interface.
4479 * @aux: The DP aux device to use for probing
4480 * @bl: The &drm_edp_backlight_info struct to fill out with information on the backlight
4481 * @max_luminance: max luminance when need luminance is set as true
4482 * @driver_pwm_freq_hz: Optional PWM frequency from the driver in hz
4483 * @edp_dpcd: A cached copy of the eDP DPCD
4484 * @current_level: Where to store the probed brightness level, if any
4485 * @current_mode: Where to store the currently set backlight control mode
4486 * @need_luminance: Tells us if a we want to manipulate backlight using luminance values
4487 *
4488 * Initializes a &drm_edp_backlight_info struct by probing @aux for it's backlight capabilities,
4489 * along with also probing the current and maximum supported brightness levels.
4490 *
4491 * If @driver_pwm_freq_hz is non-zero, this will be used as the backlight frequency. Otherwise, the
4492 * default frequency from the panel is used.
4493 *
4494 * Returns: %0 on success, negative error code on failure.
4495 */
4496int
4497drm_edp_backlight_init(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
4498 u32 max_luminance,
4499 u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE],
4500 u32 *current_level, u8 *current_mode, bool need_luminance)
4501{
4502 int ret;
4503
4504 if (edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP)
4505 bl->aux_enable = true;
4506 if (edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP)
4507 bl->aux_set = true;
4508 if (edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT)
4509 bl->lsb_reg_used = true;
4510 if ((edp_dpcd[0] & DP_EDP_15) && edp_dpcd[3] &
4511 (DP_EDP_PANEL_LUMINANCE_CONTROL_CAPABLE) && need_luminance)
4512 bl->luminance_set = true;
4513
4514 /* Sanity check caps */
4515 if (!bl->aux_set && !(edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP) &&
4516 !bl->luminance_set) {
4517 drm_dbg_kms(aux->drm_dev,
4518 "%s: Panel does not support AUX, PWM or luminance-based brightness control. Aborting\n",
4519 aux->name);
4520 return -EINVAL;
4521 }
4522
4523 if (bl->luminance_set) {
4524 bl->max = max_luminance;
4525 } else {
4526 ret = drm_edp_backlight_probe_max(aux, bl, driver_pwm_freq_hz, edp_dpcd);
4527 if (ret < 0)
4528 return ret;
4529 }
4530
4531 ret = drm_edp_backlight_probe_state(aux, bl, current_mode);
4532 if (ret < 0)
4533 return ret;
4534 *current_level = ret;
4535
4536 drm_dbg_kms(aux->drm_dev,
4537 "%s: Found backlight: aux_set=%d aux_enable=%d mode=%d\n",
4538 aux->name, bl->aux_set, bl->aux_enable, *current_mode);
4539 if (bl->aux_set) {
4540 drm_dbg_kms(aux->drm_dev,
4541 "%s: Backlight caps: level=%d/%d pwm_freq_pre_divider=%d lsb_reg_used=%d\n",
4542 aux->name, *current_level, bl->max, bl->pwm_freq_pre_divider,
4543 bl->lsb_reg_used);
4544 }
4545
4546 return 0;
4547}
4548EXPORT_SYMBOL(drm_edp_backlight_init);
4549
4550#if IS_BUILTIN(CONFIG_BACKLIGHT_CLASS_DEVICE) || \
4551 (IS_MODULE(CONFIG_DRM_KMS_HELPER) && IS_MODULE(CONFIG_BACKLIGHT_CLASS_DEVICE))
4552
4553static int dp_aux_backlight_update_status(struct backlight_device *bd)
4554{
4555 struct dp_aux_backlight *bl = bl_get_data(bl_dev: bd);
4556 u16 brightness = backlight_get_brightness(bd);
4557 int ret = 0;
4558
4559 if (!backlight_is_blank(bd)) {
4560 if (!bl->enabled) {
4561 drm_edp_backlight_enable(bl->aux, &bl->info, brightness);
4562 bl->enabled = true;
4563 return 0;
4564 }
4565 ret = drm_edp_backlight_set_level(bl->aux, &bl->info, brightness);
4566 } else {
4567 if (bl->enabled) {
4568 drm_edp_backlight_disable(bl->aux, &bl->info);
4569 bl->enabled = false;
4570 }
4571 }
4572
4573 return ret;
4574}
4575
4576static const struct backlight_ops dp_aux_bl_ops = {
4577 .update_status = dp_aux_backlight_update_status,
4578};
4579
4580/**
4581 * drm_panel_dp_aux_backlight - create and use DP AUX backlight
4582 * @panel: DRM panel
4583 * @aux: The DP AUX channel to use
4584 *
4585 * Use this function to create and handle backlight if your panel
4586 * supports backlight control over DP AUX channel using DPCD
4587 * registers as per VESA's standard backlight control interface.
4588 *
4589 * When the panel is enabled backlight will be enabled after a
4590 * successful call to &drm_panel_funcs.enable()
4591 *
4592 * When the panel is disabled backlight will be disabled before the
4593 * call to &drm_panel_funcs.disable().
4594 *
4595 * A typical implementation for a panel driver supporting backlight
4596 * control over DP AUX will call this function at probe time.
4597 * Backlight will then be handled transparently without requiring
4598 * any intervention from the driver.
4599 *
4600 * drm_panel_dp_aux_backlight() must be called after the call to drm_panel_init().
4601 *
4602 * Return: 0 on success or a negative error code on failure.
4603 */
4604int drm_panel_dp_aux_backlight(struct drm_panel *panel, struct drm_dp_aux *aux)
4605{
4606 struct dp_aux_backlight *bl;
4607 struct backlight_properties props = { 0 };
4608 u32 current_level;
4609 u8 current_mode;
4610 u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
4611 int ret;
4612
4613 if (!panel || !panel->dev || !aux)
4614 return -EINVAL;
4615
4616 ret = drm_dp_dpcd_read_data(aux, DP_EDP_DPCD_REV, buffer: edp_dpcd,
4617 EDP_DISPLAY_CTL_CAP_SIZE);
4618 if (ret < 0)
4619 return ret;
4620
4621 if (!drm_edp_backlight_supported(edp_dpcd)) {
4622 DRM_DEV_INFO(panel->dev, "DP AUX backlight is not supported\n");
4623 return 0;
4624 }
4625
4626 bl = devm_kzalloc(dev: panel->dev, size: sizeof(*bl), GFP_KERNEL);
4627 if (!bl)
4628 return -ENOMEM;
4629
4630 bl->aux = aux;
4631
4632 ret = drm_edp_backlight_init(aux, &bl->info, 0, 0, edp_dpcd,
4633 &current_level, &current_mode, false);
4634 if (ret < 0)
4635 return ret;
4636
4637 props.type = BACKLIGHT_RAW;
4638 props.brightness = current_level;
4639 props.max_brightness = bl->info.max;
4640
4641 bl->base = devm_backlight_device_register(dev: panel->dev, name: "dp_aux_backlight",
4642 parent: panel->dev, devdata: bl,
4643 ops: &dp_aux_bl_ops, props: &props);
4644 if (IS_ERR(ptr: bl->base))
4645 return PTR_ERR(ptr: bl->base);
4646
4647 backlight_disable(bd: bl->base);
4648
4649 panel->backlight = bl->base;
4650
4651 return 0;
4652}
4653EXPORT_SYMBOL(drm_panel_dp_aux_backlight);
4654
4655#endif
4656
4657/* See DP Standard v2.1 2.6.4.4.1.1, 2.8.4.4, 2.8.7 */
4658static int drm_dp_link_data_symbol_cycles(int lane_count, int pixels,
4659 int bpp_x16, int symbol_size,
4660 bool is_mst)
4661{
4662 int cycles = DIV_ROUND_UP(pixels * bpp_x16, 16 * symbol_size * lane_count);
4663 int align = is_mst ? 4 / lane_count : 1;
4664
4665 return ALIGN(cycles, align);
4666}
4667
4668/**
4669 * drm_dp_link_symbol_cycles - calculate the link symbol count with/without dsc
4670 * @lane_count: DP link lane count
4671 * @pixels: number of pixels in a scanline
4672 * @dsc_slice_count: number of slices for DSC or '0' for non-DSC
4673 * @bpp_x16: bits per pixel in .4 binary fixed format
4674 * @symbol_size: DP symbol size
4675 * @is_mst: %true for MST and %false for SST
4676 *
4677 * Calculate the link symbol cycles for both DSC (@dsc_slice_count !=0) and
4678 * non-DSC case (@dsc_slice_count == 0) and return the count.
4679 */
4680int drm_dp_link_symbol_cycles(int lane_count, int pixels, int dsc_slice_count,
4681 int bpp_x16, int symbol_size, bool is_mst)
4682{
4683 int slice_count = dsc_slice_count ? : 1;
4684 int slice_pixels = DIV_ROUND_UP(pixels, slice_count);
4685 int slice_data_cycles = drm_dp_link_data_symbol_cycles(lane_count,
4686 pixels: slice_pixels,
4687 bpp_x16,
4688 symbol_size,
4689 is_mst);
4690 int slice_eoc_cycles = 0;
4691
4692 if (dsc_slice_count)
4693 slice_eoc_cycles = is_mst ? 4 / lane_count : 1;
4694
4695 return slice_count * (slice_data_cycles + slice_eoc_cycles);
4696}
4697EXPORT_SYMBOL(drm_dp_link_symbol_cycles);
4698
4699/**
4700 * drm_dp_bw_overhead - Calculate the BW overhead of a DP link stream
4701 * @lane_count: DP link lane count
4702 * @hactive: pixel count of the active period in one scanline of the stream
4703 * @dsc_slice_count: number of slices for DSC or '0' for non-DSC
4704 * @bpp_x16: bits per pixel in .4 binary fixed point
4705 * @flags: DRM_DP_OVERHEAD_x flags
4706 *
4707 * Calculate the BW allocation overhead of a DP link stream, depending
4708 * on the link's
4709 * - @lane_count
4710 * - SST/MST mode (@flags / %DRM_DP_OVERHEAD_MST)
4711 * - symbol size (@flags / %DRM_DP_OVERHEAD_UHBR)
4712 * - FEC mode (@flags / %DRM_DP_OVERHEAD_FEC)
4713 * - SSC/REF_CLK mode (@flags / %DRM_DP_OVERHEAD_SSC_REF_CLK)
4714 * as well as the stream's
4715 * - @hactive timing
4716 * - @bpp_x16 color depth
4717 * - compression mode (@dsc_slice_count != 0)
4718 * Note that this overhead doesn't account for the 8b/10b, 128b/132b
4719 * channel coding efficiency, for that see
4720 * @drm_dp_link_bw_channel_coding_efficiency().
4721 *
4722 * Returns the overhead as 100% + overhead% in 1ppm units.
4723 */
4724int drm_dp_bw_overhead(int lane_count, int hactive,
4725 int dsc_slice_count,
4726 int bpp_x16, unsigned long flags)
4727{
4728 int symbol_size = flags & DRM_DP_BW_OVERHEAD_UHBR ? 32 : 8;
4729 bool is_mst = flags & DRM_DP_BW_OVERHEAD_MST;
4730 u32 overhead = 1000000;
4731 int symbol_cycles;
4732
4733 if (lane_count == 0 || hactive == 0 || bpp_x16 == 0) {
4734 DRM_DEBUG_KMS("Invalid BW overhead params: lane_count %d, hactive %d, bpp_x16 " FXP_Q4_FMT "\n",
4735 lane_count, hactive,
4736 FXP_Q4_ARGS(bpp_x16));
4737 return 0;
4738 }
4739
4740 /*
4741 * DP Standard v2.1 2.6.4.1
4742 * SSC downspread and ref clock variation margin:
4743 * 5300ppm + 300ppm ~ 0.6%
4744 */
4745 if (flags & DRM_DP_BW_OVERHEAD_SSC_REF_CLK)
4746 overhead += 6000;
4747
4748 /*
4749 * DP Standard v2.1 2.6.4.1.1, 3.5.1.5.4:
4750 * FEC symbol insertions for 8b/10b channel coding:
4751 * After each 250 data symbols on 2-4 lanes:
4752 * 250 LL + 5 FEC_PARITY_PH + 1 CD_ADJ (256 byte FEC block)
4753 * After each 2 x 250 data symbols on 1 lane:
4754 * 2 * 250 LL + 11 FEC_PARITY_PH + 1 CD_ADJ (512 byte FEC block)
4755 * After 256 (2-4 lanes) or 128 (1 lane) FEC blocks:
4756 * 256 * 256 bytes + 1 FEC_PM
4757 * or
4758 * 128 * 512 bytes + 1 FEC_PM
4759 * (256 * 6 + 1) / (256 * 250) = 2.4015625 %
4760 */
4761 if (flags & DRM_DP_BW_OVERHEAD_FEC)
4762 overhead += 24016;
4763
4764 /*
4765 * DP Standard v2.1 2.7.9, 5.9.7
4766 * The FEC overhead for UHBR is accounted for in its 96.71% channel
4767 * coding efficiency.
4768 */
4769 WARN_ON((flags & DRM_DP_BW_OVERHEAD_UHBR) &&
4770 (flags & DRM_DP_BW_OVERHEAD_FEC));
4771
4772 symbol_cycles = drm_dp_link_symbol_cycles(lane_count, hactive,
4773 dsc_slice_count,
4774 bpp_x16, symbol_size,
4775 is_mst);
4776
4777 return DIV_ROUND_UP_ULL(mul_u32_u32(symbol_cycles * symbol_size * lane_count,
4778 overhead * 16),
4779 hactive * bpp_x16);
4780}
4781EXPORT_SYMBOL(drm_dp_bw_overhead);
4782
4783/**
4784 * drm_dp_bw_channel_coding_efficiency - Get a DP link's channel coding efficiency
4785 * @is_uhbr: Whether the link has a 128b/132b channel coding
4786 *
4787 * Return the channel coding efficiency of the given DP link type, which is
4788 * either 8b/10b or 128b/132b (aka UHBR). The corresponding overhead includes
4789 * the 8b -> 10b, 128b -> 132b pixel data to link symbol conversion overhead
4790 * and for 128b/132b any link or PHY level control symbol insertion overhead
4791 * (LLCP, FEC, PHY sync, see DP Standard v2.1 3.5.2.18). For 8b/10b the
4792 * corresponding FEC overhead is BW allocation specific, included in the value
4793 * returned by drm_dp_bw_overhead().
4794 *
4795 * Returns the efficiency in the 100%/coding-overhead% ratio in
4796 * 1ppm units.
4797 */
4798int drm_dp_bw_channel_coding_efficiency(bool is_uhbr)
4799{
4800 if (is_uhbr)
4801 return 967100;
4802 else
4803 /*
4804 * Note that on 8b/10b MST the efficiency is only
4805 * 78.75% due to the 1 out of 64 MTPH packet overhead,
4806 * not accounted for here.
4807 */
4808 return 800000;
4809}
4810EXPORT_SYMBOL(drm_dp_bw_channel_coding_efficiency);
4811
4812/**
4813 * drm_dp_max_dprx_data_rate - Get the max data bandwidth of a DPRX sink
4814 * @max_link_rate: max DPRX link rate in 10kbps units
4815 * @max_lanes: max DPRX lane count
4816 *
4817 * Given a link rate and lanes, get the data bandwidth.
4818 *
4819 * Data bandwidth is the actual payload rate, which depends on the data
4820 * bandwidth efficiency and the link rate.
4821 *
4822 * Note that protocol layers above the DPRX link level considered here can
4823 * further limit the maximum data rate. Such layers are the MST topology (with
4824 * limits on the link between the source and first branch device as well as on
4825 * the whole MST path until the DPRX link) and (Thunderbolt) DP tunnels -
4826 * which in turn can encapsulate an MST link with its own limit - with each
4827 * SST or MST encapsulated tunnel sharing the BW of a tunnel group.
4828 *
4829 * Returns the maximum data rate in kBps units.
4830 */
4831int drm_dp_max_dprx_data_rate(int max_link_rate, int max_lanes)
4832{
4833 int ch_coding_efficiency =
4834 drm_dp_bw_channel_coding_efficiency(drm_dp_is_uhbr_rate(link_rate: max_link_rate));
4835
4836 return DIV_ROUND_DOWN_ULL(mul_u32_u32(max_link_rate * 10 * max_lanes,
4837 ch_coding_efficiency),
4838 1000000 * 8);
4839}
4840EXPORT_SYMBOL(drm_dp_max_dprx_data_rate);
4841

source code of linux/drivers/gpu/drm/display/drm_dp_helper.c