1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Chrontel CH7033 Video Encoder Driver
4 *
5 * Copyright (C) 2019,2020 Lubomir Rintel
6 */
7
8#include <linux/gpio/consumer.h>
9#include <linux/i2c.h>
10#include <linux/module.h>
11#include <linux/regmap.h>
12
13#include <drm/drm_atomic_helper.h>
14#include <drm/drm_bridge.h>
15#include <drm/drm_edid.h>
16#include <drm/drm_of.h>
17#include <drm/drm_print.h>
18#include <drm/drm_probe_helper.h>
19
20/* Page 0, Register 0x07 */
21enum {
22 DRI_PD = BIT(3),
23 IO_PD = BIT(5),
24};
25
26/* Page 0, Register 0x08 */
27enum {
28 DRI_PDDRI = GENMASK(7, 4),
29 PDDAC = GENMASK(3, 1),
30 PANEN = BIT(0),
31};
32
33/* Page 0, Register 0x09 */
34enum {
35 DPD = BIT(7),
36 GCKOFF = BIT(6),
37 TV_BP = BIT(5),
38 SCLPD = BIT(4),
39 SDPD = BIT(3),
40 VGA_PD = BIT(2),
41 HDBKPD = BIT(1),
42 HDMI_PD = BIT(0),
43};
44
45/* Page 0, Register 0x0a */
46enum {
47 MEMINIT = BIT(7),
48 MEMIDLE = BIT(6),
49 MEMPD = BIT(5),
50 STOP = BIT(4),
51 LVDS_PD = BIT(3),
52 HD_DVIB = BIT(2),
53 HDCP_PD = BIT(1),
54 MCU_PD = BIT(0),
55};
56
57/* Page 0, Register 0x18 */
58enum {
59 IDF = GENMASK(7, 4),
60 INTEN = BIT(3),
61 SWAP = GENMASK(2, 0),
62};
63
64enum {
65 BYTE_SWAP_RGB = 0,
66 BYTE_SWAP_RBG = 1,
67 BYTE_SWAP_GRB = 2,
68 BYTE_SWAP_GBR = 3,
69 BYTE_SWAP_BRG = 4,
70 BYTE_SWAP_BGR = 5,
71};
72
73/* Page 0, Register 0x19 */
74enum {
75 HPO_I = BIT(5),
76 VPO_I = BIT(4),
77 DEPO_I = BIT(3),
78 CRYS_EN = BIT(2),
79 GCLKFREQ = GENMASK(2, 0),
80};
81
82/* Page 0, Register 0x2e */
83enum {
84 HFLIP = BIT(7),
85 VFLIP = BIT(6),
86 DEPO_O = BIT(5),
87 HPO_O = BIT(4),
88 VPO_O = BIT(3),
89 TE = GENMASK(2, 0),
90};
91
92/* Page 0, Register 0x2b */
93enum {
94 SWAPS = GENMASK(7, 4),
95 VFMT = GENMASK(3, 0),
96};
97
98/* Page 0, Register 0x54 */
99enum {
100 COMP_BP = BIT(7),
101 DAC_EN_T = BIT(6),
102 HWO_HDMI_HI = GENMASK(5, 3),
103 HOO_HDMI_HI = GENMASK(2, 0),
104};
105
106/* Page 0, Register 0x57 */
107enum {
108 FLDSEN = BIT(7),
109 VWO_HDMI_HI = GENMASK(5, 3),
110 VOO_HDMI_HI = GENMASK(2, 0),
111};
112
113/* Page 0, Register 0x7e */
114enum {
115 HDMI_LVDS_SEL = BIT(7),
116 DE_GEN = BIT(6),
117 PWM_INDEX_HI = BIT(5),
118 USE_DE = BIT(4),
119 R_INT = GENMASK(3, 0),
120};
121
122/* Page 1, Register 0x07 */
123enum {
124 BPCKSEL = BIT(7),
125 DRI_CMFB_EN = BIT(6),
126 CEC_PUEN = BIT(5),
127 CEC_T = BIT(3),
128 CKINV = BIT(2),
129 CK_TVINV = BIT(1),
130 DRI_CKS2 = BIT(0),
131};
132
133/* Page 1, Register 0x08 */
134enum {
135 DACG = BIT(6),
136 DACKTST = BIT(5),
137 DEDGEB = BIT(4),
138 SYO = BIT(3),
139 DRI_IT_LVDS = GENMASK(2, 1),
140 DISPON = BIT(0),
141};
142
143/* Page 1, Register 0x0c */
144enum {
145 DRI_PLL_CP = GENMASK(7, 6),
146 DRI_PLL_DIVSEL = BIT(5),
147 DRI_PLL_N1_1 = BIT(4),
148 DRI_PLL_N1_0 = BIT(3),
149 DRI_PLL_N3_1 = BIT(2),
150 DRI_PLL_N3_0 = BIT(1),
151 DRI_PLL_CKTSTEN = BIT(0),
152};
153
154/* Page 1, Register 0x6b */
155enum {
156 VCO3CS = GENMASK(7, 6),
157 ICPGBK2_0 = GENMASK(5, 3),
158 DRI_VCO357SC = BIT(2),
159 PDPLL2 = BIT(1),
160 DRI_PD_SER = BIT(0),
161};
162
163/* Page 1, Register 0x6c */
164enum {
165 PLL2N11 = GENMASK(7, 4),
166 PLL2N5_4 = BIT(3),
167 PLL2N5_TOP = BIT(2),
168 DRI_PLL_PD = BIT(1),
169 PD_I2CM = BIT(0),
170};
171
172/* Page 3, Register 0x28 */
173enum {
174 DIFF_EN = GENMASK(7, 6),
175 CORREC_EN = GENMASK(5, 4),
176 VGACLK_BP = BIT(3),
177 HM_LV_SEL = BIT(2),
178 HD_VGA_SEL = BIT(1),
179};
180
181/* Page 3, Register 0x2a */
182enum {
183 LVDSCLK_BP = BIT(7),
184 HDTVCLK_BP = BIT(6),
185 HDMICLK_BP = BIT(5),
186 HDTV_BP = BIT(4),
187 HDMI_BP = BIT(3),
188 THRWL = GENMASK(2, 0),
189};
190
191/* Page 4, Register 0x52 */
192enum {
193 PGM_ARSTB = BIT(7),
194 MCU_ARSTB = BIT(6),
195 MCU_RETB = BIT(2),
196 RESETIB = BIT(1),
197 RESETDB = BIT(0),
198};
199
200struct ch7033_priv {
201 struct regmap *regmap;
202 struct drm_bridge *next_bridge;
203 struct drm_bridge bridge;
204 struct drm_connector connector;
205};
206
207#define conn_to_ch7033_priv(x) \
208 container_of(x, struct ch7033_priv, connector)
209#define bridge_to_ch7033_priv(x) \
210 container_of(x, struct ch7033_priv, bridge)
211
212
213static enum drm_connector_status ch7033_connector_detect(
214 struct drm_connector *connector, bool force)
215{
216 struct ch7033_priv *priv = conn_to_ch7033_priv(connector);
217
218 return drm_bridge_detect(bridge: priv->next_bridge, connector);
219}
220
221static const struct drm_connector_funcs ch7033_connector_funcs = {
222 .reset = drm_atomic_helper_connector_reset,
223 .fill_modes = drm_helper_probe_single_connector_modes,
224 .detect = ch7033_connector_detect,
225 .destroy = drm_connector_cleanup,
226 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
227 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
228};
229
230static int ch7033_connector_get_modes(struct drm_connector *connector)
231{
232 struct ch7033_priv *priv = conn_to_ch7033_priv(connector);
233 const struct drm_edid *drm_edid;
234 int ret;
235
236 drm_edid = drm_bridge_edid_read(bridge: priv->next_bridge, connector);
237 drm_edid_connector_update(connector, edid: drm_edid);
238 if (drm_edid) {
239 ret = drm_edid_connector_add_modes(connector);
240 drm_edid_free(drm_edid);
241 } else {
242 ret = drm_add_modes_noedid(connector, hdisplay: 1920, vdisplay: 1080);
243 drm_set_preferred_mode(connector, hpref: 1024, vpref: 768);
244 }
245
246 return ret;
247}
248
249static struct drm_encoder *ch7033_connector_best_encoder(
250 struct drm_connector *connector)
251{
252 struct ch7033_priv *priv = conn_to_ch7033_priv(connector);
253
254 return priv->bridge.encoder;
255}
256
257static const struct drm_connector_helper_funcs ch7033_connector_helper_funcs = {
258 .get_modes = ch7033_connector_get_modes,
259 .best_encoder = ch7033_connector_best_encoder,
260};
261
262static void ch7033_hpd_event(void *arg, enum drm_connector_status status)
263{
264 struct ch7033_priv *priv = arg;
265
266 if (priv->bridge.dev)
267 drm_helper_hpd_irq_event(dev: priv->connector.dev);
268}
269
270static int ch7033_bridge_attach(struct drm_bridge *bridge,
271 struct drm_encoder *encoder,
272 enum drm_bridge_attach_flags flags)
273{
274 struct ch7033_priv *priv = bridge_to_ch7033_priv(bridge);
275 struct drm_connector *connector = &priv->connector;
276 int ret;
277
278 ret = drm_bridge_attach(encoder, bridge: priv->next_bridge, previous: bridge,
279 flags: DRM_BRIDGE_ATTACH_NO_CONNECTOR);
280 if (ret)
281 return ret;
282
283 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)
284 return 0;
285
286 if (priv->next_bridge->ops & DRM_BRIDGE_OP_DETECT) {
287 connector->polled = DRM_CONNECTOR_POLL_HPD;
288 } else {
289 connector->polled = DRM_CONNECTOR_POLL_CONNECT |
290 DRM_CONNECTOR_POLL_DISCONNECT;
291 }
292
293 if (priv->next_bridge->ops & DRM_BRIDGE_OP_HPD) {
294 drm_bridge_hpd_enable(bridge: priv->next_bridge, cb: ch7033_hpd_event,
295 data: priv);
296 }
297
298 drm_connector_helper_add(connector,
299 funcs: &ch7033_connector_helper_funcs);
300 ret = drm_connector_init_with_ddc(dev: bridge->dev, connector: &priv->connector,
301 funcs: &ch7033_connector_funcs,
302 connector_type: priv->next_bridge->type,
303 ddc: priv->next_bridge->ddc);
304 if (ret) {
305 DRM_ERROR("Failed to initialize connector\n");
306 return ret;
307 }
308
309 return drm_connector_attach_encoder(connector: &priv->connector, encoder);
310}
311
312static void ch7033_bridge_detach(struct drm_bridge *bridge)
313{
314 struct ch7033_priv *priv = bridge_to_ch7033_priv(bridge);
315
316 if (priv->next_bridge->ops & DRM_BRIDGE_OP_HPD)
317 drm_bridge_hpd_disable(bridge: priv->next_bridge);
318 drm_connector_cleanup(connector: &priv->connector);
319}
320
321static enum drm_mode_status ch7033_bridge_mode_valid(struct drm_bridge *bridge,
322 const struct drm_display_info *info,
323 const struct drm_display_mode *mode)
324{
325 if (mode->clock > 165000)
326 return MODE_CLOCK_HIGH;
327 if (mode->hdisplay >= 1920)
328 return MODE_BAD_HVALUE;
329 if (mode->vdisplay >= 1080)
330 return MODE_BAD_VVALUE;
331 return MODE_OK;
332}
333
334static void ch7033_bridge_disable(struct drm_bridge *bridge)
335{
336 struct ch7033_priv *priv = bridge_to_ch7033_priv(bridge);
337
338 regmap_write(map: priv->regmap, reg: 0x03, val: 0x04);
339 regmap_update_bits(map: priv->regmap, reg: 0x52, mask: RESETDB, val: 0x00);
340}
341
342static void ch7033_bridge_enable(struct drm_bridge *bridge)
343{
344 struct ch7033_priv *priv = bridge_to_ch7033_priv(bridge);
345
346 regmap_write(map: priv->regmap, reg: 0x03, val: 0x04);
347 regmap_update_bits(map: priv->regmap, reg: 0x52, mask: RESETDB, val: RESETDB);
348}
349
350static void ch7033_bridge_mode_set(struct drm_bridge *bridge,
351 const struct drm_display_mode *mode,
352 const struct drm_display_mode *adjusted_mode)
353{
354 struct ch7033_priv *priv = bridge_to_ch7033_priv(bridge);
355 int hbporch = mode->hsync_start - mode->hdisplay;
356 int hsynclen = mode->hsync_end - mode->hsync_start;
357 int vbporch = mode->vsync_start - mode->vdisplay;
358 int vsynclen = mode->vsync_end - mode->vsync_start;
359
360 /*
361 * Page 4
362 */
363 regmap_write(map: priv->regmap, reg: 0x03, val: 0x04);
364
365 /* Turn everything off to set all the registers to their defaults. */
366 regmap_write(map: priv->regmap, reg: 0x52, val: 0x00);
367 /* Bring I/O block up. */
368 regmap_write(map: priv->regmap, reg: 0x52, val: RESETIB);
369
370 /*
371 * Page 0
372 */
373 regmap_write(map: priv->regmap, reg: 0x03, val: 0x00);
374
375 /* Bring up parts we need from the power down. */
376 regmap_update_bits(map: priv->regmap, reg: 0x07, mask: DRI_PD | IO_PD, val: 0);
377 regmap_update_bits(map: priv->regmap, reg: 0x08, mask: DRI_PDDRI | PDDAC | PANEN, val: 0);
378 regmap_update_bits(map: priv->regmap, reg: 0x09, mask: DPD | GCKOFF |
379 HDMI_PD | VGA_PD, val: 0);
380 regmap_update_bits(map: priv->regmap, reg: 0x0a, mask: HD_DVIB, val: 0);
381
382 /* Horizontal input timing. */
383 regmap_write(map: priv->regmap, reg: 0x0b, val: (mode->htotal >> 8) << 3 |
384 (mode->hdisplay >> 8));
385 regmap_write(map: priv->regmap, reg: 0x0c, val: mode->hdisplay);
386 regmap_write(map: priv->regmap, reg: 0x0d, val: mode->htotal);
387 regmap_write(map: priv->regmap, reg: 0x0e, val: (hsynclen >> 8) << 3 |
388 (hbporch >> 8));
389 regmap_write(map: priv->regmap, reg: 0x0f, val: hbporch);
390 regmap_write(map: priv->regmap, reg: 0x10, val: hsynclen);
391
392 /* Vertical input timing. */
393 regmap_write(map: priv->regmap, reg: 0x11, val: (mode->vtotal >> 8) << 3 |
394 (mode->vdisplay >> 8));
395 regmap_write(map: priv->regmap, reg: 0x12, val: mode->vdisplay);
396 regmap_write(map: priv->regmap, reg: 0x13, val: mode->vtotal);
397 regmap_write(map: priv->regmap, reg: 0x14, val: ((vsynclen >> 8) << 3) |
398 (vbporch >> 8));
399 regmap_write(map: priv->regmap, reg: 0x15, val: vbporch);
400 regmap_write(map: priv->regmap, reg: 0x16, val: vsynclen);
401
402 /* Input color swap. */
403 regmap_update_bits(map: priv->regmap, reg: 0x18, mask: SWAP, val: BYTE_SWAP_BGR);
404
405 /* Input clock and sync polarity. */
406 regmap_update_bits(map: priv->regmap, reg: 0x19, mask: 0x1, val: mode->clock >> 16);
407 regmap_update_bits(map: priv->regmap, reg: 0x19, mask: HPO_I | VPO_I | GCLKFREQ,
408 val: (mode->flags & DRM_MODE_FLAG_PHSYNC) ? HPO_I : 0 |
409 (mode->flags & DRM_MODE_FLAG_PVSYNC) ? VPO_I : 0 |
410 mode->clock >> 16);
411 regmap_write(map: priv->regmap, reg: 0x1a, val: mode->clock >> 8);
412 regmap_write(map: priv->regmap, reg: 0x1b, val: mode->clock);
413
414 /* Horizontal output timing. */
415 regmap_write(map: priv->regmap, reg: 0x1f, val: (mode->htotal >> 8) << 3 |
416 (mode->hdisplay >> 8));
417 regmap_write(map: priv->regmap, reg: 0x20, val: mode->hdisplay);
418 regmap_write(map: priv->regmap, reg: 0x21, val: mode->htotal);
419
420 /* Vertical output timing. */
421 regmap_write(map: priv->regmap, reg: 0x25, val: (mode->vtotal >> 8) << 3 |
422 (mode->vdisplay >> 8));
423 regmap_write(map: priv->regmap, reg: 0x26, val: mode->vdisplay);
424 regmap_write(map: priv->regmap, reg: 0x27, val: mode->vtotal);
425
426 /* VGA channel bypass */
427 regmap_update_bits(map: priv->regmap, reg: 0x2b, mask: VFMT, val: 9);
428
429 /* Output sync polarity. */
430 regmap_update_bits(map: priv->regmap, reg: 0x2e, mask: HPO_O | VPO_O,
431 val: (mode->flags & DRM_MODE_FLAG_PHSYNC) ? HPO_O : 0 |
432 (mode->flags & DRM_MODE_FLAG_PVSYNC) ? VPO_O : 0);
433
434 /* HDMI horizontal output timing. */
435 regmap_update_bits(map: priv->regmap, reg: 0x54, mask: HWO_HDMI_HI | HOO_HDMI_HI,
436 val: (hsynclen >> 8) << 3 |
437 (hbporch >> 8));
438 regmap_write(map: priv->regmap, reg: 0x55, val: hbporch);
439 regmap_write(map: priv->regmap, reg: 0x56, val: hsynclen);
440
441 /* HDMI vertical output timing. */
442 regmap_update_bits(map: priv->regmap, reg: 0x57, mask: VWO_HDMI_HI | VOO_HDMI_HI,
443 val: (vsynclen >> 8) << 3 |
444 (vbporch >> 8));
445 regmap_write(map: priv->regmap, reg: 0x58, val: vbporch);
446 regmap_write(map: priv->regmap, reg: 0x59, val: vsynclen);
447
448 /* Pick HDMI, not LVDS. */
449 regmap_update_bits(map: priv->regmap, reg: 0x7e, mask: HDMI_LVDS_SEL, val: HDMI_LVDS_SEL);
450
451 /*
452 * Page 1
453 */
454 regmap_write(map: priv->regmap, reg: 0x03, val: 0x01);
455
456 /* No idea what these do, but VGA is wobbly and blinky without them. */
457 regmap_update_bits(map: priv->regmap, reg: 0x07, mask: CKINV, val: CKINV);
458 regmap_update_bits(map: priv->regmap, reg: 0x08, mask: DISPON, val: DISPON);
459
460 /* DRI PLL */
461 regmap_update_bits(map: priv->regmap, reg: 0x0c, mask: DRI_PLL_DIVSEL, val: DRI_PLL_DIVSEL);
462 if (mode->clock <= 40000) {
463 regmap_update_bits(map: priv->regmap, reg: 0x0c, mask: DRI_PLL_N1_1 |
464 DRI_PLL_N1_0 |
465 DRI_PLL_N3_1 |
466 DRI_PLL_N3_0,
467 val: 0);
468 } else if (mode->clock < 80000) {
469 regmap_update_bits(map: priv->regmap, reg: 0x0c, mask: DRI_PLL_N1_1 |
470 DRI_PLL_N1_0 |
471 DRI_PLL_N3_1 |
472 DRI_PLL_N3_0,
473 val: DRI_PLL_N3_0 |
474 DRI_PLL_N1_0);
475 } else {
476 regmap_update_bits(map: priv->regmap, reg: 0x0c, mask: DRI_PLL_N1_1 |
477 DRI_PLL_N1_0 |
478 DRI_PLL_N3_1 |
479 DRI_PLL_N3_0,
480 val: DRI_PLL_N3_1 |
481 DRI_PLL_N1_1);
482 }
483
484 /* This seems to be color calibration for VGA. */
485 regmap_write(map: priv->regmap, reg: 0x64, val: 0x29); /* LSB Blue */
486 regmap_write(map: priv->regmap, reg: 0x65, val: 0x29); /* LSB Green */
487 regmap_write(map: priv->regmap, reg: 0x66, val: 0x29); /* LSB Red */
488 regmap_write(map: priv->regmap, reg: 0x67, val: 0x00); /* MSB Blue */
489 regmap_write(map: priv->regmap, reg: 0x68, val: 0x00); /* MSB Green */
490 regmap_write(map: priv->regmap, reg: 0x69, val: 0x00); /* MSB Red */
491
492 regmap_update_bits(map: priv->regmap, reg: 0x6b, mask: DRI_PD_SER, val: 0x00);
493 regmap_update_bits(map: priv->regmap, reg: 0x6c, mask: DRI_PLL_PD, val: 0x00);
494
495 /*
496 * Page 3
497 */
498 regmap_write(map: priv->regmap, reg: 0x03, val: 0x03);
499
500 /* More bypasses and apparently another HDMI/LVDS selector. */
501 regmap_update_bits(map: priv->regmap, reg: 0x28, mask: VGACLK_BP | HM_LV_SEL,
502 val: VGACLK_BP | HM_LV_SEL);
503 regmap_update_bits(map: priv->regmap, reg: 0x2a, mask: HDMICLK_BP | HDMI_BP,
504 val: HDMICLK_BP | HDMI_BP);
505
506 /*
507 * Page 4
508 */
509 regmap_write(map: priv->regmap, reg: 0x03, val: 0x04);
510
511 /* Output clock. */
512 regmap_write(map: priv->regmap, reg: 0x10, val: mode->clock >> 16);
513 regmap_write(map: priv->regmap, reg: 0x11, val: mode->clock >> 8);
514 regmap_write(map: priv->regmap, reg: 0x12, val: mode->clock);
515}
516
517static const struct drm_bridge_funcs ch7033_bridge_funcs = {
518 .attach = ch7033_bridge_attach,
519 .detach = ch7033_bridge_detach,
520 .mode_valid = ch7033_bridge_mode_valid,
521 .disable = ch7033_bridge_disable,
522 .enable = ch7033_bridge_enable,
523 .mode_set = ch7033_bridge_mode_set,
524};
525
526static const struct regmap_config ch7033_regmap_config = {
527 .reg_bits = 8,
528 .val_bits = 8,
529 .max_register = 0x7f,
530};
531
532static int ch7033_probe(struct i2c_client *client)
533{
534 struct device *dev = &client->dev;
535 struct ch7033_priv *priv;
536 unsigned int val;
537 int ret;
538
539 priv = devm_drm_bridge_alloc(dev, struct ch7033_priv, bridge,
540 &ch7033_bridge_funcs);
541 if (IS_ERR(ptr: priv))
542 return PTR_ERR(ptr: priv);
543
544 dev_set_drvdata(dev, data: priv);
545
546 ret = drm_of_find_panel_or_bridge(np: dev->of_node, port: 1, endpoint: -1, NULL,
547 bridge: &priv->next_bridge);
548 if (ret)
549 return ret;
550
551 priv->regmap = devm_regmap_init_i2c(client, &ch7033_regmap_config);
552 if (IS_ERR(ptr: priv->regmap)) {
553 dev_err(&client->dev, "regmap init failed\n");
554 return PTR_ERR(ptr: priv->regmap);
555 }
556
557 ret = regmap_read(map: priv->regmap, reg: 0x00, val: &val);
558 if (ret < 0) {
559 dev_err(&client->dev, "error reading the model id: %d\n", ret);
560 return ret;
561 }
562 if ((val & 0xf7) != 0x56) {
563 dev_err(&client->dev, "the device is not a ch7033\n");
564 return -ENODEV;
565 }
566
567 regmap_write(map: priv->regmap, reg: 0x03, val: 0x04);
568 ret = regmap_read(map: priv->regmap, reg: 0x51, val: &val);
569 if (ret < 0) {
570 dev_err(&client->dev, "error reading the model id: %d\n", ret);
571 return ret;
572 }
573 if ((val & 0x0f) != 3) {
574 dev_err(&client->dev, "unknown revision %u\n", val);
575 return -ENODEV;
576 }
577
578 INIT_LIST_HEAD(list: &priv->bridge.list);
579 priv->bridge.of_node = dev->of_node;
580 drm_bridge_add(bridge: &priv->bridge);
581
582 dev_info(dev, "Chrontel CH7033 Video Encoder\n");
583 return 0;
584}
585
586static void ch7033_remove(struct i2c_client *client)
587{
588 struct device *dev = &client->dev;
589 struct ch7033_priv *priv = dev_get_drvdata(dev);
590
591 drm_bridge_remove(bridge: &priv->bridge);
592}
593
594static const struct of_device_id ch7033_dt_ids[] = {
595 { .compatible = "chrontel,ch7033", },
596 { }
597};
598MODULE_DEVICE_TABLE(of, ch7033_dt_ids);
599
600static const struct i2c_device_id ch7033_ids[] = {
601 { "ch7033" },
602 { }
603};
604MODULE_DEVICE_TABLE(i2c, ch7033_ids);
605
606static struct i2c_driver ch7033_driver = {
607 .probe = ch7033_probe,
608 .remove = ch7033_remove,
609 .driver = {
610 .name = "ch7033",
611 .of_match_table = ch7033_dt_ids,
612 },
613 .id_table = ch7033_ids,
614};
615
616module_i2c_driver(ch7033_driver);
617
618MODULE_AUTHOR("Lubomir Rintel <lkundrak@v3.sk>");
619MODULE_DESCRIPTION("Chrontel CH7033 Video Encoder Driver");
620MODULE_LICENSE("GPL v2");
621

source code of linux/drivers/gpu/drm/bridge/chrontel-ch7033.c