1// SPDX-License-Identifier: MIT
2/*
3 * Copyright 2025 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 */
24#include "ras.h"
25#include "ras_gfx_v9_0.h"
26#include "ras_core_status.h"
27
28enum ta_gfx_v9_subblock {
29 /*CPC*/
30 TA_GFX_V9__GFX_CPC_INDEX_START = 0,
31 TA_GFX_V9__GFX_CPC_SCRATCH = TA_GFX_V9__GFX_CPC_INDEX_START,
32 TA_GFX_V9__GFX_CPC_UCODE,
33 TA_GFX_V9__GFX_DC_STATE_ME1,
34 TA_GFX_V9__GFX_DC_CSINVOC_ME1,
35 TA_GFX_V9__GFX_DC_RESTORE_ME1,
36 TA_GFX_V9__GFX_DC_STATE_ME2,
37 TA_GFX_V9__GFX_DC_CSINVOC_ME2,
38 TA_GFX_V9__GFX_DC_RESTORE_ME2,
39 TA_GFX_V9__GFX_CPC_INDEX_END = TA_GFX_V9__GFX_DC_RESTORE_ME2,
40 /* CPF*/
41 TA_GFX_V9__GFX_CPF_INDEX_START,
42 TA_GFX_V9__GFX_CPF_ROQ_ME2 = TA_GFX_V9__GFX_CPF_INDEX_START,
43 TA_GFX_V9__GFX_CPF_ROQ_ME1,
44 TA_GFX_V9__GFX_CPF_TAG,
45 TA_GFX_V9__GFX_CPF_INDEX_END = TA_GFX_V9__GFX_CPF_TAG,
46 /* CPG*/
47 TA_GFX_V9__GFX_CPG_INDEX_START,
48 TA_GFX_V9__GFX_CPG_DMA_ROQ = TA_GFX_V9__GFX_CPG_INDEX_START,
49 TA_GFX_V9__GFX_CPG_DMA_TAG,
50 TA_GFX_V9__GFX_CPG_TAG,
51 TA_GFX_V9__GFX_CPG_INDEX_END = TA_GFX_V9__GFX_CPG_TAG,
52 /* GDS*/
53 TA_GFX_V9__GFX_GDS_INDEX_START,
54 TA_GFX_V9__GFX_GDS_MEM = TA_GFX_V9__GFX_GDS_INDEX_START,
55 TA_GFX_V9__GFX_GDS_INPUT_QUEUE,
56 TA_GFX_V9__GFX_GDS_OA_PHY_CMD_RAM_MEM,
57 TA_GFX_V9__GFX_GDS_OA_PHY_DATA_RAM_MEM,
58 TA_GFX_V9__GFX_GDS_OA_PIPE_MEM,
59 TA_GFX_V9__GFX_GDS_INDEX_END = TA_GFX_V9__GFX_GDS_OA_PIPE_MEM,
60 /* SPI*/
61 TA_GFX_V9__GFX_SPI_SR_MEM,
62 /* SQ*/
63 TA_GFX_V9__GFX_SQ_INDEX_START,
64 TA_GFX_V9__GFX_SQ_SGPR = TA_GFX_V9__GFX_SQ_INDEX_START,
65 TA_GFX_V9__GFX_SQ_LDS_D,
66 TA_GFX_V9__GFX_SQ_LDS_I,
67 TA_GFX_V9__GFX_SQ_VGPR, /* VGPR = SP*/
68 TA_GFX_V9__GFX_SQ_INDEX_END = TA_GFX_V9__GFX_SQ_VGPR,
69 /* SQC (3 ranges)*/
70 TA_GFX_V9__GFX_SQC_INDEX_START,
71 /* SQC range 0*/
72 TA_GFX_V9__GFX_SQC_INDEX0_START = TA_GFX_V9__GFX_SQC_INDEX_START,
73 TA_GFX_V9__GFX_SQC_INST_UTCL1_LFIFO =
74 TA_GFX_V9__GFX_SQC_INDEX0_START,
75 TA_GFX_V9__GFX_SQC_DATA_CU0_WRITE_DATA_BUF,
76 TA_GFX_V9__GFX_SQC_DATA_CU0_UTCL1_LFIFO,
77 TA_GFX_V9__GFX_SQC_DATA_CU1_WRITE_DATA_BUF,
78 TA_GFX_V9__GFX_SQC_DATA_CU1_UTCL1_LFIFO,
79 TA_GFX_V9__GFX_SQC_DATA_CU2_WRITE_DATA_BUF,
80 TA_GFX_V9__GFX_SQC_DATA_CU2_UTCL1_LFIFO,
81 TA_GFX_V9__GFX_SQC_INDEX0_END =
82 TA_GFX_V9__GFX_SQC_DATA_CU2_UTCL1_LFIFO,
83 /* SQC range 1*/
84 TA_GFX_V9__GFX_SQC_INDEX1_START,
85 TA_GFX_V9__GFX_SQC_INST_BANKA_TAG_RAM =
86 TA_GFX_V9__GFX_SQC_INDEX1_START,
87 TA_GFX_V9__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO,
88 TA_GFX_V9__GFX_SQC_INST_BANKA_MISS_FIFO,
89 TA_GFX_V9__GFX_SQC_INST_BANKA_BANK_RAM,
90 TA_GFX_V9__GFX_SQC_DATA_BANKA_TAG_RAM,
91 TA_GFX_V9__GFX_SQC_DATA_BANKA_HIT_FIFO,
92 TA_GFX_V9__GFX_SQC_DATA_BANKA_MISS_FIFO,
93 TA_GFX_V9__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM,
94 TA_GFX_V9__GFX_SQC_DATA_BANKA_BANK_RAM,
95 TA_GFX_V9__GFX_SQC_INDEX1_END =
96 TA_GFX_V9__GFX_SQC_DATA_BANKA_BANK_RAM,
97 /* SQC range 2*/
98 TA_GFX_V9__GFX_SQC_INDEX2_START,
99 TA_GFX_V9__GFX_SQC_INST_BANKB_TAG_RAM =
100 TA_GFX_V9__GFX_SQC_INDEX2_START,
101 TA_GFX_V9__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO,
102 TA_GFX_V9__GFX_SQC_INST_BANKB_MISS_FIFO,
103 TA_GFX_V9__GFX_SQC_INST_BANKB_BANK_RAM,
104 TA_GFX_V9__GFX_SQC_DATA_BANKB_TAG_RAM,
105 TA_GFX_V9__GFX_SQC_DATA_BANKB_HIT_FIFO,
106 TA_GFX_V9__GFX_SQC_DATA_BANKB_MISS_FIFO,
107 TA_GFX_V9__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM,
108 TA_GFX_V9__GFX_SQC_DATA_BANKB_BANK_RAM,
109 TA_GFX_V9__GFX_SQC_INDEX2_END =
110 TA_GFX_V9__GFX_SQC_DATA_BANKB_BANK_RAM,
111 TA_GFX_V9__GFX_SQC_INDEX_END = TA_GFX_V9__GFX_SQC_INDEX2_END,
112 /* TA*/
113 TA_GFX_V9__GFX_TA_INDEX_START,
114 TA_GFX_V9__GFX_TA_FS_DFIFO = TA_GFX_V9__GFX_TA_INDEX_START,
115 TA_GFX_V9__GFX_TA_FS_AFIFO,
116 TA_GFX_V9__GFX_TA_FL_LFIFO,
117 TA_GFX_V9__GFX_TA_FX_LFIFO,
118 TA_GFX_V9__GFX_TA_FS_CFIFO,
119 TA_GFX_V9__GFX_TA_INDEX_END = TA_GFX_V9__GFX_TA_FS_CFIFO,
120 /* TCA*/
121 TA_GFX_V9__GFX_TCA_INDEX_START,
122 TA_GFX_V9__GFX_TCA_HOLE_FIFO = TA_GFX_V9__GFX_TCA_INDEX_START,
123 TA_GFX_V9__GFX_TCA_REQ_FIFO,
124 TA_GFX_V9__GFX_TCA_INDEX_END = TA_GFX_V9__GFX_TCA_REQ_FIFO,
125 /* TCC (5 sub-ranges)*/
126 TA_GFX_V9__GFX_TCC_INDEX_START,
127 /* TCC range 0*/
128 TA_GFX_V9__GFX_TCC_INDEX0_START = TA_GFX_V9__GFX_TCC_INDEX_START,
129 TA_GFX_V9__GFX_TCC_CACHE_DATA = TA_GFX_V9__GFX_TCC_INDEX0_START,
130 TA_GFX_V9__GFX_TCC_CACHE_DATA_BANK_0_1,
131 TA_GFX_V9__GFX_TCC_CACHE_DATA_BANK_1_0,
132 TA_GFX_V9__GFX_TCC_CACHE_DATA_BANK_1_1,
133 TA_GFX_V9__GFX_TCC_CACHE_DIRTY_BANK_0,
134 TA_GFX_V9__GFX_TCC_CACHE_DIRTY_BANK_1,
135 TA_GFX_V9__GFX_TCC_HIGH_RATE_TAG,
136 TA_GFX_V9__GFX_TCC_LOW_RATE_TAG,
137 TA_GFX_V9__GFX_TCC_INDEX0_END = TA_GFX_V9__GFX_TCC_LOW_RATE_TAG,
138 /* TCC range 1*/
139 TA_GFX_V9__GFX_TCC_INDEX1_START,
140 TA_GFX_V9__GFX_TCC_IN_USE_DEC = TA_GFX_V9__GFX_TCC_INDEX1_START,
141 TA_GFX_V9__GFX_TCC_IN_USE_TRANSFER,
142 TA_GFX_V9__GFX_TCC_INDEX1_END =
143 TA_GFX_V9__GFX_TCC_IN_USE_TRANSFER,
144 /* TCC range 2*/
145 TA_GFX_V9__GFX_TCC_INDEX2_START,
146 TA_GFX_V9__GFX_TCC_RETURN_DATA = TA_GFX_V9__GFX_TCC_INDEX2_START,
147 TA_GFX_V9__GFX_TCC_RETURN_CONTROL,
148 TA_GFX_V9__GFX_TCC_UC_ATOMIC_FIFO,
149 TA_GFX_V9__GFX_TCC_WRITE_RETURN,
150 TA_GFX_V9__GFX_TCC_WRITE_CACHE_READ,
151 TA_GFX_V9__GFX_TCC_SRC_FIFO,
152 TA_GFX_V9__GFX_TCC_SRC_FIFO_NEXT_RAM,
153 TA_GFX_V9__GFX_TCC_CACHE_TAG_PROBE_FIFO,
154 TA_GFX_V9__GFX_TCC_INDEX2_END =
155 TA_GFX_V9__GFX_TCC_CACHE_TAG_PROBE_FIFO,
156 /* TCC range 3*/
157 TA_GFX_V9__GFX_TCC_INDEX3_START,
158 TA_GFX_V9__GFX_TCC_LATENCY_FIFO = TA_GFX_V9__GFX_TCC_INDEX3_START,
159 TA_GFX_V9__GFX_TCC_LATENCY_FIFO_NEXT_RAM,
160 TA_GFX_V9__GFX_TCC_INDEX3_END =
161 TA_GFX_V9__GFX_TCC_LATENCY_FIFO_NEXT_RAM,
162 /* TCC range 4*/
163 TA_GFX_V9__GFX_TCC_INDEX4_START,
164 TA_GFX_V9__GFX_TCC_WRRET_TAG_WRITE_RETURN =
165 TA_GFX_V9__GFX_TCC_INDEX4_START,
166 TA_GFX_V9__GFX_TCC_ATOMIC_RETURN_BUFFER,
167 TA_GFX_V9__GFX_TCC_INDEX4_END =
168 TA_GFX_V9__GFX_TCC_ATOMIC_RETURN_BUFFER,
169 TA_GFX_V9__GFX_TCC_INDEX_END = TA_GFX_V9__GFX_TCC_INDEX4_END,
170 /* TCI*/
171 TA_GFX_V9__GFX_TCI_WRITE_RAM,
172 /* TCP*/
173 TA_GFX_V9__GFX_TCP_INDEX_START,
174 TA_GFX_V9__GFX_TCP_CACHE_RAM = TA_GFX_V9__GFX_TCP_INDEX_START,
175 TA_GFX_V9__GFX_TCP_LFIFO_RAM,
176 TA_GFX_V9__GFX_TCP_CMD_FIFO,
177 TA_GFX_V9__GFX_TCP_VM_FIFO,
178 TA_GFX_V9__GFX_TCP_DB_RAM,
179 TA_GFX_V9__GFX_TCP_UTCL1_LFIFO0,
180 TA_GFX_V9__GFX_TCP_UTCL1_LFIFO1,
181 TA_GFX_V9__GFX_TCP_INDEX_END = TA_GFX_V9__GFX_TCP_UTCL1_LFIFO1,
182 /* TD*/
183 TA_GFX_V9__GFX_TD_INDEX_START,
184 TA_GFX_V9__GFX_TD_SS_FIFO_LO = TA_GFX_V9__GFX_TD_INDEX_START,
185 TA_GFX_V9__GFX_TD_SS_FIFO_HI,
186 TA_GFX_V9__GFX_TD_CS_FIFO,
187 TA_GFX_V9__GFX_TD_INDEX_END = TA_GFX_V9__GFX_TD_CS_FIFO,
188 /* EA (3 sub-ranges)*/
189 TA_GFX_V9__GFX_EA_INDEX_START,
190 /* EA range 0*/
191 TA_GFX_V9__GFX_EA_INDEX0_START = TA_GFX_V9__GFX_EA_INDEX_START,
192 TA_GFX_V9__GFX_EA_DRAMRD_CMDMEM = TA_GFX_V9__GFX_EA_INDEX0_START,
193 TA_GFX_V9__GFX_EA_DRAMWR_CMDMEM,
194 TA_GFX_V9__GFX_EA_DRAMWR_DATAMEM,
195 TA_GFX_V9__GFX_EA_RRET_TAGMEM,
196 TA_GFX_V9__GFX_EA_WRET_TAGMEM,
197 TA_GFX_V9__GFX_EA_GMIRD_CMDMEM,
198 TA_GFX_V9__GFX_EA_GMIWR_CMDMEM,
199 TA_GFX_V9__GFX_EA_GMIWR_DATAMEM,
200 TA_GFX_V9__GFX_EA_INDEX0_END = TA_GFX_V9__GFX_EA_GMIWR_DATAMEM,
201 /* EA range 1*/
202 TA_GFX_V9__GFX_EA_INDEX1_START,
203 TA_GFX_V9__GFX_EA_DRAMRD_PAGEMEM = TA_GFX_V9__GFX_EA_INDEX1_START,
204 TA_GFX_V9__GFX_EA_DRAMWR_PAGEMEM,
205 TA_GFX_V9__GFX_EA_IORD_CMDMEM,
206 TA_GFX_V9__GFX_EA_IOWR_CMDMEM,
207 TA_GFX_V9__GFX_EA_IOWR_DATAMEM,
208 TA_GFX_V9__GFX_EA_GMIRD_PAGEMEM,
209 TA_GFX_V9__GFX_EA_GMIWR_PAGEMEM,
210 TA_GFX_V9__GFX_EA_INDEX1_END = TA_GFX_V9__GFX_EA_GMIWR_PAGEMEM,
211 /* EA range 2*/
212 TA_GFX_V9__GFX_EA_INDEX2_START,
213 TA_GFX_V9__GFX_EA_MAM_D0MEM = TA_GFX_V9__GFX_EA_INDEX2_START,
214 TA_GFX_V9__GFX_EA_MAM_D1MEM,
215 TA_GFX_V9__GFX_EA_MAM_D2MEM,
216 TA_GFX_V9__GFX_EA_MAM_D3MEM,
217 TA_GFX_V9__GFX_EA_INDEX2_END = TA_GFX_V9__GFX_EA_MAM_D3MEM,
218 TA_GFX_V9__GFX_EA_INDEX_END = TA_GFX_V9__GFX_EA_INDEX2_END,
219 /* UTC VM L2 bank*/
220 TA_GFX_V9__UTC_VML2_BANK_CACHE,
221 /* UTC VM walker*/
222 TA_GFX_V9__UTC_VML2_WALKER,
223 /* UTC ATC L2 2MB cache*/
224 TA_GFX_V9__UTC_ATCL2_CACHE_2M_BANK,
225 /* UTC ATC L2 4KB cache*/
226 TA_GFX_V9__UTC_ATCL2_CACHE_4K_BANK,
227 TA_GFX_V9__GFX_MAX
228};
229
230struct ras_gfx_subblock_t {
231 unsigned char *name;
232 int ta_subblock;
233 int hw_supported_error_type;
234 int sw_supported_error_type;
235};
236
237#define RAS_GFX_SUB_BLOCK(subblock, a, b, c, d, e, f, g, h) \
238 [RAS_GFX_V9__##subblock] = { \
239 #subblock, \
240 TA_GFX_V9__##subblock, \
241 ((a) | ((b) << 1) | ((c) << 2) | ((d) << 3)), \
242 (((e) << 1) | ((f) << 3) | (g) | ((h) << 2)), \
243 }
244
245const struct ras_gfx_subblock_t ras_gfx_v9_0_subblocks[] = {
246 RAS_GFX_SUB_BLOCK(GFX_CPC_SCRATCH, 0, 1, 1, 1, 1, 0, 0, 1),
247 RAS_GFX_SUB_BLOCK(GFX_CPC_UCODE, 0, 1, 1, 1, 1, 0, 0, 1),
248 RAS_GFX_SUB_BLOCK(GFX_DC_STATE_ME1, 1, 0, 0, 1, 0, 0, 1, 0),
249 RAS_GFX_SUB_BLOCK(GFX_DC_CSINVOC_ME1, 1, 0, 0, 1, 0, 0, 0, 0),
250 RAS_GFX_SUB_BLOCK(GFX_DC_RESTORE_ME1, 1, 0, 0, 1, 0, 0, 0, 0),
251 RAS_GFX_SUB_BLOCK(GFX_DC_STATE_ME2, 1, 0, 0, 1, 0, 0, 0, 0),
252 RAS_GFX_SUB_BLOCK(GFX_DC_CSINVOC_ME2, 1, 0, 0, 1, 0, 0, 0, 0),
253 RAS_GFX_SUB_BLOCK(GFX_DC_RESTORE_ME2, 1, 0, 0, 1, 0, 0, 0, 0),
254 RAS_GFX_SUB_BLOCK(GFX_CPF_ROQ_ME2, 1, 0, 0, 1, 0, 0, 0, 0),
255 RAS_GFX_SUB_BLOCK(GFX_CPF_ROQ_ME1, 1, 0, 0, 1, 0, 0, 1, 0),
256 RAS_GFX_SUB_BLOCK(GFX_CPF_TAG, 0, 1, 1, 1, 1, 0, 0, 1),
257 RAS_GFX_SUB_BLOCK(GFX_CPG_DMA_ROQ, 1, 0, 0, 1, 0, 0, 1, 0),
258 RAS_GFX_SUB_BLOCK(GFX_CPG_DMA_TAG, 0, 1, 1, 1, 0, 1, 0, 1),
259 RAS_GFX_SUB_BLOCK(GFX_CPG_TAG, 0, 1, 1, 1, 1, 1, 0, 1),
260 RAS_GFX_SUB_BLOCK(GFX_GDS_MEM, 0, 1, 1, 1, 0, 0, 0, 0),
261 RAS_GFX_SUB_BLOCK(GFX_GDS_INPUT_QUEUE, 1, 0, 0, 1, 0, 0, 0, 0),
262 RAS_GFX_SUB_BLOCK(GFX_GDS_OA_PHY_CMD_RAM_MEM, 0, 1, 1, 1, 0, 0, 0,
263 0),
264 RAS_GFX_SUB_BLOCK(GFX_GDS_OA_PHY_DATA_RAM_MEM, 1, 0, 0, 1, 0, 0, 0,
265 0),
266 RAS_GFX_SUB_BLOCK(GFX_GDS_OA_PIPE_MEM, 0, 1, 1, 1, 0, 0, 0, 0),
267 RAS_GFX_SUB_BLOCK(GFX_SPI_SR_MEM, 1, 0, 0, 1, 0, 0, 0, 0),
268 RAS_GFX_SUB_BLOCK(GFX_SQ_SGPR, 0, 1, 1, 1, 0, 0, 0, 0),
269 RAS_GFX_SUB_BLOCK(GFX_SQ_LDS_D, 0, 1, 1, 1, 1, 0, 0, 1),
270 RAS_GFX_SUB_BLOCK(GFX_SQ_LDS_I, 0, 1, 1, 1, 0, 0, 0, 0),
271 RAS_GFX_SUB_BLOCK(GFX_SQ_VGPR, 0, 1, 1, 1, 0, 0, 0, 0),
272 RAS_GFX_SUB_BLOCK(GFX_SQC_INST_UTCL1_LFIFO, 0, 1, 1, 1, 0, 0, 0, 1),
273 RAS_GFX_SUB_BLOCK(GFX_SQC_DATA_CU0_WRITE_DATA_BUF, 0, 1, 1, 1, 0, 0,
274 0, 0),
275 RAS_GFX_SUB_BLOCK(GFX_SQC_DATA_CU0_UTCL1_LFIFO, 0, 1, 1, 1, 0, 0, 0,
276 0),
277 RAS_GFX_SUB_BLOCK(GFX_SQC_DATA_CU1_WRITE_DATA_BUF, 0, 1, 1, 1, 0, 0,
278 0, 0),
279 RAS_GFX_SUB_BLOCK(GFX_SQC_DATA_CU1_UTCL1_LFIFO, 0, 1, 1, 1, 1, 0, 0,
280 0),
281 RAS_GFX_SUB_BLOCK(GFX_SQC_DATA_CU2_WRITE_DATA_BUF, 0, 1, 1, 1, 0, 0,
282 0, 0),
283 RAS_GFX_SUB_BLOCK(GFX_SQC_DATA_CU2_UTCL1_LFIFO, 0, 1, 1, 1, 0, 0, 0,
284 0),
285 RAS_GFX_SUB_BLOCK(GFX_SQC_INST_BANKA_TAG_RAM, 0, 1, 1, 1, 1, 0, 0,
286 1),
287 RAS_GFX_SUB_BLOCK(GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO, 1, 0, 0, 1, 0,
288 0, 0, 0),
289 RAS_GFX_SUB_BLOCK(GFX_SQC_INST_BANKA_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0,
290 0),
291 RAS_GFX_SUB_BLOCK(GFX_SQC_INST_BANKA_BANK_RAM, 0, 1, 1, 1, 0, 0, 0,
292 0),
293 RAS_GFX_SUB_BLOCK(GFX_SQC_DATA_BANKA_TAG_RAM, 0, 1, 1, 1, 0, 0, 0,
294 0),
295 RAS_GFX_SUB_BLOCK(GFX_SQC_DATA_BANKA_HIT_FIFO, 1, 0, 0, 1, 0, 0, 0,
296 0),
297 RAS_GFX_SUB_BLOCK(GFX_SQC_DATA_BANKA_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0,
298 0),
299 RAS_GFX_SUB_BLOCK(GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM, 1, 0, 0, 1, 0, 0,
300 0, 0),
301 RAS_GFX_SUB_BLOCK(GFX_SQC_DATA_BANKA_BANK_RAM, 0, 1, 1, 1, 0, 0, 0,
302 0),
303 RAS_GFX_SUB_BLOCK(GFX_SQC_INST_BANKB_TAG_RAM, 0, 1, 1, 1, 1, 0, 0,
304 0),
305 RAS_GFX_SUB_BLOCK(GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO, 1, 0, 0, 1, 0,
306 0, 0, 0),
307 RAS_GFX_SUB_BLOCK(GFX_SQC_INST_BANKB_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0,
308 0),
309 RAS_GFX_SUB_BLOCK(GFX_SQC_INST_BANKB_BANK_RAM, 0, 1, 1, 1, 0, 0, 0,
310 0),
311 RAS_GFX_SUB_BLOCK(GFX_SQC_DATA_BANKB_TAG_RAM, 0, 1, 1, 1, 0, 0, 0,
312 0),
313 RAS_GFX_SUB_BLOCK(GFX_SQC_DATA_BANKB_HIT_FIFO, 1, 0, 0, 1, 0, 0, 0,
314 0),
315 RAS_GFX_SUB_BLOCK(GFX_SQC_DATA_BANKB_MISS_FIFO, 1, 0, 0, 1, 0, 0, 0,
316 0),
317 RAS_GFX_SUB_BLOCK(GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM, 1, 0, 0, 1, 0, 0,
318 0, 0),
319 RAS_GFX_SUB_BLOCK(GFX_SQC_DATA_BANKB_BANK_RAM, 0, 1, 1, 1, 0, 0, 0,
320 0),
321 RAS_GFX_SUB_BLOCK(GFX_TA_FS_DFIFO, 0, 1, 1, 1, 1, 0, 0, 1),
322 RAS_GFX_SUB_BLOCK(GFX_TA_FS_AFIFO, 1, 0, 0, 1, 0, 0, 0, 0),
323 RAS_GFX_SUB_BLOCK(GFX_TA_FL_LFIFO, 1, 0, 0, 1, 0, 0, 0, 0),
324 RAS_GFX_SUB_BLOCK(GFX_TA_FX_LFIFO, 1, 0, 0, 1, 0, 0, 0, 0),
325 RAS_GFX_SUB_BLOCK(GFX_TA_FS_CFIFO, 1, 0, 0, 1, 0, 0, 0, 0),
326 RAS_GFX_SUB_BLOCK(GFX_TCA_HOLE_FIFO, 1, 0, 0, 1, 0, 1, 1, 0),
327 RAS_GFX_SUB_BLOCK(GFX_TCA_REQ_FIFO, 1, 0, 0, 1, 0, 0, 0, 0),
328 RAS_GFX_SUB_BLOCK(GFX_TCC_CACHE_DATA, 0, 1, 1, 1, 1, 0, 0, 1),
329 RAS_GFX_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_0_1, 0, 1, 1, 1, 1, 0, 0,
330 1),
331 RAS_GFX_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_1_0, 0, 1, 1, 1, 1, 0, 0,
332 1),
333 RAS_GFX_SUB_BLOCK(GFX_TCC_CACHE_DATA_BANK_1_1, 0, 1, 1, 1, 1, 0, 0,
334 1),
335 RAS_GFX_SUB_BLOCK(GFX_TCC_CACHE_DIRTY_BANK_0, 0, 1, 1, 1, 0, 0, 0,
336 0),
337 RAS_GFX_SUB_BLOCK(GFX_TCC_CACHE_DIRTY_BANK_1, 0, 1, 1, 1, 0, 0, 0,
338 0),
339 RAS_GFX_SUB_BLOCK(GFX_TCC_HIGH_RATE_TAG, 0, 1, 1, 1, 0, 0, 0, 0),
340 RAS_GFX_SUB_BLOCK(GFX_TCC_LOW_RATE_TAG, 0, 1, 1, 1, 0, 0, 0, 0),
341 RAS_GFX_SUB_BLOCK(GFX_TCC_IN_USE_DEC, 1, 0, 0, 1, 0, 0, 0, 0),
342 RAS_GFX_SUB_BLOCK(GFX_TCC_IN_USE_TRANSFER, 1, 0, 0, 1, 0, 0, 0, 0),
343 RAS_GFX_SUB_BLOCK(GFX_TCC_RETURN_DATA, 1, 0, 0, 1, 0, 0, 0, 0),
344 RAS_GFX_SUB_BLOCK(GFX_TCC_RETURN_CONTROL, 1, 0, 0, 1, 0, 0, 0, 0),
345 RAS_GFX_SUB_BLOCK(GFX_TCC_UC_ATOMIC_FIFO, 1, 0, 0, 1, 0, 0, 0, 0),
346 RAS_GFX_SUB_BLOCK(GFX_TCC_WRITE_RETURN, 1, 0, 0, 1, 0, 1, 1, 0),
347 RAS_GFX_SUB_BLOCK(GFX_TCC_WRITE_CACHE_READ, 1, 0, 0, 1, 0, 0, 0, 0),
348 RAS_GFX_SUB_BLOCK(GFX_TCC_SRC_FIFO, 0, 1, 1, 1, 0, 0, 0, 0),
349 RAS_GFX_SUB_BLOCK(GFX_TCC_SRC_FIFO_NEXT_RAM, 1, 0, 0, 1, 0, 0, 1, 0),
350 RAS_GFX_SUB_BLOCK(GFX_TCC_CACHE_TAG_PROBE_FIFO, 1, 0, 0, 1, 0, 0, 0,
351 0),
352 RAS_GFX_SUB_BLOCK(GFX_TCC_LATENCY_FIFO, 1, 0, 0, 1, 0, 0, 0, 0),
353 RAS_GFX_SUB_BLOCK(GFX_TCC_LATENCY_FIFO_NEXT_RAM, 1, 0, 0, 1, 0, 0, 0,
354 0),
355 RAS_GFX_SUB_BLOCK(GFX_TCC_WRRET_TAG_WRITE_RETURN, 1, 0, 0, 1, 0, 0,
356 0, 0),
357 RAS_GFX_SUB_BLOCK(GFX_TCC_ATOMIC_RETURN_BUFFER, 1, 0, 0, 1, 0, 0, 0,
358 0),
359 RAS_GFX_SUB_BLOCK(GFX_TCI_WRITE_RAM, 1, 0, 0, 1, 0, 0, 0, 0),
360 RAS_GFX_SUB_BLOCK(GFX_TCP_CACHE_RAM, 0, 1, 1, 1, 1, 0, 0, 1),
361 RAS_GFX_SUB_BLOCK(GFX_TCP_LFIFO_RAM, 0, 1, 1, 1, 0, 0, 0, 0),
362 RAS_GFX_SUB_BLOCK(GFX_TCP_CMD_FIFO, 1, 0, 0, 1, 0, 0, 0, 0),
363 RAS_GFX_SUB_BLOCK(GFX_TCP_VM_FIFO, 0, 1, 1, 1, 0, 0, 0, 0),
364 RAS_GFX_SUB_BLOCK(GFX_TCP_DB_RAM, 1, 0, 0, 1, 0, 0, 0, 0),
365 RAS_GFX_SUB_BLOCK(GFX_TCP_UTCL1_LFIFO0, 0, 1, 1, 1, 0, 0, 0, 0),
366 RAS_GFX_SUB_BLOCK(GFX_TCP_UTCL1_LFIFO1, 0, 1, 1, 1, 0, 0, 0, 0),
367 RAS_GFX_SUB_BLOCK(GFX_TD_SS_FIFO_LO, 0, 1, 1, 1, 1, 0, 0, 1),
368 RAS_GFX_SUB_BLOCK(GFX_TD_SS_FIFO_HI, 0, 1, 1, 1, 0, 0, 0, 0),
369 RAS_GFX_SUB_BLOCK(GFX_TD_CS_FIFO, 1, 0, 0, 1, 0, 0, 0, 0),
370 RAS_GFX_SUB_BLOCK(GFX_EA_DRAMRD_CMDMEM, 0, 1, 1, 1, 1, 0, 0, 1),
371 RAS_GFX_SUB_BLOCK(GFX_EA_DRAMWR_CMDMEM, 0, 1, 1, 1, 0, 0, 0, 0),
372 RAS_GFX_SUB_BLOCK(GFX_EA_DRAMWR_DATAMEM, 0, 1, 1, 1, 0, 0, 0, 0),
373 RAS_GFX_SUB_BLOCK(GFX_EA_RRET_TAGMEM, 0, 1, 1, 1, 0, 0, 0, 0),
374 RAS_GFX_SUB_BLOCK(GFX_EA_WRET_TAGMEM, 0, 1, 1, 1, 0, 0, 0, 0),
375 RAS_GFX_SUB_BLOCK(GFX_EA_GMIRD_CMDMEM, 0, 1, 1, 1, 0, 0, 0, 0),
376 RAS_GFX_SUB_BLOCK(GFX_EA_GMIWR_CMDMEM, 0, 1, 1, 1, 0, 0, 0, 0),
377 RAS_GFX_SUB_BLOCK(GFX_EA_GMIWR_DATAMEM, 0, 1, 1, 1, 0, 0, 0, 0),
378 RAS_GFX_SUB_BLOCK(GFX_EA_DRAMRD_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0),
379 RAS_GFX_SUB_BLOCK(GFX_EA_DRAMWR_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0),
380 RAS_GFX_SUB_BLOCK(GFX_EA_IORD_CMDMEM, 1, 0, 0, 1, 0, 0, 0, 0),
381 RAS_GFX_SUB_BLOCK(GFX_EA_IOWR_CMDMEM, 1, 0, 0, 1, 0, 0, 0, 0),
382 RAS_GFX_SUB_BLOCK(GFX_EA_IOWR_DATAMEM, 1, 0, 0, 1, 0, 0, 0, 0),
383 RAS_GFX_SUB_BLOCK(GFX_EA_GMIRD_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0),
384 RAS_GFX_SUB_BLOCK(GFX_EA_GMIWR_PAGEMEM, 1, 0, 0, 1, 0, 0, 0, 0),
385 RAS_GFX_SUB_BLOCK(GFX_EA_MAM_D0MEM, 1, 0, 0, 1, 0, 0, 0, 0),
386 RAS_GFX_SUB_BLOCK(GFX_EA_MAM_D1MEM, 1, 0, 0, 1, 0, 0, 0, 0),
387 RAS_GFX_SUB_BLOCK(GFX_EA_MAM_D2MEM, 1, 0, 0, 1, 0, 0, 0, 0),
388 RAS_GFX_SUB_BLOCK(GFX_EA_MAM_D3MEM, 1, 0, 0, 1, 0, 0, 0, 0),
389 RAS_GFX_SUB_BLOCK(UTC_VML2_BANK_CACHE, 0, 1, 1, 1, 0, 0, 0, 0),
390 RAS_GFX_SUB_BLOCK(UTC_VML2_WALKER, 0, 1, 1, 1, 0, 0, 0, 0),
391 RAS_GFX_SUB_BLOCK(UTC_ATCL2_CACHE_2M_BANK, 1, 0, 0, 1, 0, 0, 0, 0),
392 RAS_GFX_SUB_BLOCK(UTC_ATCL2_CACHE_4K_BANK, 0, 1, 1, 1, 0, 0, 0, 0),
393};
394
395static int gfx_v9_0_get_ta_subblock(struct ras_core_context *ras_core,
396 uint32_t error_type, uint32_t subblock, uint32_t *ta_subblock)
397{
398 const struct ras_gfx_subblock_t *gfx_subblock;
399
400 if (subblock >= ARRAY_SIZE(ras_gfx_v9_0_subblocks))
401 return -EINVAL;
402
403 gfx_subblock = &ras_gfx_v9_0_subblocks[subblock];
404 if (!gfx_subblock->name)
405 return -EPERM;
406
407 if (!(gfx_subblock->hw_supported_error_type & error_type)) {
408 RAS_DEV_ERR(ras_core->dev, "GFX Subblock %s, hardware do not support type 0x%x\n",
409 gfx_subblock->name, error_type);
410 return -EPERM;
411 }
412
413 if (!(gfx_subblock->sw_supported_error_type & error_type)) {
414 RAS_DEV_ERR(ras_core->dev, "GFX Subblock %s, driver do not support type 0x%x\n",
415 gfx_subblock->name, error_type);
416 return -EPERM;
417 }
418
419 *ta_subblock = gfx_subblock->ta_subblock;
420
421 return 0;
422}
423
424const struct ras_gfx_ip_func gfx_ras_func_v9_0 = {
425 .get_ta_subblock = gfx_v9_0_get_ta_subblock,
426};
427

source code of linux/drivers/gpu/drm/amd/ras/rascore/ras_gfx_v9_0.c