1/* SPDX-License-Identifier: MIT */
2/*
3 * Copyright 2025 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 */
24#ifndef __RAS_GFX_V9_0_H__
25#define __RAS_GFX_V9_0_H__
26
27enum ras_gfx_v9_subblock {
28 /* CPC */
29 RAS_GFX_V9__GFX_CPC_INDEX_START = 0,
30 RAS_GFX_V9__GFX_CPC_SCRATCH =
31 RAS_GFX_V9__GFX_CPC_INDEX_START,
32 RAS_GFX_V9__GFX_CPC_UCODE,
33 RAS_GFX_V9__GFX_DC_STATE_ME1,
34 RAS_GFX_V9__GFX_DC_CSINVOC_ME1,
35 RAS_GFX_V9__GFX_DC_RESTORE_ME1,
36 RAS_GFX_V9__GFX_DC_STATE_ME2,
37 RAS_GFX_V9__GFX_DC_CSINVOC_ME2,
38 RAS_GFX_V9__GFX_DC_RESTORE_ME2,
39 RAS_GFX_V9__GFX_CPC_INDEX_END =
40 RAS_GFX_V9__GFX_DC_RESTORE_ME2,
41 /* CPF */
42 RAS_GFX_V9__GFX_CPF_INDEX_START,
43 RAS_GFX_V9__GFX_CPF_ROQ_ME2 =
44 RAS_GFX_V9__GFX_CPF_INDEX_START,
45 RAS_GFX_V9__GFX_CPF_ROQ_ME1,
46 RAS_GFX_V9__GFX_CPF_TAG,
47 RAS_GFX_V9__GFX_CPF_INDEX_END = RAS_GFX_V9__GFX_CPF_TAG,
48 /* CPG */
49 RAS_GFX_V9__GFX_CPG_INDEX_START,
50 RAS_GFX_V9__GFX_CPG_DMA_ROQ =
51 RAS_GFX_V9__GFX_CPG_INDEX_START,
52 RAS_GFX_V9__GFX_CPG_DMA_TAG,
53 RAS_GFX_V9__GFX_CPG_TAG,
54 RAS_GFX_V9__GFX_CPG_INDEX_END = RAS_GFX_V9__GFX_CPG_TAG,
55 /* GDS */
56 RAS_GFX_V9__GFX_GDS_INDEX_START,
57 RAS_GFX_V9__GFX_GDS_MEM = RAS_GFX_V9__GFX_GDS_INDEX_START,
58 RAS_GFX_V9__GFX_GDS_INPUT_QUEUE,
59 RAS_GFX_V9__GFX_GDS_OA_PHY_CMD_RAM_MEM,
60 RAS_GFX_V9__GFX_GDS_OA_PHY_DATA_RAM_MEM,
61 RAS_GFX_V9__GFX_GDS_OA_PIPE_MEM,
62 RAS_GFX_V9__GFX_GDS_INDEX_END =
63 RAS_GFX_V9__GFX_GDS_OA_PIPE_MEM,
64 /* SPI */
65 RAS_GFX_V9__GFX_SPI_SR_MEM,
66 /* SQ */
67 RAS_GFX_V9__GFX_SQ_INDEX_START,
68 RAS_GFX_V9__GFX_SQ_SGPR = RAS_GFX_V9__GFX_SQ_INDEX_START,
69 RAS_GFX_V9__GFX_SQ_LDS_D,
70 RAS_GFX_V9__GFX_SQ_LDS_I,
71 RAS_GFX_V9__GFX_SQ_VGPR,
72 RAS_GFX_V9__GFX_SQ_INDEX_END = RAS_GFX_V9__GFX_SQ_VGPR,
73 /* SQC (3 ranges) */
74 RAS_GFX_V9__GFX_SQC_INDEX_START,
75 /* SQC range 0 */
76 RAS_GFX_V9__GFX_SQC_INDEX0_START =
77 RAS_GFX_V9__GFX_SQC_INDEX_START,
78 RAS_GFX_V9__GFX_SQC_INST_UTCL1_LFIFO =
79 RAS_GFX_V9__GFX_SQC_INDEX0_START,
80 RAS_GFX_V9__GFX_SQC_DATA_CU0_WRITE_DATA_BUF,
81 RAS_GFX_V9__GFX_SQC_DATA_CU0_UTCL1_LFIFO,
82 RAS_GFX_V9__GFX_SQC_DATA_CU1_WRITE_DATA_BUF,
83 RAS_GFX_V9__GFX_SQC_DATA_CU1_UTCL1_LFIFO,
84 RAS_GFX_V9__GFX_SQC_DATA_CU2_WRITE_DATA_BUF,
85 RAS_GFX_V9__GFX_SQC_DATA_CU2_UTCL1_LFIFO,
86 RAS_GFX_V9__GFX_SQC_INDEX0_END =
87 RAS_GFX_V9__GFX_SQC_DATA_CU2_UTCL1_LFIFO,
88 /* SQC range 1 */
89 RAS_GFX_V9__GFX_SQC_INDEX1_START,
90 RAS_GFX_V9__GFX_SQC_INST_BANKA_TAG_RAM =
91 RAS_GFX_V9__GFX_SQC_INDEX1_START,
92 RAS_GFX_V9__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO,
93 RAS_GFX_V9__GFX_SQC_INST_BANKA_MISS_FIFO,
94 RAS_GFX_V9__GFX_SQC_INST_BANKA_BANK_RAM,
95 RAS_GFX_V9__GFX_SQC_DATA_BANKA_TAG_RAM,
96 RAS_GFX_V9__GFX_SQC_DATA_BANKA_HIT_FIFO,
97 RAS_GFX_V9__GFX_SQC_DATA_BANKA_MISS_FIFO,
98 RAS_GFX_V9__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM,
99 RAS_GFX_V9__GFX_SQC_DATA_BANKA_BANK_RAM,
100 RAS_GFX_V9__GFX_SQC_INDEX1_END =
101 RAS_GFX_V9__GFX_SQC_DATA_BANKA_BANK_RAM,
102 /* SQC range 2 */
103 RAS_GFX_V9__GFX_SQC_INDEX2_START,
104 RAS_GFX_V9__GFX_SQC_INST_BANKB_TAG_RAM =
105 RAS_GFX_V9__GFX_SQC_INDEX2_START,
106 RAS_GFX_V9__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO,
107 RAS_GFX_V9__GFX_SQC_INST_BANKB_MISS_FIFO,
108 RAS_GFX_V9__GFX_SQC_INST_BANKB_BANK_RAM,
109 RAS_GFX_V9__GFX_SQC_DATA_BANKB_TAG_RAM,
110 RAS_GFX_V9__GFX_SQC_DATA_BANKB_HIT_FIFO,
111 RAS_GFX_V9__GFX_SQC_DATA_BANKB_MISS_FIFO,
112 RAS_GFX_V9__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM,
113 RAS_GFX_V9__GFX_SQC_DATA_BANKB_BANK_RAM,
114 RAS_GFX_V9__GFX_SQC_INDEX2_END =
115 RAS_GFX_V9__GFX_SQC_DATA_BANKB_BANK_RAM,
116 RAS_GFX_V9__GFX_SQC_INDEX_END =
117 RAS_GFX_V9__GFX_SQC_INDEX2_END,
118 /* TA */
119 RAS_GFX_V9__GFX_TA_INDEX_START,
120 RAS_GFX_V9__GFX_TA_FS_DFIFO =
121 RAS_GFX_V9__GFX_TA_INDEX_START,
122 RAS_GFX_V9__GFX_TA_FS_AFIFO,
123 RAS_GFX_V9__GFX_TA_FL_LFIFO,
124 RAS_GFX_V9__GFX_TA_FX_LFIFO,
125 RAS_GFX_V9__GFX_TA_FS_CFIFO,
126 RAS_GFX_V9__GFX_TA_INDEX_END = RAS_GFX_V9__GFX_TA_FS_CFIFO,
127 /* TCA */
128 RAS_GFX_V9__GFX_TCA_INDEX_START,
129 RAS_GFX_V9__GFX_TCA_HOLE_FIFO =
130 RAS_GFX_V9__GFX_TCA_INDEX_START,
131 RAS_GFX_V9__GFX_TCA_REQ_FIFO,
132 RAS_GFX_V9__GFX_TCA_INDEX_END =
133 RAS_GFX_V9__GFX_TCA_REQ_FIFO,
134 /* TCC (5 sub-ranges) */
135 RAS_GFX_V9__GFX_TCC_INDEX_START,
136 /* TCC range 0 */
137 RAS_GFX_V9__GFX_TCC_INDEX0_START =
138 RAS_GFX_V9__GFX_TCC_INDEX_START,
139 RAS_GFX_V9__GFX_TCC_CACHE_DATA =
140 RAS_GFX_V9__GFX_TCC_INDEX0_START,
141 RAS_GFX_V9__GFX_TCC_CACHE_DATA_BANK_0_1,
142 RAS_GFX_V9__GFX_TCC_CACHE_DATA_BANK_1_0,
143 RAS_GFX_V9__GFX_TCC_CACHE_DATA_BANK_1_1,
144 RAS_GFX_V9__GFX_TCC_CACHE_DIRTY_BANK_0,
145 RAS_GFX_V9__GFX_TCC_CACHE_DIRTY_BANK_1,
146 RAS_GFX_V9__GFX_TCC_HIGH_RATE_TAG,
147 RAS_GFX_V9__GFX_TCC_LOW_RATE_TAG,
148 RAS_GFX_V9__GFX_TCC_INDEX0_END =
149 RAS_GFX_V9__GFX_TCC_LOW_RATE_TAG,
150 /* TCC range 1 */
151 RAS_GFX_V9__GFX_TCC_INDEX1_START,
152 RAS_GFX_V9__GFX_TCC_IN_USE_DEC =
153 RAS_GFX_V9__GFX_TCC_INDEX1_START,
154 RAS_GFX_V9__GFX_TCC_IN_USE_TRANSFER,
155 RAS_GFX_V9__GFX_TCC_INDEX1_END =
156 RAS_GFX_V9__GFX_TCC_IN_USE_TRANSFER,
157 /* TCC range 2 */
158 RAS_GFX_V9__GFX_TCC_INDEX2_START,
159 RAS_GFX_V9__GFX_TCC_RETURN_DATA =
160 RAS_GFX_V9__GFX_TCC_INDEX2_START,
161 RAS_GFX_V9__GFX_TCC_RETURN_CONTROL,
162 RAS_GFX_V9__GFX_TCC_UC_ATOMIC_FIFO,
163 RAS_GFX_V9__GFX_TCC_WRITE_RETURN,
164 RAS_GFX_V9__GFX_TCC_WRITE_CACHE_READ,
165 RAS_GFX_V9__GFX_TCC_SRC_FIFO,
166 RAS_GFX_V9__GFX_TCC_SRC_FIFO_NEXT_RAM,
167 RAS_GFX_V9__GFX_TCC_CACHE_TAG_PROBE_FIFO,
168 RAS_GFX_V9__GFX_TCC_INDEX2_END =
169 RAS_GFX_V9__GFX_TCC_CACHE_TAG_PROBE_FIFO,
170 /* TCC range 3 */
171 RAS_GFX_V9__GFX_TCC_INDEX3_START,
172 RAS_GFX_V9__GFX_TCC_LATENCY_FIFO =
173 RAS_GFX_V9__GFX_TCC_INDEX3_START,
174 RAS_GFX_V9__GFX_TCC_LATENCY_FIFO_NEXT_RAM,
175 RAS_GFX_V9__GFX_TCC_INDEX3_END =
176 RAS_GFX_V9__GFX_TCC_LATENCY_FIFO_NEXT_RAM,
177 /* TCC range 4 */
178 RAS_GFX_V9__GFX_TCC_INDEX4_START,
179 RAS_GFX_V9__GFX_TCC_WRRET_TAG_WRITE_RETURN =
180 RAS_GFX_V9__GFX_TCC_INDEX4_START,
181 RAS_GFX_V9__GFX_TCC_ATOMIC_RETURN_BUFFER,
182 RAS_GFX_V9__GFX_TCC_INDEX4_END =
183 RAS_GFX_V9__GFX_TCC_ATOMIC_RETURN_BUFFER,
184 RAS_GFX_V9__GFX_TCC_INDEX_END =
185 RAS_GFX_V9__GFX_TCC_INDEX4_END,
186 /* TCI */
187 RAS_GFX_V9__GFX_TCI_WRITE_RAM,
188 /* TCP */
189 RAS_GFX_V9__GFX_TCP_INDEX_START,
190 RAS_GFX_V9__GFX_TCP_CACHE_RAM =
191 RAS_GFX_V9__GFX_TCP_INDEX_START,
192 RAS_GFX_V9__GFX_TCP_LFIFO_RAM,
193 RAS_GFX_V9__GFX_TCP_CMD_FIFO,
194 RAS_GFX_V9__GFX_TCP_VM_FIFO,
195 RAS_GFX_V9__GFX_TCP_DB_RAM,
196 RAS_GFX_V9__GFX_TCP_UTCL1_LFIFO0,
197 RAS_GFX_V9__GFX_TCP_UTCL1_LFIFO1,
198 RAS_GFX_V9__GFX_TCP_INDEX_END =
199 RAS_GFX_V9__GFX_TCP_UTCL1_LFIFO1,
200 /* TD */
201 RAS_GFX_V9__GFX_TD_INDEX_START,
202 RAS_GFX_V9__GFX_TD_SS_FIFO_LO =
203 RAS_GFX_V9__GFX_TD_INDEX_START,
204 RAS_GFX_V9__GFX_TD_SS_FIFO_HI,
205 RAS_GFX_V9__GFX_TD_CS_FIFO,
206 RAS_GFX_V9__GFX_TD_INDEX_END = RAS_GFX_V9__GFX_TD_CS_FIFO,
207 /* EA (3 sub-ranges) */
208 RAS_GFX_V9__GFX_EA_INDEX_START,
209 /* EA range 0 */
210 RAS_GFX_V9__GFX_EA_INDEX0_START =
211 RAS_GFX_V9__GFX_EA_INDEX_START,
212 RAS_GFX_V9__GFX_EA_DRAMRD_CMDMEM =
213 RAS_GFX_V9__GFX_EA_INDEX0_START,
214 RAS_GFX_V9__GFX_EA_DRAMWR_CMDMEM,
215 RAS_GFX_V9__GFX_EA_DRAMWR_DATAMEM,
216 RAS_GFX_V9__GFX_EA_RRET_TAGMEM,
217 RAS_GFX_V9__GFX_EA_WRET_TAGMEM,
218 RAS_GFX_V9__GFX_EA_GMIRD_CMDMEM,
219 RAS_GFX_V9__GFX_EA_GMIWR_CMDMEM,
220 RAS_GFX_V9__GFX_EA_GMIWR_DATAMEM,
221 RAS_GFX_V9__GFX_EA_INDEX0_END =
222 RAS_GFX_V9__GFX_EA_GMIWR_DATAMEM,
223 /* EA range 1 */
224 RAS_GFX_V9__GFX_EA_INDEX1_START,
225 RAS_GFX_V9__GFX_EA_DRAMRD_PAGEMEM =
226 RAS_GFX_V9__GFX_EA_INDEX1_START,
227 RAS_GFX_V9__GFX_EA_DRAMWR_PAGEMEM,
228 RAS_GFX_V9__GFX_EA_IORD_CMDMEM,
229 RAS_GFX_V9__GFX_EA_IOWR_CMDMEM,
230 RAS_GFX_V9__GFX_EA_IOWR_DATAMEM,
231 RAS_GFX_V9__GFX_EA_GMIRD_PAGEMEM,
232 RAS_GFX_V9__GFX_EA_GMIWR_PAGEMEM,
233 RAS_GFX_V9__GFX_EA_INDEX1_END =
234 RAS_GFX_V9__GFX_EA_GMIWR_PAGEMEM,
235 /* EA range 2 */
236 RAS_GFX_V9__GFX_EA_INDEX2_START,
237 RAS_GFX_V9__GFX_EA_MAM_D0MEM =
238 RAS_GFX_V9__GFX_EA_INDEX2_START,
239 RAS_GFX_V9__GFX_EA_MAM_D1MEM,
240 RAS_GFX_V9__GFX_EA_MAM_D2MEM,
241 RAS_GFX_V9__GFX_EA_MAM_D3MEM,
242 RAS_GFX_V9__GFX_EA_INDEX2_END =
243 RAS_GFX_V9__GFX_EA_MAM_D3MEM,
244 RAS_GFX_V9__GFX_EA_INDEX_END =
245 RAS_GFX_V9__GFX_EA_INDEX2_END,
246 /* UTC VM L2 bank */
247 RAS_GFX_V9__UTC_VML2_BANK_CACHE,
248 /* UTC VM walker */
249 RAS_GFX_V9__UTC_VML2_WALKER,
250 /* UTC ATC L2 2MB cache */
251 RAS_GFX_V9__UTC_ATCL2_CACHE_2M_BANK,
252 /* UTC ATC L2 4KB cache */
253 RAS_GFX_V9__UTC_ATCL2_CACHE_4K_BANK,
254 RAS_GFX_V9__GFX_MAX
255};
256
257extern const struct ras_gfx_ip_func gfx_ras_func_v9_0;
258
259#endif
260

source code of linux/drivers/gpu/drm/amd/ras/rascore/ras_gfx_v9_0.h