1/*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#ifndef __DAL_HUBP_H__
27#define __DAL_HUBP_H__
28
29/**
30 * DOC: overview
31 *
32 * Display Controller Hub (DCHUB) is the gateway between the Scalable Data Port
33 * (SDP) and DCN. This component has multiple features, such as memory
34 * arbitration, rotation, and cursor manipulation.
35 *
36 * There is one HUBP allocated per pipe, which fetches data and converts
37 * different pixel formats (i.e. ARGB8888, NV12, etc) into linear, interleaved
38 * and fixed-depth streams of pixel data.
39 */
40
41#include "mem_input.h"
42#include "cursor_reg_cache.h"
43
44#include "dml2_0/dml21/inc/dml_top_dchub_registers.h"
45#include "dml2_0/dml21/inc/dml_top_types.h"
46
47#define OPP_ID_INVALID 0xf
48#define MAX_TTU 0xffffff
49
50enum cursor_pitch {
51 CURSOR_PITCH_64_PIXELS = 0,
52 CURSOR_PITCH_128_PIXELS,
53 CURSOR_PITCH_256_PIXELS
54};
55
56enum cursor_lines_per_chunk {
57 CURSOR_LINE_PER_CHUNK_1 = 0, /* new for DCN2 */
58 CURSOR_LINE_PER_CHUNK_2 = 1,
59 CURSOR_LINE_PER_CHUNK_4,
60 CURSOR_LINE_PER_CHUNK_8,
61 CURSOR_LINE_PER_CHUNK_16
62};
63
64enum hubp_ind_block_size {
65 hubp_ind_block_unconstrained = 0,
66 hubp_ind_block_64b,
67 hubp_ind_block_128b,
68 hubp_ind_block_64b_no_128bcl,
69};
70
71enum hubp_3dlut_fl_mode {
72 hubp_3dlut_fl_mode_disable = 0,
73 hubp_3dlut_fl_mode_native_1 = 1,
74 hubp_3dlut_fl_mode_native_2 = 2,
75 hubp_3dlut_fl_mode_transform = 3
76};
77
78enum hubp_3dlut_fl_format {
79 hubp_3dlut_fl_format_unorm_12msb_bitslice = 0,
80 hubp_3dlut_fl_format_unorm_12lsb_bitslice = 1,
81 hubp_3dlut_fl_format_float_fp1_5_10 = 2
82};
83
84enum hubp_3dlut_fl_addressing_mode {
85 hubp_3dlut_fl_addressing_mode_sw_linear = 0,
86 hubp_3dlut_fl_addressing_mode_simple_linear = 1
87};
88
89enum hubp_3dlut_fl_width {
90 hubp_3dlut_fl_width_17 = 17,
91 hubp_3dlut_fl_width_33 = 33,
92 hubp_3dlut_fl_width_transformed = 4916, //mpc default
93};
94
95enum hubp_3dlut_fl_crossbar_bit_slice {
96 hubp_3dlut_fl_crossbar_bit_slice_0_15 = 0,
97 hubp_3dlut_fl_crossbar_bit_slice_16_31 = 1,
98 hubp_3dlut_fl_crossbar_bit_slice_32_47 = 2,
99 hubp_3dlut_fl_crossbar_bit_slice_48_63 = 3
100};
101
102struct hubp_fl_3dlut_config {
103 bool enabled;
104 enum hubp_3dlut_fl_width width;
105 enum hubp_3dlut_fl_mode mode;
106 enum hubp_3dlut_fl_format format;
107 uint16_t bias;
108 uint16_t scale;
109 struct dc_plane_address address;
110 enum hubp_3dlut_fl_addressing_mode addr_mode;
111 enum dc_cm2_gpu_mem_layout layout;
112 uint8_t protection_bits;
113 enum hubp_3dlut_fl_crossbar_bit_slice crossbar_bit_slice_y_g;
114 enum hubp_3dlut_fl_crossbar_bit_slice crossbar_bit_slice_cb_b;
115 enum hubp_3dlut_fl_crossbar_bit_slice crossbar_bit_slice_cr_r;
116};
117
118struct hubp {
119 const struct hubp_funcs *funcs;
120 struct dc_context *ctx;
121 struct dc_plane_address request_address;
122 int inst;
123
124 /* run time states */
125 int opp_id;
126 int mpcc_id;
127 struct dc_cursor_attributes curs_attr;
128 struct dc_cursor_position curs_pos;
129 bool cursor_offload;
130 bool power_gated;
131
132 struct cursor_position_cache_hubp pos;
133 struct cursor_attribute_cache_hubp att;
134 struct cursor_rect cur_rect;
135 bool use_mall_for_cursor;
136};
137
138struct surface_flip_registers {
139 uint32_t DCSURF_SURFACE_CONTROL;
140 uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH;
141 uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS;
142 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH;
143 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS;
144 uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C;
145 uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_C;
146 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C;
147 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C;
148 uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH;
149 uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS;
150 uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH;
151 uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS;
152 bool tmz_surface;
153 bool immediate;
154 uint8_t vmid;
155 bool grph_stereo;
156};
157
158struct hubp_funcs {
159 void (*hubp_setup)(
160 struct hubp *hubp,
161 struct _vcs_dpi_display_dlg_regs_st *dlg_regs,
162 struct _vcs_dpi_display_ttu_regs_st *ttu_regs,
163 struct _vcs_dpi_display_rq_regs_st *rq_regs,
164 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest);
165
166 void (*hubp_setup2)(
167 struct hubp *hubp,
168 struct dml2_dchub_per_pipe_register_set *pipe_regs,
169 union dml2_global_sync_programming *pipe_global_sync,
170 struct dc_crtc_timing *timing);
171
172 void (*hubp_setup_interdependent)(
173 struct hubp *hubp,
174 struct _vcs_dpi_display_dlg_regs_st *dlg_regs,
175 struct _vcs_dpi_display_ttu_regs_st *ttu_regs);
176
177 void (*hubp_setup_interdependent2)(
178 struct hubp *hubp,
179 struct dml2_dchub_per_pipe_register_set *pipe_regs);
180
181 void (*dcc_control)(struct hubp *hubp, bool enable,
182 enum hubp_ind_block_size blk_size);
183
184 void (*hubp_reset)(struct hubp *hubp);
185
186 void (*mem_program_viewport)(
187 struct hubp *hubp,
188 const struct rect *viewport,
189 const struct rect *viewport_c);
190
191 bool (*hubp_program_surface_flip_and_addr)(
192 struct hubp *hubp,
193 const struct dc_plane_address *address,
194 bool flip_immediate);
195
196 void (*hubp_program_pte_vm)(
197 struct hubp *hubp,
198 enum surface_pixel_format format,
199 struct dc_tiling_info *tiling_info,
200 enum dc_rotation_angle rotation);
201
202 void (*hubp_set_vm_system_aperture_settings)(
203 struct hubp *hubp,
204 struct vm_system_aperture_param *apt);
205
206 void (*hubp_set_vm_context0_settings)(
207 struct hubp *hubp,
208 const struct vm_context0_param *vm0);
209
210 void (*hubp_program_surface_config)(
211 struct hubp *hubp,
212 enum surface_pixel_format format,
213 struct dc_tiling_info *tiling_info,
214 struct plane_size *plane_size,
215 enum dc_rotation_angle rotation,
216 struct dc_plane_dcc_param *dcc,
217 bool horizontal_mirror,
218 unsigned int compa_level);
219
220 bool (*hubp_is_flip_pending)(struct hubp *hubp);
221
222 void (*set_blank)(struct hubp *hubp, bool blank);
223 void (*set_blank_regs)(struct hubp *hubp, bool blank);
224 void (*phantom_hubp_post_enable)(struct hubp *hubp);
225 void (*set_hubp_blank_en)(struct hubp *hubp, bool blank);
226
227 void (*set_cursor_attributes)(
228 struct hubp *hubp,
229 const struct dc_cursor_attributes *attr);
230
231 void (*set_cursor_position)(
232 struct hubp *hubp,
233 const struct dc_cursor_position *pos,
234 const struct dc_cursor_mi_param *param);
235
236 void (*hubp_disconnect)(struct hubp *hubp);
237
238 void (*hubp_clk_cntl)(struct hubp *hubp, bool enable);
239 void (*hubp_vtg_sel)(struct hubp *hubp, uint32_t otg_inst);
240 void (*hubp_read_state)(struct hubp *hubp);
241 void (*hubp_read_reg_state)(struct hubp *hubp, struct dcn_hubp_reg_state *reg_state);
242 void (*hubp_clear_underflow)(struct hubp *hubp);
243 void (*hubp_disable_control)(struct hubp *hubp, bool disable_hubp);
244 unsigned int (*hubp_get_underflow_status)(struct hubp *hubp);
245 void (*hubp_init)(struct hubp *hubp);
246
247 void (*dmdata_set_attributes)(
248 struct hubp *hubp,
249 const struct dc_dmdata_attributes *attr);
250
251 void (*dmdata_load)(
252 struct hubp *hubp,
253 uint32_t dmdata_sw_size,
254 const uint32_t *dmdata_sw_data);
255 bool (*dmdata_status_done)(struct hubp *hubp);
256 void (*hubp_enable_tripleBuffer)(
257 struct hubp *hubp,
258 bool enable);
259
260 bool (*hubp_is_triplebuffer_enabled)(
261 struct hubp *hubp);
262
263 void (*hubp_set_flip_control_surface_gsl)(
264 struct hubp *hubp,
265 bool enable);
266
267 void (*validate_dml_output)(
268 struct hubp *hubp,
269 struct dc_context *ctx,
270 struct _vcs_dpi_display_rq_regs_st *dml_rq_regs,
271 struct _vcs_dpi_display_dlg_regs_st *dml_dlg_attr,
272 struct _vcs_dpi_display_ttu_regs_st *dml_ttu_attr);
273 void (*set_unbounded_requesting)(
274 struct hubp *hubp,
275 bool enable);
276 bool (*hubp_in_blank)(struct hubp *hubp);
277 void (*hubp_soft_reset)(struct hubp *hubp, bool reset);
278
279 void (*hubp_set_flip_int)(struct hubp *hubp);
280
281 void (*hubp_update_force_pstate_disallow)(struct hubp *hubp, bool allow);
282 void (*hubp_update_force_cursor_pstate_disallow)(struct hubp *hubp, bool allow);
283 void (*hubp_update_mall_sel)(struct hubp *hubp, uint32_t mall_sel, bool c_cursor);
284 void (*hubp_prepare_subvp_buffering)(struct hubp *hubp, bool enable);
285 void (*hubp_surface_update_lock)(struct hubp *hubp,
286 bool lock);
287
288 void (*program_extended_blank)(struct hubp *hubp,
289 unsigned int min_dst_y_next_start_optimized);
290
291 void (*hubp_wait_pipe_read_start)(struct hubp *hubp);
292 void (*hubp_program_mcache_id_and_split_coordinate)(struct hubp *hubp, struct dml2_hubp_pipe_mcache_regs *mcache_regs);
293 void (*hubp_update_3dlut_fl_bias_scale)(struct hubp *hubp, uint16_t bias, uint16_t scale);
294 void (*hubp_program_3dlut_fl_mode)(struct hubp *hubp,
295 enum hubp_3dlut_fl_mode mode);
296 void (*hubp_program_3dlut_fl_format)(struct hubp *hubp,
297 enum hubp_3dlut_fl_format format);
298 void (*hubp_program_3dlut_fl_addr)(struct hubp *hubp,
299 const struct dc_plane_address address);
300 void (*hubp_program_3dlut_fl_dlg_param)(struct hubp *hubp, int refcyc_per_3dlut_group);
301 void (*hubp_enable_3dlut_fl)(struct hubp *hubp, bool enable);
302 void (*hubp_program_3dlut_fl_addressing_mode)(struct hubp *hubp, enum hubp_3dlut_fl_addressing_mode addr_mode);
303 void (*hubp_program_3dlut_fl_width)(struct hubp *hubp, enum hubp_3dlut_fl_width width);
304 void (*hubp_program_3dlut_fl_tmz_protected)(struct hubp *hubp, uint8_t protection_bits);
305 void (*hubp_program_3dlut_fl_crossbar)(struct hubp *hubp,
306 enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_y_g,
307 enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_cb_b,
308 enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_cr_r);
309 int (*hubp_get_3dlut_fl_done)(struct hubp *hubp);
310 void (*hubp_program_3dlut_fl_config)(struct hubp *hubp, struct hubp_fl_3dlut_config *cfg);
311 void (*hubp_clear_tiling)(struct hubp *hubp);
312 uint32_t (*hubp_get_current_read_line)(struct hubp *hubp);
313 uint32_t (*hubp_get_det_config_error)(struct hubp *hubp);
314};
315
316#endif
317

source code of linux/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h