1/* SPDX-License-Identifier: MIT */
2/* Copyright © 2022 Advanced Micro Devices, Inc. All rights reserved. */
3
4#ifndef __DAL_CURSOR_CACHE_H__
5#define __DAL_CURSOR_CACHE_H__
6
7union reg_cursor_control_cfg {
8 struct {
9 uint32_t cur_enable: 1;
10 uint32_t reser0: 3;
11 uint32_t cur_2x_magnify: 1;
12 uint32_t reser1: 3;
13 uint32_t mode: 3;
14 uint32_t reser2: 5;
15 uint32_t pitch: 2;
16 uint32_t reser3: 6;
17 uint32_t line_per_chunk: 5;
18 uint32_t reser4: 3;
19 } bits;
20 uint32_t raw;
21};
22struct cursor_position_cache_hubp {
23 union reg_cursor_control_cfg cur_ctl;
24 union reg_position_cfg {
25 struct {
26 uint32_t x_pos: 16;
27 uint32_t y_pos: 16;
28 } bits;
29 uint32_t raw;
30 } position;
31 union reg_hot_spot_cfg {
32 struct {
33 uint32_t x_hot: 16;
34 uint32_t y_hot: 16;
35 } bits;
36 uint32_t raw;
37 } hot_spot;
38 union reg_dst_offset_cfg {
39 struct {
40 uint32_t dst_x_offset: 13;
41 uint32_t reserved: 19;
42 } bits;
43 uint32_t raw;
44 } dst_offset;
45};
46
47struct cursor_attribute_cache_hubp {
48 uint32_t SURFACE_ADDR_HIGH;
49 uint32_t SURFACE_ADDR;
50 union reg_cursor_control_cfg cur_ctl;
51 union reg_cursor_size_cfg {
52 struct {
53 uint32_t width: 16;
54 uint32_t height: 16;
55 } bits;
56 uint32_t raw;
57 } size;
58 union reg_cursor_settings_cfg {
59 struct {
60 uint32_t dst_y_offset: 8;
61 uint32_t chunk_hdl_adjust: 2;
62 uint32_t reserved: 22;
63 } bits;
64 uint32_t raw;
65 } settings;
66};
67
68struct cursor_rect {
69 uint32_t x;
70 uint32_t y;
71 uint32_t w;
72 uint32_t h;
73};
74
75union reg_cur0_control_cfg {
76 struct {
77 uint32_t cur0_enable: 1;
78 uint32_t expansion_mode: 1;
79 uint32_t reser0: 1;
80 uint32_t cur0_rom_en: 1;
81 uint32_t mode: 3;
82 uint32_t reserved: 25;
83 } bits;
84 uint32_t raw;
85};
86
87struct cursor_position_cache_dpp {
88 union reg_cur0_control_cfg cur0_ctl;
89};
90
91struct cursor_attribute_cache_dpp {
92 union reg_cur0_control_cfg cur0_ctl;
93 union reg_cur0_fp_scale_bias {
94 struct {
95 uint32_t fp_bias: 16;
96 uint32_t fp_scale: 16;
97 } bits;
98 uint32_t raw;
99 } fp_scale_bias;
100 union reg_cur0_fp_scale_bias_g_y {
101 struct {
102 uint32_t fp_bias_g_y: 16;
103 uint32_t fp_scale_g_y: 16;
104 } bits;
105 uint32_t raw;
106 } fp_scale_bias_g_y;
107 union reg_cur0_fp_scale_bias_rb_crcb {
108 struct {
109 uint32_t fp_bias_rb_crcb: 16;
110 uint32_t fp_scale_rb_crcb: 16;
111 } bits;
112 uint32_t raw;
113 } fp_scale_bias_rb_crcb;
114};
115
116struct cursor_attributes_cfg {
117 struct cursor_attribute_cache_hubp aHubp;
118 struct cursor_attribute_cache_dpp aDpp;
119};
120
121#endif
122

source code of linux/drivers/gpu/drm/amd/display/dc/inc/hw/cursor_reg_cache.h