1/*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25#ifndef __DAL_MEM_INPUT_H__
26#define __DAL_MEM_INPUT_H__
27
28#include "dc.h"
29#include "include/grph_object_id.h"
30
31#include "dml/display_mode_structs.h"
32#include "dml2_0/dml21/inc/dml_top_dchub_registers.h"
33
34struct dchub_init_data;
35struct cstate_pstate_watermarks_st {
36 uint32_t cstate_exit_ns;
37 uint32_t cstate_exit_z8_ns;
38 uint32_t cstate_enter_plus_exit_z8_ns;
39 uint32_t cstate_enter_plus_exit_ns;
40 uint32_t pstate_change_ns;
41 uint32_t fclk_pstate_change_ns;
42};
43
44struct dcn_watermarks {
45 uint32_t pte_meta_urgent_ns;
46 uint32_t urgent_ns;
47 uint32_t frac_urg_bw_nom;
48 uint32_t frac_urg_bw_flip;
49 uint32_t urgent_latency_ns;
50 struct cstate_pstate_watermarks_st cstate_pstate;
51 uint32_t usr_retraining_ns;
52};
53
54union dcn_watermark_set {
55 struct {
56 struct dcn_watermarks a;
57 struct dcn_watermarks b;
58 struct dcn_watermarks c;
59 struct dcn_watermarks d;
60 }; // legacy
61 struct {
62 struct dml2_dchub_watermark_regs a;
63 struct dml2_dchub_watermark_regs b;
64 struct dml2_dchub_watermark_regs c;
65 struct dml2_dchub_watermark_regs d;
66 } dcn4x; //dcn4+
67};
68
69struct dce_watermarks {
70 int a_mark;
71 int b_mark;
72 int c_mark;
73 int d_mark;
74};
75
76struct stutter_modes {
77 bool enhanced;
78 bool quad_dmif_buffer;
79 bool watermark_nb_pstate;
80};
81
82struct mem_input {
83 const struct mem_input_funcs *funcs;
84 struct dc_context *ctx;
85 struct dc_plane_address request_address;
86 struct dc_plane_address current_address;
87 int inst;
88 struct stutter_modes stutter_mode;
89};
90
91struct vm_system_aperture_param {
92 PHYSICAL_ADDRESS_LOC sys_default;
93 PHYSICAL_ADDRESS_LOC sys_low;
94 PHYSICAL_ADDRESS_LOC sys_high;
95};
96
97struct vm_context0_param {
98 PHYSICAL_ADDRESS_LOC pte_base;
99 PHYSICAL_ADDRESS_LOC pte_start;
100 PHYSICAL_ADDRESS_LOC pte_end;
101 PHYSICAL_ADDRESS_LOC fault_default;
102};
103
104struct mem_input_funcs {
105 void (*mem_input_setup)(
106 struct mem_input *mem_input,
107 struct _vcs_dpi_display_dlg_regs_st *dlg_regs,
108 struct _vcs_dpi_display_ttu_regs_st *ttu_regs,
109 struct _vcs_dpi_display_rq_regs_st *rq_regs,
110 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest);
111
112 void (*dcc_control)(struct mem_input *mem_input, bool enable,
113 bool independent_64b_blks);
114 void (*mem_program_viewport)(
115 struct mem_input *mem_input,
116 const struct rect *viewport,
117 const struct rect *viewport_c);
118
119 void (*mem_input_program_display_marks)(
120 struct mem_input *mem_input,
121 struct dce_watermarks nbp,
122 struct dce_watermarks stutter,
123 struct dce_watermarks stutter_enter,
124 struct dce_watermarks urgent,
125 uint32_t total_dest_line_time_ns);
126
127 void (*mem_input_program_chroma_display_marks)(
128 struct mem_input *mem_input,
129 struct dce_watermarks nbp,
130 struct dce_watermarks stutter,
131 struct dce_watermarks urgent,
132 uint32_t total_dest_line_time_ns);
133
134 void (*allocate_mem_input)(
135 struct mem_input *mem_input,
136 uint32_t h_total,/* for current target */
137 uint32_t v_total,/* for current target */
138 uint32_t pix_clk_khz,/* for current target */
139 uint32_t total_streams_num);
140
141 void (*free_mem_input)(
142 struct mem_input *mem_input,
143 uint32_t paths_num);
144
145 bool (*mem_input_program_surface_flip_and_addr)(
146 struct mem_input *mem_input,
147 const struct dc_plane_address *address,
148 bool flip_immediate);
149
150 void (*mem_input_program_pte_vm)(
151 struct mem_input *mem_input,
152 enum surface_pixel_format format,
153 struct dc_tiling_info *tiling_info,
154 enum dc_rotation_angle rotation);
155
156 void (*mem_input_set_vm_system_aperture_settings)(
157 struct mem_input *mem_input,
158 struct vm_system_aperture_param *apt);
159
160 void (*mem_input_set_vm_context0_settings)(
161 struct mem_input *mem_input,
162 const struct vm_context0_param *vm0);
163
164 void (*mem_input_program_surface_config)(
165 struct mem_input *mem_input,
166 enum surface_pixel_format format,
167 struct dc_tiling_info *tiling_info,
168 struct plane_size *plane_size,
169 enum dc_rotation_angle rotation,
170 struct dc_plane_dcc_param *dcc,
171 bool horizontal_mirror);
172
173 bool (*mem_input_is_flip_pending)(struct mem_input *mem_input);
174
175 void (*mem_input_update_dchub)(struct mem_input *mem_input,
176 struct dchub_init_data *dh_data);
177
178 void (*set_blank)(struct mem_input *mi, bool blank);
179 void (*set_hubp_blank_en)(struct mem_input *mi, bool blank);
180
181 void (*set_cursor_attributes)(
182 struct mem_input *mem_input,
183 const struct dc_cursor_attributes *attr);
184
185 void (*set_cursor_position)(
186 struct mem_input *mem_input,
187 const struct dc_cursor_position *pos,
188 const struct dc_cursor_mi_param *param);
189
190 void (*mem_input_clear_tiling)(
191 struct mem_input *mem_input);
192};
193
194#endif
195

source code of linux/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h