| 1 | // SPDX-License-Identifier: MIT |
| 2 | /* |
| 3 | * Copyright 2023 Advanced Micro Devices, Inc. |
| 4 | * |
| 5 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 6 | * copy of this software and associated documentation files (the "Software"), |
| 7 | * to deal in the Software without restriction, including without limitation |
| 8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 9 | * and/or sell copies of the Software, and to permit persons to whom the |
| 10 | * Software is furnished to do so, subject to the following conditions: |
| 11 | * |
| 12 | * The above copyright notice and this permission notice shall be included in |
| 13 | * all copies or substantial portions of the Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 21 | * OTHER DEALINGS IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: AMD |
| 24 | * |
| 25 | */ |
| 26 | |
| 27 | #include "amdgpu_dm_replay.h" |
| 28 | #include "dc_dmub_srv.h" |
| 29 | #include "dc.h" |
| 30 | #include "dm_helpers.h" |
| 31 | #include "amdgpu_dm.h" |
| 32 | #include "modules/power/power_helpers.h" |
| 33 | #include "dmub/inc/dmub_cmd.h" |
| 34 | #include "dc/inc/link_service.h" |
| 35 | |
| 36 | /* |
| 37 | * amdgpu_dm_link_supports_replay() - check if the link supports replay |
| 38 | * @link: link |
| 39 | * @aconnector: aconnector |
| 40 | * |
| 41 | */ |
| 42 | bool amdgpu_dm_link_supports_replay(struct dc_link *link, struct amdgpu_dm_connector *aconnector) |
| 43 | { |
| 44 | struct dm_connector_state *state = to_dm_connector_state(aconnector->base.state); |
| 45 | struct dpcd_caps *dpcd_caps = &link->dpcd_caps; |
| 46 | struct adaptive_sync_caps *as_caps = &link->dpcd_caps.adaptive_sync_caps; |
| 47 | |
| 48 | if (!state->freesync_capable) |
| 49 | return false; |
| 50 | |
| 51 | if (!aconnector->vsdb_info.replay_mode) |
| 52 | return false; |
| 53 | |
| 54 | // Check the eDP version |
| 55 | if (dpcd_caps->edp_rev < EDP_REVISION_13) |
| 56 | return false; |
| 57 | |
| 58 | if (!dpcd_caps->alpm_caps.bits.AUX_WAKE_ALPM_CAP) |
| 59 | return false; |
| 60 | |
| 61 | // Check adaptive sync support cap |
| 62 | if (!as_caps->dp_adap_sync_caps.bits.ADAPTIVE_SYNC_SDP_SUPPORT) |
| 63 | return false; |
| 64 | |
| 65 | // Sink shall populate line deviation information |
| 66 | if (dpcd_caps->pr_info.pixel_deviation_per_line == 0 || |
| 67 | dpcd_caps->pr_info.max_deviation_line == 0) |
| 68 | return false; |
| 69 | |
| 70 | return true; |
| 71 | } |
| 72 | |
| 73 | /* |
| 74 | * amdgpu_dm_set_replay_caps() - setup Replay capabilities |
| 75 | * @link: link |
| 76 | * @aconnector: aconnector |
| 77 | * |
| 78 | */ |
| 79 | bool amdgpu_dm_set_replay_caps(struct dc_link *link, struct amdgpu_dm_connector *aconnector) |
| 80 | { |
| 81 | struct replay_config pr_config = { 0 }; |
| 82 | union replay_debug_flags *debug_flags = NULL; |
| 83 | struct dc *dc = link->ctx->dc; |
| 84 | |
| 85 | // If Replay is already set to support, return true to skip checks |
| 86 | if (link->replay_settings.config.replay_supported) |
| 87 | return true; |
| 88 | |
| 89 | if (!dc_is_embedded_signal(signal: link->connector_signal)) |
| 90 | return false; |
| 91 | |
| 92 | if (link->panel_config.psr.disallow_replay) |
| 93 | return false; |
| 94 | |
| 95 | if (!amdgpu_dm_link_supports_replay(link, aconnector)) |
| 96 | return false; |
| 97 | |
| 98 | if (!dc->ctx->dmub_srv || !dc->ctx->dmub_srv->dmub || |
| 99 | !dc->ctx->dmub_srv->dmub->feature_caps.replay_supported) |
| 100 | return false; |
| 101 | |
| 102 | // Mark Replay is supported in pr_config |
| 103 | pr_config.replay_supported = true; |
| 104 | |
| 105 | debug_flags = (union replay_debug_flags *)&pr_config.debug_flags; |
| 106 | debug_flags->u32All = 0; |
| 107 | debug_flags->bitfields.visual_confirm = |
| 108 | link->ctx->dc->debug.visual_confirm == VISUAL_CONFIRM_REPLAY; |
| 109 | |
| 110 | init_replay_config(link, pr_config: &pr_config); |
| 111 | |
| 112 | return true; |
| 113 | } |
| 114 | |
| 115 | /* |
| 116 | * amdgpu_dm_link_setup_replay() - configure replay link |
| 117 | * @link: link |
| 118 | * @aconnector: aconnector |
| 119 | * |
| 120 | */ |
| 121 | bool amdgpu_dm_link_setup_replay(struct dc_link *link, struct amdgpu_dm_connector *aconnector) |
| 122 | { |
| 123 | struct replay_config *pr_config; |
| 124 | |
| 125 | if (link == NULL || aconnector == NULL) |
| 126 | return false; |
| 127 | |
| 128 | pr_config = &link->replay_settings.config; |
| 129 | |
| 130 | if (!pr_config->replay_supported) |
| 131 | return false; |
| 132 | |
| 133 | pr_config->replay_power_opt_supported = 0x11; |
| 134 | pr_config->replay_smu_opt_supported = false; |
| 135 | pr_config->replay_enable_option |= pr_enable_option_static_screen; |
| 136 | pr_config->replay_support_fast_resync_in_ultra_sleep_mode = aconnector->max_vfreq >= 2 * aconnector->min_vfreq; |
| 137 | pr_config->replay_timing_sync_supported = false; |
| 138 | |
| 139 | if (!pr_config->replay_timing_sync_supported) |
| 140 | pr_config->replay_enable_option &= ~pr_enable_option_general_ui; |
| 141 | |
| 142 | link->replay_settings.replay_feature_enabled = true; |
| 143 | |
| 144 | return true; |
| 145 | } |
| 146 | |
| 147 | /* |
| 148 | * amdgpu_dm_replay_enable() - enable replay f/w |
| 149 | * @stream: stream state |
| 150 | * |
| 151 | * Return: true if success |
| 152 | */ |
| 153 | bool amdgpu_dm_replay_enable(struct dc_stream_state *stream, bool wait) |
| 154 | { |
| 155 | bool replay_active = true; |
| 156 | struct dc_link *link = NULL; |
| 157 | |
| 158 | if (stream == NULL) |
| 159 | return false; |
| 160 | |
| 161 | link = stream->link; |
| 162 | |
| 163 | if (link) { |
| 164 | link->dc->link_srv->edp_setup_replay(link, stream); |
| 165 | link->dc->link_srv->edp_set_coasting_vtotal(link, stream->timing.v_total, 0); |
| 166 | DRM_DEBUG_DRIVER("Enabling replay...\n" ); |
| 167 | link->dc->link_srv->edp_set_replay_allow_active(link, &replay_active, wait, false, NULL); |
| 168 | return true; |
| 169 | } |
| 170 | |
| 171 | return false; |
| 172 | } |
| 173 | |
| 174 | /* |
| 175 | * amdgpu_dm_replay_disable() - disable replay f/w |
| 176 | * @stream: stream state |
| 177 | * |
| 178 | * Return: true if success |
| 179 | */ |
| 180 | bool amdgpu_dm_replay_disable(struct dc_stream_state *stream) |
| 181 | { |
| 182 | bool replay_active = false; |
| 183 | struct dc_link *link = NULL; |
| 184 | |
| 185 | if (stream == NULL) |
| 186 | return false; |
| 187 | |
| 188 | link = stream->link; |
| 189 | |
| 190 | if (link) { |
| 191 | DRM_DEBUG_DRIVER("Disabling replay...\n" ); |
| 192 | link->dc->link_srv->edp_set_replay_allow_active(stream->link, &replay_active, true, false, NULL); |
| 193 | return true; |
| 194 | } |
| 195 | |
| 196 | return false; |
| 197 | } |
| 198 | |
| 199 | /* |
| 200 | * amdgpu_dm_replay_disable_all() - disable replay f/w |
| 201 | * if replay is enabled on any stream |
| 202 | * |
| 203 | * Return: true if success |
| 204 | */ |
| 205 | bool amdgpu_dm_replay_disable_all(struct amdgpu_display_manager *dm) |
| 206 | { |
| 207 | DRM_DEBUG_DRIVER("Disabling replay if replay is enabled on any stream\n" ); |
| 208 | return dc_set_replay_allow_active(dc: dm->dc, active: false); |
| 209 | } |
| 210 | |