1	// SPDX-License-Identifier: MIT
2	/*
3	* Copyright 2018 Advanced Micro Devices, Inc.
4	*
5	* Permission is hereby granted, free of charge, to any person obtaining a
6	* copy of this software and associated documentation files (the "Software"),
7	* to deal in the Software without restriction, including without limitation
8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
9	* and/or sell copies of the Software, and to permit persons to whom the
10	* Software is furnished to do so, subject to the following conditions:
11	*
12	* The above copyright notice and this permission notice shall be included in
13	* all copies or substantial portions of the Software.
14	*
15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21	* OTHER DEALINGS IN THE SOFTWARE.
22	*
23	* Authors: AMD
24	*
25	*/
26
27	#include <linux/string_helpers.h>
28	#include <linux/uaccess.h>
29	#include <media/cec-notifier.h>
30
31	#include "dc.h"
32	#include "amdgpu.h"
33	#include "amdgpu_dm.h"
34	#include "amdgpu_dm_debugfs.h"
35	#include "amdgpu_dm_replay.h"
36	#include "dm_helpers.h"
37	#include "dmub/dmub_srv.h"
38	#include "resource.h"
39	#include "dsc.h"
40	#include "link_hwss.h"
41	#include "dc/dc_dmub_srv.h"
42	#include "link/protocols/link_dp_capability.h"
43	#include "inc/hw/dchubbub.h"
44
45	#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
46	#include "amdgpu_dm_psr.h"
47	#endif
48
49	struct dmub_debugfs_trace_header {
50	uint32_t entry_count;
51	uint32_t reserved[3];
52	};
53
54	struct dmub_debugfs_trace_entry {
55	uint32_t trace_code;
56	uint32_t tick_count;
57	uint32_t param0;
58	uint32_t param1;
59	};
60
61	static const char *const mst_progress_status[] = {
62	"probe",
63	"remote_edid",
64	"allocate_new_payload",
65	"clear_allocated_payload",
66	};
67
68	/* parse_write_buffer_into_params - Helper function to parse debugfs write buffer into an array
69	*
70	* Function takes in attributes passed to debugfs write entry
71	* and writes into param array.
72	* The user passes max_param_num to identify maximum number of
73	* parameters that could be parsed.
74	*
75	*/
76	static int parse_write_buffer_into_params(char *wr_buf, uint32_t wr_buf_size,
77	long *param, const char __user *buf,
78	int max_param_num,
79	uint8_t *param_nums)
80	{
81	char *wr_buf_ptr = NULL;
82	uint32_t wr_buf_count = 0;
83	int r;
84	char *sub_str = NULL;
85	const char delimiter[3] = {' ', '\n', '\0'};
86	uint8_t param_index = 0;
87
88	*param_nums = 0;
89
90	wr_buf_ptr = wr_buf;
91
92	/* r is bytes not be copied */
93	if (copy_from_user(to: wr_buf_ptr, from: buf, n: wr_buf_size)) {
94	DRM_DEBUG_DRIVER("user data could not be read successfully\n");
95	return -EFAULT;
96	}
97
98	/* check number of parameters. isspace could not differ space and \n */
99	while ((*wr_buf_ptr != 0xa) && (wr_buf_count < wr_buf_size)) {
100	/* skip space*/
101	while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) {
102	wr_buf_ptr++;
103	wr_buf_count++;
104	}
105
106	if (wr_buf_count == wr_buf_size)
107	break;
108
109	/* skip non-space*/
110	while ((!isspace(*wr_buf_ptr)) && (wr_buf_count < wr_buf_size)) {
111	wr_buf_ptr++;
112	wr_buf_count++;
113	}
114
115	(*param_nums)++;
116
117	if (wr_buf_count == wr_buf_size)
118	break;
119	}
120
121	if (*param_nums > max_param_num)
122	*param_nums = max_param_num;
123
124	wr_buf_ptr = wr_buf; /* reset buf pointer */
125	wr_buf_count = 0; /* number of char already checked */
126
127	while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) {
128	wr_buf_ptr++;
129	wr_buf_count++;
130	}
131
132	while (param_index < *param_nums) {
133	/* after strsep, wr_buf_ptr will be moved to after space */
134	sub_str = strsep(&wr_buf_ptr, delimiter);
135
136	r = kstrtol(s: sub_str, base: 16, res: &(param[param_index]));
137
138	if (r)
139	DRM_DEBUG_DRIVER("string to int convert error code: %d\n", r);
140
141	param_index++;
142	}
143
144	return 0;
145	}
146
147	/* function description
148	* get/ set DP configuration: lane_count, link_rate, spread_spectrum
149	*
150	* valid lane count value: 1, 2, 4
151	* valid link rate value:
152	* 06h = 1.62Gbps per lane
153	* 0Ah = 2.7Gbps per lane
154	* 0Ch = 3.24Gbps per lane
155	* 14h = 5.4Gbps per lane
156	* 1Eh = 8.1Gbps per lane
157	*
158	* debugfs is located at /sys/kernel/debug/dri/0/DP-x/link_settings
159	*
160	* --- to get dp configuration
161	*
162	* cat /sys/kernel/debug/dri/0/DP-x/link_settings
163	*
164	* It will list current, verified, reported, preferred dp configuration.
165	* current -- for current video mode
166	* verified --- maximum configuration which pass link training
167	* reported --- DP rx report caps (DPCD register offset 0, 1 2)
168	* preferred --- user force settings
169	*
170	* --- set (or force) dp configuration
171	*
172	* echo <lane_count> <link_rate> > link_settings
173	*
174	* for example, to force to 2 lane, 2.7GHz,
175	* echo 4 0xa > /sys/kernel/debug/dri/0/DP-x/link_settings
176	*
177	* spread_spectrum could not be changed dynamically.
178	*
179	* in case invalid lane count, link rate are force, no hw programming will be
180	* done. please check link settings after force operation to see if HW get
181	* programming.
182	*
183	* cat /sys/kernel/debug/dri/0/DP-x/link_settings
184	*
185	* check current and preferred settings.
186	*
187	*/
188	static ssize_t dp_link_settings_read(struct file *f, char __user *buf,
189	size_t size, loff_t *pos)
190	{
191	struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
192	struct dc_link *link = connector->dc_link;
193	char *rd_buf = NULL;
194	char *rd_buf_ptr = NULL;
195	const uint32_t rd_buf_size = 100;
196	uint32_t result = 0;
197	uint8_t str_len = 0;
198	int r;
199
200	if (*pos & 3 || size & 3)
201	return -EINVAL;
202
203	rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
204	if (!rd_buf)
205	return 0;
206
207	rd_buf_ptr = rd_buf;
208
209	str_len = strlen("Current: %d 0x%x %d ");
210	snprintf(buf: rd_buf_ptr, size: str_len, fmt: "Current: %d 0x%x %d ",
211	link->cur_link_settings.lane_count,
212	link->cur_link_settings.link_rate,
213	link->cur_link_settings.link_spread);
214	rd_buf_ptr += str_len;
215
216	str_len = strlen("Verified: %d 0x%x %d ");
217	snprintf(buf: rd_buf_ptr, size: str_len, fmt: "Verified: %d 0x%x %d ",
218	link->verified_link_cap.lane_count,
219	link->verified_link_cap.link_rate,
220	link->verified_link_cap.link_spread);
221	rd_buf_ptr += str_len;
222
223	str_len = strlen("Reported: %d 0x%x %d ");
224	snprintf(buf: rd_buf_ptr, size: str_len, fmt: "Reported: %d 0x%x %d ",
225	link->reported_link_cap.lane_count,
226	link->reported_link_cap.link_rate,
227	link->reported_link_cap.link_spread);
228	rd_buf_ptr += str_len;
229
230	str_len = strlen("Preferred: %d 0x%x %d ");
231	snprintf(buf: rd_buf_ptr, size: str_len, fmt: "Preferred: %d 0x%x %d\n",
232	link->preferred_link_setting.lane_count,
233	link->preferred_link_setting.link_rate,
234	link->preferred_link_setting.link_spread);
235
236	while (size) {
237	if (*pos >= rd_buf_size)
238	break;
239
240	r = put_user(*(rd_buf + result), buf);
241	if (r) {
242	kfree(objp: rd_buf);
243	return r; /* r = -EFAULT */
244	}
245
246	buf += 1;
247	size -= 1;
248	*pos += 1;
249	result += 1;
250	}
251
252	kfree(objp: rd_buf);
253	return result;
254	}
255
256	static ssize_t dp_link_settings_write(struct file *f, const char __user *buf,
257	size_t size, loff_t *pos)
258	{
259	struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
260	struct dc_link *link = connector->dc_link;
261	struct amdgpu_device *adev = drm_to_adev(ddev: connector->base.dev);
262	struct dc *dc = (struct dc *)link->dc;
263	struct dc_link_settings prefer_link_settings = {0};
264	char *wr_buf = NULL;
265	const uint32_t wr_buf_size = 40;
266	/* 0: lane_count; 1: link_rate */
267	int max_param_num = 2;
268	uint8_t param_nums = 0;
269	long param[2];
270	bool valid_input = true;
271
272	if (size == 0)
273	return -EINVAL;
274
275	wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
276	if (!wr_buf)
277	return -ENOSPC;
278
279	if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
280	param: (long *)param, buf,
281	max_param_num,
282	param_nums: &param_nums)) {
283	kfree(objp: wr_buf);
284	return -EINVAL;
285	}
286
287	if (param_nums <= 0) {
288	kfree(objp: wr_buf);
289	DRM_DEBUG_DRIVER("user data not be read\n");
290	return -EINVAL;
291	}
292
293	switch (param[0]) {
294	case LANE_COUNT_ONE:
295	case LANE_COUNT_TWO:
296	case LANE_COUNT_FOUR:
297	break;
298	default:
299	valid_input = false;
300	break;
301	}
302
303	switch (param[1]) {
304	case LINK_RATE_LOW:
305	case LINK_RATE_HIGH:
306	case LINK_RATE_RBR2:
307	case LINK_RATE_HIGH2:
308	case LINK_RATE_HIGH3:
309	case LINK_RATE_UHBR10:
310	case LINK_RATE_UHBR13_5:
311	case LINK_RATE_UHBR20:
312	break;
313	default:
314	valid_input = false;
315	break;
316	}
317
318	if (!valid_input) {
319	kfree(objp: wr_buf);
320	DRM_DEBUG_DRIVER("Invalid Input value No HW will be programmed\n");
321	mutex_lock(&adev->dm.dc_lock);
322	dc_link_set_preferred_training_settings(dc, NULL, NULL, link, skip_immediate_retrain: false);
323	mutex_unlock(lock: &adev->dm.dc_lock);
324	return size;
325	}
326
327	/* save user force lane_count, link_rate to preferred settings
328	* spread spectrum will not be changed
329	*/
330	prefer_link_settings.link_spread = link->cur_link_settings.link_spread;
331	prefer_link_settings.use_link_rate_set = false;
332	prefer_link_settings.lane_count = param[0];
333	prefer_link_settings.link_rate = param[1];
334
335	mutex_lock(&adev->dm.dc_lock);
336	dc_link_set_preferred_training_settings(dc, link_setting: &prefer_link_settings, NULL, link, skip_immediate_retrain: false);
337	mutex_unlock(lock: &adev->dm.dc_lock);
338
339	kfree(objp: wr_buf);
340	return size;
341	}
342
343	static bool dp_mst_is_end_device(struct amdgpu_dm_connector *aconnector)
344	{
345	bool is_end_device = false;
346	struct drm_dp_mst_topology_mgr *mgr = NULL;
347	struct drm_dp_mst_port *port = NULL;
348
349	if (aconnector->mst_root && aconnector->mst_root->mst_mgr.mst_state) {
350	mgr = &aconnector->mst_root->mst_mgr;
351	port = aconnector->mst_output_port;
352
353	drm_modeset_lock(lock: &mgr->base.lock, NULL);
354	if (port->pdt == DP_PEER_DEVICE_SST_SINK ||
355	port->pdt == DP_PEER_DEVICE_DP_LEGACY_CONV)
356	is_end_device = true;
357	drm_modeset_unlock(lock: &mgr->base.lock);
358	}
359
360	return is_end_device;
361	}
362
363	/* Change MST link setting
364	*
365	* valid lane count value: 1, 2, 4
366	* valid link rate value:
367	* 06h = 1.62Gbps per lane
368	* 0Ah = 2.7Gbps per lane
369	* 0Ch = 3.24Gbps per lane
370	* 14h = 5.4Gbps per lane
371	* 1Eh = 8.1Gbps per lane
372	* 3E8h = 10.0Gbps per lane
373	* 546h = 13.5Gbps per lane
374	* 7D0h = 20.0Gbps per lane
375	*
376	* debugfs is located at /sys/kernel/debug/dri/0/DP-x/mst_link_settings
377	*
378	* for example, to force to 2 lane, 10.0GHz,
379	* echo 2 0x3e8 > /sys/kernel/debug/dri/0/DP-x/mst_link_settings
380	*
381	* Valid input will trigger hotplug event to get new link setting applied
382	* Invalid input will trigger training setting reset
383	*
384	* The usage can be referred to link_settings entry
385	*
386	*/
387	static ssize_t dp_mst_link_setting(struct file *f, const char __user *buf,
388	size_t size, loff_t *pos)
389	{
390	struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
391	struct dc_link *link = aconnector->dc_link;
392	struct amdgpu_device *adev = drm_to_adev(ddev: aconnector->base.dev);
393	struct dc *dc = (struct dc *)link->dc;
394	struct dc_link_settings prefer_link_settings = {0};
395	char *wr_buf = NULL;
396	const uint32_t wr_buf_size = 40;
397	/* 0: lane_count; 1: link_rate */
398	int max_param_num = 2;
399	uint8_t param_nums = 0;
400	long param[2];
401	bool valid_input = true;
402
403	if (!dp_mst_is_end_device(aconnector))
404	return -EINVAL;
405
406	if (size == 0)
407	return -EINVAL;
408
409	wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
410	if (!wr_buf)
411	return -ENOSPC;
412
413	if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
414	param: (long *)param, buf,
415	max_param_num,
416	param_nums: &param_nums)) {
417	kfree(objp: wr_buf);
418	return -EINVAL;
419	}
420
421	if (param_nums <= 0) {
422	kfree(objp: wr_buf);
423	DRM_DEBUG_DRIVER("user data not be read\n");
424	return -EINVAL;
425	}
426
427	switch (param[0]) {
428	case LANE_COUNT_ONE:
429	case LANE_COUNT_TWO:
430	case LANE_COUNT_FOUR:
431	break;
432	default:
433	valid_input = false;
434	break;
435	}
436
437	switch (param[1]) {
438	case LINK_RATE_LOW:
439	case LINK_RATE_HIGH:
440	case LINK_RATE_RBR2:
441	case LINK_RATE_HIGH2:
442	case LINK_RATE_HIGH3:
443	case LINK_RATE_UHBR10:
444	case LINK_RATE_UHBR13_5:
445	case LINK_RATE_UHBR20:
446	break;
447	default:
448	valid_input = false;
449	break;
450	}
451
452	if (!valid_input) {
453	kfree(objp: wr_buf);
454	DRM_DEBUG_DRIVER("Invalid Input value No HW will be programmed\n");
455	mutex_lock(&adev->dm.dc_lock);
456	dc_link_set_preferred_training_settings(dc, NULL, NULL, link, skip_immediate_retrain: false);
457	mutex_unlock(lock: &adev->dm.dc_lock);
458	return -EINVAL;
459	}
460
461	/* save user force lane_count, link_rate to preferred settings
462	* spread spectrum will not be changed
463	*/
464	prefer_link_settings.link_spread = link->cur_link_settings.link_spread;
465	prefer_link_settings.use_link_rate_set = false;
466	prefer_link_settings.lane_count = param[0];
467	prefer_link_settings.link_rate = param[1];
468
469	/* skip immediate retrain, and train to new link setting after hotplug event triggered */
470	mutex_lock(&adev->dm.dc_lock);
471	dc_link_set_preferred_training_settings(dc, link_setting: &prefer_link_settings, NULL, link, skip_immediate_retrain: true);
472	mutex_unlock(lock: &adev->dm.dc_lock);
473
474	mutex_lock(&aconnector->base.dev->mode_config.mutex);
475	aconnector->base.force = DRM_FORCE_OFF;
476	mutex_unlock(lock: &aconnector->base.dev->mode_config.mutex);
477	drm_kms_helper_hotplug_event(dev: aconnector->base.dev);
478
479	msleep(msecs: 100);
480
481	mutex_lock(&aconnector->base.dev->mode_config.mutex);
482	aconnector->base.force = DRM_FORCE_UNSPECIFIED;
483	mutex_unlock(lock: &aconnector->base.dev->mode_config.mutex);
484	drm_kms_helper_hotplug_event(dev: aconnector->base.dev);
485
486	kfree(objp: wr_buf);
487	return size;
488	}
489
490	/* function: get current DP PHY settings: voltage swing, pre-emphasis,
491	* post-cursor2 (defined by VESA DP specification)
492	*
493	* valid values
494	* voltage swing: 0,1,2,3
495	* pre-emphasis : 0,1,2,3
496	* post cursor2 : 0,1,2,3
497	*
498	*
499	* how to use this debugfs
500	*
501	* debugfs is located at /sys/kernel/debug/dri/0/DP-x
502	*
503	* there will be directories, like DP-1, DP-2,DP-3, etc. for DP display
504	*
505	* To figure out which DP-x is the display for DP to be check,
506	* cd DP-x
507	* ls -ll
508	* There should be debugfs file, like link_settings, phy_settings.
509	* cat link_settings
510	* from lane_count, link_rate to figure which DP-x is for display to be worked
511	* on
512	*
513	* To get current DP PHY settings,
514	* cat phy_settings
515	*
516	* To change DP PHY settings,
517	* echo <voltage_swing> <pre-emphasis> <post_cursor2> > phy_settings
518	* for examle, to change voltage swing to 2, pre-emphasis to 3, post_cursor2 to
519	* 0,
520	* echo 2 3 0 > phy_settings
521	*
522	* To check if change be applied, get current phy settings by
523	* cat phy_settings
524	*
525	* In case invalid values are set by user, like
526	* echo 1 4 0 > phy_settings
527	*
528	* HW will NOT be programmed by these settings.
529	* cat phy_settings will show the previous valid settings.
530	*/
531	static ssize_t dp_phy_settings_read(struct file *f, char __user *buf,
532	size_t size, loff_t *pos)
533	{
534	struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
535	struct dc_link *link = connector->dc_link;
536	char *rd_buf = NULL;
537	const uint32_t rd_buf_size = 20;
538	uint32_t result = 0;
539	int r;
540
541	if (*pos & 3 || size & 3)
542	return -EINVAL;
543
544	rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
545	if (!rd_buf)
546	return -EINVAL;
547
548	snprintf(buf: rd_buf, size: rd_buf_size, fmt: " %d %d %d\n",
549	link->cur_lane_setting[0].VOLTAGE_SWING,
550	link->cur_lane_setting[0].PRE_EMPHASIS,
551	link->cur_lane_setting[0].POST_CURSOR2);
552
553	while (size) {
554	if (*pos >= rd_buf_size)
555	break;
556
557	r = put_user((*(rd_buf + result)), buf);
558	if (r) {
559	kfree(objp: rd_buf);
560	return r; /* r = -EFAULT */
561	}
562
563	buf += 1;
564	size -= 1;
565	*pos += 1;
566	result += 1;
567	}
568
569	kfree(objp: rd_buf);
570	return result;
571	}
572
573	static int dp_lttpr_status_show(struct seq_file *m, void *unused)
574	{
575	struct drm_connector *connector = m->private;
576	struct amdgpu_dm_connector *aconnector =
577	to_amdgpu_dm_connector(connector);
578	struct dc_lttpr_caps caps = aconnector->dc_link->dpcd_caps.lttpr_caps;
579
580	if (connector->status != connector_status_connected)
581	return -ENODEV;
582
583	seq_printf(m, fmt: "phy repeater count: %u (raw: 0x%x)\n",
584	dp_parse_lttpr_repeater_count(lttpr_repeater_count: caps.phy_repeater_cnt),
585	caps.phy_repeater_cnt);
586
587	seq_puts(m, s: "phy repeater mode: ");
588
589	switch (caps.mode) {
590	case DP_PHY_REPEATER_MODE_TRANSPARENT:
591	seq_puts(m, s: "transparent");
592	break;
593	case DP_PHY_REPEATER_MODE_NON_TRANSPARENT:
594	seq_puts(m, s: "non-transparent");
595	break;
596	case 0x00:
597	seq_puts(m, s: "non lttpr");
598	break;
599	default:
600	seq_printf(m, fmt: "read error (raw: 0x%x)", caps.mode);
601	break;
602	}
603
604	seq_puts(m, s: "\n");
605	return 0;
606	}
607
608	static ssize_t dp_phy_settings_write(struct file *f, const char __user *buf,
609	size_t size, loff_t *pos)
610	{
611	struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
612	struct dc_link *link = connector->dc_link;
613	struct dc *dc = (struct dc *)link->dc;
614	char *wr_buf = NULL;
615	uint32_t wr_buf_size = 40;
616	long param[3];
617	bool use_prefer_link_setting;
618	struct link_training_settings link_lane_settings = {0};
619	int max_param_num = 3;
620	uint8_t param_nums = 0;
621	int r = 0;
622
623
624	if (size == 0)
625	return -EINVAL;
626
627	wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
628	if (!wr_buf)
629	return -ENOSPC;
630
631	if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
632	param: (long *)param, buf,
633	max_param_num,
634	param_nums: &param_nums)) {
635	kfree(objp: wr_buf);
636	return -EINVAL;
637	}
638
639	if (param_nums <= 0) {
640	kfree(objp: wr_buf);
641	DRM_DEBUG_DRIVER("user data not be read\n");
642	return -EINVAL;
643	}
644
645	if ((param[0] > VOLTAGE_SWING_MAX_LEVEL) ||
646	(param[1] > PRE_EMPHASIS_MAX_LEVEL) ||
647	(param[2] > POST_CURSOR2_MAX_LEVEL)) {
648	kfree(objp: wr_buf);
649	DRM_DEBUG_DRIVER("Invalid Input No HW will be programmed\n");
650	return size;
651	}
652
653	/* get link settings: lane count, link rate */
654	use_prefer_link_setting =
655	((link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN) &&
656	(link->test_pattern_enabled));
657
658	memset(&link_lane_settings, 0, sizeof(link_lane_settings));
659
660	if (use_prefer_link_setting) {
661	link_lane_settings.link_settings.lane_count =
662	link->preferred_link_setting.lane_count;
663	link_lane_settings.link_settings.link_rate =
664	link->preferred_link_setting.link_rate;
665	link_lane_settings.link_settings.link_spread =
666	link->preferred_link_setting.link_spread;
667	} else {
668	link_lane_settings.link_settings.lane_count =
669	link->cur_link_settings.lane_count;
670	link_lane_settings.link_settings.link_rate =
671	link->cur_link_settings.link_rate;
672	link_lane_settings.link_settings.link_spread =
673	link->cur_link_settings.link_spread;
674	}
675
676	/* apply phy settings from user */
677	for (r = 0; r < link_lane_settings.link_settings.lane_count; r++) {
678	link_lane_settings.hw_lane_settings[r].VOLTAGE_SWING =
679	(enum dc_voltage_swing) (param[0]);
680	link_lane_settings.hw_lane_settings[r].PRE_EMPHASIS =
681	(enum dc_pre_emphasis) (param[1]);
682	link_lane_settings.hw_lane_settings[r].POST_CURSOR2 =
683	(enum dc_post_cursor2) (param[2]);
684	}
685
686	/* program ASIC registers and DPCD registers */
687	dc_link_set_drive_settings(dc, lt_settings: &link_lane_settings, link);
688
689	kfree(objp: wr_buf);
690	return size;
691	}
692
693	/* function description
694	*
695	* set PHY layer or Link layer test pattern
696	* PHY test pattern is used for PHY SI check.
697	* Link layer test will not affect PHY SI.
698	*
699	* Reset Test Pattern:
700	* 0 = DP_TEST_PATTERN_VIDEO_MODE
701	*
702	* PHY test pattern supported:
703	* 1 = DP_TEST_PATTERN_D102
704	* 2 = DP_TEST_PATTERN_SYMBOL_ERROR
705	* 3 = DP_TEST_PATTERN_PRBS7
706	* 4 = DP_TEST_PATTERN_80BIT_CUSTOM
707	* 5 = DP_TEST_PATTERN_CP2520_1
708	* 6 = DP_TEST_PATTERN_CP2520_2 = DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE
709	* 7 = DP_TEST_PATTERN_CP2520_3
710	*
711	* DP PHY Link Training Patterns
712	* 8 = DP_TEST_PATTERN_TRAINING_PATTERN1
713	* 9 = DP_TEST_PATTERN_TRAINING_PATTERN2
714	* a = DP_TEST_PATTERN_TRAINING_PATTERN3
715	* b = DP_TEST_PATTERN_TRAINING_PATTERN4
716	*
717	* DP Link Layer Test pattern
718	* c = DP_TEST_PATTERN_COLOR_SQUARES
719	* d = DP_TEST_PATTERN_COLOR_SQUARES_CEA
720	* e = DP_TEST_PATTERN_VERTICAL_BARS
721	* f = DP_TEST_PATTERN_HORIZONTAL_BARS
722	* 10= DP_TEST_PATTERN_COLOR_RAMP
723	*
724	* debugfs phy_test_pattern is located at /syskernel/debug/dri/0/DP-x
725	*
726	* --- set test pattern
727	* echo <test pattern #> > test_pattern
728	*
729	* If test pattern # is not supported, NO HW programming will be done.
730	* for DP_TEST_PATTERN_80BIT_CUSTOM, it needs extra 10 bytes of data
731	* for the user pattern. input 10 bytes data are separated by space
732	*
733	* echo 0x4 0x11 0x22 0x33 0x44 0x55 0x66 0x77 0x88 0x99 0xaa > test_pattern
734	*
735	* --- reset test pattern
736	* echo 0 > test_pattern
737	*
738	* --- HPD detection is disabled when set PHY test pattern
739	*
740	* when PHY test pattern (pattern # within [1,7]) is set, HPD pin of HW ASIC
741	* is disable. User could unplug DP display from DP connected and plug scope to
742	* check test pattern PHY SI.
743	* If there is need unplug scope and plug DP display back, do steps below:
744	* echo 0 > phy_test_pattern
745	* unplug scope
746	* plug DP display.
747	*
748	* "echo 0 > phy_test_pattern" will re-enable HPD pin again so that video sw
749	* driver could detect "unplug scope" and "plug DP display"
750	*/
751	static ssize_t dp_phy_test_pattern_debugfs_write(struct file *f, const char __user *buf,
752	size_t size, loff_t *pos)
753	{
754	struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
755	struct dc_link *link = connector->dc_link;
756	char *wr_buf = NULL;
757	uint32_t wr_buf_size = 100;
758	long param[11] = {0x0};
759	int max_param_num = 11;
760	enum dp_test_pattern test_pattern = DP_TEST_PATTERN_UNSUPPORTED;
761	bool disable_hpd = false;
762	bool supports_hpd = link->irq_source_hpd != DC_IRQ_SOURCE_INVALID;
763	bool valid_test_pattern = false;
764	uint8_t param_nums = 0;
765	/* init with default 80bit custom pattern */
766	uint8_t custom_pattern[10] = {
767	0x1f, 0x7c, 0xf0, 0xc1, 0x07,
768	0x1f, 0x7c, 0xf0, 0xc1, 0x07
769	};
770	struct dc_link_settings prefer_link_settings = {LANE_COUNT_UNKNOWN,
771	LINK_RATE_UNKNOWN, LINK_SPREAD_DISABLED};
772	struct dc_link_settings cur_link_settings = {LANE_COUNT_UNKNOWN,
773	LINK_RATE_UNKNOWN, LINK_SPREAD_DISABLED};
774	struct link_training_settings link_training_settings = {0};
775	int i;
776
777	if (size == 0)
778	return -EINVAL;
779
780	wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
781	if (!wr_buf)
782	return -ENOSPC;
783
784	if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
785	param: (long *)param, buf,
786	max_param_num,
787	param_nums: &param_nums)) {
788	kfree(objp: wr_buf);
789	return -EINVAL;
790	}
791
792	if (param_nums <= 0) {
793	kfree(objp: wr_buf);
794	DRM_DEBUG_DRIVER("user data not be read\n");
795	return -EINVAL;
796	}
797
798
799	test_pattern = param[0];
800
801	switch (test_pattern) {
802	case DP_TEST_PATTERN_VIDEO_MODE:
803	case DP_TEST_PATTERN_COLOR_SQUARES:
804	case DP_TEST_PATTERN_COLOR_SQUARES_CEA:
805	case DP_TEST_PATTERN_VERTICAL_BARS:
806	case DP_TEST_PATTERN_HORIZONTAL_BARS:
807	case DP_TEST_PATTERN_COLOR_RAMP:
808	valid_test_pattern = true;
809	break;
810
811	case DP_TEST_PATTERN_D102:
812	case DP_TEST_PATTERN_SYMBOL_ERROR:
813	case DP_TEST_PATTERN_PRBS7:
814	case DP_TEST_PATTERN_80BIT_CUSTOM:
815	case DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE:
816	case DP_TEST_PATTERN_TRAINING_PATTERN4:
817	disable_hpd = true;
818	valid_test_pattern = true;
819	break;
820
821	default:
822	valid_test_pattern = false;
823	test_pattern = DP_TEST_PATTERN_UNSUPPORTED;
824	break;
825	}
826
827	if (!valid_test_pattern) {
828	kfree(objp: wr_buf);
829	DRM_DEBUG_DRIVER("Invalid Test Pattern Parameters\n");
830	return size;
831	}
832
833	if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM) {
834	for (i = 0; i < 10; i++) {
835	if ((uint8_t) param[i + 1] != 0x0)
836	break;
837	}
838
839	if (i < 10) {
840	/* not use default value */
841	for (i = 0; i < 10; i++)
842	custom_pattern[i] = (uint8_t) param[i + 1];
843	}
844	}
845
846	/* Usage: set DP physical test pattern using debugfs with normal DP
847	* panel. Then plug out DP panel and connect a scope to measure
848	* For normal video mode and test pattern generated from CRCT,
849	* they are visibile to user. So do not disable HPD.
850	* Video Mode is also set to clear the test pattern, so enable HPD
851	* because it might have been disabled after a test pattern was set.
852	* AUX depends on HPD * sequence dependent, do not move!
853	*/
854	if (supports_hpd && !disable_hpd)
855	dc_link_enable_hpd(link);
856
857	prefer_link_settings.lane_count = link->verified_link_cap.lane_count;
858	prefer_link_settings.link_rate = link->verified_link_cap.link_rate;
859	prefer_link_settings.link_spread = link->verified_link_cap.link_spread;
860
861	cur_link_settings.lane_count = link->cur_link_settings.lane_count;
862	cur_link_settings.link_rate = link->cur_link_settings.link_rate;
863	cur_link_settings.link_spread = link->cur_link_settings.link_spread;
864
865	link_training_settings.link_settings = cur_link_settings;
866
867
868	if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) {
869	if (prefer_link_settings.lane_count != LANE_COUNT_UNKNOWN &&
870	prefer_link_settings.link_rate != LINK_RATE_UNKNOWN &&
871	(prefer_link_settings.lane_count != cur_link_settings.lane_count ||
872	prefer_link_settings.link_rate != cur_link_settings.link_rate))
873	link_training_settings.link_settings = prefer_link_settings;
874	}
875
876	for (i = 0; i < (unsigned int)(link_training_settings.link_settings.lane_count); i++)
877	link_training_settings.hw_lane_settings[i] = link->cur_lane_setting[i];
878
879	dc_link_dp_set_test_pattern(
880	link,
881	test_pattern,
882	test_pattern_color_space: DP_TEST_PATTERN_COLOR_SPACE_RGB,
883	p_link_settings: &link_training_settings,
884	p_custom_pattern: custom_pattern,
885	cust_pattern_size: 10);
886
887	/* Usage: Set DP physical test pattern using AMDDP with normal DP panel
888	* Then plug out DP panel and connect a scope to measure DP PHY signal.
889	* Need disable interrupt to avoid SW driver disable DP output. This is
890	* done after the test pattern is set.
891	*/
892	if (valid_test_pattern && supports_hpd && disable_hpd)
893	dc_link_disable_hpd(link);
894
895	kfree(objp: wr_buf);
896
897	return size;
898	}
899
900	/*
901	* Returns the DMCUB tracebuffer contents.
902	* Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_tracebuffer
903	*/
904	static int dmub_tracebuffer_show(struct seq_file *m, void *data)
905	{
906	struct amdgpu_device *adev = m->private;
907	struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
908	struct dmub_fw_meta_info *fw_meta_info = NULL;
909	struct dmub_debugfs_trace_entry *entries;
910	uint8_t *tbuf_base;
911	uint32_t tbuf_size, max_entries, num_entries, first_entry, i;
912
913	if (!fb_info)
914	return 0;
915
916	tbuf_base = (uint8_t *)fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr;
917	if (!tbuf_base)
918	return 0;
919
920	if (adev->dm.dmub_srv)
921	fw_meta_info = &adev->dm.dmub_srv->meta_info;
922
923	tbuf_size = fw_meta_info ? fw_meta_info->trace_buffer_size :
924	DMUB_TRACE_BUFFER_SIZE;
925	max_entries = (tbuf_size - sizeof(struct dmub_debugfs_trace_header)) /
926	sizeof(struct dmub_debugfs_trace_entry);
927
928	num_entries =
929	((struct dmub_debugfs_trace_header *)tbuf_base)->entry_count;
930
931	/* DMCUB tracebuffer is a ring. If it rolled over, print a hint that
932	* entries are being overwritten.
933	*/
934	if (num_entries > max_entries)
935	seq_printf(m, fmt: "...\n");
936
937	first_entry = num_entries % max_entries;
938	num_entries = min(num_entries, max_entries);
939
940	entries = (struct dmub_debugfs_trace_entry
941	*)(tbuf_base +
942	sizeof(struct dmub_debugfs_trace_header));
943
944	/* To print entries chronologically, start from the first entry till the
945	* top of buffer, then from base of buffer to first entry.
946	*/
947	for (i = first_entry; i < num_entries; ++i) {
948	struct dmub_debugfs_trace_entry *entry = &entries[i];
949
950	seq_printf(m,
951	fmt: "trace_code=%u tick_count=%u param0=%u param1=%u\n",
952	entry->trace_code, entry->tick_count, entry->param0,
953	entry->param1);
954	}
955	for (i = 0; i < first_entry; ++i) {
956	struct dmub_debugfs_trace_entry *entry = &entries[i];
957
958	seq_printf(m,
959	fmt: "trace_code=%u tick_count=%u param0=%u param1=%u\n",
960	entry->trace_code, entry->tick_count, entry->param0,
961	entry->param1);
962	}
963
964	return 0;
965	}
966
967	/*
968	* Returns the DMCUB firmware state contents.
969	* Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_fw_state
970	*/
971	static int dmub_fw_state_show(struct seq_file *m, void *data)
972	{
973	struct amdgpu_device *adev = m->private;
974	struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info;
975	uint8_t *state_base;
976	uint32_t state_size;
977
978	if (!fb_info)
979	return 0;
980
981	state_base = (uint8_t *)fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr;
982	if (!state_base)
983	return 0;
984
985	state_size = fb_info->fb[DMUB_WINDOW_6_FW_STATE].size;
986
987	return seq_write(seq: m, data: state_base, len: state_size);
988	}
989
990	/* replay_capability_show() - show eDP panel replay capability
991	*
992	* The read function: replay_capability_show
993	* Shows if sink and driver has Replay capability or not.
994	*
995	* cat /sys/kernel/debug/dri/0/eDP-X/replay_capability
996	*
997	* Expected output:
998	* "Sink support: no\n" - if panel doesn't support Replay
999	* "Sink support: yes\n" - if panel supports Replay
1000	* "Driver support: no\n" - if driver doesn't support Replay
1001	* "Driver support: yes\n" - if driver supports Replay
1002	*/
1003	static int replay_capability_show(struct seq_file *m, void *data)
1004	{
1005	struct drm_connector *connector = m->private;
1006	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
1007	struct dc_link *link = aconnector->dc_link;
1008	bool sink_support_replay = false;
1009	bool driver_support_replay = false;
1010
1011	if (!link)
1012	return -ENODEV;
1013
1014	if (link->type == dc_connection_none)
1015	return -ENODEV;
1016
1017	if (!(link->connector_signal & SIGNAL_TYPE_EDP))
1018	return -ENODEV;
1019
1020	/* If Replay is already set to support, skip the checks */
1021	if (link->replay_settings.config.replay_supported) {
1022	sink_support_replay = true;
1023	driver_support_replay = true;
1024	} else if ((amdgpu_dc_debug_mask & DC_DISABLE_REPLAY)) {
1025	sink_support_replay = amdgpu_dm_link_supports_replay(link, aconnector);
1026	} else {
1027	struct dc *dc = link->ctx->dc;
1028
1029	sink_support_replay = amdgpu_dm_link_supports_replay(link, aconnector);
1030	if (dc->ctx->dmub_srv && dc->ctx->dmub_srv->dmub)
1031	driver_support_replay =
1032	(bool)dc->ctx->dmub_srv->dmub->feature_caps.replay_supported;
1033	}
1034
1035	seq_printf(m, fmt: "Sink support: %s\n", str_yes_no(v: sink_support_replay));
1036	seq_printf(m, fmt: "Driver support: %s\n", str_yes_no(v: driver_support_replay));
1037	seq_printf(m, fmt: "Config support: %s\n", str_yes_no(v: link->replay_settings.config.replay_supported));
1038
1039	return 0;
1040	}
1041
1042	/* psr_capability_show() - show eDP panel PSR capability
1043	*
1044	* The read function: sink_psr_capability_show
1045	* Shows if sink has PSR capability or not.
1046	* If yes - the PSR version is appended
1047	*
1048	* cat /sys/kernel/debug/dri/0/eDP-X/psr_capability
1049	*
1050	* Expected output:
1051	* "Sink support: no\n" - if panel doesn't support PSR
1052	* "Sink support: yes [0x01]\n" - if panel supports PSR1
1053	* "Driver support: no\n" - if driver doesn't support PSR
1054	* "Driver support: yes [0x01]\n" - if driver supports PSR1
1055	*/
1056	static int psr_capability_show(struct seq_file *m, void *data)
1057	{
1058	struct drm_connector *connector = m->private;
1059	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
1060	struct dc_link *link = aconnector->dc_link;
1061
1062	if (!link)
1063	return -ENODEV;
1064
1065	if (link->type == dc_connection_none)
1066	return -ENODEV;
1067
1068	if (!(link->connector_signal & SIGNAL_TYPE_EDP))
1069	return -ENODEV;
1070
1071	seq_printf(m, fmt: "Sink support: %s", str_yes_no(v: link->dpcd_caps.psr_info.psr_version != 0));
1072	if (link->dpcd_caps.psr_info.psr_version)
1073	seq_printf(m, fmt: " [0x%02x]", link->dpcd_caps.psr_info.psr_version);
1074	seq_puts(m, s: "\n");
1075
1076	seq_printf(m, fmt: "Driver support: %s", str_yes_no(v: link->psr_settings.psr_feature_enabled));
1077	if (link->psr_settings.psr_version)
1078	seq_printf(m, fmt: " [0x%02x]", link->psr_settings.psr_version);
1079	seq_puts(m, s: "\n");
1080
1081	return 0;
1082	}
1083
1084	/*
1085	* Returns the current bpc for the crtc.
1086	* Example usage: cat /sys/kernel/debug/dri/0/crtc-0/amdgpu_current_bpc
1087	*/
1088	static int amdgpu_current_bpc_show(struct seq_file *m, void *data)
1089	{
1090	struct drm_crtc *crtc = m->private;
1091	struct drm_device *dev = crtc->dev;
1092	struct dm_crtc_state *dm_crtc_state = NULL;
1093	int res = -ENODEV;
1094	unsigned int bpc;
1095
1096	mutex_lock(&dev->mode_config.mutex);
1097	drm_modeset_lock(lock: &crtc->mutex, NULL);
1098	if (crtc->state == NULL)
1099	goto unlock;
1100
1101	dm_crtc_state = to_dm_crtc_state(crtc->state);
1102	if (dm_crtc_state->stream == NULL)
1103	goto unlock;
1104
1105	switch (dm_crtc_state->stream->timing.display_color_depth) {
1106	case COLOR_DEPTH_666:
1107	bpc = 6;
1108	break;
1109	case COLOR_DEPTH_888:
1110	bpc = 8;
1111	break;
1112	case COLOR_DEPTH_101010:
1113	bpc = 10;
1114	break;
1115	case COLOR_DEPTH_121212:
1116	bpc = 12;
1117	break;
1118	case COLOR_DEPTH_161616:
1119	bpc = 16;
1120	break;
1121	default:
1122	goto unlock;
1123	}
1124
1125	seq_printf(m, fmt: "Current: %u\n", bpc);
1126	res = 0;
1127
1128	unlock:
1129	drm_modeset_unlock(lock: &crtc->mutex);
1130	mutex_unlock(lock: &dev->mode_config.mutex);
1131
1132	return res;
1133	}
1134	DEFINE_SHOW_ATTRIBUTE(amdgpu_current_bpc);
1135
1136	/*
1137	* Returns the current colorspace for the crtc.
1138	* Example usage: cat /sys/kernel/debug/dri/0/crtc-0/amdgpu_current_colorspace
1139	*/
1140	static int amdgpu_current_colorspace_show(struct seq_file *m, void *data)
1141	{
1142	struct drm_crtc *crtc = m->private;
1143	struct drm_device *dev = crtc->dev;
1144	struct dm_crtc_state *dm_crtc_state = NULL;
1145	int res = -ENODEV;
1146
1147	mutex_lock(&dev->mode_config.mutex);
1148	drm_modeset_lock(lock: &crtc->mutex, NULL);
1149	if (crtc->state == NULL)
1150	goto unlock;
1151
1152	dm_crtc_state = to_dm_crtc_state(crtc->state);
1153	if (dm_crtc_state->stream == NULL)
1154	goto unlock;
1155
1156	switch (dm_crtc_state->stream->output_color_space) {
1157	case COLOR_SPACE_SRGB:
1158	seq_puts(m, s: "sRGB");
1159	break;
1160	case COLOR_SPACE_YCBCR601:
1161	case COLOR_SPACE_YCBCR601_LIMITED:
1162	seq_puts(m, s: "BT601_YCC");
1163	break;
1164	case COLOR_SPACE_YCBCR709:
1165	case COLOR_SPACE_YCBCR709_LIMITED:
1166	seq_puts(m, s: "BT709_YCC");
1167	break;
1168	case COLOR_SPACE_ADOBERGB:
1169	seq_puts(m, s: "opRGB");
1170	break;
1171	case COLOR_SPACE_2020_RGB_FULLRANGE:
1172	seq_puts(m, s: "BT2020_RGB");
1173	break;
1174	case COLOR_SPACE_2020_YCBCR_LIMITED:
1175	seq_puts(m, s: "BT2020_YCC");
1176	break;
1177	default:
1178	goto unlock;
1179	}
1180	res = 0;
1181
1182	unlock:
1183	drm_modeset_unlock(lock: &crtc->mutex);
1184	mutex_unlock(lock: &dev->mode_config.mutex);
1185
1186	return res;
1187	}
1188	DEFINE_SHOW_ATTRIBUTE(amdgpu_current_colorspace);
1189
1190
1191	/*
1192	* Example usage:
1193	* Disable dsc passthrough, i.e.,: have dsc decoding at converver, not external RX
1194	* echo 1 /sys/kernel/debug/dri/0/DP-1/dsc_disable_passthrough
1195	* Enable dsc passthrough, i.e.,: have dsc passthrough to external RX
1196	* echo 0 /sys/kernel/debug/dri/0/DP-1/dsc_disable_passthrough
1197	*/
1198	static ssize_t dp_dsc_passthrough_set(struct file *f, const char __user *buf,
1199	size_t size, loff_t *pos)
1200	{
1201	struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1202	char *wr_buf = NULL;
1203	uint32_t wr_buf_size = 42;
1204	int max_param_num = 1;
1205	long param;
1206	uint8_t param_nums = 0;
1207
1208	if (size == 0)
1209	return -EINVAL;
1210
1211	wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1212
1213	if (!wr_buf) {
1214	DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1215	return -ENOSPC;
1216	}
1217
1218	if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
1219	param: &param, buf,
1220	max_param_num,
1221	param_nums: &param_nums)) {
1222	kfree(objp: wr_buf);
1223	return -EINVAL;
1224	}
1225
1226	aconnector->dsc_settings.dsc_force_disable_passthrough = param;
1227
1228	kfree(objp: wr_buf);
1229	return 0;
1230	}
1231
1232	/*
1233	* Returns the HDCP capability of the Display (1.4 for now).
1234	*
1235	* NOTE* Not all HDMI displays report their HDCP caps even when they are capable.
1236	* Since its rare for a display to not be HDCP 1.4 capable, we set HDMI as always capable.
1237	*
1238	* Example usage: cat /sys/kernel/debug/dri/0/DP-1/hdcp_sink_capability
1239	* or cat /sys/kernel/debug/dri/0/HDMI-A-1/hdcp_sink_capability
1240	*/
1241	static int hdcp_sink_capability_show(struct seq_file *m, void *data)
1242	{
1243	struct drm_connector *connector = m->private;
1244	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
1245	bool hdcp_cap, hdcp2_cap;
1246
1247	if (connector->status != connector_status_connected)
1248	return -ENODEV;
1249
1250	seq_printf(m, fmt: "%s:%d HDCP version: ", connector->name, connector->base.id);
1251
1252	hdcp_cap = dc_link_is_hdcp14(link: aconnector->dc_link, signal: aconnector->dc_sink->sink_signal);
1253	hdcp2_cap = dc_link_is_hdcp22(link: aconnector->dc_link, signal: aconnector->dc_sink->sink_signal);
1254
1255
1256	if (hdcp_cap)
1257	seq_printf(m, fmt: "%s ", "HDCP1.4");
1258	if (hdcp2_cap)
1259	seq_printf(m, fmt: "%s ", "HDCP2.2");
1260
1261	if (!hdcp_cap && !hdcp2_cap)
1262	seq_printf(m, fmt: "%s ", "None");
1263
1264	seq_puts(m, s: "\n");
1265
1266	return 0;
1267	}
1268
1269	/*
1270	* Returns whether the connected display is internal and not hotpluggable.
1271	* Example usage: cat /sys/kernel/debug/dri/0/DP-1/internal_display
1272	*/
1273	static int internal_display_show(struct seq_file *m, void *data)
1274	{
1275	struct drm_connector *connector = m->private;
1276	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
1277	struct dc_link *link = aconnector->dc_link;
1278
1279	seq_printf(m, fmt: "Internal: %u\n", link->is_internal_display);
1280
1281	return 0;
1282	}
1283
1284	/*
1285	* Returns the number of segments used if ODM Combine mode is enabled.
1286	* Example usage: cat /sys/kernel/debug/dri/0/DP-1/odm_combine_segments
1287	*/
1288	static int odm_combine_segments_show(struct seq_file *m, void *unused)
1289	{
1290	struct drm_connector *connector = m->private;
1291	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
1292	struct dc_link *link = aconnector->dc_link;
1293	struct pipe_ctx *pipe_ctx = NULL;
1294	int i, segments = -EOPNOTSUPP;
1295
1296	for (i = 0; i < MAX_PIPES; i++) {
1297	pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i];
1298	if (pipe_ctx->stream &&
1299	pipe_ctx->stream->link == link)
1300	break;
1301	}
1302
1303	if (connector->status != connector_status_connected)
1304	return -ENODEV;
1305
1306	if (pipe_ctx && pipe_ctx->stream_res.tg &&
1307	pipe_ctx->stream_res.tg->funcs->get_odm_combine_segments)
1308	pipe_ctx->stream_res.tg->funcs->get_odm_combine_segments(pipe_ctx->stream_res.tg, &segments);
1309
1310	seq_printf(m, fmt: "%d\n", segments);
1311	return 0;
1312	}
1313
1314	/* function description
1315	*
1316	* generic SDP message access for testing
1317	*
1318	* debugfs sdp_message is located at /syskernel/debug/dri/0/DP-x
1319	*
1320	* SDP header
1321	* Hb0 : Secondary-Data Packet ID
1322	* Hb1 : Secondary-Data Packet type
1323	* Hb2 : Secondary-Data-packet-specific header, Byte 0
1324	* Hb3 : Secondary-Data-packet-specific header, Byte 1
1325	*
1326	* for using custom sdp message: input 4 bytes SDP header and 32 bytes raw data
1327	*/
1328	static ssize_t dp_sdp_message_debugfs_write(struct file *f, const char __user *buf,
1329	size_t size, loff_t *pos)
1330	{
1331	int r;
1332	uint8_t data[36] = {0};
1333	struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
1334	struct dm_crtc_state *acrtc_state;
1335	uint32_t write_size = 36;
1336
1337	if (connector->base.status != connector_status_connected)
1338	return -ENODEV;
1339
1340	if (size == 0)
1341	return 0;
1342
1343	acrtc_state = to_dm_crtc_state(connector->base.state->crtc->state);
1344
1345	r = copy_from_user(to: data, from: buf, n: write_size);
1346
1347	write_size -= r;
1348
1349	dc_stream_send_dp_sdp(stream: acrtc_state->stream, custom_sdp_message: data, sdp_message_size: write_size);
1350
1351	return write_size;
1352	}
1353
1354	/* function: Read link's DSC & FEC capabilities
1355	*
1356	*
1357	* Access it with the following command (you need to specify
1358	* connector like DP-1):
1359	*
1360	* cat /sys/kernel/debug/dri/0/DP-X/dp_dsc_fec_support
1361	*
1362	*/
1363	static int dp_dsc_fec_support_show(struct seq_file *m, void *data)
1364	{
1365	struct drm_connector *connector = m->private;
1366	struct drm_modeset_acquire_ctx ctx;
1367	struct drm_device *dev = connector->dev;
1368	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
1369	int ret = 0;
1370	bool try_again = false;
1371	bool is_fec_supported = false;
1372	bool is_dsc_supported = false;
1373	struct dpcd_caps dpcd_caps;
1374
1375	drm_modeset_acquire_init(ctx: &ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE);
1376	do {
1377	try_again = false;
1378	ret = drm_modeset_lock(lock: &dev->mode_config.connection_mutex, ctx: &ctx);
1379	if (ret) {
1380	if (ret == -EDEADLK) {
1381	ret = drm_modeset_backoff(ctx: &ctx);
1382	if (!ret) {
1383	try_again = true;
1384	continue;
1385	}
1386	}
1387	break;
1388	}
1389	if (connector->status != connector_status_connected) {
1390	ret = -ENODEV;
1391	break;
1392	}
1393	dpcd_caps = aconnector->dc_link->dpcd_caps;
1394	if (aconnector->mst_output_port) {
1395	/* aconnector sets dsc_aux during get_modes call
1396	* if MST connector has it means it can either
1397	* enable DSC on the sink device or on MST branch
1398	* its connected to.
1399	*/
1400	if (aconnector->dsc_aux) {
1401	is_fec_supported = true;
1402	is_dsc_supported = true;
1403	}
1404	} else {
1405	is_fec_supported = dpcd_caps.fec_cap.raw & 0x1;
1406	is_dsc_supported = dpcd_caps.dsc_caps.dsc_basic_caps.raw[0] & 0x1;
1407	}
1408	} while (try_again);
1409
1410	drm_modeset_drop_locks(ctx: &ctx);
1411	drm_modeset_acquire_fini(ctx: &ctx);
1412
1413	seq_printf(m, fmt: "FEC_Sink_Support: %s\n", str_yes_no(v: is_fec_supported));
1414	seq_printf(m, fmt: "DSC_Sink_Support: %s\n", str_yes_no(v: is_dsc_supported));
1415
1416	return ret;
1417	}
1418
1419	/* function: Trigger virtual HPD redetection on connector
1420	*
1421	* This function will perform link rediscovery, link disable
1422	* and enable, and dm connector state update.
1423	*
1424	* Retrigger HPD on an existing connector by echoing 1 into
1425	* its respectful "trigger_hotplug" debugfs entry:
1426	*
1427	* echo 1 > /sys/kernel/debug/dri/0/DP-X/trigger_hotplug
1428	*
1429	* This function can perform HPD unplug:
1430	*
1431	* echo 0 > /sys/kernel/debug/dri/0/DP-X/trigger_hotplug
1432	*
1433	*/
1434	static ssize_t trigger_hotplug(struct file *f, const char __user *buf,
1435	size_t size, loff_t *pos)
1436	{
1437	struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1438	struct drm_connector *connector = &aconnector->base;
1439	struct dc_link *link = NULL;
1440	struct drm_device *dev = connector->dev;
1441	struct amdgpu_device *adev = drm_to_adev(ddev: dev);
1442	enum dc_connection_type new_connection_type = dc_connection_none;
1443	char *wr_buf = NULL;
1444	uint32_t wr_buf_size = 42;
1445	int max_param_num = 1;
1446	long param[1] = {0};
1447	uint8_t param_nums = 0;
1448	bool ret = false;
1449
1450	if (!aconnector->dc_link)
1451	return -EINVAL;
1452
1453	if (size == 0)
1454	return -EINVAL;
1455
1456	wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1457
1458	if (!wr_buf) {
1459	DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1460	return -ENOSPC;
1461	}
1462
1463	if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
1464	param: (long *)param, buf,
1465	max_param_num,
1466	param_nums: &param_nums)) {
1467	kfree(objp: wr_buf);
1468	return -EINVAL;
1469	}
1470
1471	kfree(objp: wr_buf);
1472
1473	if (param_nums <= 0) {
1474	DRM_DEBUG_DRIVER("user data not be read\n");
1475	return -EINVAL;
1476	}
1477
1478	mutex_lock(&aconnector->hpd_lock);
1479
1480	/* Don't support for mst end device*/
1481	if (aconnector->mst_root) {
1482	mutex_unlock(lock: &aconnector->hpd_lock);
1483	return -EINVAL;
1484	}
1485
1486	if (param[0] == 1) {
1487
1488	if (!dc_link_detect_connection_type(link: aconnector->dc_link, type: &new_connection_type) &&
1489	new_connection_type != dc_connection_none)
1490	goto unlock;
1491
1492	mutex_lock(&adev->dm.dc_lock);
1493	ret = dc_link_detect(link: aconnector->dc_link, reason: DETECT_REASON_HPD);
1494	mutex_unlock(lock: &adev->dm.dc_lock);
1495
1496	if (!ret)
1497	goto unlock;
1498
1499	amdgpu_dm_update_connector_after_detect(aconnector);
1500
1501	drm_modeset_lock_all(dev);
1502	dm_restore_drm_connector_state(dev, connector);
1503	drm_modeset_unlock_all(dev);
1504
1505	drm_kms_helper_connector_hotplug_event(connector);
1506	} else if (param[0] == 0) {
1507	if (!aconnector->dc_link)
1508	goto unlock;
1509
1510	link = aconnector->dc_link;
1511
1512	if (link->local_sink) {
1513	dc_sink_release(sink: link->local_sink);
1514	link->local_sink = NULL;
1515	}
1516
1517	link->dpcd_sink_count = 0;
1518	link->type = dc_connection_none;
1519	link->dongle_max_pix_clk = 0;
1520
1521	amdgpu_dm_update_connector_after_detect(aconnector);
1522
1523	/* If the aconnector is the root node in mst topology */
1524	if (aconnector->mst_mgr.mst_state == true)
1525	dc_link_reset_cur_dp_mst_topology(link);
1526
1527	drm_modeset_lock_all(dev);
1528	dm_restore_drm_connector_state(dev, connector);
1529	drm_modeset_unlock_all(dev);
1530
1531	drm_kms_helper_connector_hotplug_event(connector);
1532	}
1533
1534	unlock:
1535	mutex_unlock(lock: &aconnector->hpd_lock);
1536
1537	return size;
1538	}
1539
1540	/* function: read DSC status on the connector
1541	*
1542	* The read function: dp_dsc_clock_en_read
1543	* returns current status of DSC clock on the connector.
1544	* The return is a boolean flag: 1 or 0.
1545	*
1546	* Access it with the following command (you need to specify
1547	* connector like DP-1):
1548	*
1549	* cat /sys/kernel/debug/dri/0/DP-X/dsc_clock_en
1550	*
1551	* Expected output:
1552	* 1 - means that DSC is currently enabled
1553	* 0 - means that DSC is disabled
1554	*/
1555	static ssize_t dp_dsc_clock_en_read(struct file *f, char __user *buf,
1556	size_t size, loff_t *pos)
1557	{
1558	char *rd_buf = NULL;
1559	struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1560	struct display_stream_compressor *dsc;
1561	struct dcn_dsc_state dsc_state = {0};
1562	const uint32_t rd_buf_size = 10;
1563	struct pipe_ctx *pipe_ctx;
1564	ssize_t result = 0;
1565	int i, r, str_len = 10;
1566
1567	rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
1568
1569	if (!rd_buf)
1570	return -ENOMEM;
1571
1572	for (i = 0; i < MAX_PIPES; i++) {
1573	pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1574	if (pipe_ctx->stream &&
1575	pipe_ctx->stream->link == aconnector->dc_link &&
1576	pipe_ctx->stream->sink &&
1577	pipe_ctx->stream->sink == aconnector->dc_sink)
1578	break;
1579	}
1580
1581	dsc = pipe_ctx->stream_res.dsc;
1582	if (dsc)
1583	dsc->funcs->dsc_read_state(dsc, &dsc_state);
1584
1585	snprintf(buf: rd_buf, size: str_len,
1586	fmt: "%d\n",
1587	dsc_state.dsc_clock_en);
1588
1589	while (size) {
1590	if (*pos >= rd_buf_size)
1591	break;
1592
1593	r = put_user(*(rd_buf + result), buf);
1594	if (r) {
1595	kfree(objp: rd_buf);
1596	return r; /* r = -EFAULT */
1597	}
1598
1599	buf += 1;
1600	size -= 1;
1601	*pos += 1;
1602	result += 1;
1603	}
1604
1605	kfree(objp: rd_buf);
1606	return result;
1607	}
1608
1609	/* function: write force DSC on the connector
1610	*
1611	* The write function: dp_dsc_clock_en_write
1612	* enables to force DSC on the connector.
1613	* User can write to either force enable or force disable DSC
1614	* on the next modeset or set it to driver default
1615	*
1616	* Accepted inputs:
1617	* 0 - default DSC enablement policy
1618	* 1 - force enable DSC on the connector
1619	* 2 - force disable DSC on the connector (might cause fail in atomic_check)
1620	*
1621	* Writing DSC settings is done with the following command:
1622	* - To force enable DSC (you need to specify
1623	* connector like DP-1):
1624	*
1625	* echo 0x1 > /sys/kernel/debug/dri/0/DP-X/dsc_clock_en
1626	*
1627	* - To return to default state set the flag to zero and
1628	* let driver deal with DSC automatically
1629	* (you need to specify connector like DP-1):
1630	*
1631	* echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_clock_en
1632	*
1633	*/
1634	static ssize_t dp_dsc_clock_en_write(struct file *f, const char __user *buf,
1635	size_t size, loff_t *pos)
1636	{
1637	struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1638	struct drm_connector *connector = &aconnector->base;
1639	struct drm_device *dev = connector->dev;
1640	struct drm_crtc *crtc = NULL;
1641	struct dm_crtc_state *dm_crtc_state = NULL;
1642	struct pipe_ctx *pipe_ctx;
1643	int i;
1644	char *wr_buf = NULL;
1645	uint32_t wr_buf_size = 42;
1646	int max_param_num = 1;
1647	long param[1] = {0};
1648	uint8_t param_nums = 0;
1649
1650	if (size == 0)
1651	return -EINVAL;
1652
1653	wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1654
1655	if (!wr_buf) {
1656	DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1657	return -ENOSPC;
1658	}
1659
1660	if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
1661	param: (long *)param, buf,
1662	max_param_num,
1663	param_nums: &param_nums)) {
1664	kfree(objp: wr_buf);
1665	return -EINVAL;
1666	}
1667
1668	if (param_nums <= 0) {
1669	DRM_DEBUG_DRIVER("user data not be read\n");
1670	kfree(objp: wr_buf);
1671	return -EINVAL;
1672	}
1673
1674	for (i = 0; i < MAX_PIPES; i++) {
1675	pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1676	if (pipe_ctx->stream &&
1677	pipe_ctx->stream->link == aconnector->dc_link &&
1678	pipe_ctx->stream->sink &&
1679	pipe_ctx->stream->sink == aconnector->dc_sink)
1680	break;
1681	}
1682
1683	if (!pipe_ctx->stream)
1684	goto done;
1685
1686	// Get CRTC state
1687	mutex_lock(&dev->mode_config.mutex);
1688	drm_modeset_lock(lock: &dev->mode_config.connection_mutex, NULL);
1689
1690	if (connector->state == NULL)
1691	goto unlock;
1692
1693	crtc = connector->state->crtc;
1694	if (crtc == NULL)
1695	goto unlock;
1696
1697	drm_modeset_lock(lock: &crtc->mutex, NULL);
1698	if (crtc->state == NULL)
1699	goto unlock;
1700
1701	dm_crtc_state = to_dm_crtc_state(crtc->state);
1702	if (dm_crtc_state->stream == NULL)
1703	goto unlock;
1704
1705	if (param[0] == 1)
1706	aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_ENABLE;
1707	else if (param[0] == 2)
1708	aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_DISABLE;
1709	else
1710	aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_DEFAULT;
1711
1712	dm_crtc_state->dsc_force_changed = true;
1713
1714	unlock:
1715	if (crtc)
1716	drm_modeset_unlock(lock: &crtc->mutex);
1717	drm_modeset_unlock(lock: &dev->mode_config.connection_mutex);
1718	mutex_unlock(lock: &dev->mode_config.mutex);
1719
1720	done:
1721	kfree(objp: wr_buf);
1722	return size;
1723	}
1724
1725	/* function: read DSC slice width parameter on the connector
1726	*
1727	* The read function: dp_dsc_slice_width_read
1728	* returns dsc slice width used in the current configuration
1729	* The return is an integer: 0 or other positive number
1730	*
1731	* Access the status with the following command:
1732	*
1733	* cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_width
1734	*
1735	* 0 - means that DSC is disabled
1736	*
1737	* Any other number more than zero represents the
1738	* slice width currently used by DSC in pixels
1739	*
1740	*/
1741	static ssize_t dp_dsc_slice_width_read(struct file *f, char __user *buf,
1742	size_t size, loff_t *pos)
1743	{
1744	char *rd_buf = NULL;
1745	struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1746	struct display_stream_compressor *dsc;
1747	struct dcn_dsc_state dsc_state = {0};
1748	const uint32_t rd_buf_size = 100;
1749	struct pipe_ctx *pipe_ctx;
1750	ssize_t result = 0;
1751	int i, r, str_len = 30;
1752
1753	rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
1754
1755	if (!rd_buf)
1756	return -ENOMEM;
1757
1758	for (i = 0; i < MAX_PIPES; i++) {
1759	pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1760	if (pipe_ctx->stream &&
1761	pipe_ctx->stream->link == aconnector->dc_link &&
1762	pipe_ctx->stream->sink &&
1763	pipe_ctx->stream->sink == aconnector->dc_sink)
1764	break;
1765	}
1766
1767	dsc = pipe_ctx->stream_res.dsc;
1768	if (dsc)
1769	dsc->funcs->dsc_read_state(dsc, &dsc_state);
1770
1771	snprintf(buf: rd_buf, size: str_len,
1772	fmt: "%d\n",
1773	dsc_state.dsc_slice_width);
1774
1775	while (size) {
1776	if (*pos >= rd_buf_size)
1777	break;
1778
1779	r = put_user(*(rd_buf + result), buf);
1780	if (r) {
1781	kfree(objp: rd_buf);
1782	return r; /* r = -EFAULT */
1783	}
1784
1785	buf += 1;
1786	size -= 1;
1787	*pos += 1;
1788	result += 1;
1789	}
1790
1791	kfree(objp: rd_buf);
1792	return result;
1793	}
1794
1795	/* function: write DSC slice width parameter
1796	*
1797	* The write function: dp_dsc_slice_width_write
1798	* overwrites automatically generated DSC configuration
1799	* of slice width.
1800	*
1801	* The user has to write the slice width divisible by the
1802	* picture width.
1803	*
1804	* Also the user has to write width in hexidecimal
1805	* rather than in decimal.
1806	*
1807	* Writing DSC settings is done with the following command:
1808	* - To force overwrite slice width: (example sets to 1920 pixels)
1809	*
1810	* echo 0x780 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_width
1811	*
1812	* - To stop overwriting and let driver find the optimal size,
1813	* set the width to zero:
1814	*
1815	* echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_width
1816	*
1817	*/
1818	static ssize_t dp_dsc_slice_width_write(struct file *f, const char __user *buf,
1819	size_t size, loff_t *pos)
1820	{
1821	struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1822	struct pipe_ctx *pipe_ctx;
1823	struct drm_connector *connector = &aconnector->base;
1824	struct drm_device *dev = connector->dev;
1825	struct drm_crtc *crtc = NULL;
1826	struct dm_crtc_state *dm_crtc_state = NULL;
1827	int i;
1828	char *wr_buf = NULL;
1829	uint32_t wr_buf_size = 42;
1830	int max_param_num = 1;
1831	long param[1] = {0};
1832	uint8_t param_nums = 0;
1833
1834	if (size == 0)
1835	return -EINVAL;
1836
1837	wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
1838
1839	if (!wr_buf) {
1840	DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
1841	return -ENOSPC;
1842	}
1843
1844	if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
1845	param: (long *)param, buf,
1846	max_param_num,
1847	param_nums: &param_nums)) {
1848	kfree(objp: wr_buf);
1849	return -EINVAL;
1850	}
1851
1852	if (param_nums <= 0) {
1853	DRM_DEBUG_DRIVER("user data not be read\n");
1854	kfree(objp: wr_buf);
1855	return -EINVAL;
1856	}
1857
1858	for (i = 0; i < MAX_PIPES; i++) {
1859	pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1860	if (pipe_ctx->stream &&
1861	pipe_ctx->stream->link == aconnector->dc_link &&
1862	pipe_ctx->stream->sink &&
1863	pipe_ctx->stream->sink == aconnector->dc_sink)
1864	break;
1865	}
1866
1867	if (!pipe_ctx->stream)
1868	goto done;
1869
1870	// Safely get CRTC state
1871	mutex_lock(&dev->mode_config.mutex);
1872	drm_modeset_lock(lock: &dev->mode_config.connection_mutex, NULL);
1873
1874	if (connector->state == NULL)
1875	goto unlock;
1876
1877	crtc = connector->state->crtc;
1878	if (crtc == NULL)
1879	goto unlock;
1880
1881	drm_modeset_lock(lock: &crtc->mutex, NULL);
1882	if (crtc->state == NULL)
1883	goto unlock;
1884
1885	dm_crtc_state = to_dm_crtc_state(crtc->state);
1886	if (dm_crtc_state->stream == NULL)
1887	goto unlock;
1888
1889	if (param[0] > 0)
1890	aconnector->dsc_settings.dsc_num_slices_h = DIV_ROUND_UP(
1891	pipe_ctx->stream->timing.h_addressable,
1892	param[0]);
1893	else
1894	aconnector->dsc_settings.dsc_num_slices_h = 0;
1895
1896	dm_crtc_state->dsc_force_changed = true;
1897
1898	unlock:
1899	if (crtc)
1900	drm_modeset_unlock(lock: &crtc->mutex);
1901	drm_modeset_unlock(lock: &dev->mode_config.connection_mutex);
1902	mutex_unlock(lock: &dev->mode_config.mutex);
1903
1904	done:
1905	kfree(objp: wr_buf);
1906	return size;
1907	}
1908
1909	/* function: read DSC slice height parameter on the connector
1910	*
1911	* The read function: dp_dsc_slice_height_read
1912	* returns dsc slice height used in the current configuration
1913	* The return is an integer: 0 or other positive number
1914	*
1915	* Access the status with the following command:
1916	*
1917	* cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_height
1918	*
1919	* 0 - means that DSC is disabled
1920	*
1921	* Any other number more than zero represents the
1922	* slice height currently used by DSC in pixels
1923	*
1924	*/
1925	static ssize_t dp_dsc_slice_height_read(struct file *f, char __user *buf,
1926	size_t size, loff_t *pos)
1927	{
1928	char *rd_buf = NULL;
1929	struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
1930	struct display_stream_compressor *dsc;
1931	struct dcn_dsc_state dsc_state = {0};
1932	const uint32_t rd_buf_size = 100;
1933	struct pipe_ctx *pipe_ctx;
1934	ssize_t result = 0;
1935	int i, r, str_len = 30;
1936
1937	rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
1938
1939	if (!rd_buf)
1940	return -ENOMEM;
1941
1942	for (i = 0; i < MAX_PIPES; i++) {
1943	pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
1944	if (pipe_ctx->stream &&
1945	pipe_ctx->stream->link == aconnector->dc_link &&
1946	pipe_ctx->stream->sink &&
1947	pipe_ctx->stream->sink == aconnector->dc_sink)
1948	break;
1949	}
1950
1951	dsc = pipe_ctx->stream_res.dsc;
1952	if (dsc)
1953	dsc->funcs->dsc_read_state(dsc, &dsc_state);
1954
1955	snprintf(buf: rd_buf, size: str_len,
1956	fmt: "%d\n",
1957	dsc_state.dsc_slice_height);
1958
1959	while (size) {
1960	if (*pos >= rd_buf_size)
1961	break;
1962
1963	r = put_user(*(rd_buf + result), buf);
1964	if (r) {
1965	kfree(objp: rd_buf);
1966	return r; /* r = -EFAULT */
1967	}
1968
1969	buf += 1;
1970	size -= 1;
1971	*pos += 1;
1972	result += 1;
1973	}
1974
1975	kfree(objp: rd_buf);
1976	return result;
1977	}
1978
1979	/* function: write DSC slice height parameter
1980	*
1981	* The write function: dp_dsc_slice_height_write
1982	* overwrites automatically generated DSC configuration
1983	* of slice height.
1984	*
1985	* The user has to write the slice height divisible by the
1986	* picture height.
1987	*
1988	* Also the user has to write height in hexidecimal
1989	* rather than in decimal.
1990	*
1991	* Writing DSC settings is done with the following command:
1992	* - To force overwrite slice height (example sets to 128 pixels):
1993	*
1994	* echo 0x80 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_height
1995	*
1996	* - To stop overwriting and let driver find the optimal size,
1997	* set the height to zero:
1998	*
1999	* echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_height
2000	*
2001	*/
2002	static ssize_t dp_dsc_slice_height_write(struct file *f, const char __user *buf,
2003	size_t size, loff_t *pos)
2004	{
2005	struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2006	struct drm_connector *connector = &aconnector->base;
2007	struct drm_device *dev = connector->dev;
2008	struct drm_crtc *crtc = NULL;
2009	struct dm_crtc_state *dm_crtc_state = NULL;
2010	struct pipe_ctx *pipe_ctx;
2011	int i;
2012	char *wr_buf = NULL;
2013	uint32_t wr_buf_size = 42;
2014	int max_param_num = 1;
2015	uint8_t param_nums = 0;
2016	long param[1] = {0};
2017
2018	if (size == 0)
2019	return -EINVAL;
2020
2021	wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
2022
2023	if (!wr_buf) {
2024	DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
2025	return -ENOSPC;
2026	}
2027
2028	if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
2029	param: (long *)param, buf,
2030	max_param_num,
2031	param_nums: &param_nums)) {
2032	kfree(objp: wr_buf);
2033	return -EINVAL;
2034	}
2035
2036	if (param_nums <= 0) {
2037	DRM_DEBUG_DRIVER("user data not be read\n");
2038	kfree(objp: wr_buf);
2039	return -EINVAL;
2040	}
2041
2042	for (i = 0; i < MAX_PIPES; i++) {
2043	pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2044	if (pipe_ctx->stream &&
2045	pipe_ctx->stream->link == aconnector->dc_link &&
2046	pipe_ctx->stream->sink &&
2047	pipe_ctx->stream->sink == aconnector->dc_sink)
2048	break;
2049	}
2050
2051	if (!pipe_ctx->stream)
2052	goto done;
2053
2054	// Get CRTC state
2055	mutex_lock(&dev->mode_config.mutex);
2056	drm_modeset_lock(lock: &dev->mode_config.connection_mutex, NULL);
2057
2058	if (connector->state == NULL)
2059	goto unlock;
2060
2061	crtc = connector->state->crtc;
2062	if (crtc == NULL)
2063	goto unlock;
2064
2065	drm_modeset_lock(lock: &crtc->mutex, NULL);
2066	if (crtc->state == NULL)
2067	goto unlock;
2068
2069	dm_crtc_state = to_dm_crtc_state(crtc->state);
2070	if (dm_crtc_state->stream == NULL)
2071	goto unlock;
2072
2073	if (param[0] > 0)
2074	aconnector->dsc_settings.dsc_num_slices_v = DIV_ROUND_UP(
2075	pipe_ctx->stream->timing.v_addressable,
2076	param[0]);
2077	else
2078	aconnector->dsc_settings.dsc_num_slices_v = 0;
2079
2080	dm_crtc_state->dsc_force_changed = true;
2081
2082	unlock:
2083	if (crtc)
2084	drm_modeset_unlock(lock: &crtc->mutex);
2085	drm_modeset_unlock(lock: &dev->mode_config.connection_mutex);
2086	mutex_unlock(lock: &dev->mode_config.mutex);
2087
2088	done:
2089	kfree(objp: wr_buf);
2090	return size;
2091	}
2092
2093	/* function: read DSC target rate on the connector in bits per pixel
2094	*
2095	* The read function: dp_dsc_bits_per_pixel_read
2096	* returns target rate of compression in bits per pixel
2097	* The return is an integer: 0 or other positive integer
2098	*
2099	* Access it with the following command:
2100	*
2101	* cat /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel
2102	*
2103	* 0 - means that DSC is disabled
2104	*/
2105	static ssize_t dp_dsc_bits_per_pixel_read(struct file *f, char __user *buf,
2106	size_t size, loff_t *pos)
2107	{
2108	char *rd_buf = NULL;
2109	struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2110	struct display_stream_compressor *dsc;
2111	struct dcn_dsc_state dsc_state = {0};
2112	const uint32_t rd_buf_size = 100;
2113	struct pipe_ctx *pipe_ctx;
2114	ssize_t result = 0;
2115	int i, r, str_len = 30;
2116
2117	rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2118
2119	if (!rd_buf)
2120	return -ENOMEM;
2121
2122	for (i = 0; i < MAX_PIPES; i++) {
2123	pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2124	if (pipe_ctx->stream &&
2125	pipe_ctx->stream->link == aconnector->dc_link &&
2126	pipe_ctx->stream->sink &&
2127	pipe_ctx->stream->sink == aconnector->dc_sink)
2128	break;
2129	}
2130
2131	dsc = pipe_ctx->stream_res.dsc;
2132	if (dsc)
2133	dsc->funcs->dsc_read_state(dsc, &dsc_state);
2134
2135	snprintf(buf: rd_buf, size: str_len,
2136	fmt: "%d\n",
2137	dsc_state.dsc_bits_per_pixel);
2138
2139	while (size) {
2140	if (*pos >= rd_buf_size)
2141	break;
2142
2143	r = put_user(*(rd_buf + result), buf);
2144	if (r) {
2145	kfree(objp: rd_buf);
2146	return r; /* r = -EFAULT */
2147	}
2148
2149	buf += 1;
2150	size -= 1;
2151	*pos += 1;
2152	result += 1;
2153	}
2154
2155	kfree(objp: rd_buf);
2156	return result;
2157	}
2158
2159	/* function: write DSC target rate in bits per pixel
2160	*
2161	* The write function: dp_dsc_bits_per_pixel_write
2162	* overwrites automatically generated DSC configuration
2163	* of DSC target bit rate.
2164	*
2165	* Also the user has to write bpp in hexidecimal
2166	* rather than in decimal.
2167	*
2168	* Writing DSC settings is done with the following command:
2169	* - To force overwrite rate (example sets to 256 bpp x 1/16):
2170	*
2171	* echo 0x100 > /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel
2172	*
2173	* - To stop overwriting and let driver find the optimal rate,
2174	* set the rate to zero:
2175	*
2176	* echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel
2177	*
2178	*/
2179	static ssize_t dp_dsc_bits_per_pixel_write(struct file *f, const char __user *buf,
2180	size_t size, loff_t *pos)
2181	{
2182	struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2183	struct drm_connector *connector = &aconnector->base;
2184	struct drm_device *dev = connector->dev;
2185	struct drm_crtc *crtc = NULL;
2186	struct dm_crtc_state *dm_crtc_state = NULL;
2187	struct pipe_ctx *pipe_ctx;
2188	int i;
2189	char *wr_buf = NULL;
2190	uint32_t wr_buf_size = 42;
2191	int max_param_num = 1;
2192	uint8_t param_nums = 0;
2193	long param[1] = {0};
2194
2195	if (size == 0)
2196	return -EINVAL;
2197
2198	wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
2199
2200	if (!wr_buf) {
2201	DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
2202	return -ENOSPC;
2203	}
2204
2205	if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
2206	param: (long *)param, buf,
2207	max_param_num,
2208	param_nums: &param_nums)) {
2209	kfree(objp: wr_buf);
2210	return -EINVAL;
2211	}
2212
2213	if (param_nums <= 0) {
2214	DRM_DEBUG_DRIVER("user data not be read\n");
2215	kfree(objp: wr_buf);
2216	return -EINVAL;
2217	}
2218
2219	for (i = 0; i < MAX_PIPES; i++) {
2220	pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2221	if (pipe_ctx->stream &&
2222	pipe_ctx->stream->link == aconnector->dc_link &&
2223	pipe_ctx->stream->sink &&
2224	pipe_ctx->stream->sink == aconnector->dc_sink)
2225	break;
2226	}
2227
2228	if (!pipe_ctx->stream)
2229	goto done;
2230
2231	// Get CRTC state
2232	mutex_lock(&dev->mode_config.mutex);
2233	drm_modeset_lock(lock: &dev->mode_config.connection_mutex, NULL);
2234
2235	if (connector->state == NULL)
2236	goto unlock;
2237
2238	crtc = connector->state->crtc;
2239	if (crtc == NULL)
2240	goto unlock;
2241
2242	drm_modeset_lock(lock: &crtc->mutex, NULL);
2243	if (crtc->state == NULL)
2244	goto unlock;
2245
2246	dm_crtc_state = to_dm_crtc_state(crtc->state);
2247	if (dm_crtc_state->stream == NULL)
2248	goto unlock;
2249
2250	aconnector->dsc_settings.dsc_bits_per_pixel = param[0];
2251
2252	dm_crtc_state->dsc_force_changed = true;
2253
2254	unlock:
2255	if (crtc)
2256	drm_modeset_unlock(lock: &crtc->mutex);
2257	drm_modeset_unlock(lock: &dev->mode_config.connection_mutex);
2258	mutex_unlock(lock: &dev->mode_config.mutex);
2259
2260	done:
2261	kfree(objp: wr_buf);
2262	return size;
2263	}
2264
2265	/* function: read DSC picture width parameter on the connector
2266	*
2267	* The read function: dp_dsc_pic_width_read
2268	* returns dsc picture width used in the current configuration
2269	* It is the same as h_addressable of the current
2270	* display's timing
2271	* The return is an integer: 0 or other positive integer
2272	* If 0 then DSC is disabled.
2273	*
2274	* Access it with the following command:
2275	*
2276	* cat /sys/kernel/debug/dri/0/DP-X/dsc_pic_width
2277	*
2278	* 0 - means that DSC is disabled
2279	*/
2280	static ssize_t dp_dsc_pic_width_read(struct file *f, char __user *buf,
2281	size_t size, loff_t *pos)
2282	{
2283	char *rd_buf = NULL;
2284	struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2285	struct display_stream_compressor *dsc;
2286	struct dcn_dsc_state dsc_state = {0};
2287	const uint32_t rd_buf_size = 100;
2288	struct pipe_ctx *pipe_ctx;
2289	ssize_t result = 0;
2290	int i, r, str_len = 30;
2291
2292	rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2293
2294	if (!rd_buf)
2295	return -ENOMEM;
2296
2297	for (i = 0; i < MAX_PIPES; i++) {
2298	pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2299	if (pipe_ctx->stream &&
2300	pipe_ctx->stream->link == aconnector->dc_link &&
2301	pipe_ctx->stream->sink &&
2302	pipe_ctx->stream->sink == aconnector->dc_sink)
2303	break;
2304	}
2305
2306	dsc = pipe_ctx->stream_res.dsc;
2307	if (dsc)
2308	dsc->funcs->dsc_read_state(dsc, &dsc_state);
2309
2310	snprintf(buf: rd_buf, size: str_len,
2311	fmt: "%d\n",
2312	dsc_state.dsc_pic_width);
2313
2314	while (size) {
2315	if (*pos >= rd_buf_size)
2316	break;
2317
2318	r = put_user(*(rd_buf + result), buf);
2319	if (r) {
2320	kfree(objp: rd_buf);
2321	return r; /* r = -EFAULT */
2322	}
2323
2324	buf += 1;
2325	size -= 1;
2326	*pos += 1;
2327	result += 1;
2328	}
2329
2330	kfree(objp: rd_buf);
2331	return result;
2332	}
2333
2334	static ssize_t dp_dsc_pic_height_read(struct file *f, char __user *buf,
2335	size_t size, loff_t *pos)
2336	{
2337	char *rd_buf = NULL;
2338	struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2339	struct display_stream_compressor *dsc;
2340	struct dcn_dsc_state dsc_state = {0};
2341	const uint32_t rd_buf_size = 100;
2342	struct pipe_ctx *pipe_ctx;
2343	ssize_t result = 0;
2344	int i, r, str_len = 30;
2345
2346	rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2347
2348	if (!rd_buf)
2349	return -ENOMEM;
2350
2351	for (i = 0; i < MAX_PIPES; i++) {
2352	pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2353	if (pipe_ctx->stream &&
2354	pipe_ctx->stream->link == aconnector->dc_link &&
2355	pipe_ctx->stream->sink &&
2356	pipe_ctx->stream->sink == aconnector->dc_sink)
2357	break;
2358	}
2359
2360	dsc = pipe_ctx->stream_res.dsc;
2361	if (dsc)
2362	dsc->funcs->dsc_read_state(dsc, &dsc_state);
2363
2364	snprintf(buf: rd_buf, size: str_len,
2365	fmt: "%d\n",
2366	dsc_state.dsc_pic_height);
2367
2368	while (size) {
2369	if (*pos >= rd_buf_size)
2370	break;
2371
2372	r = put_user(*(rd_buf + result), buf);
2373	if (r) {
2374	kfree(objp: rd_buf);
2375	return r; /* r = -EFAULT */
2376	}
2377
2378	buf += 1;
2379	size -= 1;
2380	*pos += 1;
2381	result += 1;
2382	}
2383
2384	kfree(objp: rd_buf);
2385	return result;
2386	}
2387
2388	/* function: read DSC chunk size parameter on the connector
2389	*
2390	* The read function: dp_dsc_chunk_size_read
2391	* returns dsc chunk size set in the current configuration
2392	* The value is calculated automatically by DSC code
2393	* and depends on slice parameters and bpp target rate
2394	* The return is an integer: 0 or other positive integer
2395	* If 0 then DSC is disabled.
2396	*
2397	* Access it with the following command:
2398	*
2399	* cat /sys/kernel/debug/dri/0/DP-X/dsc_chunk_size
2400	*
2401	* 0 - means that DSC is disabled
2402	*/
2403	static ssize_t dp_dsc_chunk_size_read(struct file *f, char __user *buf,
2404	size_t size, loff_t *pos)
2405	{
2406	char *rd_buf = NULL;
2407	struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2408	struct display_stream_compressor *dsc;
2409	struct dcn_dsc_state dsc_state = {0};
2410	const uint32_t rd_buf_size = 100;
2411	struct pipe_ctx *pipe_ctx;
2412	ssize_t result = 0;
2413	int i, r, str_len = 30;
2414
2415	rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2416
2417	if (!rd_buf)
2418	return -ENOMEM;
2419
2420	for (i = 0; i < MAX_PIPES; i++) {
2421	pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2422	if (pipe_ctx->stream &&
2423	pipe_ctx->stream->link == aconnector->dc_link &&
2424	pipe_ctx->stream->sink &&
2425	pipe_ctx->stream->sink == aconnector->dc_sink)
2426	break;
2427	}
2428
2429	dsc = pipe_ctx->stream_res.dsc;
2430	if (dsc)
2431	dsc->funcs->dsc_read_state(dsc, &dsc_state);
2432
2433	snprintf(buf: rd_buf, size: str_len,
2434	fmt: "%d\n",
2435	dsc_state.dsc_chunk_size);
2436
2437	while (size) {
2438	if (*pos >= rd_buf_size)
2439	break;
2440
2441	r = put_user(*(rd_buf + result), buf);
2442	if (r) {
2443	kfree(objp: rd_buf);
2444	return r; /* r = -EFAULT */
2445	}
2446
2447	buf += 1;
2448	size -= 1;
2449	*pos += 1;
2450	result += 1;
2451	}
2452
2453	kfree(objp: rd_buf);
2454	return result;
2455	}
2456
2457	/* function: read DSC slice bpg offset on the connector
2458	*
2459	* The read function: dp_dsc_slice_bpg_offset_read
2460	* returns dsc bpg slice offset set in the current configuration
2461	* The value is calculated automatically by DSC code
2462	* and depends on slice parameters and bpp target rate
2463	* The return is an integer: 0 or other positive integer
2464	* If 0 then DSC is disabled.
2465	*
2466	* Access it with the following command:
2467	*
2468	* cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_bpg_offset
2469	*
2470	* 0 - means that DSC is disabled
2471	*/
2472	static ssize_t dp_dsc_slice_bpg_offset_read(struct file *f, char __user *buf,
2473	size_t size, loff_t *pos)
2474	{
2475	char *rd_buf = NULL;
2476	struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2477	struct display_stream_compressor *dsc;
2478	struct dcn_dsc_state dsc_state = {0};
2479	const uint32_t rd_buf_size = 100;
2480	struct pipe_ctx *pipe_ctx;
2481	ssize_t result = 0;
2482	int i, r, str_len = 30;
2483
2484	rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2485
2486	if (!rd_buf)
2487	return -ENOMEM;
2488
2489	for (i = 0; i < MAX_PIPES; i++) {
2490	pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i];
2491	if (pipe_ctx->stream &&
2492	pipe_ctx->stream->link == aconnector->dc_link &&
2493	pipe_ctx->stream->sink &&
2494	pipe_ctx->stream->sink == aconnector->dc_sink)
2495	break;
2496	}
2497
2498	dsc = pipe_ctx->stream_res.dsc;
2499	if (dsc)
2500	dsc->funcs->dsc_read_state(dsc, &dsc_state);
2501
2502	snprintf(buf: rd_buf, size: str_len,
2503	fmt: "%d\n",
2504	dsc_state.dsc_slice_bpg_offset);
2505
2506	while (size) {
2507	if (*pos >= rd_buf_size)
2508	break;
2509
2510	r = put_user(*(rd_buf + result), buf);
2511	if (r) {
2512	kfree(objp: rd_buf);
2513	return r; /* r = -EFAULT */
2514	}
2515
2516	buf += 1;
2517	size -= 1;
2518	*pos += 1;
2519	result += 1;
2520	}
2521
2522	kfree(objp: rd_buf);
2523	return result;
2524	}
2525
2526
2527	/*
2528	* function description: Read max_requested_bpc property from the connector
2529	*
2530	* Access it with the following command:
2531	*
2532	* cat /sys/kernel/debug/dri/0/DP-X/max_bpc
2533	*
2534	*/
2535	static ssize_t dp_max_bpc_read(struct file *f, char __user *buf,
2536	size_t size, loff_t *pos)
2537	{
2538	struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2539	struct drm_connector *connector = &aconnector->base;
2540	struct drm_device *dev = connector->dev;
2541	struct dm_connector_state *state;
2542	ssize_t result = 0;
2543	char *rd_buf = NULL;
2544	char *rd_buf_ptr = NULL;
2545	const uint32_t rd_buf_size = 10;
2546	int r;
2547
2548	rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
2549
2550	if (!rd_buf)
2551	return -ENOMEM;
2552
2553	mutex_lock(&dev->mode_config.mutex);
2554	drm_modeset_lock(lock: &dev->mode_config.connection_mutex, NULL);
2555
2556	if (connector->state == NULL)
2557	goto unlock;
2558
2559	state = to_dm_connector_state(connector->state);
2560
2561	rd_buf_ptr = rd_buf;
2562	snprintf(buf: rd_buf_ptr, size: rd_buf_size,
2563	fmt: "%u\n",
2564	state->base.max_requested_bpc);
2565
2566	while (size) {
2567	if (*pos >= rd_buf_size)
2568	break;
2569
2570	r = put_user(*(rd_buf + result), buf);
2571	if (r) {
2572	result = r; /* r = -EFAULT */
2573	goto unlock;
2574	}
2575	buf += 1;
2576	size -= 1;
2577	*pos += 1;
2578	result += 1;
2579	}
2580	unlock:
2581	drm_modeset_unlock(lock: &dev->mode_config.connection_mutex);
2582	mutex_unlock(lock: &dev->mode_config.mutex);
2583	kfree(objp: rd_buf);
2584	return result;
2585	}
2586
2587
2588	/*
2589	* function description: Set max_requested_bpc property on the connector
2590	*
2591	* This function will not force the input BPC on connector, it will only
2592	* change the max value. This is equivalent to setting max_bpc through
2593	* xrandr.
2594	*
2595	* The BPC value written must be >= 6 and <= 16. Values outside of this
2596	* range will result in errors.
2597	*
2598	* BPC values:
2599	* 0x6 - 6 BPC
2600	* 0x8 - 8 BPC
2601	* 0xa - 10 BPC
2602	* 0xc - 12 BPC
2603	* 0x10 - 16 BPC
2604	*
2605	* Write the max_bpc in the following way:
2606	*
2607	* echo 0x6 > /sys/kernel/debug/dri/0/DP-X/max_bpc
2608	*
2609	*/
2610	static ssize_t dp_max_bpc_write(struct file *f, const char __user *buf,
2611	size_t size, loff_t *pos)
2612	{
2613	struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2614	struct drm_connector *connector = &aconnector->base;
2615	struct dm_connector_state *state;
2616	struct drm_device *dev = connector->dev;
2617	char *wr_buf = NULL;
2618	uint32_t wr_buf_size = 42;
2619	int max_param_num = 1;
2620	long param[1] = {0};
2621	uint8_t param_nums = 0;
2622
2623	if (size == 0)
2624	return -EINVAL;
2625
2626	wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
2627
2628	if (!wr_buf) {
2629	DRM_DEBUG_DRIVER("no memory to allocate write buffer\n");
2630	return -ENOSPC;
2631	}
2632
2633	if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
2634	param: (long *)param, buf,
2635	max_param_num,
2636	param_nums: &param_nums)) {
2637	kfree(objp: wr_buf);
2638	return -EINVAL;
2639	}
2640
2641	if (param_nums <= 0) {
2642	DRM_DEBUG_DRIVER("user data not be read\n");
2643	kfree(objp: wr_buf);
2644	return -EINVAL;
2645	}
2646
2647	if (param[0] < 6 || param[0] > 16) {
2648	DRM_DEBUG_DRIVER("bad max_bpc value\n");
2649	kfree(objp: wr_buf);
2650	return -EINVAL;
2651	}
2652
2653	mutex_lock(&dev->mode_config.mutex);
2654	drm_modeset_lock(lock: &dev->mode_config.connection_mutex, NULL);
2655
2656	if (connector->state == NULL)
2657	goto unlock;
2658
2659	state = to_dm_connector_state(connector->state);
2660	state->base.max_requested_bpc = param[0];
2661	unlock:
2662	drm_modeset_unlock(lock: &dev->mode_config.connection_mutex);
2663	mutex_unlock(lock: &dev->mode_config.mutex);
2664
2665	kfree(objp: wr_buf);
2666	return size;
2667	}
2668
2669	/*
2670	* IPS status. Read only.
2671	*
2672	* Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_ips_status
2673	*/
2674	static int ips_status_show(struct seq_file *m, void *unused)
2675	{
2676	struct amdgpu_device *adev = m->private;
2677	struct dc *dc = adev->dm.dc;
2678	struct dc_dmub_srv *dc_dmub_srv;
2679
2680	seq_printf(m, fmt: "IPS config: %d\n", dc->config.disable_ips);
2681	seq_printf(m, fmt: "Idle optimization: %d\n", dc->idle_optimizations_allowed);
2682
2683	if (adev->dm.idle_workqueue) {
2684	seq_printf(m, fmt: "Idle workqueue - enabled: %d\n", adev->dm.idle_workqueue->enable);
2685	seq_printf(m, fmt: "Idle workqueue - running: %d\n", adev->dm.idle_workqueue->running);
2686	}
2687
2688	dc_dmub_srv = dc->ctx->dmub_srv;
2689	if (dc_dmub_srv && dc_dmub_srv->dmub) {
2690	uint32_t rcg_count, ips1_count, ips2_count;
2691	volatile const struct dmub_shared_state_ips_fw *ips_fw =
2692	&dc_dmub_srv->dmub->shared_state[DMUB_SHARED_SHARE_FEATURE__IPS_FW].data.ips_fw;
2693	rcg_count = ips_fw->rcg_entry_count;
2694	ips1_count = ips_fw->ips1_entry_count;
2695	ips2_count = ips_fw->ips2_entry_count;
2696	seq_printf(m, fmt: "entry counts: rcg=%u ips1=%u ips2=%u\n",
2697	rcg_count,
2698	ips1_count,
2699	ips2_count);
2700	rcg_count = ips_fw->rcg_exit_count;
2701	ips1_count = ips_fw->ips1_exit_count;
2702	ips2_count = ips_fw->ips2_exit_count;
2703	seq_printf(m, fmt: "exit counts: rcg=%u ips1=%u ips2=%u",
2704	rcg_count,
2705	ips1_count,
2706	ips2_count);
2707	seq_puts(m, s: "\n");
2708	}
2709	return 0;
2710	}
2711
2712	/*
2713	* Backlight at this moment. Read only.
2714	* As written to display, taking ABM and backlight lut into account.
2715	* Ranges from 0x0 to 0x10000 (= 100% PWM)
2716	*
2717	* Example usage: cat /sys/kernel/debug/dri/0/eDP-1/current_backlight
2718	*/
2719	static int current_backlight_show(struct seq_file *m, void *unused)
2720	{
2721	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private);
2722	struct dc_link *link = aconnector->dc_link;
2723	unsigned int backlight;
2724
2725	backlight = dc_link_get_backlight_level(dc_link: link);
2726	seq_printf(m, fmt: "0x%x\n", backlight);
2727
2728	return 0;
2729	}
2730
2731	/*
2732	* Backlight value that is being approached. Read only.
2733	* As written to display, taking ABM and backlight lut into account.
2734	* Ranges from 0x0 to 0x10000 (= 100% PWM)
2735	*
2736	* Example usage: cat /sys/kernel/debug/dri/0/eDP-1/target_backlight
2737	*/
2738	static int target_backlight_show(struct seq_file *m, void *unused)
2739	{
2740	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private);
2741	struct dc_link *link = aconnector->dc_link;
2742	unsigned int backlight;
2743
2744	backlight = dc_link_get_target_backlight_pwm(link);
2745	seq_printf(m, fmt: "0x%x\n", backlight);
2746
2747	return 0;
2748	}
2749
2750	/*
2751	* function description: Determine if the connector is mst connector
2752	*
2753	* This function helps to determine whether a connector is a mst connector.
2754	* - "root" stands for the root connector of the topology
2755	* - "branch" stands for branch device of the topology
2756	* - "end" stands for leaf node connector of the topology
2757	* - "no" stands for the connector is not a device of a mst topology
2758	* Access it with the following command:
2759	*
2760	* cat /sys/kernel/debug/dri/0/DP-X/is_mst_connector
2761	*
2762	*/
2763	static int dp_is_mst_connector_show(struct seq_file *m, void *unused)
2764	{
2765	struct drm_connector *connector = m->private;
2766	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
2767	struct drm_dp_mst_topology_mgr *mgr = NULL;
2768	struct drm_dp_mst_port *port = NULL;
2769	char *role = NULL;
2770
2771	mutex_lock(&aconnector->hpd_lock);
2772
2773	if (aconnector->mst_mgr.mst_state) {
2774	role = "root";
2775	} else if (aconnector->mst_root &&
2776	aconnector->mst_root->mst_mgr.mst_state) {
2777
2778	role = "end";
2779
2780	mgr = &aconnector->mst_root->mst_mgr;
2781	port = aconnector->mst_output_port;
2782
2783	drm_modeset_lock(lock: &mgr->base.lock, NULL);
2784	if (port->pdt == DP_PEER_DEVICE_MST_BRANCHING &&
2785	port->mcs)
2786	role = "branch";
2787	drm_modeset_unlock(lock: &mgr->base.lock);
2788
2789	} else {
2790	role = "no";
2791	}
2792
2793	seq_printf(m, fmt: "%s\n", role);
2794
2795	mutex_unlock(lock: &aconnector->hpd_lock);
2796
2797	return 0;
2798	}
2799
2800	/*
2801	* function description: Read out the mst progress status
2802	*
2803	* This function helps to determine the mst progress status of
2804	* a mst connector.
2805	*
2806	* Access it with the following command:
2807	*
2808	* cat /sys/kernel/debug/dri/0/DP-X/mst_progress_status
2809	*
2810	*/
2811	static int dp_mst_progress_status_show(struct seq_file *m, void *unused)
2812	{
2813	struct drm_connector *connector = m->private;
2814	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
2815	struct amdgpu_device *adev = drm_to_adev(ddev: connector->dev);
2816	int i;
2817
2818	mutex_lock(&aconnector->hpd_lock);
2819	mutex_lock(&adev->dm.dc_lock);
2820
2821	if (aconnector->mst_status == MST_STATUS_DEFAULT) {
2822	seq_puts(m, s: "disabled\n");
2823	} else {
2824	for (i = 0; i < sizeof(mst_progress_status)/sizeof(char *); i++)
2825	seq_printf(m, fmt: "%s:%s\n",
2826	mst_progress_status[i],
2827	aconnector->mst_status & BIT(i) ? "done" : "not_done");
2828	}
2829
2830	mutex_unlock(lock: &adev->dm.dc_lock);
2831	mutex_unlock(lock: &aconnector->hpd_lock);
2832
2833	return 0;
2834	}
2835
2836	/*
2837	* Reports whether the connected display is a USB4 DPIA tunneled display
2838	* Example usage: cat /sys/kernel/debug/dri/0/DP-8/is_dpia_link
2839	*/
2840	static int is_dpia_link_show(struct seq_file *m, void *data)
2841	{
2842	struct drm_connector *connector = m->private;
2843	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
2844	struct dc_link *link = aconnector->dc_link;
2845
2846	if (connector->status != connector_status_connected)
2847	return -ENODEV;
2848
2849	seq_printf(m, fmt: "%s\n", (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) ? "yes" :
2850	(link->ep_type == DISPLAY_ENDPOINT_PHY) ? "no" : "unknown");
2851
2852	return 0;
2853	}
2854
2855	/**
2856	* hdmi_cec_state_show - Read out the HDMI-CEC feature status
2857	* @m: sequence file.
2858	* @data: unused.
2859	*
2860	* Return 0 on success
2861	*/
2862	static int hdmi_cec_state_show(struct seq_file *m, void *data)
2863	{
2864	struct drm_connector *connector = m->private;
2865	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
2866
2867	seq_printf(m, fmt: "%s:%d\n", connector->name, connector->base.id);
2868	seq_printf(m, fmt: "HDMI-CEC status: %d\n", aconnector->notifier ? 1 : 0);
2869
2870	return 0;
2871	}
2872
2873	/**
2874	* hdmi_cec_state_write - Enable/Disable HDMI-CEC feature from driver side
2875	* @f: file structure.
2876	* @buf: userspace buffer. set to '1' to enable; '0' to disable cec feature.
2877	* @size: size of buffer from userpsace.
2878	* @pos: unused.
2879	*
2880	* Return size on success, error code on failure
2881	*/
2882	static ssize_t hdmi_cec_state_write(struct file *f, const char __user *buf,
2883	size_t size, loff_t *pos)
2884	{
2885	int ret;
2886	bool enable;
2887	struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private;
2888	struct drm_device *ddev = aconnector->base.dev;
2889
2890	if (size == 0)
2891	return -EINVAL;
2892
2893	ret = kstrtobool_from_user(s: buf, count: size, res: &enable);
2894	if (ret) {
2895	drm_dbg_driver(ddev, "invalid user data !\n");
2896	return ret;
2897	}
2898
2899	if (enable) {
2900	if (aconnector->notifier)
2901	return -EINVAL;
2902	ret = amdgpu_dm_initialize_hdmi_connector(aconnector);
2903	if (ret)
2904	return ret;
2905	hdmi_cec_set_edid(aconnector);
2906	} else {
2907	if (!aconnector->notifier)
2908	return -EINVAL;
2909	cec_notifier_conn_unregister(n: aconnector->notifier);
2910	aconnector->notifier = NULL;
2911	}
2912
2913	return size;
2914	}
2915
2916	DEFINE_SHOW_ATTRIBUTE(dp_dsc_fec_support);
2917	DEFINE_SHOW_ATTRIBUTE(dmub_fw_state);
2918	DEFINE_SHOW_ATTRIBUTE(dmub_tracebuffer);
2919	DEFINE_SHOW_ATTRIBUTE(dp_lttpr_status);
2920	DEFINE_SHOW_ATTRIBUTE(hdcp_sink_capability);
2921	DEFINE_SHOW_ATTRIBUTE(internal_display);
2922	DEFINE_SHOW_ATTRIBUTE(odm_combine_segments);
2923	DEFINE_SHOW_ATTRIBUTE(replay_capability);
2924	DEFINE_SHOW_ATTRIBUTE(psr_capability);
2925	DEFINE_SHOW_ATTRIBUTE(dp_is_mst_connector);
2926	DEFINE_SHOW_ATTRIBUTE(dp_mst_progress_status);
2927	DEFINE_SHOW_ATTRIBUTE(is_dpia_link);
2928	DEFINE_SHOW_STORE_ATTRIBUTE(hdmi_cec_state);
2929
2930	static const struct file_operations dp_dsc_clock_en_debugfs_fops = {
2931	.owner = THIS_MODULE,
2932	.read = dp_dsc_clock_en_read,
2933	.write = dp_dsc_clock_en_write,
2934	.llseek = default_llseek
2935	};
2936
2937	static const struct file_operations dp_dsc_slice_width_debugfs_fops = {
2938	.owner = THIS_MODULE,
2939	.read = dp_dsc_slice_width_read,
2940	.write = dp_dsc_slice_width_write,
2941	.llseek = default_llseek
2942	};
2943
2944	static const struct file_operations dp_dsc_slice_height_debugfs_fops = {
2945	.owner = THIS_MODULE,
2946	.read = dp_dsc_slice_height_read,
2947	.write = dp_dsc_slice_height_write,
2948	.llseek = default_llseek
2949	};
2950
2951	static const struct file_operations dp_dsc_bits_per_pixel_debugfs_fops = {
2952	.owner = THIS_MODULE,
2953	.read = dp_dsc_bits_per_pixel_read,
2954	.write = dp_dsc_bits_per_pixel_write,
2955	.llseek = default_llseek
2956	};
2957
2958	static const struct file_operations dp_dsc_pic_width_debugfs_fops = {
2959	.owner = THIS_MODULE,
2960	.read = dp_dsc_pic_width_read,
2961	.llseek = default_llseek
2962	};
2963
2964	static const struct file_operations dp_dsc_pic_height_debugfs_fops = {
2965	.owner = THIS_MODULE,
2966	.read = dp_dsc_pic_height_read,
2967	.llseek = default_llseek
2968	};
2969
2970	static const struct file_operations dp_dsc_chunk_size_debugfs_fops = {
2971	.owner = THIS_MODULE,
2972	.read = dp_dsc_chunk_size_read,
2973	.llseek = default_llseek
2974	};
2975
2976	static const struct file_operations dp_dsc_slice_bpg_offset_debugfs_fops = {
2977	.owner = THIS_MODULE,
2978	.read = dp_dsc_slice_bpg_offset_read,
2979	.llseek = default_llseek
2980	};
2981
2982	static const struct file_operations trigger_hotplug_debugfs_fops = {
2983	.owner = THIS_MODULE,
2984	.write = trigger_hotplug,
2985	.llseek = default_llseek
2986	};
2987
2988	static const struct file_operations dp_link_settings_debugfs_fops = {
2989	.owner = THIS_MODULE,
2990	.read = dp_link_settings_read,
2991	.write = dp_link_settings_write,
2992	.llseek = default_llseek
2993	};
2994
2995	static const struct file_operations dp_phy_settings_debugfs_fop = {
2996	.owner = THIS_MODULE,
2997	.read = dp_phy_settings_read,
2998	.write = dp_phy_settings_write,
2999	.llseek = default_llseek
3000	};
3001
3002	static const struct file_operations dp_phy_test_pattern_fops = {
3003	.owner = THIS_MODULE,
3004	.write = dp_phy_test_pattern_debugfs_write,
3005	.llseek = default_llseek
3006	};
3007
3008	static const struct file_operations sdp_message_fops = {
3009	.owner = THIS_MODULE,
3010	.write = dp_sdp_message_debugfs_write,
3011	.llseek = default_llseek
3012	};
3013
3014	static const struct file_operations dp_max_bpc_debugfs_fops = {
3015	.owner = THIS_MODULE,
3016	.read = dp_max_bpc_read,
3017	.write = dp_max_bpc_write,
3018	.llseek = default_llseek
3019	};
3020
3021	static const struct file_operations dp_dsc_disable_passthrough_debugfs_fops = {
3022	.owner = THIS_MODULE,
3023	.write = dp_dsc_passthrough_set,
3024	.llseek = default_llseek
3025	};
3026
3027	static const struct file_operations dp_mst_link_settings_debugfs_fops = {
3028	.owner = THIS_MODULE,
3029	.write = dp_mst_link_setting,
3030	.llseek = default_llseek
3031	};
3032
3033	static const struct {
3034	char *name;
3035	const struct file_operations *fops;
3036	} dp_debugfs_entries[] = {
3037	{"link_settings", &dp_link_settings_debugfs_fops},
3038	{"phy_settings", &dp_phy_settings_debugfs_fop},
3039	{"lttpr_status", &dp_lttpr_status_fops},
3040	{"test_pattern", &dp_phy_test_pattern_fops},
3041	{"hdcp_sink_capability", &hdcp_sink_capability_fops},
3042	{"sdp_message", &sdp_message_fops},
3043	{"dsc_clock_en", &dp_dsc_clock_en_debugfs_fops},
3044	{"dsc_slice_width", &dp_dsc_slice_width_debugfs_fops},
3045	{"dsc_slice_height", &dp_dsc_slice_height_debugfs_fops},
3046	{"dsc_bits_per_pixel", &dp_dsc_bits_per_pixel_debugfs_fops},
3047	{"dsc_pic_width", &dp_dsc_pic_width_debugfs_fops},
3048	{"dsc_pic_height", &dp_dsc_pic_height_debugfs_fops},
3049	{"dsc_chunk_size", &dp_dsc_chunk_size_debugfs_fops},
3050	{"dsc_slice_bpg", &dp_dsc_slice_bpg_offset_debugfs_fops},
3051	{"dp_dsc_fec_support", &dp_dsc_fec_support_fops},
3052	{"max_bpc", &dp_max_bpc_debugfs_fops},
3053	{"dsc_disable_passthrough", &dp_dsc_disable_passthrough_debugfs_fops},
3054	{"is_mst_connector", &dp_is_mst_connector_fops},
3055	{"mst_progress_status", &dp_mst_progress_status_fops},
3056	{"is_dpia_link", &is_dpia_link_fops},
3057	{"mst_link_settings", &dp_mst_link_settings_debugfs_fops}
3058	};
3059
3060	static const struct {
3061	char *name;
3062	const struct file_operations *fops;
3063	} hdmi_debugfs_entries[] = {
3064	{"hdcp_sink_capability", &hdcp_sink_capability_fops},
3065	{"hdmi_cec_state", &hdmi_cec_state_fops}
3066	};
3067
3068	/*
3069	* Force YUV420 output if available from the given mode
3070	*/
3071	static int force_yuv420_output_set(void *data, u64 val)
3072	{
3073	struct amdgpu_dm_connector *connector = data;
3074
3075	connector->force_yuv420_output = (bool)val;
3076
3077	return 0;
3078	}
3079
3080	/*
3081	* Check if YUV420 is forced when available from the given mode
3082	*/
3083	static int force_yuv420_output_get(void *data, u64 *val)
3084	{
3085	struct amdgpu_dm_connector *connector = data;
3086
3087	*val = connector->force_yuv420_output;
3088
3089	return 0;
3090	}
3091
3092	DEFINE_DEBUGFS_ATTRIBUTE(force_yuv420_output_fops, force_yuv420_output_get,
3093	force_yuv420_output_set, "%llu\n");
3094
3095	/*
3096	* Read Replay state
3097	*/
3098	static int replay_get_state(void *data, u64 *val)
3099	{
3100	struct amdgpu_dm_connector *connector = data;
3101	struct dc_link *link = connector->dc_link;
3102	uint64_t state = REPLAY_STATE_INVALID;
3103
3104	dc_link_get_replay_state(dc_link: link, state: &state);
3105
3106	*val = state;
3107
3108	return 0;
3109	}
3110
3111	/*
3112	* Start / Stop capture Replay residency
3113	*/
3114	static int replay_set_residency(void *data, u64 val)
3115	{
3116	struct amdgpu_dm_connector *connector = data;
3117	struct dc_link *link = connector->dc_link;
3118	bool is_start = (val != 0);
3119	u32 residency = 0;
3120
3121	link->dc->link_srv->edp_replay_residency(link, &residency, is_start, PR_RESIDENCY_MODE_PHY);
3122	return 0;
3123	}
3124
3125	/*
3126	* Read Replay residency
3127	*/
3128	static int replay_get_residency(void *data, u64 *val)
3129	{
3130	struct amdgpu_dm_connector *connector = data;
3131	struct dc_link *link = connector->dc_link;
3132	u32 residency = 0;
3133
3134	link->dc->link_srv->edp_replay_residency(link, &residency, false, PR_RESIDENCY_MODE_PHY);
3135	*val = (u64)residency;
3136
3137	return 0;
3138	}
3139
3140	/*
3141	* Read PSR state
3142	*/
3143	static int psr_get(void *data, u64 *val)
3144	{
3145	struct amdgpu_dm_connector *connector = data;
3146	struct dc_link *link = connector->dc_link;
3147	enum dc_psr_state state = PSR_STATE0;
3148
3149	dc_link_get_psr_state(dc_link: link, state: &state);
3150
3151	*val = state;
3152
3153	return 0;
3154	}
3155
3156	/*
3157	* Read PSR state residency
3158	*/
3159	static int psr_read_residency(void *data, u64 *val)
3160	{
3161	struct amdgpu_dm_connector *connector = data;
3162	struct dc_link *link = connector->dc_link;
3163	u32 residency = 0;
3164
3165	link->dc->link_srv->edp_get_psr_residency(link, &residency, PSR_RESIDENCY_MODE_PHY);
3166
3167	*val = (u64)residency;
3168
3169	return 0;
3170	}
3171
3172	/* read allow_edp_hotplug_detection */
3173	static int allow_edp_hotplug_detection_get(void *data, u64 *val)
3174	{
3175	struct amdgpu_dm_connector *aconnector = data;
3176	struct drm_connector *connector = &aconnector->base;
3177	struct drm_device *dev = connector->dev;
3178	struct amdgpu_device *adev = drm_to_adev(ddev: dev);
3179
3180	*val = adev->dm.dc->config.allow_edp_hotplug_detection;
3181
3182	return 0;
3183	}
3184
3185	/* set allow_edp_hotplug_detection */
3186	static int allow_edp_hotplug_detection_set(void *data, u64 val)
3187	{
3188	struct amdgpu_dm_connector *aconnector = data;
3189	struct drm_connector *connector = &aconnector->base;
3190	struct drm_device *dev = connector->dev;
3191	struct amdgpu_device *adev = drm_to_adev(ddev: dev);
3192
3193	adev->dm.dc->config.allow_edp_hotplug_detection = (uint32_t) val;
3194
3195	return 0;
3196	}
3197
3198	/* check if kernel disallow eDP enter psr state
3199	* cat /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_psr
3200	* 0: allow edp enter psr; 1: disallow
3201	*/
3202	static int disallow_edp_enter_psr_get(void *data, u64 *val)
3203	{
3204	struct amdgpu_dm_connector *aconnector = data;
3205
3206	*val = (u64) aconnector->disallow_edp_enter_psr;
3207	return 0;
3208	}
3209
3210	/* set kernel disallow eDP enter psr state
3211	* echo 0x0 /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_psr
3212	* 0: allow edp enter psr; 1: disallow
3213	*
3214	* usage: test app read crc from PSR eDP rx.
3215	*
3216	* during kernel boot up, kernel write dpcd 0x170 = 5.
3217	* this notify eDP rx psr enable and let rx check crc.
3218	* rx fw will start checking crc for rx internal logic.
3219	* crc read count within dpcd 0x246 is not updated and
3220	* value is 0. when eDP tx driver wants to read rx crc
3221	* from dpcd 0x246, 0x270, read count 0 lead tx driver
3222	* timeout.
3223	*
3224	* to avoid this, we add this debugfs to let test app to disbable
3225	* rx crc checking for rx internal logic. then test app can read
3226	* non-zero crc read count.
3227	*
3228	* expected app sequence is as below:
3229	* 1. disable eDP PHY and notify eDP rx with dpcd 0x600 = 2.
3230	* 2. echo 0x1 /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_psr
3231	* 3. enable eDP PHY and notify eDP rx with dpcd 0x600 = 1 but
3232	* without dpcd 0x170 = 5.
3233	* 4. read crc from rx dpcd 0x270, 0x246, etc.
3234	* 5. echo 0x0 /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_psr.
3235	* this will let eDP back to normal with psr setup dpcd 0x170 = 5.
3236	*/
3237	static int disallow_edp_enter_psr_set(void *data, u64 val)
3238	{
3239	struct amdgpu_dm_connector *aconnector = data;
3240
3241	aconnector->disallow_edp_enter_psr = val ? true : false;
3242	return 0;
3243	}
3244
3245	static int dmub_trace_mask_set(void *data, u64 val)
3246	{
3247	struct amdgpu_device *adev = data;
3248	struct dmub_srv *srv = adev->dm.dc->ctx->dmub_srv->dmub;
3249	enum dmub_gpint_command cmd;
3250	u64 mask = 0xffff;
3251	u8 shift = 0;
3252	u32 res;
3253	int i;
3254
3255	if (!srv->fw_version)
3256	return -EINVAL;
3257
3258	for (i = 0; i < 4; i++) {
3259	res = (val & mask) >> shift;
3260
3261	switch (i) {
3262	case 0:
3263	cmd = DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD0;
3264	break;
3265	case 1:
3266	cmd = DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD1;
3267	break;
3268	case 2:
3269	cmd = DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD2;
3270	break;
3271	case 3:
3272	cmd = DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD3;
3273	break;
3274	}
3275
3276	if (!dc_wake_and_execute_gpint(ctx: adev->dm.dc->ctx, command_code: cmd, param: res, NULL, wait_type: DM_DMUB_WAIT_TYPE_WAIT))
3277	return -EIO;
3278
3279	usleep_range(min: 100, max: 1000);
3280
3281	mask <<= 16;
3282	shift += 16;
3283	}
3284
3285	return 0;
3286	}
3287
3288	static int dmub_trace_mask_show(void *data, u64 *val)
3289	{
3290	enum dmub_gpint_command cmd = DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD0;
3291	struct amdgpu_device *adev = data;
3292	struct dmub_srv *srv = adev->dm.dc->ctx->dmub_srv->dmub;
3293	u8 shift = 0;
3294	u64 raw = 0;
3295	u64 res = 0;
3296	int i = 0;
3297
3298	if (!srv->fw_version)
3299	return -EINVAL;
3300
3301	while (i < 4) {
3302	uint32_t response;
3303
3304	if (!dc_wake_and_execute_gpint(ctx: adev->dm.dc->ctx, command_code: cmd, param: 0, response: &response, wait_type: DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY))
3305	return -EIO;
3306
3307	raw = response;
3308	usleep_range(min: 100, max: 1000);
3309
3310	cmd++;
3311	res |= (raw << shift);
3312	shift += 16;
3313	i++;
3314	}
3315
3316	*val = res;
3317
3318	return 0;
3319	}
3320
3321	DEFINE_DEBUGFS_ATTRIBUTE(dmub_trace_mask_fops, dmub_trace_mask_show,
3322	dmub_trace_mask_set, "0x%llx\n");
3323
3324	/*
3325	* Set dmcub trace event IRQ enable or disable.
3326	* Usage to enable dmcub trace event IRQ: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en
3327	* Usage to disable dmcub trace event IRQ: echo 0 > /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en
3328	*/
3329	static int dmcub_trace_event_state_set(void *data, u64 val)
3330	{
3331	struct amdgpu_device *adev = data;
3332
3333	if (val == 1 || val == 0) {
3334	dc_dmub_trace_event_control(dc: adev->dm.dc, enable: val);
3335	adev->dm.dmcub_trace_event_en = (bool)val;
3336	} else
3337	return 0;
3338
3339	return 0;
3340	}
3341
3342	/*
3343	* The interface doesn't need get function, so it will return the
3344	* value of zero
3345	* Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en
3346	*/
3347	static int dmcub_trace_event_state_get(void *data, u64 *val)
3348	{
3349	struct amdgpu_device *adev = data;
3350
3351	*val = adev->dm.dmcub_trace_event_en;
3352	return 0;
3353	}
3354
3355	DEFINE_DEBUGFS_ATTRIBUTE(dmcub_trace_event_state_fops, dmcub_trace_event_state_get,
3356	dmcub_trace_event_state_set, "%llu\n");
3357
3358	DEFINE_DEBUGFS_ATTRIBUTE(replay_state_fops, replay_get_state, NULL, "%llu\n");
3359	DEFINE_DEBUGFS_ATTRIBUTE(replay_residency_fops, replay_get_residency, replay_set_residency,
3360	"%llu\n");
3361	DEFINE_DEBUGFS_ATTRIBUTE(psr_fops, psr_get, NULL, "%llu\n");
3362	DEFINE_DEBUGFS_ATTRIBUTE(psr_residency_fops, psr_read_residency, NULL,
3363	"%llu\n");
3364
3365	DEFINE_DEBUGFS_ATTRIBUTE(allow_edp_hotplug_detection_fops,
3366	allow_edp_hotplug_detection_get,
3367	allow_edp_hotplug_detection_set, "%llu\n");
3368
3369	DEFINE_DEBUGFS_ATTRIBUTE(disallow_edp_enter_psr_fops,
3370	disallow_edp_enter_psr_get,
3371	disallow_edp_enter_psr_set, "%llu\n");
3372
3373	DEFINE_SHOW_ATTRIBUTE(current_backlight);
3374	DEFINE_SHOW_ATTRIBUTE(target_backlight);
3375	DEFINE_SHOW_ATTRIBUTE(ips_status);
3376
3377	static const struct {
3378	char *name;
3379	const struct file_operations *fops;
3380	} connector_debugfs_entries[] = {
3381	{"force_yuv420_output", &force_yuv420_output_fops},
3382	{"trigger_hotplug", &trigger_hotplug_debugfs_fops},
3383	{"internal_display", &internal_display_fops},
3384	{"odm_combine_segments", &odm_combine_segments_fops}
3385	};
3386
3387	/*
3388	* Returns supported customized link rates by this eDP panel.
3389	* Example usage: cat /sys/kernel/debug/dri/0/eDP-x/ilr_setting
3390	*/
3391	static int edp_ilr_show(struct seq_file *m, void *unused)
3392	{
3393	struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private);
3394	struct dc_link *link = aconnector->dc_link;
3395	uint8_t supported_link_rates[16];
3396	uint32_t link_rate_in_khz;
3397	uint32_t entry = 0;
3398	uint8_t dpcd_rev;
3399
3400	memset(supported_link_rates, 0, sizeof(supported_link_rates));
3401	dm_helpers_dp_read_dpcd(ctx: link->ctx, link, DP_SUPPORTED_LINK_RATES,
3402	data: supported_link_rates, size: sizeof(supported_link_rates));
3403
3404	dpcd_rev = link->dpcd_caps.dpcd_rev.raw;
3405
3406	if (dpcd_rev >= DP_DPCD_REV_13 &&
3407	(supported_link_rates[entry+1] != 0 || supported_link_rates[entry] != 0)) {
3408
3409	for (entry = 0; entry < 16; entry += 2) {
3410	link_rate_in_khz = (supported_link_rates[entry+1] * 0x100 +
3411	supported_link_rates[entry]) * 200;
3412	seq_printf(m, fmt: "[%d] %d kHz\n", entry/2, link_rate_in_khz);
3413	}
3414	} else {
3415	seq_puts(m, s: "ILR is not supported by this eDP panel.\n");
3416	}
3417
3418	return 0;
3419	}
3420
3421	/*
3422	* Set supported customized link rate to eDP panel.
3423	*
3424	* echo <lane_count> <link_rate option> > ilr_setting
3425	*
3426	* for example, supported ILR : [0] 1620000 kHz [1] 2160000 kHz [2] 2430000 kHz ...
3427	* echo 4 1 > /sys/kernel/debug/dri/0/eDP-x/ilr_setting
3428	* to set 4 lanes and 2.16 GHz
3429	*/
3430	static ssize_t edp_ilr_write(struct file *f, const char __user *buf,
3431	size_t size, loff_t *pos)
3432	{
3433	struct amdgpu_dm_connector *connector = file_inode(f)->i_private;
3434	struct dc_link *link = connector->dc_link;
3435	struct amdgpu_device *adev = drm_to_adev(ddev: connector->base.dev);
3436	struct dc *dc = (struct dc *)link->dc;
3437	struct dc_link_settings prefer_link_settings;
3438	char *wr_buf = NULL;
3439	const uint32_t wr_buf_size = 40;
3440	/* 0: lane_count; 1: link_rate */
3441	int max_param_num = 2;
3442	uint8_t param_nums = 0;
3443	long param[2];
3444	bool valid_input = true;
3445
3446	if (size == 0)
3447	return -EINVAL;
3448
3449	wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL);
3450	if (!wr_buf)
3451	return -ENOMEM;
3452
3453	if (parse_write_buffer_into_params(wr_buf, wr_buf_size,
3454	param: (long *)param, buf,
3455	max_param_num,
3456	param_nums: &param_nums)) {
3457	kfree(objp: wr_buf);
3458	return -EINVAL;
3459	}
3460
3461	if (param_nums <= 0) {
3462	kfree(objp: wr_buf);
3463	return -EINVAL;
3464	}
3465
3466	switch (param[0]) {
3467	case LANE_COUNT_ONE:
3468	case LANE_COUNT_TWO:
3469	case LANE_COUNT_FOUR:
3470	break;
3471	default:
3472	valid_input = false;
3473	break;
3474	}
3475
3476	if (param[1] >= link->dpcd_caps.edp_supported_link_rates_count)
3477	valid_input = false;
3478
3479	if (!valid_input) {
3480	kfree(objp: wr_buf);
3481	DRM_DEBUG_DRIVER("Invalid Input value. No HW will be programmed\n");
3482	prefer_link_settings.use_link_rate_set = false;
3483	mutex_lock(&adev->dm.dc_lock);
3484	dc_link_set_preferred_training_settings(dc, NULL, NULL, link, skip_immediate_retrain: false);
3485	mutex_unlock(lock: &adev->dm.dc_lock);
3486	return size;
3487	}
3488
3489	/* save user force lane_count, link_rate to preferred settings
3490	* spread spectrum will not be changed
3491	*/
3492	prefer_link_settings.link_spread = link->cur_link_settings.link_spread;
3493	prefer_link_settings.lane_count = param[0];
3494	prefer_link_settings.use_link_rate_set = true;
3495	prefer_link_settings.link_rate_set = param[1];
3496	prefer_link_settings.link_rate = link->dpcd_caps.edp_supported_link_rates[param[1]];
3497
3498	mutex_lock(&adev->dm.dc_lock);
3499	dc_link_set_preferred_training_settings(dc, link_setting: &prefer_link_settings,
3500	NULL, link, skip_immediate_retrain: false);
3501	mutex_unlock(lock: &adev->dm.dc_lock);
3502
3503	kfree(objp: wr_buf);
3504	return size;
3505	}
3506
3507	static int edp_ilr_open(struct inode *inode, struct file *file)
3508	{
3509	return single_open(file, edp_ilr_show, inode->i_private);
3510	}
3511
3512	static const struct file_operations edp_ilr_debugfs_fops = {
3513	.owner = THIS_MODULE,
3514	.open = edp_ilr_open,
3515	.read = seq_read,
3516	.llseek = seq_lseek,
3517	.release = single_release,
3518	.write = edp_ilr_write
3519	};
3520
3521	void connector_debugfs_init(struct amdgpu_dm_connector *connector)
3522	{
3523	int i;
3524	struct dentry *dir = connector->base.debugfs_entry;
3525
3526	if (connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
3527	connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) {
3528	for (i = 0; i < ARRAY_SIZE(dp_debugfs_entries); i++) {
3529	debugfs_create_file(dp_debugfs_entries[i].name,
3530	0644, dir, connector,
3531	dp_debugfs_entries[i].fops);
3532	}
3533	}
3534	if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) {
3535	debugfs_create_file("replay_capability", 0444, dir, connector,
3536	&replay_capability_fops);
3537	debugfs_create_file("replay_state", 0444, dir, connector, &replay_state_fops);
3538	debugfs_create_file_unsafe(name: "replay_residency", mode: 0444, parent: dir,
3539	data: connector, fops: &replay_residency_fops);
3540	debugfs_create_file_unsafe(name: "psr_capability", mode: 0444, parent: dir, data: connector, fops: &psr_capability_fops);
3541	debugfs_create_file_unsafe(name: "psr_state", mode: 0444, parent: dir, data: connector, fops: &psr_fops);
3542	debugfs_create_file_unsafe(name: "psr_residency", mode: 0444, parent: dir,
3543	data: connector, fops: &psr_residency_fops);
3544	debugfs_create_file("amdgpu_current_backlight_pwm", 0444, dir, connector,
3545	&current_backlight_fops);
3546	debugfs_create_file("amdgpu_target_backlight_pwm", 0444, dir, connector,
3547	&target_backlight_fops);
3548	debugfs_create_file("ilr_setting", 0644, dir, connector,
3549	&edp_ilr_debugfs_fops);
3550	debugfs_create_file("allow_edp_hotplug_detection", 0644, dir, connector,
3551	&allow_edp_hotplug_detection_fops);
3552	debugfs_create_file("disallow_edp_enter_psr", 0644, dir, connector,
3553	&disallow_edp_enter_psr_fops);
3554	}
3555
3556	for (i = 0; i < ARRAY_SIZE(connector_debugfs_entries); i++) {
3557	debugfs_create_file(connector_debugfs_entries[i].name,
3558	0644, dir, connector,
3559	connector_debugfs_entries[i].fops);
3560	}
3561
3562	if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) {
3563	for (i = 0; i < ARRAY_SIZE(hdmi_debugfs_entries); i++) {
3564	debugfs_create_file(hdmi_debugfs_entries[i].name,
3565	0644, dir, connector,
3566	hdmi_debugfs_entries[i].fops);
3567	}
3568	}
3569	}
3570
3571	#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
3572	/*
3573	* Set crc window coordinate x start
3574	*/
3575	static int crc_win_x_start_set(void *data, u64 val)
3576	{
3577	struct drm_crtc *crtc = data;
3578	struct drm_device *drm_dev = crtc->dev;
3579	struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3580
3581	spin_lock_irq(lock: &drm_dev->event_lock);
3582	acrtc->dm_irq_params.window_param[0].x_start = (uint16_t) val;
3583	acrtc->dm_irq_params.window_param[0].update_win = false;
3584	spin_unlock_irq(lock: &drm_dev->event_lock);
3585
3586	return 0;
3587	}
3588
3589	/*
3590	* Get crc window coordinate x start
3591	*/
3592	static int crc_win_x_start_get(void *data, u64 *val)
3593	{
3594	struct drm_crtc *crtc = data;
3595	struct drm_device *drm_dev = crtc->dev;
3596	struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3597
3598	spin_lock_irq(lock: &drm_dev->event_lock);
3599	*val = acrtc->dm_irq_params.window_param[0].x_start;
3600	spin_unlock_irq(lock: &drm_dev->event_lock);
3601
3602	return 0;
3603	}
3604
3605	DEFINE_DEBUGFS_ATTRIBUTE(crc_win_x_start_fops, crc_win_x_start_get,
3606	crc_win_x_start_set, "%llu\n");
3607
3608
3609	/*
3610	* Set crc window coordinate y start
3611	*/
3612	static int crc_win_y_start_set(void *data, u64 val)
3613	{
3614	struct drm_crtc *crtc = data;
3615	struct drm_device *drm_dev = crtc->dev;
3616	struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3617
3618	spin_lock_irq(lock: &drm_dev->event_lock);
3619	acrtc->dm_irq_params.window_param[0].y_start = (uint16_t) val;
3620	acrtc->dm_irq_params.window_param[0].update_win = false;
3621	spin_unlock_irq(lock: &drm_dev->event_lock);
3622
3623	return 0;
3624	}
3625
3626	/*
3627	* Get crc window coordinate y start
3628	*/
3629	static int crc_win_y_start_get(void *data, u64 *val)
3630	{
3631	struct drm_crtc *crtc = data;
3632	struct drm_device *drm_dev = crtc->dev;
3633	struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3634
3635	spin_lock_irq(lock: &drm_dev->event_lock);
3636	*val = acrtc->dm_irq_params.window_param[0].y_start;
3637	spin_unlock_irq(lock: &drm_dev->event_lock);
3638
3639	return 0;
3640	}
3641
3642	DEFINE_DEBUGFS_ATTRIBUTE(crc_win_y_start_fops, crc_win_y_start_get,
3643	crc_win_y_start_set, "%llu\n");
3644
3645	/*
3646	* Set crc window coordinate x end
3647	*/
3648	static int crc_win_x_end_set(void *data, u64 val)
3649	{
3650	struct drm_crtc *crtc = data;
3651	struct drm_device *drm_dev = crtc->dev;
3652	struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3653
3654	spin_lock_irq(lock: &drm_dev->event_lock);
3655	acrtc->dm_irq_params.window_param[0].x_end = (uint16_t) val;
3656	acrtc->dm_irq_params.window_param[0].update_win = false;
3657	spin_unlock_irq(lock: &drm_dev->event_lock);
3658
3659	return 0;
3660	}
3661
3662	/*
3663	* Get crc window coordinate x end
3664	*/
3665	static int crc_win_x_end_get(void *data, u64 *val)
3666	{
3667	struct drm_crtc *crtc = data;
3668	struct drm_device *drm_dev = crtc->dev;
3669	struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3670
3671	spin_lock_irq(lock: &drm_dev->event_lock);
3672	*val = acrtc->dm_irq_params.window_param[0].x_end;
3673	spin_unlock_irq(lock: &drm_dev->event_lock);
3674
3675	return 0;
3676	}
3677
3678	DEFINE_DEBUGFS_ATTRIBUTE(crc_win_x_end_fops, crc_win_x_end_get,
3679	crc_win_x_end_set, "%llu\n");
3680
3681	/*
3682	* Set crc window coordinate y end
3683	*/
3684	static int crc_win_y_end_set(void *data, u64 val)
3685	{
3686	struct drm_crtc *crtc = data;
3687	struct drm_device *drm_dev = crtc->dev;
3688	struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3689
3690	spin_lock_irq(lock: &drm_dev->event_lock);
3691	acrtc->dm_irq_params.window_param[0].y_end = (uint16_t) val;
3692	acrtc->dm_irq_params.window_param[0].update_win = false;
3693	spin_unlock_irq(lock: &drm_dev->event_lock);
3694
3695	return 0;
3696	}
3697
3698	/*
3699	* Get crc window coordinate y end
3700	*/
3701	static int crc_win_y_end_get(void *data, u64 *val)
3702	{
3703	struct drm_crtc *crtc = data;
3704	struct drm_device *drm_dev = crtc->dev;
3705	struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3706
3707	spin_lock_irq(lock: &drm_dev->event_lock);
3708	*val = acrtc->dm_irq_params.window_param[0].y_end;
3709	spin_unlock_irq(lock: &drm_dev->event_lock);
3710
3711	return 0;
3712	}
3713
3714	DEFINE_DEBUGFS_ATTRIBUTE(crc_win_y_end_fops, crc_win_y_end_get,
3715	crc_win_y_end_set, "%llu\n");
3716	/*
3717	* Trigger to commit crc window
3718	*/
3719	static int crc_win_update_set(void *data, u64 val)
3720	{
3721	struct drm_crtc *crtc = data;
3722	struct amdgpu_crtc *acrtc;
3723	struct amdgpu_device *adev = drm_to_adev(ddev: crtc->dev);
3724
3725	if (val) {
3726	acrtc = to_amdgpu_crtc(crtc);
3727	mutex_lock(&adev->dm.dc_lock);
3728	/* PSR may write to OTG CRC window control register,
3729	* so close it before starting secure_display.
3730	*/
3731	amdgpu_dm_psr_disable(stream: acrtc->dm_irq_params.stream, wait: true);
3732
3733	spin_lock_irq(lock: &adev_to_drm(adev)->event_lock);
3734
3735	acrtc->dm_irq_params.window_param[0].enable = true;
3736	acrtc->dm_irq_params.window_param[0].update_win = true;
3737	acrtc->dm_irq_params.window_param[0].skip_frame_cnt = 0;
3738	acrtc->dm_irq_params.crc_window_activated = true;
3739
3740	spin_unlock_irq(lock: &adev_to_drm(adev)->event_lock);
3741	mutex_unlock(lock: &adev->dm.dc_lock);
3742	}
3743
3744	return 0;
3745	}
3746
3747	/*
3748	* Get crc window update flag
3749	*/
3750	static int crc_win_update_get(void *data, u64 *val)
3751	{
3752	*val = 0;
3753	return 0;
3754	}
3755
3756	DEFINE_DEBUGFS_ATTRIBUTE(crc_win_update_fops, crc_win_update_get,
3757	crc_win_update_set, "%llu\n");
3758	#endif
3759	void crtc_debugfs_init(struct drm_crtc *crtc)
3760	{
3761	#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
3762	struct dentry *dir = debugfs_lookup(name: "crc", parent: crtc->debugfs_entry);
3763
3764	if (!dir)
3765	return;
3766
3767	debugfs_create_file_unsafe(name: "crc_win_x_start", mode: 0644, parent: dir, data: crtc,
3768	fops: &crc_win_x_start_fops);
3769	debugfs_create_file_unsafe(name: "crc_win_y_start", mode: 0644, parent: dir, data: crtc,
3770	fops: &crc_win_y_start_fops);
3771	debugfs_create_file_unsafe(name: "crc_win_x_end", mode: 0644, parent: dir, data: crtc,
3772	fops: &crc_win_x_end_fops);
3773	debugfs_create_file_unsafe(name: "crc_win_y_end", mode: 0644, parent: dir, data: crtc,
3774	fops: &crc_win_y_end_fops);
3775	debugfs_create_file_unsafe(name: "crc_win_update", mode: 0644, parent: dir, data: crtc,
3776	fops: &crc_win_update_fops);
3777	dput(dir);
3778	#endif
3779	debugfs_create_file("amdgpu_current_bpc", 0644, crtc->debugfs_entry,
3780	crtc, &amdgpu_current_bpc_fops);
3781	debugfs_create_file("amdgpu_current_colorspace", 0644, crtc->debugfs_entry,
3782	crtc, &amdgpu_current_colorspace_fops);
3783	}
3784
3785	/*
3786	* Writes DTN log state to the user supplied buffer.
3787	* Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log
3788	*/
3789	static ssize_t dtn_log_read(
3790	struct file *f,
3791	char __user *buf,
3792	size_t size,
3793	loff_t *pos)
3794	{
3795	struct amdgpu_device *adev = file_inode(f)->i_private;
3796	struct dc *dc = adev->dm.dc;
3797	struct dc_log_buffer_ctx log_ctx = { 0 };
3798	ssize_t result = 0;
3799
3800	if (!buf || !size)
3801	return -EINVAL;
3802
3803	if (!dc->hwss.log_hw_state)
3804	return 0;
3805
3806	dc->hwss.log_hw_state(dc, &log_ctx);
3807
3808	if (*pos < log_ctx.pos) {
3809	size_t to_copy = log_ctx.pos - *pos;
3810
3811	to_copy = min(to_copy, size);
3812
3813	if (!copy_to_user(to: buf, from: log_ctx.buf + *pos, n: to_copy)) {
3814	*pos += to_copy;
3815	result = to_copy;
3816	}
3817	}
3818
3819	kfree(objp: log_ctx.buf);
3820
3821	return result;
3822	}
3823
3824	/*
3825	* Writes DTN log state to dmesg when triggered via a write.
3826	* Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log
3827	*/
3828	static ssize_t dtn_log_write(
3829	struct file *f,
3830	const char __user *buf,
3831	size_t size,
3832	loff_t *pos)
3833	{
3834	struct amdgpu_device *adev = file_inode(f)->i_private;
3835	struct dc *dc = adev->dm.dc;
3836
3837	/* Write triggers log output via dmesg. */
3838	if (size == 0)
3839	return 0;
3840
3841	if (dc->hwss.log_hw_state)
3842	dc->hwss.log_hw_state(dc, NULL);
3843
3844	return size;
3845	}
3846
3847	static int mst_topo_show(struct seq_file *m, void *unused)
3848	{
3849	struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
3850	struct drm_device *dev = adev_to_drm(adev);
3851	struct drm_connector *connector;
3852	struct drm_connector_list_iter conn_iter;
3853	struct amdgpu_dm_connector *aconnector;
3854
3855	drm_connector_list_iter_begin(dev, iter: &conn_iter);
3856	drm_for_each_connector_iter(connector, &conn_iter) {
3857	if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
3858	continue;
3859
3860	aconnector = to_amdgpu_dm_connector(connector);
3861
3862	/* Ensure we're only dumping the topology of a root mst node */
3863	if (!aconnector->mst_mgr.mst_state)
3864	continue;
3865
3866	seq_printf(m, fmt: "\nMST topology for connector %d\n", aconnector->connector_id);
3867	drm_dp_mst_dump_topology(m, mgr: &aconnector->mst_mgr);
3868	}
3869	drm_connector_list_iter_end(iter: &conn_iter);
3870
3871	return 0;
3872	}
3873
3874	/*
3875	* Sets trigger hpd for MST topologies.
3876	* All connected connectors will be rediscovered and re started as needed if val of 1 is sent.
3877	* All topologies will be disconnected if val of 0 is set .
3878	* Usage to enable topologies: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst
3879	* Usage to disable topologies: echo 0 > /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst
3880	*/
3881	static int trigger_hpd_mst_set(void *data, u64 val)
3882	{
3883	struct amdgpu_device *adev = data;
3884	struct drm_device *dev = adev_to_drm(adev);
3885	struct drm_connector_list_iter iter;
3886	struct amdgpu_dm_connector *aconnector;
3887	struct drm_connector *connector;
3888	struct dc_link *link = NULL;
3889	int ret;
3890
3891	if (val == 1) {
3892	drm_connector_list_iter_begin(dev, iter: &iter);
3893	drm_for_each_connector_iter(connector, &iter) {
3894	aconnector = to_amdgpu_dm_connector(connector);
3895	if (aconnector->dc_link->type == dc_connection_mst_branch &&
3896	aconnector->mst_mgr.aux) {
3897	mutex_lock(&adev->dm.dc_lock);
3898	ret = dc_link_detect(link: aconnector->dc_link, reason: DETECT_REASON_HPD);
3899	mutex_unlock(lock: &adev->dm.dc_lock);
3900
3901	if (!ret)
3902	DRM_ERROR("DM_MST: Failed to detect dc link!");
3903
3904	ret = drm_dp_mst_topology_mgr_set_mst(mgr: &aconnector->mst_mgr, mst_state: true);
3905	if (ret < 0)
3906	DRM_ERROR("DM_MST: Failed to set the device into MST mode!");
3907	}
3908	}
3909	} else if (val == 0) {
3910	drm_connector_list_iter_begin(dev, iter: &iter);
3911	drm_for_each_connector_iter(connector, &iter) {
3912	aconnector = to_amdgpu_dm_connector(connector);
3913	if (!aconnector->dc_link)
3914	continue;
3915
3916	if (!aconnector->mst_root)
3917	continue;
3918
3919	link = aconnector->dc_link;
3920	dc_link_dp_receiver_power_ctrl(link, on: false);
3921	drm_dp_mst_topology_mgr_set_mst(mgr: &aconnector->mst_root->mst_mgr, mst_state: false);
3922	link->mst_stream_alloc_table.stream_count = 0;
3923	memset(link->mst_stream_alloc_table.stream_allocations, 0,
3924	sizeof(link->mst_stream_alloc_table.stream_allocations));
3925	}
3926	} else {
3927	return 0;
3928	}
3929	drm_kms_helper_hotplug_event(dev);
3930
3931	return 0;
3932	}
3933
3934	/*
3935	* The interface doesn't need get function, so it will return the
3936	* value of zero
3937	* Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst
3938	*/
3939	static int trigger_hpd_mst_get(void *data, u64 *val)
3940	{
3941	*val = 0;
3942	return 0;
3943	}
3944
3945	DEFINE_DEBUGFS_ATTRIBUTE(trigger_hpd_mst_ops, trigger_hpd_mst_get,
3946	trigger_hpd_mst_set, "%llu\n");
3947
3948
3949	/*
3950	* Sets the force_timing_sync debug option from the given string.
3951	* All connected displays will be force synchronized immediately.
3952	* Usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_force_timing_sync
3953	*/
3954	static int force_timing_sync_set(void *data, u64 val)
3955	{
3956	struct amdgpu_device *adev = data;
3957
3958	adev->dm.force_timing_sync = (bool)val;
3959
3960	amdgpu_dm_trigger_timing_sync(dev: adev_to_drm(adev));
3961
3962	return 0;
3963	}
3964
3965	/*
3966	* Gets the force_timing_sync debug option value into the given buffer.
3967	* Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_force_timing_sync
3968	*/
3969	static int force_timing_sync_get(void *data, u64 *val)
3970	{
3971	struct amdgpu_device *adev = data;
3972
3973	*val = adev->dm.force_timing_sync;
3974
3975	return 0;
3976	}
3977
3978	DEFINE_DEBUGFS_ATTRIBUTE(force_timing_sync_ops, force_timing_sync_get,
3979	force_timing_sync_set, "%llu\n");
3980
3981
3982	/*
3983	* Disables all HPD and HPD RX interrupt handling in the
3984	* driver when set to 1. Default is 0.
3985	*/
3986	static int disable_hpd_set(void *data, u64 val)
3987	{
3988	struct amdgpu_device *adev = data;
3989
3990	adev->dm.disable_hpd_irq = (bool)val;
3991
3992	return 0;
3993	}
3994
3995
3996	/*
3997	* Returns 1 if HPD and HPRX interrupt handling is disabled,
3998	* 0 otherwise.
3999	*/
4000	static int disable_hpd_get(void *data, u64 *val)
4001	{
4002	struct amdgpu_device *adev = data;
4003
4004	*val = adev->dm.disable_hpd_irq;
4005
4006	return 0;
4007	}
4008
4009	DEFINE_DEBUGFS_ATTRIBUTE(disable_hpd_ops, disable_hpd_get,
4010	disable_hpd_set, "%llu\n");
4011
4012	/*
4013	* Prints hardware capabilities. These are used for IGT testing.
4014	*/
4015	static int capabilities_show(struct seq_file *m, void *unused)
4016	{
4017	struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
4018	struct dc *dc = adev->dm.dc;
4019	bool mall_supported = dc->caps.mall_size_total;
4020	bool subvp_supported = dc->caps.subvp_fw_processing_delay_us;
4021	unsigned int mall_in_use = false;
4022	unsigned int subvp_in_use = false;
4023
4024	struct hubbub *hubbub = dc->res_pool->hubbub;
4025
4026	if (hubbub && hubbub->funcs->get_mall_en)
4027	hubbub->funcs->get_mall_en(hubbub, &mall_in_use);
4028
4029	if (dc->cap_funcs.get_subvp_en)
4030	subvp_in_use = dc->cap_funcs.get_subvp_en(dc, dc->current_state);
4031
4032	seq_printf(m, fmt: "mall supported: %s, enabled: %s\n",
4033	mall_supported ? "yes" : "no", mall_in_use ? "yes" : "no");
4034	seq_printf(m, fmt: "sub-viewport supported: %s, enabled: %s\n",
4035	subvp_supported ? "yes" : "no", subvp_in_use ? "yes" : "no");
4036
4037	return 0;
4038	}
4039
4040	DEFINE_SHOW_ATTRIBUTE(capabilities);
4041
4042	/*
4043	* Temporary w/a to force sst sequence in M42D DP2 mst receiver
4044	* Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dp_set_mst_en_for_sst
4045	*/
4046	static int dp_force_sst_set(void *data, u64 val)
4047	{
4048	struct amdgpu_device *adev = data;
4049
4050	adev->dm.dc->debug.set_mst_en_for_sst = val;
4051
4052	return 0;
4053	}
4054
4055	static int dp_force_sst_get(void *data, u64 *val)
4056	{
4057	struct amdgpu_device *adev = data;
4058
4059	*val = adev->dm.dc->debug.set_mst_en_for_sst;
4060
4061	return 0;
4062	}
4063	DEFINE_DEBUGFS_ATTRIBUTE(dp_set_mst_en_for_sst_ops, dp_force_sst_get,
4064	dp_force_sst_set, "%llu\n");
4065
4066	/*
4067	* Force DP2 sequence without VESA certified cable.
4068	* Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dp_ignore_cable_id
4069	*/
4070	static int dp_ignore_cable_id_set(void *data, u64 val)
4071	{
4072	struct amdgpu_device *adev = data;
4073
4074	adev->dm.dc->debug.ignore_cable_id = val;
4075
4076	return 0;
4077	}
4078
4079	static int dp_ignore_cable_id_get(void *data, u64 *val)
4080	{
4081	struct amdgpu_device *adev = data;
4082
4083	*val = adev->dm.dc->debug.ignore_cable_id;
4084
4085	return 0;
4086	}
4087	DEFINE_DEBUGFS_ATTRIBUTE(dp_ignore_cable_id_ops, dp_ignore_cable_id_get,
4088	dp_ignore_cable_id_set, "%llu\n");
4089
4090	/*
4091	* Sets the DC visual confirm debug option from the given string.
4092	* Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_visual_confirm
4093	*/
4094	static int visual_confirm_set(void *data, u64 val)
4095	{
4096	struct amdgpu_device *adev = data;
4097
4098	adev->dm.dc->debug.visual_confirm = (enum visual_confirm)val;
4099
4100	return 0;
4101	}
4102
4103	/*
4104	* Reads the DC visual confirm debug option value into the given buffer.
4105	* Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_visual_confirm
4106	*/
4107	static int visual_confirm_get(void *data, u64 *val)
4108	{
4109	struct amdgpu_device *adev = data;
4110
4111	*val = adev->dm.dc->debug.visual_confirm;
4112
4113	return 0;
4114	}
4115
4116	DEFINE_SHOW_ATTRIBUTE(mst_topo);
4117	DEFINE_DEBUGFS_ATTRIBUTE(visual_confirm_fops, visual_confirm_get,
4118	visual_confirm_set, "%llu\n");
4119
4120
4121	/*
4122	* Sets the DC skip_detection_link_training debug option from the given string.
4123	* Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_skip_detection_link_training
4124	*/
4125	static int skip_detection_link_training_set(void *data, u64 val)
4126	{
4127	struct amdgpu_device *adev = data;
4128
4129	if (val == 0)
4130	adev->dm.dc->debug.skip_detection_link_training = false;
4131	else
4132	adev->dm.dc->debug.skip_detection_link_training = true;
4133
4134	return 0;
4135	}
4136
4137	/*
4138	* Reads the DC skip_detection_link_training debug option value into the given buffer.
4139	* Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_skip_detection_link_training
4140	*/
4141	static int skip_detection_link_training_get(void *data, u64 *val)
4142	{
4143	struct amdgpu_device *adev = data;
4144
4145	*val = adev->dm.dc->debug.skip_detection_link_training;
4146
4147	return 0;
4148	}
4149
4150	DEFINE_DEBUGFS_ATTRIBUTE(skip_detection_link_training_fops,
4151	skip_detection_link_training_get,
4152	skip_detection_link_training_set, "%llu\n");
4153
4154	/*
4155	* Dumps the DCC_EN bit for each pipe.
4156	* Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dcc_en
4157	*/
4158	static ssize_t dcc_en_bits_read(
4159	struct file *f,
4160	char __user *buf,
4161	size_t size,
4162	loff_t *pos)
4163	{
4164	struct amdgpu_device *adev = file_inode(f)->i_private;
4165	struct dc *dc = adev->dm.dc;
4166	char *rd_buf = NULL;
4167	const uint32_t rd_buf_size = 32;
4168	uint32_t result = 0;
4169	int offset = 0;
4170	int num_pipes = dc->res_pool->pipe_count;
4171	int *dcc_en_bits;
4172	int i, r;
4173
4174	dcc_en_bits = kcalloc(num_pipes, sizeof(int), GFP_KERNEL);
4175	if (!dcc_en_bits)
4176	return -ENOMEM;
4177
4178	if (!dc->hwss.get_dcc_en_bits) {
4179	kfree(objp: dcc_en_bits);
4180	return 0;
4181	}
4182
4183	dc->hwss.get_dcc_en_bits(dc, dcc_en_bits);
4184
4185	rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL);
4186	if (!rd_buf) {
4187	kfree(objp: dcc_en_bits);
4188	return -ENOMEM;
4189	}
4190
4191	for (i = 0; i < num_pipes; i++)
4192	offset += snprintf(buf: rd_buf + offset, size: rd_buf_size - offset,
4193	fmt: "%d ", dcc_en_bits[i]);
4194	rd_buf[strlen(rd_buf)] = '\n';
4195
4196	kfree(objp: dcc_en_bits);
4197
4198	while (size) {
4199	if (*pos >= rd_buf_size)
4200	break;
4201	r = put_user(*(rd_buf + result), buf);
4202	if (r) {
4203	kfree(objp: rd_buf);
4204	return r; /* r = -EFAULT */
4205	}
4206	buf += 1;
4207	size -= 1;
4208	*pos += 1;
4209	result += 1;
4210	}
4211
4212	kfree(objp: rd_buf);
4213	return result;
4214	}
4215
4216	void dtn_debugfs_init(struct amdgpu_device *adev)
4217	{
4218	static const struct file_operations dtn_log_fops = {
4219	.owner = THIS_MODULE,
4220	.read = dtn_log_read,
4221	.write = dtn_log_write,
4222	.llseek = default_llseek
4223	};
4224	static const struct file_operations dcc_en_bits_fops = {
4225	.owner = THIS_MODULE,
4226	.read = dcc_en_bits_read,
4227	.llseek = default_llseek
4228	};
4229
4230	struct drm_minor *minor = adev_to_drm(adev)->primary;
4231	struct dentry *root = minor->debugfs_root;
4232
4233	debugfs_create_file("amdgpu_mst_topology", 0444, root,
4234	adev, &mst_topo_fops);
4235	debugfs_create_file("amdgpu_dm_capabilities", 0444, root,
4236	adev, &capabilities_fops);
4237	debugfs_create_file("amdgpu_dm_dtn_log", 0644, root, adev,
4238	&dtn_log_fops);
4239	debugfs_create_file("amdgpu_dm_dp_set_mst_en_for_sst", 0644, root, adev,
4240	&dp_set_mst_en_for_sst_ops);
4241	debugfs_create_file("amdgpu_dm_dp_ignore_cable_id", 0644, root, adev,
4242	&dp_ignore_cable_id_ops);
4243
4244	debugfs_create_file_unsafe(name: "amdgpu_dm_visual_confirm", mode: 0644, parent: root, data: adev,
4245	fops: &visual_confirm_fops);
4246
4247	debugfs_create_file_unsafe(name: "amdgpu_dm_skip_detection_link_training", mode: 0644, parent: root, data: adev,
4248	fops: &skip_detection_link_training_fops);
4249
4250	debugfs_create_file_unsafe(name: "amdgpu_dm_dmub_tracebuffer", mode: 0644, parent: root,
4251	data: adev, fops: &dmub_tracebuffer_fops);
4252
4253	debugfs_create_file_unsafe(name: "amdgpu_dm_dmub_fw_state", mode: 0644, parent: root,
4254	data: adev, fops: &dmub_fw_state_fops);
4255
4256	debugfs_create_file_unsafe(name: "amdgpu_dm_force_timing_sync", mode: 0644, parent: root,
4257	data: adev, fops: &force_timing_sync_ops);
4258
4259	debugfs_create_file_unsafe(name: "amdgpu_dm_dmub_trace_mask", mode: 0644, parent: root,
4260	data: adev, fops: &dmub_trace_mask_fops);
4261
4262	debugfs_create_file_unsafe(name: "amdgpu_dm_dmcub_trace_event_en", mode: 0644, parent: root,
4263	data: adev, fops: &dmcub_trace_event_state_fops);
4264
4265	debugfs_create_file_unsafe(name: "amdgpu_dm_trigger_hpd_mst", mode: 0644, parent: root,
4266	data: adev, fops: &trigger_hpd_mst_ops);
4267
4268	debugfs_create_file_unsafe(name: "amdgpu_dm_dcc_en", mode: 0644, parent: root, data: adev,
4269	fops: &dcc_en_bits_fops);
4270
4271	debugfs_create_file_unsafe(name: "amdgpu_dm_disable_hpd", mode: 0644, parent: root, data: adev,
4272	fops: &disable_hpd_ops);
4273
4274	if (adev->dm.dc->caps.ips_support)
4275	debugfs_create_file_unsafe(name: "amdgpu_dm_ips_status", mode: 0644, parent: root, data: adev,
4276	fops: &ips_status_fops);
4277	}
4278