1// SPDX-License-Identifier: MIT
2/*
3 * Copyright 2022 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26#include <drm/drm_vblank.h>
27#include <drm/drm_atomic_helper.h>
28
29#include "dc.h"
30#include "amdgpu.h"
31#include "amdgpu_dm_psr.h"
32#include "amdgpu_dm_replay.h"
33#include "amdgpu_dm_crtc.h"
34#include "amdgpu_dm_plane.h"
35#include "amdgpu_dm_trace.h"
36#include "amdgpu_dm_debugfs.h"
37
38#define HPD_DETECTION_PERIOD_uS 2000000
39#define HPD_DETECTION_TIME_uS 100000
40
41void amdgpu_dm_crtc_handle_vblank(struct amdgpu_crtc *acrtc)
42{
43 struct drm_crtc *crtc = &acrtc->base;
44 struct drm_device *dev = crtc->dev;
45 unsigned long flags;
46
47 drm_crtc_handle_vblank(crtc);
48
49 spin_lock_irqsave(&dev->event_lock, flags);
50
51 /* Send completion event for cursor-only commits */
52 if (acrtc->event && acrtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
53 drm_crtc_send_vblank_event(crtc, e: acrtc->event);
54 drm_crtc_vblank_put(crtc);
55 acrtc->event = NULL;
56 }
57
58 spin_unlock_irqrestore(lock: &dev->event_lock, flags);
59}
60
61bool amdgpu_dm_crtc_modeset_required(struct drm_crtc_state *crtc_state,
62 struct dc_stream_state *new_stream,
63 struct dc_stream_state *old_stream)
64{
65 return crtc_state->active && drm_atomic_crtc_needs_modeset(state: crtc_state);
66}
67
68bool amdgpu_dm_crtc_vrr_active_irq(struct amdgpu_crtc *acrtc)
69
70{
71 return acrtc->dm_irq_params.freesync_config.state ==
72 VRR_STATE_ACTIVE_VARIABLE ||
73 acrtc->dm_irq_params.freesync_config.state ==
74 VRR_STATE_ACTIVE_FIXED;
75}
76
77int amdgpu_dm_crtc_set_vupdate_irq(struct drm_crtc *crtc, bool enable)
78{
79 enum dc_irq_source irq_source;
80 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
81 struct amdgpu_device *adev = drm_to_adev(ddev: crtc->dev);
82 int rc;
83
84 if (acrtc->otg_inst == -1)
85 return 0;
86
87 irq_source = IRQ_TYPE_VUPDATE + acrtc->otg_inst;
88
89 rc = dc_interrupt_set(dc: adev->dm.dc, src: irq_source, enable) ? 0 : -EBUSY;
90
91 DRM_DEBUG_VBL("crtc %d - vupdate irq %sabling: r=%d\n",
92 acrtc->crtc_id, enable ? "en" : "dis", rc);
93 return rc;
94}
95
96bool amdgpu_dm_crtc_vrr_active(const struct dm_crtc_state *dm_state)
97{
98 return dm_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE ||
99 dm_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
100}
101
102/**
103 * amdgpu_dm_crtc_set_panel_sr_feature() - Manage panel self-refresh features.
104 *
105 * @vblank_work: is a pointer to a struct vblank_control_work object.
106 * @vblank_enabled: indicates whether the DRM vblank counter is currently
107 * enabled (true) or disabled (false).
108 * @allow_sr_entry: represents whether entry into the self-refresh mode is
109 * allowed (true) or not allowed (false).
110 *
111 * The DRM vblank counter enable/disable action is used as the trigger to enable
112 * or disable various panel self-refresh features:
113 *
114 * Panel Replay and PSR SU
115 * - Enable when:
116 * - VRR is disabled
117 * - vblank counter is disabled
118 * - entry is allowed: usermode demonstrates an adequate number of fast
119 * commits)
120 * - CRC capture window isn't active
121 * - Keep enabled even when vblank counter gets enabled
122 *
123 * PSR1
124 * - Enable condition same as above
125 * - Disable when vblank counter is enabled
126 */
127static void amdgpu_dm_crtc_set_panel_sr_feature(
128 struct vblank_control_work *vblank_work,
129 bool vblank_enabled, bool allow_sr_entry)
130{
131 struct dc_link *link = vblank_work->stream->link;
132 bool is_sr_active = (link->replay_settings.replay_allow_active ||
133 link->psr_settings.psr_allow_active);
134 bool is_crc_window_active = false;
135 bool vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc: vblank_work->acrtc);
136
137#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
138 is_crc_window_active =
139 amdgpu_dm_crc_window_is_activated(crtc: &vblank_work->acrtc->base);
140#endif
141
142 if (link->replay_settings.replay_feature_enabled && !vrr_active &&
143 allow_sr_entry && !is_sr_active && !is_crc_window_active) {
144 amdgpu_dm_replay_enable(stream: vblank_work->stream, enable: true);
145 } else if (vblank_enabled) {
146 if (link->psr_settings.psr_version < DC_PSR_VERSION_SU_1 && is_sr_active)
147 amdgpu_dm_psr_disable(stream: vblank_work->stream, wait: false);
148 } else if (link->psr_settings.psr_feature_enabled && !vrr_active &&
149 allow_sr_entry && !is_sr_active && !is_crc_window_active) {
150
151 struct amdgpu_dm_connector *aconn =
152 (struct amdgpu_dm_connector *) vblank_work->stream->dm_stream_context;
153
154 if (!aconn->disallow_edp_enter_psr) {
155 struct amdgpu_display_manager *dm = vblank_work->dm;
156
157 amdgpu_dm_psr_enable(stream: vblank_work->stream);
158 if (dm->idle_workqueue &&
159 (dm->dc->config.disable_ips == DMUB_IPS_ENABLE) &&
160 dm->dc->idle_optimizations_allowed &&
161 dm->idle_workqueue->enable &&
162 !dm->idle_workqueue->running)
163 schedule_work(work: &dm->idle_workqueue->work);
164 }
165 }
166}
167
168bool amdgpu_dm_is_headless(struct amdgpu_device *adev)
169{
170 struct drm_connector *connector;
171 struct drm_connector_list_iter iter;
172 struct drm_device *dev;
173 bool is_headless = true;
174
175 if (adev == NULL)
176 return true;
177
178 dev = adev->dm.ddev;
179
180 drm_connector_list_iter_begin(dev, iter: &iter);
181 drm_for_each_connector_iter(connector, &iter) {
182
183 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
184 continue;
185
186 if (connector->status == connector_status_connected) {
187 is_headless = false;
188 break;
189 }
190 }
191 drm_connector_list_iter_end(iter: &iter);
192 return is_headless;
193}
194
195static void amdgpu_dm_idle_worker(struct work_struct *work)
196{
197 struct idle_workqueue *idle_work;
198
199 idle_work = container_of(work, struct idle_workqueue, work);
200 idle_work->dm->idle_workqueue->running = true;
201
202 while (idle_work->enable) {
203 fsleep(HPD_DETECTION_PERIOD_uS);
204 mutex_lock(&idle_work->dm->dc_lock);
205 if (!idle_work->dm->dc->idle_optimizations_allowed) {
206 mutex_unlock(lock: &idle_work->dm->dc_lock);
207 break;
208 }
209 dc_allow_idle_optimizations(idle_work->dm->dc, false);
210
211 mutex_unlock(lock: &idle_work->dm->dc_lock);
212 fsleep(HPD_DETECTION_TIME_uS);
213 mutex_lock(&idle_work->dm->dc_lock);
214
215 if (!amdgpu_dm_is_headless(adev: idle_work->dm->adev) &&
216 !amdgpu_dm_psr_is_active_allowed(dm: idle_work->dm)) {
217 mutex_unlock(lock: &idle_work->dm->dc_lock);
218 break;
219 }
220
221 if (idle_work->enable) {
222 dc_post_update_surfaces_to_stream(dc: idle_work->dm->dc);
223 dc_allow_idle_optimizations(idle_work->dm->dc, true);
224 }
225 mutex_unlock(lock: &idle_work->dm->dc_lock);
226 }
227 idle_work->dm->idle_workqueue->running = false;
228}
229
230struct idle_workqueue *idle_create_workqueue(struct amdgpu_device *adev)
231{
232 struct idle_workqueue *idle_work;
233
234 idle_work = kzalloc(sizeof(*idle_work), GFP_KERNEL);
235 if (ZERO_OR_NULL_PTR(idle_work))
236 return NULL;
237
238 idle_work->dm = &adev->dm;
239 idle_work->enable = false;
240 idle_work->running = false;
241 INIT_WORK(&idle_work->work, amdgpu_dm_idle_worker);
242
243 return idle_work;
244}
245
246static void amdgpu_dm_crtc_vblank_control_worker(struct work_struct *work)
247{
248 struct vblank_control_work *vblank_work =
249 container_of(work, struct vblank_control_work, work);
250 struct amdgpu_display_manager *dm = vblank_work->dm;
251
252 mutex_lock(&dm->dc_lock);
253
254 if (vblank_work->enable)
255 dm->active_vblank_irq_count++;
256 else if (dm->active_vblank_irq_count)
257 dm->active_vblank_irq_count--;
258
259 if (dm->active_vblank_irq_count > 0)
260 dc_allow_idle_optimizations(dm->dc, false);
261
262 /*
263 * Control PSR based on vblank requirements from OS
264 *
265 * If panel supports PSR SU, there's no need to disable PSR when OS is
266 * submitting fast atomic commits (we infer this by whether the OS
267 * requests vblank events). Fast atomic commits will simply trigger a
268 * full-frame-update (FFU); a specific case of selective-update (SU)
269 * where the SU region is the full hactive*vactive region. See
270 * fill_dc_dirty_rects().
271 */
272 if (vblank_work->stream && vblank_work->stream->link && vblank_work->acrtc) {
273 amdgpu_dm_crtc_set_panel_sr_feature(
274 vblank_work, vblank_enabled: vblank_work->enable,
275 allow_sr_entry: vblank_work->acrtc->dm_irq_params.allow_sr_entry);
276 }
277
278 if (dm->active_vblank_irq_count == 0) {
279 dc_post_update_surfaces_to_stream(dc: dm->dc);
280 dc_allow_idle_optimizations(dm->dc, true);
281 }
282
283 mutex_unlock(lock: &dm->dc_lock);
284
285 dc_stream_release(dc_stream: vblank_work->stream);
286
287 kfree(objp: vblank_work);
288}
289
290static inline int amdgpu_dm_crtc_set_vblank(struct drm_crtc *crtc, bool enable)
291{
292 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
293 struct amdgpu_device *adev = drm_to_adev(ddev: crtc->dev);
294 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
295 struct amdgpu_display_manager *dm = &adev->dm;
296 struct vblank_control_work *work;
297 int irq_type;
298 int rc = 0;
299
300 if (enable && !acrtc->base.enabled) {
301 drm_dbg_vbl(crtc->dev,
302 "Reject vblank enable on unconfigured CRTC %d (enabled=%d)\n",
303 acrtc->crtc_id, acrtc->base.enabled);
304 return -EINVAL;
305 }
306
307 irq_type = amdgpu_display_crtc_idx_to_irq_type(adev, crtc: acrtc->crtc_id);
308
309 if (enable) {
310 struct dc *dc = adev->dm.dc;
311 struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc);
312 struct psr_settings *psr = &acrtc_state->stream->link->psr_settings;
313 struct replay_settings *pr = &acrtc_state->stream->link->replay_settings;
314 bool sr_supported = (psr->psr_version != DC_PSR_VERSION_UNSUPPORTED) ||
315 pr->config.replay_supported;
316
317 /*
318 * IPS & self-refresh feature can cause vblank counter resets between
319 * vblank disable and enable.
320 * It may cause system stuck due to waiting for the vblank counter.
321 * Call this function to estimate missed vblanks by using timestamps and
322 * update the vblank counter in DRM.
323 */
324 if (dc->caps.ips_support &&
325 dc->config.disable_ips != DMUB_IPS_DISABLE_ALL &&
326 sr_supported && vblank->config.disable_immediate)
327 drm_crtc_vblank_restore(crtc);
328 }
329
330 if (dc_supports_vrr(v: dm->dc->ctx->dce_version)) {
331 if (enable) {
332 /* vblank irq on -> Only need vupdate irq in vrr mode */
333 if (amdgpu_dm_crtc_vrr_active(dm_state: acrtc_state))
334 rc = amdgpu_dm_crtc_set_vupdate_irq(crtc, enable: true);
335 } else {
336 /* vblank irq off -> vupdate irq off */
337 rc = amdgpu_dm_crtc_set_vupdate_irq(crtc, enable: false);
338 }
339 }
340
341 if (rc)
342 return rc;
343
344 /* crtc vblank or vstartup interrupt */
345 if (enable) {
346 rc = amdgpu_irq_get(adev, src: &adev->crtc_irq, type: irq_type);
347 drm_dbg_vbl(crtc->dev, "Get crtc_irq ret=%d\n", rc);
348 } else {
349 rc = amdgpu_irq_put(adev, src: &adev->crtc_irq, type: irq_type);
350 drm_dbg_vbl(crtc->dev, "Put crtc_irq ret=%d\n", rc);
351 }
352
353 if (rc)
354 return rc;
355
356 /*
357 * hubp surface flip interrupt
358 *
359 * We have no guarantee that the frontend index maps to the same
360 * backend index - some even map to more than one.
361 *
362 * TODO: Use a different interrupt or check DC itself for the mapping.
363 */
364 if (enable) {
365 rc = amdgpu_irq_get(adev, src: &adev->pageflip_irq, type: irq_type);
366 drm_dbg_vbl(crtc->dev, "Get pageflip_irq ret=%d\n", rc);
367 } else {
368 rc = amdgpu_irq_put(adev, src: &adev->pageflip_irq, type: irq_type);
369 drm_dbg_vbl(crtc->dev, "Put pageflip_irq ret=%d\n", rc);
370 }
371
372 if (rc)
373 return rc;
374
375#if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
376 /* crtc vline0 interrupt, only available on DCN+ */
377 if (amdgpu_ip_version(adev, ip: DCE_HWIP, inst: 0) != 0) {
378 if (enable) {
379 rc = amdgpu_irq_get(adev, src: &adev->vline0_irq, type: irq_type);
380 drm_dbg_vbl(crtc->dev, "Get vline0_irq ret=%d\n", rc);
381 } else {
382 rc = amdgpu_irq_put(adev, src: &adev->vline0_irq, type: irq_type);
383 drm_dbg_vbl(crtc->dev, "Put vline0_irq ret=%d\n", rc);
384 }
385
386 if (rc)
387 return rc;
388 }
389#endif
390
391 if (amdgpu_in_reset(adev))
392 return 0;
393
394 if (dm->vblank_control_workqueue) {
395 work = kzalloc(sizeof(*work), GFP_ATOMIC);
396 if (!work)
397 return -ENOMEM;
398
399 INIT_WORK(&work->work, amdgpu_dm_crtc_vblank_control_worker);
400 work->dm = dm;
401 work->acrtc = acrtc;
402 work->enable = enable;
403
404 if (acrtc_state->stream) {
405 dc_stream_retain(dc_stream: acrtc_state->stream);
406 work->stream = acrtc_state->stream;
407 }
408
409 queue_work(wq: dm->vblank_control_workqueue, work: &work->work);
410 }
411
412 return 0;
413}
414
415int amdgpu_dm_crtc_enable_vblank(struct drm_crtc *crtc)
416{
417 return amdgpu_dm_crtc_set_vblank(crtc, enable: true);
418}
419
420void amdgpu_dm_crtc_disable_vblank(struct drm_crtc *crtc)
421{
422 amdgpu_dm_crtc_set_vblank(crtc, enable: false);
423}
424
425static void amdgpu_dm_crtc_destroy_state(struct drm_crtc *crtc,
426 struct drm_crtc_state *state)
427{
428 struct dm_crtc_state *cur = to_dm_crtc_state(state);
429
430 /* TODO Destroy dc_stream objects are stream object is flattened */
431 if (cur->stream)
432 dc_stream_release(dc_stream: cur->stream);
433
434
435 __drm_atomic_helper_crtc_destroy_state(state);
436
437
438 kfree(objp: state);
439}
440
441static struct drm_crtc_state *amdgpu_dm_crtc_duplicate_state(struct drm_crtc *crtc)
442{
443 struct dm_crtc_state *state, *cur;
444
445 cur = to_dm_crtc_state(crtc->state);
446
447 if (WARN_ON(!crtc->state))
448 return NULL;
449
450 state = kzalloc(sizeof(*state), GFP_KERNEL);
451 if (!state)
452 return NULL;
453
454 __drm_atomic_helper_crtc_duplicate_state(crtc, state: &state->base);
455
456 if (cur->stream) {
457 state->stream = cur->stream;
458 dc_stream_retain(dc_stream: state->stream);
459 }
460
461 state->active_planes = cur->active_planes;
462 state->vrr_infopacket = cur->vrr_infopacket;
463 state->abm_level = cur->abm_level;
464 state->vrr_supported = cur->vrr_supported;
465 state->freesync_config = cur->freesync_config;
466 state->cm_has_degamma = cur->cm_has_degamma;
467 state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb;
468 state->regamma_tf = cur->regamma_tf;
469 state->crc_skip_count = cur->crc_skip_count;
470 state->mpo_requested = cur->mpo_requested;
471 state->cursor_mode = cur->cursor_mode;
472 /* TODO Duplicate dc_stream after objects are stream object is flattened */
473
474 return &state->base;
475}
476
477static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
478{
479 drm_crtc_cleanup(crtc);
480 kfree(objp: crtc);
481}
482
483static void amdgpu_dm_crtc_reset_state(struct drm_crtc *crtc)
484{
485 struct dm_crtc_state *state;
486
487 if (crtc->state)
488 amdgpu_dm_crtc_destroy_state(crtc, state: crtc->state);
489
490 state = kzalloc(sizeof(*state), GFP_KERNEL);
491 if (WARN_ON(!state))
492 return;
493
494 __drm_atomic_helper_crtc_reset(crtc, state: &state->base);
495}
496
497#ifdef CONFIG_DEBUG_FS
498static int amdgpu_dm_crtc_late_register(struct drm_crtc *crtc)
499{
500 crtc_debugfs_init(crtc);
501
502 return 0;
503}
504#endif
505
506#ifdef AMD_PRIVATE_COLOR
507/**
508 * dm_crtc_additional_color_mgmt - enable additional color properties
509 * @crtc: DRM CRTC
510 *
511 * This function lets the driver enable post-blending CRTC regamma transfer
512 * function property in addition to DRM CRTC gamma LUT. Default value means
513 * linear transfer function, which is the default CRTC gamma LUT behaviour
514 * without this property.
515 */
516static void
517dm_crtc_additional_color_mgmt(struct drm_crtc *crtc)
518{
519 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
520
521 if (adev->dm.dc->caps.color.mpc.ogam_ram)
522 drm_object_attach_property(&crtc->base,
523 adev->mode_info.regamma_tf_property,
524 AMDGPU_TRANSFER_FUNCTION_DEFAULT);
525}
526
527static int
528amdgpu_dm_atomic_crtc_set_property(struct drm_crtc *crtc,
529 struct drm_crtc_state *state,
530 struct drm_property *property,
531 uint64_t val)
532{
533 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
534 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(state);
535
536 if (property == adev->mode_info.regamma_tf_property) {
537 if (acrtc_state->regamma_tf != val) {
538 acrtc_state->regamma_tf = val;
539 acrtc_state->base.color_mgmt_changed |= 1;
540 }
541 } else {
542 drm_dbg_atomic(crtc->dev,
543 "[CRTC:%d:%s] unknown property [PROP:%d:%s]]\n",
544 crtc->base.id, crtc->name,
545 property->base.id, property->name);
546 return -EINVAL;
547 }
548
549 return 0;
550}
551
552static int
553amdgpu_dm_atomic_crtc_get_property(struct drm_crtc *crtc,
554 const struct drm_crtc_state *state,
555 struct drm_property *property,
556 uint64_t *val)
557{
558 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
559 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(state);
560
561 if (property == adev->mode_info.regamma_tf_property)
562 *val = acrtc_state->regamma_tf;
563 else
564 return -EINVAL;
565
566 return 0;
567}
568#endif
569
570/* Implemented only the options currently available for the driver */
571static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
572 .reset = amdgpu_dm_crtc_reset_state,
573 .destroy = amdgpu_dm_crtc_destroy,
574 .set_config = drm_atomic_helper_set_config,
575 .page_flip = drm_atomic_helper_page_flip,
576 .atomic_duplicate_state = amdgpu_dm_crtc_duplicate_state,
577 .atomic_destroy_state = amdgpu_dm_crtc_destroy_state,
578 .set_crc_source = amdgpu_dm_crtc_set_crc_source,
579 .verify_crc_source = amdgpu_dm_crtc_verify_crc_source,
580 .get_crc_sources = amdgpu_dm_crtc_get_crc_sources,
581 .get_vblank_counter = amdgpu_get_vblank_counter_kms,
582 .enable_vblank = amdgpu_dm_crtc_enable_vblank,
583 .disable_vblank = amdgpu_dm_crtc_disable_vblank,
584 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
585#if defined(CONFIG_DEBUG_FS)
586 .late_register = amdgpu_dm_crtc_late_register,
587#endif
588#ifdef AMD_PRIVATE_COLOR
589 .atomic_set_property = amdgpu_dm_atomic_crtc_set_property,
590 .atomic_get_property = amdgpu_dm_atomic_crtc_get_property,
591#endif
592};
593
594static void amdgpu_dm_crtc_helper_disable(struct drm_crtc *crtc)
595{
596}
597
598static int amdgpu_dm_crtc_count_crtc_active_planes(struct drm_crtc_state *new_crtc_state)
599{
600 struct drm_atomic_state *state = new_crtc_state->state;
601 struct drm_plane *plane;
602 int num_active = 0;
603
604 drm_for_each_plane_mask(plane, state->dev, new_crtc_state->plane_mask) {
605 struct drm_plane_state *new_plane_state;
606
607 /* Cursor planes are "fake". */
608 if (plane->type == DRM_PLANE_TYPE_CURSOR)
609 continue;
610
611 new_plane_state = drm_atomic_get_new_plane_state(state, plane);
612
613 if (!new_plane_state) {
614 /*
615 * The plane is enable on the CRTC and hasn't changed
616 * state. This means that it previously passed
617 * validation and is therefore enabled.
618 */
619 num_active += 1;
620 continue;
621 }
622
623 /* We need a framebuffer to be considered enabled. */
624 num_active += (new_plane_state->fb != NULL);
625 }
626
627 return num_active;
628}
629
630static void amdgpu_dm_crtc_update_crtc_active_planes(struct drm_crtc *crtc,
631 struct drm_crtc_state *new_crtc_state)
632{
633 struct dm_crtc_state *dm_new_crtc_state =
634 to_dm_crtc_state(new_crtc_state);
635
636 dm_new_crtc_state->active_planes = 0;
637
638 if (!dm_new_crtc_state->stream)
639 return;
640
641 dm_new_crtc_state->active_planes =
642 amdgpu_dm_crtc_count_crtc_active_planes(new_crtc_state);
643}
644
645static bool amdgpu_dm_crtc_helper_mode_fixup(struct drm_crtc *crtc,
646 const struct drm_display_mode *mode,
647 struct drm_display_mode *adjusted_mode)
648{
649 return true;
650}
651
652static int amdgpu_dm_crtc_helper_atomic_check(struct drm_crtc *crtc,
653 struct drm_atomic_state *state)
654{
655 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
656 crtc);
657 struct amdgpu_device *adev = drm_to_adev(ddev: crtc->dev);
658 struct dc *dc = adev->dm.dc;
659 struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
660 int ret = -EINVAL;
661
662 trace_amdgpu_dm_crtc_atomic_check(state: crtc_state);
663
664 amdgpu_dm_crtc_update_crtc_active_planes(crtc, new_crtc_state: crtc_state);
665
666 if (WARN_ON(unlikely(!dm_crtc_state->stream &&
667 amdgpu_dm_crtc_modeset_required(crtc_state, NULL, dm_crtc_state->stream)))) {
668 return ret;
669 }
670
671 /*
672 * We require the primary plane to be enabled whenever the CRTC is, otherwise
673 * drm_mode_cursor_universal may end up trying to enable the cursor plane while all other
674 * planes are disabled, which is not supported by the hardware. And there is legacy
675 * userspace which stops using the HW cursor altogether in response to the resulting EINVAL.
676 */
677 if (crtc_state->enable &&
678 !(crtc_state->plane_mask & drm_plane_mask(plane: crtc->primary))) {
679 DRM_DEBUG_ATOMIC("Can't enable a CRTC without enabling the primary plane\n");
680 return -EINVAL;
681 }
682
683 /*
684 * Only allow async flips for fast updates that don't change the FB
685 * pitch, the DCC state, rotation, etc.
686 */
687 if (crtc_state->async_flip &&
688 dm_crtc_state->update_type != UPDATE_TYPE_FAST) {
689 drm_dbg_atomic(crtc->dev,
690 "[CRTC:%d:%s] async flips are only supported for fast updates\n",
691 crtc->base.id, crtc->name);
692 return -EINVAL;
693 }
694
695 if (!state->legacy_cursor_update && amdgpu_dm_crtc_vrr_active(dm_state: dm_crtc_state)) {
696 struct drm_plane_state *primary_state;
697
698 /* Pull in primary plane for correct VRR handling */
699 primary_state = drm_atomic_get_plane_state(state, plane: crtc->primary);
700 if (IS_ERR(ptr: primary_state))
701 return PTR_ERR(ptr: primary_state);
702 }
703
704 /* In some use cases, like reset, no stream is attached */
705 if (!dm_crtc_state->stream)
706 return 0;
707
708 if (dc_validate_stream(dc, stream: dm_crtc_state->stream) == DC_OK)
709 return 0;
710
711 DRM_DEBUG_ATOMIC("Failed DC stream validation\n");
712 return ret;
713}
714
715static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
716 .disable = amdgpu_dm_crtc_helper_disable,
717 .atomic_check = amdgpu_dm_crtc_helper_atomic_check,
718 .mode_fixup = amdgpu_dm_crtc_helper_mode_fixup,
719 .get_scanout_position = amdgpu_crtc_get_scanout_position,
720};
721
722int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
723 struct drm_plane *plane,
724 uint32_t crtc_index)
725{
726 struct amdgpu_crtc *acrtc = NULL;
727 struct drm_plane *cursor_plane;
728 bool has_degamma;
729 int res = -ENOMEM;
730
731 cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL);
732 if (!cursor_plane)
733 goto fail;
734
735 cursor_plane->type = DRM_PLANE_TYPE_CURSOR;
736 res = amdgpu_dm_plane_init(dm, plane: cursor_plane, possible_crtcs: 0, NULL);
737
738 acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL);
739 if (!acrtc)
740 goto fail;
741
742 res = drm_crtc_init_with_planes(
743 dev: dm->ddev,
744 crtc: &acrtc->base,
745 primary: plane,
746 cursor: cursor_plane,
747 funcs: &amdgpu_dm_crtc_funcs, NULL);
748
749 if (res)
750 goto fail;
751
752 drm_crtc_helper_add(crtc: &acrtc->base, funcs: &amdgpu_dm_crtc_helper_funcs);
753
754 /* Create (reset) the plane state */
755 if (acrtc->base.funcs->reset)
756 acrtc->base.funcs->reset(&acrtc->base);
757
758 acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size;
759 acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size;
760
761 acrtc->crtc_id = crtc_index;
762 acrtc->base.enabled = false;
763 acrtc->otg_inst = -1;
764
765 dm->adev->mode_info.crtcs[crtc_index] = acrtc;
766
767 /* Don't enable DRM CRTC degamma property for
768 * 1. Degamma is replaced by color pipeline.
769 * 2. DCE since it doesn't support programmable degamma anywhere.
770 * 3. DCN401 since pre-blending degamma LUT doesn't apply to cursor.
771 */
772 if (plane->color_pipeline_property)
773 has_degamma = false;
774 else
775 has_degamma = dm->adev->dm.dc->caps.color.dpp.dcn_arch &&
776 dm->adev->dm.dc->ctx->dce_version != DCN_VERSION_4_01;
777
778 drm_crtc_enable_color_mgmt(crtc: &acrtc->base, degamma_lut_size: has_degamma ? MAX_COLOR_LUT_ENTRIES : 0,
779 has_ctm: true, MAX_COLOR_LUT_ENTRIES);
780
781 drm_mode_crtc_set_gamma_size(crtc: &acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES);
782
783#ifdef AMD_PRIVATE_COLOR
784 dm_crtc_additional_color_mgmt(&acrtc->base);
785#endif
786 return 0;
787
788fail:
789 kfree(objp: acrtc);
790 kfree(objp: cursor_plane);
791 return res;
792}
793
794

source code of linux/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c