1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/firmware.h>
25#include <linux/module.h>
26#include <linux/pci.h>
27
28#include <drm/drm_cache.h>
29#include "amdgpu.h"
30#include "gmc_v8_0.h"
31#include "amdgpu_ucode.h"
32#include "amdgpu_amdkfd.h"
33#include "amdgpu_gem.h"
34
35#include "gmc/gmc_8_1_d.h"
36#include "gmc/gmc_8_1_sh_mask.h"
37
38#include "bif/bif_5_0_d.h"
39#include "bif/bif_5_0_sh_mask.h"
40
41#include "oss/oss_3_0_d.h"
42#include "oss/oss_3_0_sh_mask.h"
43
44#include "dce/dce_10_0_d.h"
45#include "dce/dce_10_0_sh_mask.h"
46
47#include "vid.h"
48#include "vi.h"
49
50#include "amdgpu_atombios.h"
51
52#include "ivsrcid/ivsrcid_vislands30.h"
53
54static void gmc_v8_0_set_gmc_funcs(struct amdgpu_device *adev);
55static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev);
56static int gmc_v8_0_wait_for_idle(struct amdgpu_ip_block *ip_block);
57
58MODULE_FIRMWARE("amdgpu/tonga_mc.bin");
59MODULE_FIRMWARE("amdgpu/polaris11_mc.bin");
60MODULE_FIRMWARE("amdgpu/polaris10_mc.bin");
61MODULE_FIRMWARE("amdgpu/polaris12_mc.bin");
62MODULE_FIRMWARE("amdgpu/polaris12_32_mc.bin");
63MODULE_FIRMWARE("amdgpu/polaris11_k_mc.bin");
64MODULE_FIRMWARE("amdgpu/polaris10_k_mc.bin");
65MODULE_FIRMWARE("amdgpu/polaris12_k_mc.bin");
66
67static const u32 golden_settings_tonga_a11[] = {
68 mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,
69 mmMC_HUB_RDREQ_DMIF_LIMIT, 0x0000007f, 0x00000028,
70 mmMC_HUB_WDP_UMC, 0x00007fb6, 0x00000991,
71 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
72 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
73 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
74 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
75};
76
77static const u32 tonga_mgcg_cgcg_init[] = {
78 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
79};
80
81static const u32 golden_settings_fiji_a10[] = {
82 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
83 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
84 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
85 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff,
86};
87
88static const u32 fiji_mgcg_cgcg_init[] = {
89 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
90};
91
92static const u32 golden_settings_polaris11_a11[] = {
93 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
94 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
95 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
96 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
97};
98
99static const u32 golden_settings_polaris10_a11[] = {
100 mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000,
101 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff,
102 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff,
103 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff,
104 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff
105};
106
107static const u32 cz_mgcg_cgcg_init[] = {
108 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
109};
110
111static const u32 stoney_mgcg_cgcg_init[] = {
112 mmATC_MISC_CG, 0xffffffff, 0x000c0200,
113 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
114};
115
116static const u32 golden_settings_stoney_common[] = {
117 mmMC_HUB_RDREQ_UVD, MC_HUB_RDREQ_UVD__PRESCALE_MASK, 0x00000004,
118 mmMC_RD_GRP_OTH, MC_RD_GRP_OTH__UVD_MASK, 0x00600000
119};
120
121static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev)
122{
123 switch (adev->asic_type) {
124 case CHIP_FIJI:
125 amdgpu_device_program_register_sequence(adev,
126 registers: fiji_mgcg_cgcg_init,
127 ARRAY_SIZE(fiji_mgcg_cgcg_init));
128 amdgpu_device_program_register_sequence(adev,
129 registers: golden_settings_fiji_a10,
130 ARRAY_SIZE(golden_settings_fiji_a10));
131 break;
132 case CHIP_TONGA:
133 amdgpu_device_program_register_sequence(adev,
134 registers: tonga_mgcg_cgcg_init,
135 ARRAY_SIZE(tonga_mgcg_cgcg_init));
136 amdgpu_device_program_register_sequence(adev,
137 registers: golden_settings_tonga_a11,
138 ARRAY_SIZE(golden_settings_tonga_a11));
139 break;
140 case CHIP_POLARIS11:
141 case CHIP_POLARIS12:
142 case CHIP_VEGAM:
143 amdgpu_device_program_register_sequence(adev,
144 registers: golden_settings_polaris11_a11,
145 ARRAY_SIZE(golden_settings_polaris11_a11));
146 break;
147 case CHIP_POLARIS10:
148 amdgpu_device_program_register_sequence(adev,
149 registers: golden_settings_polaris10_a11,
150 ARRAY_SIZE(golden_settings_polaris10_a11));
151 break;
152 case CHIP_CARRIZO:
153 amdgpu_device_program_register_sequence(adev,
154 registers: cz_mgcg_cgcg_init,
155 ARRAY_SIZE(cz_mgcg_cgcg_init));
156 break;
157 case CHIP_STONEY:
158 amdgpu_device_program_register_sequence(adev,
159 registers: stoney_mgcg_cgcg_init,
160 ARRAY_SIZE(stoney_mgcg_cgcg_init));
161 amdgpu_device_program_register_sequence(adev,
162 registers: golden_settings_stoney_common,
163 ARRAY_SIZE(golden_settings_stoney_common));
164 break;
165 default:
166 break;
167 }
168}
169
170static void gmc_v8_0_mc_stop(struct amdgpu_device *adev)
171{
172 u32 blackout;
173 struct amdgpu_ip_block *ip_block;
174
175 ip_block = amdgpu_device_ip_get_ip_block(adev, type: AMD_IP_BLOCK_TYPE_GMC);
176 if (!ip_block)
177 return;
178
179 gmc_v8_0_wait_for_idle(ip_block);
180
181 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
182 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
183 /* Block CPU access */
184 WREG32(mmBIF_FB_EN, 0);
185 /* blackout the MC */
186 blackout = REG_SET_FIELD(blackout,
187 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 1);
188 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout);
189 }
190 /* wait for the MC to settle */
191 udelay(usec: 100);
192}
193
194static void gmc_v8_0_mc_resume(struct amdgpu_device *adev)
195{
196 u32 tmp;
197
198 /* unblackout the MC */
199 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
200 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
201 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
202 /* allow CPU access */
203 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
204 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
205 WREG32(mmBIF_FB_EN, tmp);
206}
207
208/**
209 * gmc_v8_0_init_microcode - load ucode images from disk
210 *
211 * @adev: amdgpu_device pointer
212 *
213 * Use the firmware interface to load the ucode images into
214 * the driver (not loaded into hw).
215 * Returns 0 on success, error on failure.
216 */
217static int gmc_v8_0_init_microcode(struct amdgpu_device *adev)
218{
219 const char *chip_name;
220 int err;
221
222 DRM_DEBUG("\n");
223
224 switch (adev->asic_type) {
225 case CHIP_TONGA:
226 chip_name = "tonga";
227 break;
228 case CHIP_POLARIS11:
229 if (ASICID_IS_P21(adev->pdev->device, adev->pdev->revision) ||
230 ASICID_IS_P31(adev->pdev->device, adev->pdev->revision))
231 chip_name = "polaris11_k";
232 else
233 chip_name = "polaris11";
234 break;
235 case CHIP_POLARIS10:
236 if (ASICID_IS_P30(adev->pdev->device, adev->pdev->revision))
237 chip_name = "polaris10_k";
238 else
239 chip_name = "polaris10";
240 break;
241 case CHIP_POLARIS12:
242 if (ASICID_IS_P23(adev->pdev->device, adev->pdev->revision)) {
243 chip_name = "polaris12_k";
244 } else {
245 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, ixMC_IO_DEBUG_UP_159);
246 /* Polaris12 32bit ASIC needs a special MC firmware */
247 if (RREG32(mmMC_SEQ_IO_DEBUG_DATA) == 0x05b4dc40)
248 chip_name = "polaris12_32";
249 else
250 chip_name = "polaris12";
251 }
252 break;
253 case CHIP_FIJI:
254 case CHIP_CARRIZO:
255 case CHIP_STONEY:
256 case CHIP_VEGAM:
257 return 0;
258 default:
259 return -EINVAL;
260 }
261
262 err = amdgpu_ucode_request(adev, fw: &adev->gmc.fw, required: AMDGPU_UCODE_REQUIRED,
263 fmt: "amdgpu/%s_mc.bin", chip_name);
264 if (err) {
265 pr_err("mc: Failed to load firmware \"%s_mc.bin\"\n", chip_name);
266 amdgpu_ucode_release(fw: &adev->gmc.fw);
267 }
268 return err;
269}
270
271/**
272 * gmc_v8_0_tonga_mc_load_microcode - load tonga MC ucode into the hw
273 *
274 * @adev: amdgpu_device pointer
275 *
276 * Load the GDDR MC ucode into the hw (VI).
277 * Returns 0 on success, error on failure.
278 */
279static int gmc_v8_0_tonga_mc_load_microcode(struct amdgpu_device *adev)
280{
281 const struct mc_firmware_header_v1_0 *hdr;
282 const __le32 *fw_data = NULL;
283 const __le32 *io_mc_regs = NULL;
284 u32 running;
285 int i, ucode_size, regs_size;
286
287 /* Skip MC ucode loading on SR-IOV capable boards.
288 * vbios does this for us in asic_init in that case.
289 * Skip MC ucode loading on VF, because hypervisor will do that
290 * for this adaptor.
291 */
292 if (amdgpu_sriov_bios(adev))
293 return 0;
294
295 if (!adev->gmc.fw)
296 return -EINVAL;
297
298 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data;
299 amdgpu_ucode_print_mc_hdr(hdr: &hdr->header);
300
301 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);
302 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
303 io_mc_regs = (const __le32 *)
304 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
305 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
306 fw_data = (const __le32 *)
307 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
308
309 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
310
311 if (running == 0) {
312 /* reset the engine and set to writable */
313 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
314 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
315
316 /* load mc io regs */
317 for (i = 0; i < regs_size; i++) {
318 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
319 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
320 }
321 /* load the MC ucode */
322 for (i = 0; i < ucode_size; i++)
323 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
324
325 /* put the engine back into the active state */
326 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
327 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
328 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
329
330 /* wait for training to complete */
331 for (i = 0; i < adev->usec_timeout; i++) {
332 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
333 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D0))
334 break;
335 udelay(usec: 1);
336 }
337 for (i = 0; i < adev->usec_timeout; i++) {
338 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
339 MC_SEQ_TRAIN_WAKEUP_CNTL, TRAIN_DONE_D1))
340 break;
341 udelay(usec: 1);
342 }
343 }
344
345 return 0;
346}
347
348static int gmc_v8_0_polaris_mc_load_microcode(struct amdgpu_device *adev)
349{
350 const struct mc_firmware_header_v1_0 *hdr;
351 const __le32 *fw_data = NULL;
352 const __le32 *io_mc_regs = NULL;
353 u32 data;
354 int i, ucode_size, regs_size;
355
356 /* Skip MC ucode loading on SR-IOV capable boards.
357 * vbios does this for us in asic_init in that case.
358 * Skip MC ucode loading on VF, because hypervisor will do that
359 * for this adaptor.
360 */
361 if (amdgpu_sriov_bios(adev))
362 return 0;
363
364 if (!adev->gmc.fw)
365 return -EINVAL;
366
367 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data;
368 amdgpu_ucode_print_mc_hdr(hdr: &hdr->header);
369
370 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);
371 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
372 io_mc_regs = (const __le32 *)
373 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
374 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
375 fw_data = (const __le32 *)
376 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
377
378 data = RREG32(mmMC_SEQ_MISC0);
379 data &= ~(0x40);
380 WREG32(mmMC_SEQ_MISC0, data);
381
382 /* load mc io regs */
383 for (i = 0; i < regs_size; i++) {
384 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
385 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
386 }
387
388 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
389 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
390
391 /* load the MC ucode */
392 for (i = 0; i < ucode_size; i++)
393 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
394
395 /* put the engine back into the active state */
396 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
397 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
398 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
399
400 /* wait for training to complete */
401 for (i = 0; i < adev->usec_timeout; i++) {
402 data = RREG32(mmMC_SEQ_MISC0);
403 if (data & 0x80)
404 break;
405 udelay(usec: 1);
406 }
407
408 return 0;
409}
410
411static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev,
412 struct amdgpu_gmc *mc)
413{
414 u64 base = 0;
415
416 if (!amdgpu_sriov_vf(adev))
417 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
418 base <<= 24;
419
420 amdgpu_gmc_set_agp_default(adev, mc);
421 amdgpu_gmc_vram_location(adev, mc, base);
422 amdgpu_gmc_gart_location(adev, mc, gart_placement: AMDGPU_GART_PLACEMENT_BEST_FIT);
423}
424
425/**
426 * gmc_v8_0_mc_program - program the GPU memory controller
427 *
428 * @adev: amdgpu_device pointer
429 *
430 * Set the location of vram, gart, and AGP in the GPU's
431 * physical address space (VI).
432 */
433static void gmc_v8_0_mc_program(struct amdgpu_device *adev)
434{
435 struct amdgpu_ip_block *ip_block;
436 u32 tmp;
437 int i, j;
438
439 /* Initialize HDP */
440 for (i = 0, j = 0; i < 32; i++, j += 0x6) {
441 WREG32((0xb05 + j), 0x00000000);
442 WREG32((0xb06 + j), 0x00000000);
443 WREG32((0xb07 + j), 0x00000000);
444 WREG32((0xb08 + j), 0x00000000);
445 WREG32((0xb09 + j), 0x00000000);
446 }
447 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
448
449 ip_block = amdgpu_device_ip_get_ip_block(adev, type: AMD_IP_BLOCK_TYPE_GMC);
450 if (!ip_block)
451 return;
452
453 if (gmc_v8_0_wait_for_idle(ip_block))
454 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
455
456 if (adev->mode_info.num_crtc) {
457 /* Lockout access through VGA aperture*/
458 tmp = RREG32(mmVGA_HDP_CONTROL);
459 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
460 WREG32(mmVGA_HDP_CONTROL, tmp);
461
462 /* disable VGA render */
463 tmp = RREG32(mmVGA_RENDER_CONTROL);
464 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
465 WREG32(mmVGA_RENDER_CONTROL, tmp);
466 }
467 /* Update configuration */
468 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
469 adev->gmc.vram_start >> 12);
470 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
471 adev->gmc.vram_end >> 12);
472 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
473 adev->mem_scratch.gpu_addr >> 12);
474
475 if (amdgpu_sriov_vf(adev)) {
476 tmp = ((adev->gmc.vram_end >> 24) & 0xFFFF) << 16;
477 tmp |= ((adev->gmc.vram_start >> 24) & 0xFFFF);
478 WREG32(mmMC_VM_FB_LOCATION, tmp);
479 /* XXX double check these! */
480 WREG32(mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8));
481 WREG32(mmHDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
482 WREG32(mmHDP_NONSURFACE_SIZE, 0x3FFFFFFF);
483 }
484
485 WREG32(mmMC_VM_AGP_BASE, 0);
486 WREG32(mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 22);
487 WREG32(mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 22);
488 if (gmc_v8_0_wait_for_idle(ip_block))
489 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
490
491 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
492
493 tmp = RREG32(mmHDP_MISC_CNTL);
494 tmp = REG_SET_FIELD(tmp, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 0);
495 WREG32(mmHDP_MISC_CNTL, tmp);
496
497 tmp = RREG32(mmHDP_HOST_PATH_CNTL);
498 WREG32(mmHDP_HOST_PATH_CNTL, tmp);
499}
500
501/**
502 * gmc_v8_0_mc_init - initialize the memory controller driver params
503 *
504 * @adev: amdgpu_device pointer
505 *
506 * Look up the amount of vram, vram width, and decide how to place
507 * vram and gart within the GPU's physical address space (VI).
508 * Returns 0 for success.
509 */
510static int gmc_v8_0_mc_init(struct amdgpu_device *adev)
511{
512 int r;
513 u32 tmp;
514
515 adev->gmc.vram_width = amdgpu_atombios_get_vram_width(adev);
516 if (!adev->gmc.vram_width) {
517 int chansize, numchan;
518
519 /* Get VRAM informations */
520 tmp = RREG32(mmMC_ARB_RAMCFG);
521 if (REG_GET_FIELD(tmp, MC_ARB_RAMCFG, CHANSIZE))
522 chansize = 64;
523 else
524 chansize = 32;
525
526 tmp = RREG32(mmMC_SHARED_CHMAP);
527 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
528 case 0:
529 default:
530 numchan = 1;
531 break;
532 case 1:
533 numchan = 2;
534 break;
535 case 2:
536 numchan = 4;
537 break;
538 case 3:
539 numchan = 8;
540 break;
541 case 4:
542 numchan = 3;
543 break;
544 case 5:
545 numchan = 6;
546 break;
547 case 6:
548 numchan = 10;
549 break;
550 case 7:
551 numchan = 12;
552 break;
553 case 8:
554 numchan = 16;
555 break;
556 }
557 adev->gmc.vram_width = numchan * chansize;
558 }
559 /* size in MB on si */
560 tmp = RREG32(mmCONFIG_MEMSIZE);
561 /* some boards may have garbage in the upper 16 bits */
562 if (tmp & 0xffff0000) {
563 DRM_INFO("Probable bad vram size: 0x%08x\n", tmp);
564 if (tmp & 0xffff)
565 tmp &= 0xffff;
566 }
567 adev->gmc.mc_vram_size = tmp * 1024ULL * 1024ULL;
568 adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
569
570 if (!(adev->flags & AMD_IS_APU)) {
571 r = amdgpu_device_resize_fb_bar(adev);
572 if (r)
573 return r;
574 }
575 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
576 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
577
578#ifdef CONFIG_X86_64
579 if ((adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) {
580 adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22;
581 adev->gmc.aper_size = adev->gmc.real_vram_size;
582 }
583#endif
584
585 adev->gmc.visible_vram_size = adev->gmc.aper_size;
586
587 /* set the gart size */
588 if (amdgpu_gart_size == -1) {
589 switch (adev->asic_type) {
590 case CHIP_POLARIS10: /* all engines support GPUVM */
591 case CHIP_POLARIS11: /* all engines support GPUVM */
592 case CHIP_POLARIS12: /* all engines support GPUVM */
593 case CHIP_VEGAM: /* all engines support GPUVM */
594 default:
595 adev->gmc.gart_size = 256ULL << 20;
596 break;
597 case CHIP_TONGA: /* UVD, VCE do not support GPUVM */
598 case CHIP_FIJI: /* UVD, VCE do not support GPUVM */
599 case CHIP_CARRIZO: /* UVD, VCE do not support GPUVM, DCE SG support */
600 case CHIP_STONEY: /* UVD does not support GPUVM, DCE SG support */
601 adev->gmc.gart_size = 1024ULL << 20;
602 break;
603 }
604 } else {
605 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
606 }
607
608 adev->gmc.gart_size += adev->pm.smu_prv_buffer_size;
609 gmc_v8_0_vram_gtt_location(adev, mc: &adev->gmc);
610
611 return 0;
612}
613
614/**
615 * gmc_v8_0_flush_gpu_tlb_pasid - tlb flush via pasid
616 *
617 * @adev: amdgpu_device pointer
618 * @pasid: pasid to be flush
619 * @flush_type: type of flush
620 * @all_hub: flush all hubs
621 * @inst: is used to select which instance of KIQ to use for the invalidation
622 *
623 * Flush the TLB for the requested pasid.
624 */
625static void gmc_v8_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
626 uint16_t pasid, uint32_t flush_type,
627 bool all_hub, uint32_t inst)
628{
629 u32 mask = 0x0;
630 int vmid;
631
632 for (vmid = 1; vmid < 16; vmid++) {
633 u32 tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
634
635 if ((tmp & ATC_VMID0_PASID_MAPPING__VALID_MASK) &&
636 (tmp & ATC_VMID0_PASID_MAPPING__PASID_MASK) == pasid)
637 mask |= 1 << vmid;
638 }
639
640 WREG32(mmVM_INVALIDATE_REQUEST, mask);
641 RREG32(mmVM_INVALIDATE_RESPONSE);
642}
643
644/*
645 * GART
646 * VMID 0 is the physical GPU addresses as used by the kernel.
647 * VMIDs 1-15 are used for userspace clients and are handled
648 * by the amdgpu vm/hsa code.
649 */
650
651/**
652 * gmc_v8_0_flush_gpu_tlb - gart tlb flush callback
653 *
654 * @adev: amdgpu_device pointer
655 * @vmid: vm instance to flush
656 * @vmhub: which hub to flush
657 * @flush_type: type of flush
658 *
659 * Flush the TLB for the requested page table (VI).
660 */
661static void gmc_v8_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
662 uint32_t vmhub, uint32_t flush_type)
663{
664 /* bits 0-15 are the VM contexts0-15 */
665 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
666}
667
668static uint64_t gmc_v8_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
669 unsigned int vmid, uint64_t pd_addr)
670{
671 uint32_t reg;
672
673 if (vmid < 8)
674 reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid;
675 else
676 reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8;
677 amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12);
678
679 /* bits 0-15 are the VM contexts0-15 */
680 amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid);
681
682 return pd_addr;
683}
684
685static void gmc_v8_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int vmid,
686 unsigned int pasid)
687{
688 amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid);
689}
690
691/*
692 * PTE format on VI:
693 * 63:40 reserved
694 * 39:12 4k physical page base address
695 * 11:7 fragment
696 * 6 write
697 * 5 read
698 * 4 exe
699 * 3 reserved
700 * 2 snooped
701 * 1 system
702 * 0 valid
703 *
704 * PDE format on VI:
705 * 63:59 block fragment size
706 * 58:40 reserved
707 * 39:1 physical base address of PTE
708 * bits 5:1 must be 0.
709 * 0 valid
710 */
711
712static void gmc_v8_0_get_vm_pde(struct amdgpu_device *adev, int level,
713 uint64_t *addr, uint64_t *flags)
714{
715 BUG_ON(*addr & 0xFFFFFF0000000FFFULL);
716}
717
718static void gmc_v8_0_get_vm_pte(struct amdgpu_device *adev,
719 struct amdgpu_vm *vm,
720 struct amdgpu_bo *bo,
721 uint32_t vm_flags,
722 uint64_t *flags)
723{
724 if (vm_flags & AMDGPU_VM_PAGE_EXECUTABLE)
725 *flags |= AMDGPU_PTE_EXECUTABLE;
726 else
727 *flags &= ~AMDGPU_PTE_EXECUTABLE;
728 *flags &= ~AMDGPU_PTE_PRT;
729}
730
731/**
732 * gmc_v8_0_set_fault_enable_default - update VM fault handling
733 *
734 * @adev: amdgpu_device pointer
735 * @value: true redirects VM faults to the default page
736 */
737static void gmc_v8_0_set_fault_enable_default(struct amdgpu_device *adev,
738 bool value)
739{
740 u32 tmp;
741
742 tmp = RREG32(mmVM_CONTEXT1_CNTL);
743 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
744 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
745 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
746 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
747 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
748 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
749 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
750 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
751 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
752 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
753 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
754 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
755 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
756 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
757 WREG32(mmVM_CONTEXT1_CNTL, tmp);
758}
759
760/**
761 * gmc_v8_0_set_prt() - set PRT VM fault
762 *
763 * @adev: amdgpu_device pointer
764 * @enable: enable/disable VM fault handling for PRT
765 */
766static void gmc_v8_0_set_prt(struct amdgpu_device *adev, bool enable)
767{
768 u32 tmp;
769
770 if (enable && !adev->gmc.prt_warning) {
771 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n");
772 adev->gmc.prt_warning = true;
773 }
774
775 tmp = RREG32(mmVM_PRT_CNTL);
776 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
777 CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
778 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
779 CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
780 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
781 TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS, enable);
782 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
783 TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS, enable);
784 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
785 L2_CACHE_STORE_INVALID_ENTRIES, enable);
786 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
787 L1_TLB_STORE_INVALID_ENTRIES, enable);
788 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
789 MASK_PDE0_FAULT, enable);
790 WREG32(mmVM_PRT_CNTL, tmp);
791
792 if (enable) {
793 uint32_t low = AMDGPU_VA_RESERVED_BOTTOM >>
794 AMDGPU_GPU_PAGE_SHIFT;
795 uint32_t high = adev->vm_manager.max_pfn -
796 (AMDGPU_VA_RESERVED_TOP >> AMDGPU_GPU_PAGE_SHIFT);
797
798 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
799 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
800 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
801 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
802 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
803 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
804 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
805 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
806 } else {
807 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);
808 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);
809 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);
810 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);
811 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
812 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
813 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
814 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
815 }
816}
817
818/**
819 * gmc_v8_0_gart_enable - gart enable
820 *
821 * @adev: amdgpu_device pointer
822 *
823 * This sets up the TLBs, programs the page tables for VMID0,
824 * sets up the hw for VMIDs 1-15 which are allocated on
825 * demand, and sets up the global locations for the LDS, GDS,
826 * and GPUVM for FSA64 clients (VI).
827 * Returns 0 for success, errors for failure.
828 */
829static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
830{
831 uint64_t table_addr;
832 u32 tmp, field;
833 int i;
834
835 if (adev->gart.bo == NULL) {
836 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
837 return -EINVAL;
838 }
839 amdgpu_gtt_mgr_recover(mgr: &adev->mman.gtt_mgr);
840 table_addr = amdgpu_bo_gpu_offset(bo: adev->gart.bo);
841
842 /* Setup TLB control */
843 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
844 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
845 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 1);
846 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
847 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 1);
848 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
849 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
850 /* Setup L2 cache */
851 tmp = RREG32(mmVM_L2_CNTL);
852 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
853 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
854 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE, 1);
855 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE, 1);
856 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, EFFECTIVE_L2_QUEUE_SIZE, 7);
857 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
858 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
859 WREG32(mmVM_L2_CNTL, tmp);
860 tmp = RREG32(mmVM_L2_CNTL2);
861 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
862 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
863 WREG32(mmVM_L2_CNTL2, tmp);
864
865 field = adev->vm_manager.fragment_size;
866 tmp = RREG32(mmVM_L2_CNTL3);
867 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY, 1);
868 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field);
869 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, field);
870 WREG32(mmVM_L2_CNTL3, tmp);
871 /* XXX: set to enable PTE/PDE in system memory */
872 tmp = RREG32(mmVM_L2_CNTL4);
873 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL, 0);
874 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED, 0);
875 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP, 0);
876 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL, 0);
877 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED, 0);
878 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP, 0);
879 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL, 0);
880 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED, 0);
881 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP, 0);
882 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL, 0);
883 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED, 0);
884 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP, 0);
885 WREG32(mmVM_L2_CNTL4, tmp);
886 /* setup context0 */
887 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12);
888 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12);
889 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12);
890 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
891 (u32)(adev->dummy_page_addr >> 12));
892 WREG32(mmVM_CONTEXT0_CNTL2, 0);
893 tmp = RREG32(mmVM_CONTEXT0_CNTL);
894 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
895 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
896 tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
897 WREG32(mmVM_CONTEXT0_CNTL, tmp);
898
899 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR, 0);
900 WREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR, 0);
901 WREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET, 0);
902
903 /* empty context1-15 */
904 /* FIXME start with 4G, once using 2 level pt switch to full
905 * vm size space
906 */
907 /* set vm size, must be a multiple of 4 */
908 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
909 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
910 for (i = 1; i < AMDGPU_NUM_VMID; i++) {
911 if (i < 8)
912 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
913 table_addr >> 12);
914 else
915 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
916 table_addr >> 12);
917 }
918
919 /* enable context1-15 */
920 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
921 (u32)(adev->dummy_page_addr >> 12));
922 WREG32(mmVM_CONTEXT1_CNTL2, 4);
923 tmp = RREG32(mmVM_CONTEXT1_CNTL);
924 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
925 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
926 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
927 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
928 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
929 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
930 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
931 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
932 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
933 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
934 adev->vm_manager.block_size - 9);
935 WREG32(mmVM_CONTEXT1_CNTL, tmp);
936 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
937 gmc_v8_0_set_fault_enable_default(adev, value: false);
938 else
939 gmc_v8_0_set_fault_enable_default(adev, value: true);
940
941 gmc_v8_0_flush_gpu_tlb(adev, vmid: 0, vmhub: 0, flush_type: 0);
942 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
943 (unsigned int)(adev->gmc.gart_size >> 20),
944 (unsigned long long)table_addr);
945 return 0;
946}
947
948static int gmc_v8_0_gart_init(struct amdgpu_device *adev)
949{
950 int r;
951
952 if (adev->gart.bo) {
953 WARN(1, "R600 PCIE GART already initialized\n");
954 return 0;
955 }
956 /* Initialize common gart structure */
957 r = amdgpu_gart_init(adev);
958 if (r)
959 return r;
960 adev->gart.table_size = adev->gart.num_gpu_pages * 8;
961 adev->gart.gart_pte_flags = AMDGPU_PTE_EXECUTABLE;
962 return amdgpu_gart_table_vram_alloc(adev);
963}
964
965/**
966 * gmc_v8_0_gart_disable - gart disable
967 *
968 * @adev: amdgpu_device pointer
969 *
970 * This disables all VM page table (VI).
971 */
972static void gmc_v8_0_gart_disable(struct amdgpu_device *adev)
973{
974 u32 tmp;
975
976 /* Disable all tables */
977 WREG32(mmVM_CONTEXT0_CNTL, 0);
978 WREG32(mmVM_CONTEXT1_CNTL, 0);
979 /* Setup TLB control */
980 tmp = RREG32(mmMC_VM_MX_L1_TLB_CNTL);
981 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
982 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING, 0);
983 tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_ADVANCED_DRIVER_MODEL, 0);
984 WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
985 /* Setup L2 cache */
986 tmp = RREG32(mmVM_L2_CNTL);
987 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
988 WREG32(mmVM_L2_CNTL, tmp);
989 WREG32(mmVM_L2_CNTL2, 0);
990}
991
992/**
993 * gmc_v8_0_vm_decode_fault - print human readable fault info
994 *
995 * @adev: amdgpu_device pointer
996 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
997 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
998 * @mc_client: VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT register value
999 * @pasid: debug logging only - no functional use
1000 *
1001 * Print human readable fault information (VI).
1002 */
1003static void gmc_v8_0_vm_decode_fault(struct amdgpu_device *adev, u32 status,
1004 u32 addr, u32 mc_client, unsigned int pasid)
1005{
1006 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
1007 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1008 PROTECTIONS);
1009 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
1010 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
1011 u32 mc_id;
1012
1013 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1014 MEMORY_CLIENT_ID);
1015
1016 dev_err(adev->dev, "VM fault (0x%02x, vmid %d, pasid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
1017 protections, vmid, pasid, addr,
1018 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1019 MEMORY_CLIENT_RW) ?
1020 "write" : "read", block, mc_client, mc_id);
1021}
1022
1023static int gmc_v8_0_convert_vram_type(int mc_seq_vram_type)
1024{
1025 switch (mc_seq_vram_type) {
1026 case MC_SEQ_MISC0__MT__GDDR1:
1027 return AMDGPU_VRAM_TYPE_GDDR1;
1028 case MC_SEQ_MISC0__MT__DDR2:
1029 return AMDGPU_VRAM_TYPE_DDR2;
1030 case MC_SEQ_MISC0__MT__GDDR3:
1031 return AMDGPU_VRAM_TYPE_GDDR3;
1032 case MC_SEQ_MISC0__MT__GDDR4:
1033 return AMDGPU_VRAM_TYPE_GDDR4;
1034 case MC_SEQ_MISC0__MT__GDDR5:
1035 return AMDGPU_VRAM_TYPE_GDDR5;
1036 case MC_SEQ_MISC0__MT__HBM:
1037 return AMDGPU_VRAM_TYPE_HBM;
1038 case MC_SEQ_MISC0__MT__DDR3:
1039 return AMDGPU_VRAM_TYPE_DDR3;
1040 default:
1041 return AMDGPU_VRAM_TYPE_UNKNOWN;
1042 }
1043}
1044
1045static int gmc_v8_0_early_init(struct amdgpu_ip_block *ip_block)
1046{
1047 struct amdgpu_device *adev = ip_block->adev;
1048
1049 gmc_v8_0_set_gmc_funcs(adev);
1050 gmc_v8_0_set_irq_funcs(adev);
1051
1052 adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
1053 adev->gmc.shared_aperture_end =
1054 adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
1055 adev->gmc.private_aperture_start =
1056 adev->gmc.shared_aperture_end + 1;
1057 adev->gmc.private_aperture_end =
1058 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
1059 adev->gmc.noretry_flags = AMDGPU_VM_NORETRY_FLAGS_TF;
1060
1061 return 0;
1062}
1063
1064static int gmc_v8_0_late_init(struct amdgpu_ip_block *ip_block)
1065{
1066 struct amdgpu_device *adev = ip_block->adev;
1067
1068 if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
1069 return amdgpu_irq_get(adev, src: &adev->gmc.vm_fault, type: 0);
1070 else
1071 return 0;
1072}
1073
1074static unsigned int gmc_v8_0_get_vbios_fb_size(struct amdgpu_device *adev)
1075{
1076 u32 d1vga_control = RREG32(mmD1VGA_CONTROL);
1077 unsigned int size;
1078
1079 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
1080 size = AMDGPU_VBIOS_VGA_ALLOCATION;
1081 } else {
1082 u32 viewport = RREG32(mmVIEWPORT_SIZE);
1083
1084 size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
1085 REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) *
1086 4);
1087 }
1088
1089 return size;
1090}
1091
1092#define mmMC_SEQ_MISC0_FIJI 0xA71
1093
1094static int gmc_v8_0_sw_init(struct amdgpu_ip_block *ip_block)
1095{
1096 int r;
1097 struct amdgpu_device *adev = ip_block->adev;
1098
1099 set_bit(AMDGPU_GFXHUB(0), addr: adev->vmhubs_mask);
1100
1101 if (adev->flags & AMD_IS_APU) {
1102 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
1103 } else {
1104 u32 tmp;
1105
1106 if ((adev->asic_type == CHIP_FIJI) ||
1107 (adev->asic_type == CHIP_VEGAM))
1108 tmp = RREG32(mmMC_SEQ_MISC0_FIJI);
1109 else
1110 tmp = RREG32(mmMC_SEQ_MISC0);
1111 tmp &= MC_SEQ_MISC0__MT__MASK;
1112 adev->gmc.vram_type = gmc_v8_0_convert_vram_type(mc_seq_vram_type: tmp);
1113 }
1114
1115 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT, source: &adev->gmc.vm_fault);
1116 if (r)
1117 return r;
1118
1119 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT, source: &adev->gmc.vm_fault);
1120 if (r)
1121 return r;
1122
1123 /* Adjust VM size here.
1124 * Currently set to 4GB ((1 << 20) 4k pages).
1125 * Max GPUVM size for cayman and SI is 40 bits.
1126 */
1127 amdgpu_vm_adjust_size(adev, min_vm_size: 64, fragment_size_default: 9, max_level: 1, max_bits: 40);
1128
1129 /* Set the internal MC address mask
1130 * This is the max address of the GPU's
1131 * internal address space.
1132 */
1133 adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
1134
1135 r = dma_set_mask_and_coherent(dev: adev->dev, DMA_BIT_MASK(40));
1136 if (r) {
1137 pr_warn("No suitable DMA available\n");
1138 return r;
1139 }
1140 adev->need_swiotlb = drm_need_swiotlb(dma_bits: 40);
1141
1142 r = gmc_v8_0_init_microcode(adev);
1143 if (r) {
1144 DRM_ERROR("Failed to load mc firmware!\n");
1145 return r;
1146 }
1147
1148 r = gmc_v8_0_mc_init(adev);
1149 if (r)
1150 return r;
1151
1152 amdgpu_gmc_get_vbios_allocations(adev);
1153
1154 /* Memory manager */
1155 r = amdgpu_bo_init(adev);
1156 if (r)
1157 return r;
1158
1159 r = gmc_v8_0_gart_init(adev);
1160 if (r)
1161 return r;
1162
1163 /*
1164 * number of VMs
1165 * VMID 0 is reserved for System
1166 * amdgpu graphics/compute will use VMIDs 1-7
1167 * amdkfd will use VMIDs 8-15
1168 */
1169 adev->vm_manager.first_kfd_vmid = 8;
1170 amdgpu_vm_manager_init(adev);
1171
1172 /* base offset of vram pages */
1173 if (adev->flags & AMD_IS_APU) {
1174 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
1175
1176 tmp <<= 22;
1177 adev->vm_manager.vram_base_offset = tmp;
1178 } else {
1179 adev->vm_manager.vram_base_offset = 0;
1180 }
1181
1182 adev->gmc.vm_fault_info = kmalloc(sizeof(struct kfd_vm_fault_info),
1183 GFP_KERNEL);
1184 if (!adev->gmc.vm_fault_info)
1185 return -ENOMEM;
1186 atomic_set_release(v: &adev->gmc.vm_fault_info_updated, i: 0);
1187
1188 return 0;
1189}
1190
1191static int gmc_v8_0_sw_fini(struct amdgpu_ip_block *ip_block)
1192{
1193 struct amdgpu_device *adev = ip_block->adev;
1194
1195 amdgpu_gem_force_release(adev);
1196 amdgpu_vm_manager_fini(adev);
1197 kfree(objp: adev->gmc.vm_fault_info);
1198 amdgpu_gart_table_vram_free(adev);
1199 amdgpu_bo_fini(adev);
1200 amdgpu_ucode_release(fw: &adev->gmc.fw);
1201
1202 return 0;
1203}
1204
1205static int gmc_v8_0_hw_init(struct amdgpu_ip_block *ip_block)
1206{
1207 int r;
1208 struct amdgpu_device *adev = ip_block->adev;
1209
1210 gmc_v8_0_init_golden_registers(adev);
1211
1212 gmc_v8_0_mc_program(adev);
1213
1214 if (adev->asic_type == CHIP_TONGA) {
1215 r = gmc_v8_0_tonga_mc_load_microcode(adev);
1216 if (r) {
1217 DRM_ERROR("Failed to load MC firmware!\n");
1218 return r;
1219 }
1220 } else if (adev->asic_type == CHIP_POLARIS11 ||
1221 adev->asic_type == CHIP_POLARIS10 ||
1222 adev->asic_type == CHIP_POLARIS12) {
1223 r = gmc_v8_0_polaris_mc_load_microcode(adev);
1224 if (r) {
1225 DRM_ERROR("Failed to load MC firmware!\n");
1226 return r;
1227 }
1228 }
1229
1230 r = gmc_v8_0_gart_enable(adev);
1231 if (r)
1232 return r;
1233
1234 if (amdgpu_emu_mode == 1)
1235 return amdgpu_gmc_vram_checking(adev);
1236
1237 return 0;
1238}
1239
1240static int gmc_v8_0_hw_fini(struct amdgpu_ip_block *ip_block)
1241{
1242 struct amdgpu_device *adev = ip_block->adev;
1243
1244 amdgpu_irq_put(adev, src: &adev->gmc.vm_fault, type: 0);
1245 gmc_v8_0_gart_disable(adev);
1246
1247 return 0;
1248}
1249
1250static int gmc_v8_0_suspend(struct amdgpu_ip_block *ip_block)
1251{
1252 gmc_v8_0_hw_fini(ip_block);
1253
1254 return 0;
1255}
1256
1257static int gmc_v8_0_resume(struct amdgpu_ip_block *ip_block)
1258{
1259 int r;
1260
1261 r = gmc_v8_0_hw_init(ip_block);
1262 if (r)
1263 return r;
1264
1265 amdgpu_vmid_reset_all(adev: ip_block->adev);
1266
1267 return 0;
1268}
1269
1270static bool gmc_v8_0_is_idle(struct amdgpu_ip_block *ip_block)
1271{
1272 struct amdgpu_device *adev = ip_block->adev;
1273 u32 tmp = RREG32(mmSRBM_STATUS);
1274
1275 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1276 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
1277 return false;
1278
1279 return true;
1280}
1281
1282static int gmc_v8_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
1283{
1284 unsigned int i;
1285 u32 tmp;
1286 struct amdgpu_device *adev = ip_block->adev;
1287
1288 for (i = 0; i < adev->usec_timeout; i++) {
1289 /* read MC_STATUS */
1290 tmp = RREG32(mmSRBM_STATUS) & (SRBM_STATUS__MCB_BUSY_MASK |
1291 SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1292 SRBM_STATUS__MCC_BUSY_MASK |
1293 SRBM_STATUS__MCD_BUSY_MASK |
1294 SRBM_STATUS__VMC_BUSY_MASK |
1295 SRBM_STATUS__VMC1_BUSY_MASK);
1296 if (!tmp)
1297 return 0;
1298 udelay(usec: 1);
1299 }
1300 return -ETIMEDOUT;
1301
1302}
1303
1304static bool gmc_v8_0_check_soft_reset(struct amdgpu_ip_block *ip_block)
1305{
1306 u32 srbm_soft_reset = 0;
1307 struct amdgpu_device *adev = ip_block->adev;
1308 u32 tmp = RREG32(mmSRBM_STATUS);
1309
1310 if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
1311 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1312 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
1313
1314 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1315 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
1316 if (!(adev->flags & AMD_IS_APU))
1317 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1318 SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1319 }
1320
1321 if (srbm_soft_reset) {
1322 adev->gmc.srbm_soft_reset = srbm_soft_reset;
1323 return true;
1324 }
1325
1326 adev->gmc.srbm_soft_reset = 0;
1327
1328 return false;
1329}
1330
1331static int gmc_v8_0_pre_soft_reset(struct amdgpu_ip_block *ip_block)
1332{
1333 struct amdgpu_device *adev = ip_block->adev;
1334
1335 if (!adev->gmc.srbm_soft_reset)
1336 return 0;
1337
1338 gmc_v8_0_mc_stop(adev);
1339 if (gmc_v8_0_wait_for_idle(ip_block))
1340 dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
1341
1342 return 0;
1343}
1344
1345static int gmc_v8_0_soft_reset(struct amdgpu_ip_block *ip_block)
1346{
1347 struct amdgpu_device *adev = ip_block->adev;
1348 u32 srbm_soft_reset;
1349
1350 if (!adev->gmc.srbm_soft_reset)
1351 return 0;
1352 srbm_soft_reset = adev->gmc.srbm_soft_reset;
1353
1354 if (srbm_soft_reset) {
1355 u32 tmp;
1356
1357 tmp = RREG32(mmSRBM_SOFT_RESET);
1358 tmp |= srbm_soft_reset;
1359 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1360 WREG32(mmSRBM_SOFT_RESET, tmp);
1361 tmp = RREG32(mmSRBM_SOFT_RESET);
1362
1363 udelay(usec: 50);
1364
1365 tmp &= ~srbm_soft_reset;
1366 WREG32(mmSRBM_SOFT_RESET, tmp);
1367 tmp = RREG32(mmSRBM_SOFT_RESET);
1368
1369 /* Wait a little for things to settle down */
1370 udelay(usec: 50);
1371 }
1372
1373 return 0;
1374}
1375
1376static int gmc_v8_0_post_soft_reset(struct amdgpu_ip_block *ip_block)
1377{
1378 struct amdgpu_device *adev = ip_block->adev;
1379
1380 if (!adev->gmc.srbm_soft_reset)
1381 return 0;
1382
1383 gmc_v8_0_mc_resume(adev);
1384 return 0;
1385}
1386
1387static int gmc_v8_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1388 struct amdgpu_irq_src *src,
1389 unsigned int type,
1390 enum amdgpu_interrupt_state state)
1391{
1392 u32 tmp;
1393 u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1394 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1395 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1396 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1397 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1398 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1399 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1400
1401 switch (state) {
1402 case AMDGPU_IRQ_STATE_DISABLE:
1403 /* system context */
1404 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1405 tmp &= ~bits;
1406 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1407 /* VMs */
1408 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1409 tmp &= ~bits;
1410 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1411 break;
1412 case AMDGPU_IRQ_STATE_ENABLE:
1413 /* system context */
1414 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1415 tmp |= bits;
1416 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1417 /* VMs */
1418 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1419 tmp |= bits;
1420 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1421 break;
1422 default:
1423 break;
1424 }
1425
1426 return 0;
1427}
1428
1429static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev,
1430 struct amdgpu_irq_src *source,
1431 struct amdgpu_iv_entry *entry)
1432{
1433 u32 addr, status, mc_client, vmid;
1434
1435 if (amdgpu_sriov_vf(adev)) {
1436 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1437 entry->src_id, entry->src_data[0]);
1438 dev_err(adev->dev, " Can't decode VM fault info here on SRIOV VF\n");
1439 return 0;
1440 }
1441
1442 /* Delegate to the soft IRQ handler ring */
1443 if (adev->irq.ih_soft.enabled && entry->ih != &adev->irq.ih_soft) {
1444 amdgpu_irq_delegate(adev, entry, num_dw: 4);
1445 return 1;
1446 }
1447
1448 addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1449 status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1450 mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
1451 /* reset addr and status */
1452 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1453
1454 if (!addr && !status)
1455 return 0;
1456
1457 amdgpu_vm_update_fault_cache(adev, pasid: entry->pasid,
1458 addr: ((u64)addr) << AMDGPU_GPU_PAGE_SHIFT, status, AMDGPU_GFXHUB(0));
1459
1460 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1461 gmc_v8_0_set_fault_enable_default(adev, value: false);
1462
1463 if (printk_ratelimit()) {
1464 struct amdgpu_task_info *task_info;
1465
1466 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1467 entry->src_id, entry->src_data[0]);
1468
1469 task_info = amdgpu_vm_get_task_info_pasid(adev, pasid: entry->pasid);
1470 if (task_info) {
1471 amdgpu_vm_print_task_info(adev, task_info);
1472 amdgpu_vm_put_task_info(task_info);
1473 }
1474
1475 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1476 addr);
1477 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1478 status);
1479
1480 gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client,
1481 pasid: entry->pasid);
1482 }
1483
1484 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1485 VMID);
1486 if (amdgpu_amdkfd_is_kfd_vmid(adev, vmid)
1487 && !atomic_read_acquire(v: &adev->gmc.vm_fault_info_updated)) {
1488 struct kfd_vm_fault_info *info = adev->gmc.vm_fault_info;
1489 u32 protections = REG_GET_FIELD(status,
1490 VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1491 PROTECTIONS);
1492
1493 info->vmid = vmid;
1494 info->mc_id = REG_GET_FIELD(status,
1495 VM_CONTEXT1_PROTECTION_FAULT_STATUS,
1496 MEMORY_CLIENT_ID);
1497 info->status = status;
1498 info->page_addr = addr;
1499 info->prot_valid = protections & 0x7 ? true : false;
1500 info->prot_read = protections & 0x8 ? true : false;
1501 info->prot_write = protections & 0x10 ? true : false;
1502 info->prot_exec = protections & 0x20 ? true : false;
1503 atomic_set_release(v: &adev->gmc.vm_fault_info_updated, i: 1);
1504 }
1505
1506 return 0;
1507}
1508
1509static void fiji_update_mc_medium_grain_clock_gating(struct amdgpu_device *adev,
1510 bool enable)
1511{
1512 uint32_t data;
1513
1514 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {
1515 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1516 data |= MC_HUB_MISC_HUB_CG__ENABLE_MASK;
1517 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1518
1519 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1520 data |= MC_HUB_MISC_SIP_CG__ENABLE_MASK;
1521 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1522
1523 data = RREG32(mmMC_HUB_MISC_VM_CG);
1524 data |= MC_HUB_MISC_VM_CG__ENABLE_MASK;
1525 WREG32(mmMC_HUB_MISC_VM_CG, data);
1526
1527 data = RREG32(mmMC_XPB_CLK_GAT);
1528 data |= MC_XPB_CLK_GAT__ENABLE_MASK;
1529 WREG32(mmMC_XPB_CLK_GAT, data);
1530
1531 data = RREG32(mmATC_MISC_CG);
1532 data |= ATC_MISC_CG__ENABLE_MASK;
1533 WREG32(mmATC_MISC_CG, data);
1534
1535 data = RREG32(mmMC_CITF_MISC_WR_CG);
1536 data |= MC_CITF_MISC_WR_CG__ENABLE_MASK;
1537 WREG32(mmMC_CITF_MISC_WR_CG, data);
1538
1539 data = RREG32(mmMC_CITF_MISC_RD_CG);
1540 data |= MC_CITF_MISC_RD_CG__ENABLE_MASK;
1541 WREG32(mmMC_CITF_MISC_RD_CG, data);
1542
1543 data = RREG32(mmMC_CITF_MISC_VM_CG);
1544 data |= MC_CITF_MISC_VM_CG__ENABLE_MASK;
1545 WREG32(mmMC_CITF_MISC_VM_CG, data);
1546
1547 data = RREG32(mmVM_L2_CG);
1548 data |= VM_L2_CG__ENABLE_MASK;
1549 WREG32(mmVM_L2_CG, data);
1550 } else {
1551 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1552 data &= ~MC_HUB_MISC_HUB_CG__ENABLE_MASK;
1553 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1554
1555 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1556 data &= ~MC_HUB_MISC_SIP_CG__ENABLE_MASK;
1557 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1558
1559 data = RREG32(mmMC_HUB_MISC_VM_CG);
1560 data &= ~MC_HUB_MISC_VM_CG__ENABLE_MASK;
1561 WREG32(mmMC_HUB_MISC_VM_CG, data);
1562
1563 data = RREG32(mmMC_XPB_CLK_GAT);
1564 data &= ~MC_XPB_CLK_GAT__ENABLE_MASK;
1565 WREG32(mmMC_XPB_CLK_GAT, data);
1566
1567 data = RREG32(mmATC_MISC_CG);
1568 data &= ~ATC_MISC_CG__ENABLE_MASK;
1569 WREG32(mmATC_MISC_CG, data);
1570
1571 data = RREG32(mmMC_CITF_MISC_WR_CG);
1572 data &= ~MC_CITF_MISC_WR_CG__ENABLE_MASK;
1573 WREG32(mmMC_CITF_MISC_WR_CG, data);
1574
1575 data = RREG32(mmMC_CITF_MISC_RD_CG);
1576 data &= ~MC_CITF_MISC_RD_CG__ENABLE_MASK;
1577 WREG32(mmMC_CITF_MISC_RD_CG, data);
1578
1579 data = RREG32(mmMC_CITF_MISC_VM_CG);
1580 data &= ~MC_CITF_MISC_VM_CG__ENABLE_MASK;
1581 WREG32(mmMC_CITF_MISC_VM_CG, data);
1582
1583 data = RREG32(mmVM_L2_CG);
1584 data &= ~VM_L2_CG__ENABLE_MASK;
1585 WREG32(mmVM_L2_CG, data);
1586 }
1587}
1588
1589static void fiji_update_mc_light_sleep(struct amdgpu_device *adev,
1590 bool enable)
1591{
1592 uint32_t data;
1593
1594 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) {
1595 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1596 data |= MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK;
1597 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1598
1599 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1600 data |= MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK;
1601 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1602
1603 data = RREG32(mmMC_HUB_MISC_VM_CG);
1604 data |= MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1605 WREG32(mmMC_HUB_MISC_VM_CG, data);
1606
1607 data = RREG32(mmMC_XPB_CLK_GAT);
1608 data |= MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK;
1609 WREG32(mmMC_XPB_CLK_GAT, data);
1610
1611 data = RREG32(mmATC_MISC_CG);
1612 data |= ATC_MISC_CG__MEM_LS_ENABLE_MASK;
1613 WREG32(mmATC_MISC_CG, data);
1614
1615 data = RREG32(mmMC_CITF_MISC_WR_CG);
1616 data |= MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK;
1617 WREG32(mmMC_CITF_MISC_WR_CG, data);
1618
1619 data = RREG32(mmMC_CITF_MISC_RD_CG);
1620 data |= MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK;
1621 WREG32(mmMC_CITF_MISC_RD_CG, data);
1622
1623 data = RREG32(mmMC_CITF_MISC_VM_CG);
1624 data |= MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1625 WREG32(mmMC_CITF_MISC_VM_CG, data);
1626
1627 data = RREG32(mmVM_L2_CG);
1628 data |= VM_L2_CG__MEM_LS_ENABLE_MASK;
1629 WREG32(mmVM_L2_CG, data);
1630 } else {
1631 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1632 data &= ~MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK;
1633 WREG32(mmMC_HUB_MISC_HUB_CG, data);
1634
1635 data = RREG32(mmMC_HUB_MISC_SIP_CG);
1636 data &= ~MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK;
1637 WREG32(mmMC_HUB_MISC_SIP_CG, data);
1638
1639 data = RREG32(mmMC_HUB_MISC_VM_CG);
1640 data &= ~MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1641 WREG32(mmMC_HUB_MISC_VM_CG, data);
1642
1643 data = RREG32(mmMC_XPB_CLK_GAT);
1644 data &= ~MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK;
1645 WREG32(mmMC_XPB_CLK_GAT, data);
1646
1647 data = RREG32(mmATC_MISC_CG);
1648 data &= ~ATC_MISC_CG__MEM_LS_ENABLE_MASK;
1649 WREG32(mmATC_MISC_CG, data);
1650
1651 data = RREG32(mmMC_CITF_MISC_WR_CG);
1652 data &= ~MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK;
1653 WREG32(mmMC_CITF_MISC_WR_CG, data);
1654
1655 data = RREG32(mmMC_CITF_MISC_RD_CG);
1656 data &= ~MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK;
1657 WREG32(mmMC_CITF_MISC_RD_CG, data);
1658
1659 data = RREG32(mmMC_CITF_MISC_VM_CG);
1660 data &= ~MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK;
1661 WREG32(mmMC_CITF_MISC_VM_CG, data);
1662
1663 data = RREG32(mmVM_L2_CG);
1664 data &= ~VM_L2_CG__MEM_LS_ENABLE_MASK;
1665 WREG32(mmVM_L2_CG, data);
1666 }
1667}
1668
1669static int gmc_v8_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
1670 enum amd_clockgating_state state)
1671{
1672 struct amdgpu_device *adev = ip_block->adev;
1673
1674 if (amdgpu_sriov_vf(adev))
1675 return 0;
1676
1677 switch (adev->asic_type) {
1678 case CHIP_FIJI:
1679 fiji_update_mc_medium_grain_clock_gating(adev,
1680 enable: state == AMD_CG_STATE_GATE);
1681 fiji_update_mc_light_sleep(adev,
1682 enable: state == AMD_CG_STATE_GATE);
1683 break;
1684 default:
1685 break;
1686 }
1687 return 0;
1688}
1689
1690static int gmc_v8_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
1691 enum amd_powergating_state state)
1692{
1693 return 0;
1694}
1695
1696static void gmc_v8_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)
1697{
1698 struct amdgpu_device *adev = ip_block->adev;
1699 int data;
1700
1701 if (amdgpu_sriov_vf(adev))
1702 *flags = 0;
1703
1704 /* AMD_CG_SUPPORT_MC_MGCG */
1705 data = RREG32(mmMC_HUB_MISC_HUB_CG);
1706 if (data & MC_HUB_MISC_HUB_CG__ENABLE_MASK)
1707 *flags |= AMD_CG_SUPPORT_MC_MGCG;
1708
1709 /* AMD_CG_SUPPORT_MC_LS */
1710 if (data & MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK)
1711 *flags |= AMD_CG_SUPPORT_MC_LS;
1712}
1713
1714static const struct amd_ip_funcs gmc_v8_0_ip_funcs = {
1715 .name = "gmc_v8_0",
1716 .early_init = gmc_v8_0_early_init,
1717 .late_init = gmc_v8_0_late_init,
1718 .sw_init = gmc_v8_0_sw_init,
1719 .sw_fini = gmc_v8_0_sw_fini,
1720 .hw_init = gmc_v8_0_hw_init,
1721 .hw_fini = gmc_v8_0_hw_fini,
1722 .suspend = gmc_v8_0_suspend,
1723 .resume = gmc_v8_0_resume,
1724 .is_idle = gmc_v8_0_is_idle,
1725 .wait_for_idle = gmc_v8_0_wait_for_idle,
1726 .check_soft_reset = gmc_v8_0_check_soft_reset,
1727 .pre_soft_reset = gmc_v8_0_pre_soft_reset,
1728 .soft_reset = gmc_v8_0_soft_reset,
1729 .post_soft_reset = gmc_v8_0_post_soft_reset,
1730 .set_clockgating_state = gmc_v8_0_set_clockgating_state,
1731 .set_powergating_state = gmc_v8_0_set_powergating_state,
1732 .get_clockgating_state = gmc_v8_0_get_clockgating_state,
1733};
1734
1735static const struct amdgpu_gmc_funcs gmc_v8_0_gmc_funcs = {
1736 .flush_gpu_tlb = gmc_v8_0_flush_gpu_tlb,
1737 .flush_gpu_tlb_pasid = gmc_v8_0_flush_gpu_tlb_pasid,
1738 .emit_flush_gpu_tlb = gmc_v8_0_emit_flush_gpu_tlb,
1739 .emit_pasid_mapping = gmc_v8_0_emit_pasid_mapping,
1740 .set_prt = gmc_v8_0_set_prt,
1741 .get_vm_pde = gmc_v8_0_get_vm_pde,
1742 .get_vm_pte = gmc_v8_0_get_vm_pte,
1743 .get_vbios_fb_size = gmc_v8_0_get_vbios_fb_size,
1744};
1745
1746static const struct amdgpu_irq_src_funcs gmc_v8_0_irq_funcs = {
1747 .set = gmc_v8_0_vm_fault_interrupt_state,
1748 .process = gmc_v8_0_process_interrupt,
1749};
1750
1751static void gmc_v8_0_set_gmc_funcs(struct amdgpu_device *adev)
1752{
1753 adev->gmc.gmc_funcs = &gmc_v8_0_gmc_funcs;
1754}
1755
1756static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev)
1757{
1758 adev->gmc.vm_fault.num_types = 1;
1759 adev->gmc.vm_fault.funcs = &gmc_v8_0_irq_funcs;
1760}
1761
1762const struct amdgpu_ip_block_version gmc_v8_0_ip_block = {
1763 .type = AMD_IP_BLOCK_TYPE_GMC,
1764 .major = 8,
1765 .minor = 0,
1766 .rev = 0,
1767 .funcs = &gmc_v8_0_ip_funcs,
1768};
1769
1770const struct amdgpu_ip_block_version gmc_v8_1_ip_block = {
1771 .type = AMD_IP_BLOCK_TYPE_GMC,
1772 .major = 8,
1773 .minor = 1,
1774 .rev = 0,
1775 .funcs = &gmc_v8_0_ip_funcs,
1776};
1777
1778const struct amdgpu_ip_block_version gmc_v8_5_ip_block = {
1779 .type = AMD_IP_BLOCK_TYPE_GMC,
1780 .major = 8,
1781 .minor = 5,
1782 .rev = 0,
1783 .funcs = &gmc_v8_0_ip_funcs,
1784};
1785

source code of linux/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c