| 1 | /* |
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| 2 | * Volcanic Islands IV SRC Register documentation |
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| 3 | * |
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| 4 | * Copyright (C) 2015 Advanced Micro Devices, Inc. |
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| 5 | * |
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| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 7 | * copy of this software and associated documentation files (the "Software"), |
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| 8 | * to deal in the Software without restriction, including without limitation |
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| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 11 | * Software is furnished to do so, subject to the following conditions: |
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| 12 | * |
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| 13 | * The above copyright notice and this permission notice shall be included |
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| 14 | * in all copies or substantial portions of the Software. |
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| 15 | * |
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| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
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| 17 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 19 | * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN |
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| 20 | * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
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| 21 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
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| 22 | */ |
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| 23 | |
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| 24 | #ifndef _IVSRCID_VISLANDS30_H_ |
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| 25 | #define _IVSRCID_VISLANDS30_H_ |
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| 26 | |
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| 27 | |
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| 28 | // IV Source IDs |
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| 29 | |
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| 30 | #define VISLANDS30_IV_SRCID_D1_V_UPDATE_INT 7 // 0x07 |
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| 31 | #define VISLANDS30_IV_EXTID_D1_V_UPDATE_INT 0 |
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| 32 | |
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| 33 | #define VISLANDS30_IV_SRCID_D1_GRPH_PFLIP 8 // 0x08 |
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| 34 | #define VISLANDS30_IV_EXTID_D1_GRPH_PFLIP 0 |
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| 35 | |
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| 36 | #define VISLANDS30_IV_SRCID_D2_V_UPDATE_INT 9 // 0x09 |
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| 37 | #define VISLANDS30_IV_EXTID_D2_V_UPDATE_INT 0 |
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| 38 | |
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| 39 | #define VISLANDS30_IV_SRCID_D2_GRPH_PFLIP 10 // 0x0a |
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| 40 | #define VISLANDS30_IV_EXTID_D2_GRPH_PFLIP 0 |
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| 41 | |
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| 42 | #define VISLANDS30_IV_SRCID_D3_V_UPDATE_INT 11 // 0x0b |
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| 43 | #define VISLANDS30_IV_EXTID_D3_V_UPDATE_INT 0 |
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| 44 | |
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| 45 | #define VISLANDS30_IV_SRCID_D3_GRPH_PFLIP 12 // 0x0c |
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| 46 | #define VISLANDS30_IV_EXTID_D3_GRPH_PFLIP 0 |
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| 47 | |
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| 48 | #define VISLANDS30_IV_SRCID_D4_V_UPDATE_INT 13 // 0x0d |
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| 49 | #define VISLANDS30_IV_EXTID_D4_V_UPDATE_INT 0 |
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| 50 | |
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| 51 | #define VISLANDS30_IV_SRCID_D4_GRPH_PFLIP 14 // 0x0e |
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| 52 | #define VISLANDS30_IV_EXTID_D4_GRPH_PFLIP 0 |
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| 53 | |
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| 54 | #define VISLANDS30_IV_SRCID_D5_V_UPDATE_INT 15 // 0x0f |
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| 55 | #define VISLANDS30_IV_EXTID_D5_V_UPDATE_INT 0 |
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| 56 | |
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| 57 | #define VISLANDS30_IV_SRCID_D5_GRPH_PFLIP 16 // 0x10 |
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| 58 | #define VISLANDS30_IV_EXTID_D5_GRPH_PFLIP 0 |
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| 59 | |
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| 60 | #define VISLANDS30_IV_SRCID_D6_V_UPDATE_INT 17 // 0x11 |
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| 61 | #define VISLANDS30_IV_EXTID_D6_V_UPDATE_INT 0 |
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| 62 | |
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| 63 | #define VISLANDS30_IV_SRCID_D6_GRPH_PFLIP 18 // 0x12 |
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| 64 | #define VISLANDS30_IV_EXTID_D6_GRPH_PFLIP 0 |
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| 65 | |
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| 66 | #define VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0 19 // 0x13 |
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| 67 | #define VISLANDS30_IV_EXTID_D1_VERTICAL_INTERRUPT0 7 |
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| 68 | |
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| 69 | #define VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT1 19 // 0x13 |
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| 70 | #define VISLANDS30_IV_EXTID_D1_VERTICAL_INTERRUPT1 8 |
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| 71 | |
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| 72 | #define VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT2 19 // 0x13 |
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| 73 | #define VISLANDS30_IV_EXTID_D1_VERTICAL_INTERRUPT2 9 |
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| 74 | |
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| 75 | #define VISLANDS30_IV_SRCID_D1_EXT_TIMING_SYNC_LOSS 19 // 0x13 |
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| 76 | #define VISLANDS30_IV_EXTID_D1_EXT_TIMING_SYNC_LOSS 10 |
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| 77 | |
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| 78 | #define VISLANDS30_IV_SRCID_D1_EXT_TIMING_SYNC 19 // 0x13 |
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| 79 | #define VISLANDS30_IV_EXTID_D1_EXT_TIMING_SYNC 11 |
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| 80 | |
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| 81 | #define VISLANDS30_IV_SRCID_D1_EXT_TIMING_SIGNAL 19 // 0x13 |
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| 82 | #define VISLANDS30_IV_EXTID_D1_EXT_TIMING_SIGNAL 12 |
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| 83 | |
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| 84 | #define VISLANDS30_IV_SRCID_D2_VERTICAL_INTERRUPT0 20 // 0x14 |
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| 85 | #define VISLANDS30_IV_EXTID_D2_VERTICAL_INTERRUPT0 7 |
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| 86 | |
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| 87 | #define VISLANDS30_IV_SRCID_D2_VERTICAL_INTERRUPT1 20 // 0x14 |
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| 88 | #define VISLANDS30_IV_EXTID_D2_VERTICAL_INTERRUPT1 8 |
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| 89 | |
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| 90 | #define VISLANDS30_IV_SRCID_D2_VERTICAL_INTERRUPT2 20 // 0x14 |
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| 91 | #define VISLANDS30_IV_EXTID_D2_VERTICAL_INTERRUPT2 9 |
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| 92 | |
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| 93 | #define VISLANDS30_IV_SRCID_D2_EXT_TIMING_SYNC_LOSS 20 // 0x14 |
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| 94 | #define VISLANDS30_IV_EXTID_D2_EXT_TIMING_SYNC_LOSS 10 |
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| 95 | |
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| 96 | #define VISLANDS30_IV_SRCID_D2_EXT_TIMING_SYNC 20 // 0x14 |
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| 97 | #define VISLANDS30_IV_EXTID_D2_EXT_TIMING_SYNC 11 |
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| 98 | |
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| 99 | #define VISLANDS30_IV_SRCID_D2_EXT_TIMING_SIGNAL 20 // 0x14 |
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| 100 | #define VISLANDS30_IV_EXTID_D2_EXT_TIMING_SIGNAL 12 |
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| 101 | |
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| 102 | #define VISLANDS30_IV_SRCID_D3_VERTICAL_INTERRUPT0 21 // 0x15 |
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| 103 | #define VISLANDS30_IV_EXTID_D3_VERTICAL_INTERRUPT0 7 |
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| 104 | |
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| 105 | #define VISLANDS30_IV_SRCID_D3_VERTICAL_INTERRUPT1 21 // 0x15 |
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| 106 | #define VISLANDS30_IV_EXTID_D3_VERTICAL_INTERRUPT1 8 |
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| 107 | |
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| 108 | #define VISLANDS30_IV_SRCID_D3_VERTICAL_INTERRUPT2 21 // 0x15 |
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| 109 | #define VISLANDS30_IV_EXTID_D3_VERTICAL_INTERRUPT2 9 |
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| 110 | |
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| 111 | #define VISLANDS30_IV_SRCID_D3_EXT_TIMING_SYNC_LOSS 21 // 0x15 |
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| 112 | #define VISLANDS30_IV_EXTID_D3_EXT_TIMING_SYNC_LOSS 10 |
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| 113 | |
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| 114 | #define VISLANDS30_IV_SRCID_D3_EXT_TIMING_SYNC 21 // 0x15 |
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| 115 | #define VISLANDS30_IV_EXTID_D3_EXT_TIMING_SYNC 11 |
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| 116 | |
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| 117 | #define VISLANDS30_IV_SRCID_D3_EXT_TIMING_SIGNAL 21 // 0x15 |
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| 118 | #define VISLANDS30_IV_EXTID_D3_EXT_TIMING_SIGNAL 12 |
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| 119 | |
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| 120 | #define VISLANDS30_IV_SRCID_D4_VERTICAL_INTERRUPT0 22 // 0x16 |
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| 121 | #define VISLANDS30_IV_EXTID_D4_VERTICAL_INTERRUPT0 7 |
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| 122 | |
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| 123 | #define VISLANDS30_IV_SRCID_D4_VERTICAL_INTERRUPT1 22 // 0x16 |
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| 124 | #define VISLANDS30_IV_EXTID_D4_VERTICAL_INTERRUPT1 8 |
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| 125 | |
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| 126 | #define VISLANDS30_IV_SRCID_D4_VERTICAL_INTERRUPT2 22 // 0x16 |
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| 127 | #define VISLANDS30_IV_EXTID_D4_VERTICAL_INTERRUPT2 9 |
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| 128 | |
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| 129 | #define VISLANDS30_IV_SRCID_D4_EXT_TIMING_SYNC_LOSS 22 // 0x16 |
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| 130 | #define VISLANDS30_IV_EXTID_D4_EXT_TIMING_SYNC_LOSS 10 |
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| 131 | |
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| 132 | #define VISLANDS30_IV_SRCID_D4_EXT_TIMING_SYNC 22 // 0x16 |
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| 133 | #define VISLANDS30_IV_EXTID_D4_EXT_TIMING_SYNC 11 |
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| 134 | |
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| 135 | #define VISLANDS30_IV_SRCID_D4_EXT_TIMING_SIGNAL 22 // 0x16 |
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| 136 | #define VISLANDS30_IV_EXTID_D4_EXT_TIMING_SIGNAL 12 |
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| 137 | |
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| 138 | #define VISLANDS30_IV_SRCID_D5_VERTICAL_INTERRUPT0 23 // 0x17 |
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| 139 | #define VISLANDS30_IV_EXTID_D5_VERTICAL_INTERRUPT0 7 |
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| 140 | |
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| 141 | #define VISLANDS30_IV_SRCID_D5_VERTICAL_INTERRUPT1 23 // 0x17 |
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| 142 | #define VISLANDS30_IV_EXTID_D5_VERTICAL_INTERRUPT1 8 |
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| 143 | |
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| 144 | #define VISLANDS30_IV_SRCID_D5_VERTICAL_INTERRUPT2 23 // 0x17 |
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| 145 | #define VISLANDS30_IV_EXTID_D5_VERTICAL_INTERRUPT2 9 |
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| 146 | |
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| 147 | #define VISLANDS30_IV_SRCID_D5_EXT_TIMING_SYNC_LOSS 23 // 0x17 |
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| 148 | #define VISLANDS30_IV_EXTID_D5_EXT_TIMING_SYNC_LOSS 10 |
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| 149 | |
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| 150 | #define VISLANDS30_IV_SRCID_D5_EXT_TIMING_SYNC 23 // 0x17 |
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| 151 | #define VISLANDS30_IV_EXTID_D5_EXT_TIMING_SYNC 11 |
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| 152 | |
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| 153 | #define VISLANDS30_IV_SRCID_D5_EXT_TIMING_SIGNAL 23 // 0x17 |
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| 154 | #define VISLANDS30_IV_EXTID_D5_EXT_TIMING_SIGNAL 12 |
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| 155 | |
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| 156 | #define VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0 24 // 0x18 |
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| 157 | #define VISLANDS30_IV_EXTID_D6_VERTICAL_INTERRUPT0 7 |
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| 158 | |
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| 159 | #define VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT1 24 // 0x18 |
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| 160 | #define VISLANDS30_IV_EXTID_D6_VERTICAL_INTERRUPT1 8 |
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| 161 | |
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| 162 | #define VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT2 24 // 0x18 |
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| 163 | #define VISLANDS30_IV_EXTID_D6_VERTICAL_INTERRUPT2 9 |
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| 164 | |
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| 165 | #define VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A 42 // 0x2a |
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| 166 | #define VISLANDS30_IV_EXTID_HOTPLUG_DETECT_A 0 |
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| 167 | |
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| 168 | #define VISLANDS30_IV_SRCID_HOTPLUG_DETECT_B 42 // 0x2a |
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| 169 | #define VISLANDS30_IV_EXTID_HOTPLUG_DETECT_B 1 |
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| 170 | |
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| 171 | #define VISLANDS30_IV_SRCID_HOTPLUG_DETECT_C 42 // 0x2a |
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| 172 | #define VISLANDS30_IV_EXTID_HOTPLUG_DETECT_C 2 |
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| 173 | |
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| 174 | #define VISLANDS30_IV_SRCID_HOTPLUG_DETECT_D 42 // 0x2a |
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| 175 | #define VISLANDS30_IV_EXTID_HOTPLUG_DETECT_D 3 |
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| 176 | |
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| 177 | #define VISLANDS30_IV_SRCID_HOTPLUG_DETECT_E 42 // 0x2a |
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| 178 | #define VISLANDS30_IV_EXTID_HOTPLUG_DETECT_E 4 |
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| 179 | |
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| 180 | #define VISLANDS30_IV_SRCID_HOTPLUG_DETECT_F 42 // 0x2a |
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| 181 | #define VISLANDS30_IV_EXTID_HOTPLUG_DETECT_F 5 |
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| 182 | |
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| 183 | #define VISLANDS30_IV_SRCID_HPD_RX_A 42 // 0x2a |
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| 184 | #define VISLANDS30_IV_EXTID_HPD_RX_A 6 |
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| 185 | |
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| 186 | #define VISLANDS30_IV_SRCID_HPD_RX_B 42 // 0x2a |
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| 187 | #define VISLANDS30_IV_EXTID_HPD_RX_B 7 |
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| 188 | |
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| 189 | #define VISLANDS30_IV_SRCID_HPD_RX_C 42 // 0x2a |
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| 190 | #define VISLANDS30_IV_EXTID_HPD_RX_C 8 |
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| 191 | |
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| 192 | #define VISLANDS30_IV_SRCID_HPD_RX_D 42 // 0x2a |
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| 193 | #define VISLANDS30_IV_EXTID_HPD_RX_D 9 |
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| 194 | |
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| 195 | #define VISLANDS30_IV_SRCID_HPD_RX_E 42 // 0x2a |
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| 196 | #define VISLANDS30_IV_EXTID_HPD_RX_E 10 |
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| 197 | |
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| 198 | #define VISLANDS30_IV_SRCID_HPD_RX_F 42 // 0x2a |
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| 199 | #define VISLANDS30_IV_EXTID_HPD_RX_F 11 |
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| 200 | |
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| 201 | #define VISLANDS30_IV_SRCID_GPIO_19 0x00000053 /* 83 */ |
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| 202 | |
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| 203 | #define VISLANDS30_IV_SRCID_SRBM_READ_TIMEOUT_ERR 0x00000060 /* 96 */ |
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| 204 | #define VISLANDS30_IV_SRCID_SRBM_CTX_SWITCH 0x00000061 /* 97 */ |
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| 205 | |
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| 206 | #define VISLANDS30_IV_SRBM_REG_ACCESS_ERROR 0x00000062 /* 98 */ |
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| 207 | |
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| 208 | |
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| 209 | #define VISLANDS30_IV_SRCID_UVD_ENC_GEN_PURP 0x00000077 /* 119 */ |
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| 210 | #define VISLANDS30_IV_SRCID_UVD_SYSTEM_MESSAGE 0x0000007c /* 124 */ |
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| 211 | |
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| 212 | #define VISLANDS30_IV_SRCID_BIF_PF_VF_MSGBUF_VALID 0x00000087 /* 135 */ |
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| 213 | |
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| 214 | #define VISLANDS30_IV_SRCID_BIF_VF_PF_MSGBUF_ACK 0x0000008a /* 138 */ |
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| 215 | |
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| 216 | #define VISLANDS30_IV_SRCID_SYS_PAGE_INV_FAULT 0x0000008c /* 140 */ |
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| 217 | #define VISLANDS30_IV_SRCID_SYS_MEM_PROT_FAULT 0x0000008d /* 141 */ |
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| 218 | |
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| 219 | #define VISLANDS30_IV_SRCID_SEM_PAGE_INV_FAULT 0x00000090 /* 144 */ |
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| 220 | #define VISLANDS30_IV_SRCID_SEM_MEM_PROT_FAULT 0x00000091 /* 145 */ |
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| 221 | |
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| 222 | #define VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT 0x00000092 /* 146 */ |
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| 223 | #define VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT 0x00000093 /* 147 */ |
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| 224 | |
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| 225 | #define VISLANDS30_IV_SRCID_ACP 0x000000a2 /* 162 */ |
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| 226 | |
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| 227 | #define VISLANDS30_IV_SRCID_VCE_TRAP 0x000000a7 /* 167 */ |
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| 228 | #define VISLANDS30_IV_EXTID_VCE_TRAP_GENERAL_PURPOSE 0 |
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| 229 | #define VISLANDS30_IV_EXTID_VCE_TRAP_LOW_LATENCY 1 |
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| 230 | #define VISLANDS30_IV_EXTID_VCE_TRAP_REAL_TIME 2 |
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| 231 | |
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| 232 | #define VISLANDS30_IV_SRCID_CP_INT_RB 0x000000b0 /* 176 */ |
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| 233 | #define VISLANDS30_IV_SRCID_CP_INT_IB1 0x000000b1 /* 177 */ |
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| 234 | #define VISLANDS30_IV_SRCID_CP_INT_IB2 0x000000b2 /* 178 */ |
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| 235 | #define VISLANDS30_IV_SRCID_CP_PM4_RES_BITS_ERR 0x000000b4 /* 180 */ |
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| 236 | #define VISLANDS30_IV_SRCID_CP_END_OF_PIPE 0x000000b5 /* 181 */ |
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| 237 | #define VISLANDS30_IV_SRCID_CP_BAD_OPCODE 0x000000b7 /* 183 */ |
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| 238 | #define VISLANDS30_IV_SRCID_CP_PRIV_REG_FAULT 0x000000b8 /* 184 */ |
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| 239 | #define VISLANDS30_IV_SRCID_CP_PRIV_INSTR_FAULT 0x000000b9 /* 185 */ |
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| 240 | #define VISLANDS30_IV_SRCID_CP_WAIT_MEM_SEM_FAULT 0x000000ba /* 186 */ |
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| 241 | #define VISLANDS30_IV_SRCID_CP_GUI_IDLE 0x000000bb /* 187 */ |
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| 242 | #define VISLANDS30_IV_SRCID_CP_GUI_BUSY 0x000000bc /* 188 */ |
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| 243 | |
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| 244 | #define VISLANDS30_IV_SRCID_CP_COMPUTE_QUERY_STATUS 0x000000bf /* 191 */ |
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| 245 | #define VISLANDS30_IV_SRCID_CP_ECC_ERROR 0x000000c5 /* 197 */ |
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| 246 | |
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| 247 | #define CARRIZO_IV_SRCID_CP_COMPUTE_QUERY_STATUS 0x000000c7 /* 199 */ |
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| 248 | |
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| 249 | #define VISLANDS30_IV_SRCID_CP_WAIT_REG_MEM_POLL_TIMEOUT 0x000000c0 /* 192 */ |
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| 250 | #define VISLANDS30_IV_SRCID_CP_SEM_SIG_INCOMPL 0x000000c1 /* 193 */ |
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| 251 | #define VISLANDS30_IV_SRCID_CP_PREEMPT_ACK 0x000000c2 /* 194 */ |
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| 252 | #define VISLANDS30_IV_SRCID_CP_GENERAL_PROT_FAULT 0x000000c3 /* 195 */ |
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| 253 | #define VISLANDS30_IV_SRCID_CP_GDS_ALLOC_ERROR 0x000000c4 /* 196 */ |
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| 254 | #define VISLANDS30_IV_SRCID_CP_ECC_ERROR 0x000000c5 /* 197 */ |
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| 255 | |
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| 256 | #define VISLANDS30_IV_SRCID_RLC_STRM_PERF_MONITOR 0x000000ca /* 202 */ |
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| 257 | |
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| 258 | #define VISLANDS30_IV_SDMA_ATOMIC_SRC_ID 0x000000da /* 218 */ |
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| 259 | |
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| 260 | #define VISLANDS30_IV_SRCID_SDMA_ECC_ERROR 0x000000dc /* 220 */ |
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| 261 | |
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| 262 | #define VISLANDS30_IV_SRCID_SDMA_TRAP 0x000000e0 /* 224 */ |
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| 263 | #define VISLANDS30_IV_SRCID_SDMA_SEM_INCOMPLETE 0x000000e1 /* 225 */ |
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| 264 | #define VISLANDS30_IV_SRCID_SDMA_SEM_WAIT 0x000000e2 /* 226 */ |
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| 265 | |
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| 266 | |
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| 267 | #define VISLANDS30_IV_SRCID_SMU_DISP_TIMER2_TRIGGER 0x000000e5 /* 229 */ |
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| 268 | |
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| 269 | #define VISLANDS30_IV_SRCID_CG_TSS_THERMAL_LOW_TO_HIGH 0x000000e6 /* 230 */ |
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| 270 | #define VISLANDS30_IV_SRCID_CG_TSS_THERMAL_HIGH_TO_LOW 0x000000e7 /* 231 */ |
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| 271 | |
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| 272 | #define VISLANDS30_IV_SRCID_GRBM_READ_TIMEOUT_ERR 0x000000e8 /* 232 */ |
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| 273 | #define VISLANDS30_IV_SRCID_GRBM_REG_GUI_IDLE 0x000000e9 /* 233 */ |
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| 274 | |
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| 275 | #define VISLANDS30_IV_SRCID_SQ_INTERRUPT_MSG 0x000000ef /* 239 */ |
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| 276 | |
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| 277 | #define VISLANDS30_IV_SRCID_SDMA_PREEMPT 0x000000f0 /* 240 */ |
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| 278 | #define VISLANDS30_IV_SRCID_SDMA_VM_HOLE 0x000000f2 /* 242 */ |
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| 279 | #define VISLANDS30_IV_SRCID_SDMA_CTXEMPTY 0x000000f3 /* 243 */ |
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| 280 | #define VISLANDS30_IV_SRCID_SDMA_DOORBELL_INVALID 0x000000f4 /* 244 */ |
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| 281 | #define VISLANDS30_IV_SRCID_SDMA_FROZEN 0x000000f5 /* 245 */ |
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| 282 | #define VISLANDS30_IV_SRCID_SDMA_POLL_TIMEOUT 0x000000f6 /* 246 */ |
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| 283 | #define VISLANDS30_IV_SRCID_SDMA_SRBM_WRITE 0x000000f7 /* 247 */ |
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| 284 | |
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| 285 | #define VISLANDS30_IV_SRCID_CG_THERMAL_TRIG 0x000000f8 /* 248 */ |
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| 286 | |
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| 287 | #define VISLANDS30_IV_SRCID_SMU_DISP_TIMER_TRIGGER 0x000000fd /* 253 */ |
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| 288 | |
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| 289 | /* These are not "real" source ids defined by HW */ |
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| 290 | #define VISLANDS30_IV_SRCID_VM_CONTEXT_ALL 0x00000100 /* 256 */ |
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| 291 | #define VISLANDS30_IV_EXTID_VM_CONTEXT0_ALL 0 |
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| 292 | #define VISLANDS30_IV_EXTID_VM_CONTEXT1_ALL 1 |
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| 293 | |
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| 294 | |
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| 295 | /* IV Extended IDs */ |
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| 296 | #define VISLANDS30_IV_EXTID_NONE 0x00000000 |
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| 297 | #define VISLANDS30_IV_EXTID_INVALID 0xffffffff |
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| 298 | |
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| 299 | #endif // _IVSRCID_VISLANDS30_H_ |
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| 300 | |
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