1	/*
2	* Copyright 2014 Advanced Micro Devices, Inc.
3	*
4	* Permission is hereby granted, free of charge, to any person obtaining a
5	* copy of this software and associated documentation files (the "Software"),
6	* to deal in the Software without restriction, including without limitation
7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8	* and/or sell copies of the Software, and to permit persons to whom the
9	* Software is furnished to do so, subject to the following conditions:
10	*
11	* The above copyright notice and this permission notice shall be included in
12	* all copies or substantial portions of the Software.
13	*
14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20	* OTHER DEALINGS IN THE SOFTWARE.
21	*
22	*/
23
24	#include <drm/drm_edid.h>
25	#include <drm/drm_fourcc.h>
26	#include <drm/drm_modeset_helper.h>
27	#include <drm/drm_modeset_helper_vtables.h>
28	#include <drm/drm_vblank.h>
29
30	#include "amdgpu.h"
31	#include "amdgpu_pm.h"
32	#include "amdgpu_i2c.h"
33	#include "vid.h"
34	#include "atom.h"
35	#include "amdgpu_atombios.h"
36	#include "atombios_crtc.h"
37	#include "atombios_encoders.h"
38	#include "amdgpu_pll.h"
39	#include "amdgpu_connectors.h"
40	#include "amdgpu_display.h"
41	#include "dce_v10_0.h"
42
43	#include "dce/dce_10_0_d.h"
44	#include "dce/dce_10_0_sh_mask.h"
45	#include "dce/dce_10_0_enum.h"
46	#include "oss/oss_3_0_d.h"
47	#include "oss/oss_3_0_sh_mask.h"
48	#include "gmc/gmc_8_1_d.h"
49	#include "gmc/gmc_8_1_sh_mask.h"
50
51	#include "ivsrcid/ivsrcid_vislands30.h"
52
53	static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev);
54	static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev);
55	static void dce_v10_0_hpd_int_ack(struct amdgpu_device *adev, int hpd);
56
57	static const u32 crtc_offsets[] = {
58	CRTC0_REGISTER_OFFSET,
59	CRTC1_REGISTER_OFFSET,
60	CRTC2_REGISTER_OFFSET,
61	CRTC3_REGISTER_OFFSET,
62	CRTC4_REGISTER_OFFSET,
63	CRTC5_REGISTER_OFFSET,
64	CRTC6_REGISTER_OFFSET
65	};
66
67	static const u32 hpd_offsets[] = {
68	HPD0_REGISTER_OFFSET,
69	HPD1_REGISTER_OFFSET,
70	HPD2_REGISTER_OFFSET,
71	HPD3_REGISTER_OFFSET,
72	HPD4_REGISTER_OFFSET,
73	HPD5_REGISTER_OFFSET
74	};
75
76	static const uint32_t dig_offsets[] = {
77	DIG0_REGISTER_OFFSET,
78	DIG1_REGISTER_OFFSET,
79	DIG2_REGISTER_OFFSET,
80	DIG3_REGISTER_OFFSET,
81	DIG4_REGISTER_OFFSET,
82	DIG5_REGISTER_OFFSET,
83	DIG6_REGISTER_OFFSET
84	};
85
86	static const struct {
87	uint32_t reg;
88	uint32_t vblank;
89	uint32_t vline;
90	uint32_t hpd;
91
92	} interrupt_status_offsets[] = { {
93	.reg = mmDISP_INTERRUPT_STATUS,
94	.vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
95	.vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
96	.hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
97	}, {
98	.reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
99	.vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
100	.vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
101	.hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
102	}, {
103	.reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
104	.vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
105	.vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
106	.hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
107	}, {
108	.reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
109	.vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
110	.vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
111	.hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
112	}, {
113	.reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
114	.vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
115	.vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
116	.hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
117	}, {
118	.reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
119	.vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
120	.vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
121	.hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
122	} };
123
124	static const u32 golden_settings_tonga_a11[] = {
125	mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
126	mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
127	mmFBC_MISC, 0x1f311fff, 0x12300000,
128	mmHDMI_CONTROL, 0x31000111, 0x00000011,
129	};
130
131	static const u32 tonga_mgcg_cgcg_init[] = {
132	mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
133	mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
134	};
135
136	static const u32 golden_settings_fiji_a10[] = {
137	mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
138	mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
139	mmFBC_MISC, 0x1f311fff, 0x12300000,
140	mmHDMI_CONTROL, 0x31000111, 0x00000011,
141	};
142
143	static const u32 fiji_mgcg_cgcg_init[] = {
144	mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
145	mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
146	};
147
148	static void dce_v10_0_init_golden_registers(struct amdgpu_device *adev)
149	{
150	switch (adev->asic_type) {
151	case CHIP_FIJI:
152	amdgpu_device_program_register_sequence(adev,
153	registers: fiji_mgcg_cgcg_init,
154	ARRAY_SIZE(fiji_mgcg_cgcg_init));
155	amdgpu_device_program_register_sequence(adev,
156	registers: golden_settings_fiji_a10,
157	ARRAY_SIZE(golden_settings_fiji_a10));
158	break;
159	case CHIP_TONGA:
160	amdgpu_device_program_register_sequence(adev,
161	registers: tonga_mgcg_cgcg_init,
162	ARRAY_SIZE(tonga_mgcg_cgcg_init));
163	amdgpu_device_program_register_sequence(adev,
164	registers: golden_settings_tonga_a11,
165	ARRAY_SIZE(golden_settings_tonga_a11));
166	break;
167	default:
168	break;
169	}
170	}
171
172	static u32 dce_v10_0_audio_endpt_rreg(struct amdgpu_device *adev,
173	u32 block_offset, u32 reg)
174	{
175	unsigned long flags;
176	u32 r;
177
178	spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
179	WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
180	r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
181	spin_unlock_irqrestore(lock: &adev->audio_endpt_idx_lock, flags);
182
183	return r;
184	}
185
186	static void dce_v10_0_audio_endpt_wreg(struct amdgpu_device *adev,
187	u32 block_offset, u32 reg, u32 v)
188	{
189	unsigned long flags;
190
191	spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
192	WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
193	WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
194	spin_unlock_irqrestore(lock: &adev->audio_endpt_idx_lock, flags);
195	}
196
197	static u32 dce_v10_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
198	{
199	if (crtc >= adev->mode_info.num_crtc)
200	return 0;
201	else
202	return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
203	}
204
205	static void dce_v10_0_pageflip_interrupt_init(struct amdgpu_device *adev)
206	{
207	unsigned i;
208
209	/* Enable pflip interrupts */
210	for (i = 0; i < adev->mode_info.num_crtc; i++)
211	amdgpu_irq_get(adev, src: &adev->pageflip_irq, type: i);
212	}
213
214	static void dce_v10_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
215	{
216	unsigned i;
217
218	/* Disable pflip interrupts */
219	for (i = 0; i < adev->mode_info.num_crtc; i++)
220	amdgpu_irq_put(adev, src: &adev->pageflip_irq, type: i);
221	}
222
223	/**
224	* dce_v10_0_page_flip - pageflip callback.
225	*
226	* @adev: amdgpu_device pointer
227	* @crtc_id: crtc to cleanup pageflip on
228	* @crtc_base: new address of the crtc (GPU MC address)
229	* @async: asynchronous flip
230	*
231	* Triggers the actual pageflip by updating the primary
232	* surface base address.
233	*/
234	static void dce_v10_0_page_flip(struct amdgpu_device *adev,
235	int crtc_id, u64 crtc_base, bool async)
236	{
237	struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
238	struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb;
239	u32 tmp;
240
241	/* flip at hsync for async, default is vsync */
242	tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
243	tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
244	GRPH_SURFACE_UPDATE_H_RETRACE_EN, async ? 1 : 0);
245	WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
246	/* update pitch */
247	WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,
248	fb->pitches[0] / fb->format->cpp[0]);
249	/* update the primary scanout address */
250	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
251	upper_32_bits(crtc_base));
252	/* writing to the low address triggers the update */
253	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
254	lower_32_bits(crtc_base));
255	/* post the write */
256	RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
257	}
258
259	static int dce_v10_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
260	u32 *vbl, u32 *position)
261	{
262	if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
263	return -EINVAL;
264
265	*vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
266	*position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
267
268	return 0;
269	}
270
271	/**
272	* dce_v10_0_hpd_sense - hpd sense callback.
273	*
274	* @adev: amdgpu_device pointer
275	* @hpd: hpd (hotplug detect) pin
276	*
277	* Checks if a digital monitor is connected (evergreen+).
278	* Returns true if connected, false if not connected.
279	*/
280	static bool dce_v10_0_hpd_sense(struct amdgpu_device *adev,
281	enum amdgpu_hpd_id hpd)
282	{
283	bool connected = false;
284
285	if (hpd >= adev->mode_info.num_hpd)
286	return connected;
287
288	if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) &
289	DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK)
290	connected = true;
291
292	return connected;
293	}
294
295	/**
296	* dce_v10_0_hpd_set_polarity - hpd set polarity callback.
297	*
298	* @adev: amdgpu_device pointer
299	* @hpd: hpd (hotplug detect) pin
300	*
301	* Set the polarity of the hpd pin (evergreen+).
302	*/
303	static void dce_v10_0_hpd_set_polarity(struct amdgpu_device *adev,
304	enum amdgpu_hpd_id hpd)
305	{
306	u32 tmp;
307	bool connected = dce_v10_0_hpd_sense(adev, hpd);
308
309	if (hpd >= adev->mode_info.num_hpd)
310	return;
311
312	tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
313	if (connected)
314	tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0);
315	else
316	tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1);
317	WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
318	}
319
320	/**
321	* dce_v10_0_hpd_init - hpd setup callback.
322	*
323	* @adev: amdgpu_device pointer
324	*
325	* Setup the hpd pins used by the card (evergreen+).
326	* Enable the pin, set the polarity, and enable the hpd interrupts.
327	*/
328	static void dce_v10_0_hpd_init(struct amdgpu_device *adev)
329	{
330	struct drm_device *dev = adev_to_drm(adev);
331	struct drm_connector *connector;
332	struct drm_connector_list_iter iter;
333	u32 tmp;
334
335	drm_connector_list_iter_begin(dev, iter: &iter);
336	drm_for_each_connector_iter(connector, &iter) {
337	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
338
339	if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
340	continue;
341
342	if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
343	connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
344	/* don't try to enable hpd on eDP or LVDS avoid breaking the
345	* aux dp channel on imac and help (but not completely fix)
346	* https://bugzilla.redhat.com/show_bug.cgi?id=726143
347	* also avoid interrupt storms during dpms.
348	*/
349	tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
350	tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
351	WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
352	continue;
353	}
354
355	tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
356	tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);
357	WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
358
359	tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]);
360	tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
361	DC_HPD_CONNECT_INT_DELAY,
362	AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS);
363	tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
364	DC_HPD_DISCONNECT_INT_DELAY,
365	AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS);
366	WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
367
368	dce_v10_0_hpd_int_ack(adev, hpd: amdgpu_connector->hpd.hpd);
369	dce_v10_0_hpd_set_polarity(adev, hpd: amdgpu_connector->hpd.hpd);
370	amdgpu_irq_get(adev, src: &adev->hpd_irq,
371	type: amdgpu_connector->hpd.hpd);
372	}
373	drm_connector_list_iter_end(iter: &iter);
374	}
375
376	/**
377	* dce_v10_0_hpd_fini - hpd tear down callback.
378	*
379	* @adev: amdgpu_device pointer
380	*
381	* Tear down the hpd pins used by the card (evergreen+).
382	* Disable the hpd interrupts.
383	*/
384	static void dce_v10_0_hpd_fini(struct amdgpu_device *adev)
385	{
386	struct drm_device *dev = adev_to_drm(adev);
387	struct drm_connector *connector;
388	struct drm_connector_list_iter iter;
389	u32 tmp;
390
391	drm_connector_list_iter_begin(dev, iter: &iter);
392	drm_for_each_connector_iter(connector, &iter) {
393	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
394
395	if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
396	continue;
397
398	tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
399	tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0);
400	WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
401
402	amdgpu_irq_put(adev, src: &adev->hpd_irq,
403	type: amdgpu_connector->hpd.hpd);
404	}
405	drm_connector_list_iter_end(iter: &iter);
406	}
407
408	static u32 dce_v10_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
409	{
410	return mmDC_GPIO_HPD_A;
411	}
412
413	static bool dce_v10_0_is_display_hung(struct amdgpu_device *adev)
414	{
415	u32 crtc_hung = 0;
416	u32 crtc_status[6];
417	u32 i, j, tmp;
418
419	for (i = 0; i < adev->mode_info.num_crtc; i++) {
420	tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
421	if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) {
422	crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
423	crtc_hung |= (1 << i);
424	}
425	}
426
427	for (j = 0; j < 10; j++) {
428	for (i = 0; i < adev->mode_info.num_crtc; i++) {
429	if (crtc_hung & (1 << i)) {
430	tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
431	if (tmp != crtc_status[i])
432	crtc_hung &= ~(1 << i);
433	}
434	}
435	if (crtc_hung == 0)
436	return false;
437	udelay(usec: 100);
438	}
439
440	return true;
441	}
442
443	static void dce_v10_0_set_vga_render_state(struct amdgpu_device *adev,
444	bool render)
445	{
446	u32 tmp;
447
448	/* Lockout access through VGA aperture*/
449	tmp = RREG32(mmVGA_HDP_CONTROL);
450	if (render)
451	tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
452	else
453	tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
454	WREG32(mmVGA_HDP_CONTROL, tmp);
455
456	/* disable VGA render */
457	tmp = RREG32(mmVGA_RENDER_CONTROL);
458	if (render)
459	tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
460	else
461	tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
462	WREG32(mmVGA_RENDER_CONTROL, tmp);
463	}
464
465	static int dce_v10_0_get_num_crtc(struct amdgpu_device *adev)
466	{
467	int num_crtc = 0;
468
469	switch (adev->asic_type) {
470	case CHIP_FIJI:
471	case CHIP_TONGA:
472	num_crtc = 6;
473	break;
474	default:
475	num_crtc = 0;
476	}
477	return num_crtc;
478	}
479
480	void dce_v10_0_disable_dce(struct amdgpu_device *adev)
481	{
482	/*Disable VGA render and enabled crtc, if has DCE engine*/
483	if (amdgpu_atombios_has_dce_engine_info(adev)) {
484	u32 tmp;
485	int crtc_enabled, i;
486
487	dce_v10_0_set_vga_render_state(adev, render: false);
488
489	/*Disable crtc*/
490	for (i = 0; i < dce_v10_0_get_num_crtc(adev); i++) {
491	crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
492	CRTC_CONTROL, CRTC_MASTER_EN);
493	if (crtc_enabled) {
494	WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
495	tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
496	tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
497	WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
498	WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
499	}
500	}
501	}
502	}
503
504	static void dce_v10_0_program_fmt(struct drm_encoder *encoder)
505	{
506	struct drm_device *dev = encoder->dev;
507	struct amdgpu_device *adev = drm_to_adev(ddev: dev);
508	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
509	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
510	struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
511	int bpc = 0;
512	u32 tmp = 0;
513	enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
514
515	if (connector) {
516	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
517	bpc = amdgpu_connector_get_monitor_bpc(connector);
518	dither = amdgpu_connector->dither;
519	}
520
521	/* LVDS/eDP FMT is set up by atom */
522	if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
523	return;
524
525	/* not needed for analog */
526	if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
527	(amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
528	return;
529
530	if (bpc == 0)
531	return;
532
533	switch (bpc) {
534	case 6:
535	if (dither == AMDGPU_FMT_DITHER_ENABLE) {
536	/* XXX sort out optimal dither settings */
537	tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
538	tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
539	tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
540	tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);
541	} else {
542	tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
543	tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);
544	}
545	break;
546	case 8:
547	if (dither == AMDGPU_FMT_DITHER_ENABLE) {
548	/* XXX sort out optimal dither settings */
549	tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
550	tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
551	tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
552	tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
553	tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1);
554	} else {
555	tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
556	tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1);
557	}
558	break;
559	case 10:
560	if (dither == AMDGPU_FMT_DITHER_ENABLE) {
561	/* XXX sort out optimal dither settings */
562	tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
563	tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
564	tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
565	tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
566	tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2);
567	} else {
568	tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
569	tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2);
570	}
571	break;
572	default:
573	/* not needed */
574	break;
575	}
576
577	WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
578	}
579
580
581	/* display watermark setup */
582	/**
583	* dce_v10_0_line_buffer_adjust - Set up the line buffer
584	*
585	* @adev: amdgpu_device pointer
586	* @amdgpu_crtc: the selected display controller
587	* @mode: the current display mode on the selected display
588	* controller
589	*
590	* Setup up the line buffer allocation for
591	* the selected display controller (CIK).
592	* Returns the line buffer size in pixels.
593	*/
594	static u32 dce_v10_0_line_buffer_adjust(struct amdgpu_device *adev,
595	struct amdgpu_crtc *amdgpu_crtc,
596	struct drm_display_mode *mode)
597	{
598	u32 tmp, buffer_alloc, i, mem_cfg;
599	u32 pipe_offset = amdgpu_crtc->crtc_id;
600	/*
601	* Line Buffer Setup
602	* There are 6 line buffers, one for each display controllers.
603	* There are 3 partitions per LB. Select the number of partitions
604	* to enable based on the display width. For display widths larger
605	* than 4096, you need use to use 2 display controllers and combine
606	* them using the stereo blender.
607	*/
608	if (amdgpu_crtc->base.enabled && mode) {
609	if (mode->crtc_hdisplay < 1920) {
610	mem_cfg = 1;
611	buffer_alloc = 2;
612	} else if (mode->crtc_hdisplay < 2560) {
613	mem_cfg = 2;
614	buffer_alloc = 2;
615	} else if (mode->crtc_hdisplay < 4096) {
616	mem_cfg = 0;
617	buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
618	} else {
619	DRM_DEBUG_KMS("Mode too big for LB!\n");
620	mem_cfg = 0;
621	buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
622	}
623	} else {
624	mem_cfg = 1;
625	buffer_alloc = 0;
626	}
627
628	tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);
629	tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg);
630	WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);
631
632	tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
633	tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);
634	WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);
635
636	for (i = 0; i < adev->usec_timeout; i++) {
637	tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
638	if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED))
639	break;
640	udelay(usec: 1);
641	}
642
643	if (amdgpu_crtc->base.enabled && mode) {
644	switch (mem_cfg) {
645	case 0:
646	default:
647	return 4096 * 2;
648	case 1:
649	return 1920 * 2;
650	case 2:
651	return 2560 * 2;
652	}
653	}
654
655	/* controller not enabled, so no lb used */
656	return 0;
657	}
658
659	/**
660	* cik_get_number_of_dram_channels - get the number of dram channels
661	*
662	* @adev: amdgpu_device pointer
663	*
664	* Look up the number of video ram channels (CIK).
665	* Used for display watermark bandwidth calculations
666	* Returns the number of dram channels
667	*/
668	static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
669	{
670	u32 tmp = RREG32(mmMC_SHARED_CHMAP);
671
672	switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
673	case 0:
674	default:
675	return 1;
676	case 1:
677	return 2;
678	case 2:
679	return 4;
680	case 3:
681	return 8;
682	case 4:
683	return 3;
684	case 5:
685	return 6;
686	case 6:
687	return 10;
688	case 7:
689	return 12;
690	case 8:
691	return 16;
692	}
693	}
694
695	struct dce10_wm_params {
696	u32 dram_channels; /* number of dram channels */
697	u32 yclk; /* bandwidth per dram data pin in kHz */
698	u32 sclk; /* engine clock in kHz */
699	u32 disp_clk; /* display clock in kHz */
700	u32 src_width; /* viewport width */
701	u32 active_time; /* active display time in ns */
702	u32 blank_time; /* blank time in ns */
703	bool interlaced; /* mode is interlaced */
704	fixed20_12 vsc; /* vertical scale ratio */
705	u32 num_heads; /* number of active crtcs */
706	u32 bytes_per_pixel; /* bytes per pixel display + overlay */
707	u32 lb_size; /* line buffer allocated to pipe */
708	u32 vtaps; /* vertical scaler taps */
709	};
710
711	/**
712	* dce_v10_0_dram_bandwidth - get the dram bandwidth
713	*
714	* @wm: watermark calculation data
715	*
716	* Calculate the raw dram bandwidth (CIK).
717	* Used for display watermark bandwidth calculations
718	* Returns the dram bandwidth in MBytes/s
719	*/
720	static u32 dce_v10_0_dram_bandwidth(struct dce10_wm_params *wm)
721	{
722	/* Calculate raw DRAM Bandwidth */
723	fixed20_12 dram_efficiency; /* 0.7 */
724	fixed20_12 yclk, dram_channels, bandwidth;
725	fixed20_12 a;
726
727	a.full = dfixed_const(1000);
728	yclk.full = dfixed_const(wm->yclk);
729	yclk.full = dfixed_div(A: yclk, B: a);
730	dram_channels.full = dfixed_const(wm->dram_channels * 4);
731	a.full = dfixed_const(10);
732	dram_efficiency.full = dfixed_const(7);
733	dram_efficiency.full = dfixed_div(A: dram_efficiency, B: a);
734	bandwidth.full = dfixed_mul(dram_channels, yclk);
735	bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
736
737	return dfixed_trunc(bandwidth);
738	}
739
740	/**
741	* dce_v10_0_dram_bandwidth_for_display - get the dram bandwidth for display
742	*
743	* @wm: watermark calculation data
744	*
745	* Calculate the dram bandwidth used for display (CIK).
746	* Used for display watermark bandwidth calculations
747	* Returns the dram bandwidth for display in MBytes/s
748	*/
749	static u32 dce_v10_0_dram_bandwidth_for_display(struct dce10_wm_params *wm)
750	{
751	/* Calculate DRAM Bandwidth and the part allocated to display. */
752	fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
753	fixed20_12 yclk, dram_channels, bandwidth;
754	fixed20_12 a;
755
756	a.full = dfixed_const(1000);
757	yclk.full = dfixed_const(wm->yclk);
758	yclk.full = dfixed_div(A: yclk, B: a);
759	dram_channels.full = dfixed_const(wm->dram_channels * 4);
760	a.full = dfixed_const(10);
761	disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
762	disp_dram_allocation.full = dfixed_div(A: disp_dram_allocation, B: a);
763	bandwidth.full = dfixed_mul(dram_channels, yclk);
764	bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
765
766	return dfixed_trunc(bandwidth);
767	}
768
769	/**
770	* dce_v10_0_data_return_bandwidth - get the data return bandwidth
771	*
772	* @wm: watermark calculation data
773	*
774	* Calculate the data return bandwidth used for display (CIK).
775	* Used for display watermark bandwidth calculations
776	* Returns the data return bandwidth in MBytes/s
777	*/
778	static u32 dce_v10_0_data_return_bandwidth(struct dce10_wm_params *wm)
779	{
780	/* Calculate the display Data return Bandwidth */
781	fixed20_12 return_efficiency; /* 0.8 */
782	fixed20_12 sclk, bandwidth;
783	fixed20_12 a;
784
785	a.full = dfixed_const(1000);
786	sclk.full = dfixed_const(wm->sclk);
787	sclk.full = dfixed_div(A: sclk, B: a);
788	a.full = dfixed_const(10);
789	return_efficiency.full = dfixed_const(8);
790	return_efficiency.full = dfixed_div(A: return_efficiency, B: a);
791	a.full = dfixed_const(32);
792	bandwidth.full = dfixed_mul(a, sclk);
793	bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
794
795	return dfixed_trunc(bandwidth);
796	}
797
798	/**
799	* dce_v10_0_dmif_request_bandwidth - get the dmif bandwidth
800	*
801	* @wm: watermark calculation data
802	*
803	* Calculate the dmif bandwidth used for display (CIK).
804	* Used for display watermark bandwidth calculations
805	* Returns the dmif bandwidth in MBytes/s
806	*/
807	static u32 dce_v10_0_dmif_request_bandwidth(struct dce10_wm_params *wm)
808	{
809	/* Calculate the DMIF Request Bandwidth */
810	fixed20_12 disp_clk_request_efficiency; /* 0.8 */
811	fixed20_12 disp_clk, bandwidth;
812	fixed20_12 a, b;
813
814	a.full = dfixed_const(1000);
815	disp_clk.full = dfixed_const(wm->disp_clk);
816	disp_clk.full = dfixed_div(A: disp_clk, B: a);
817	a.full = dfixed_const(32);
818	b.full = dfixed_mul(a, disp_clk);
819
820	a.full = dfixed_const(10);
821	disp_clk_request_efficiency.full = dfixed_const(8);
822	disp_clk_request_efficiency.full = dfixed_div(A: disp_clk_request_efficiency, B: a);
823
824	bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
825
826	return dfixed_trunc(bandwidth);
827	}
828
829	/**
830	* dce_v10_0_available_bandwidth - get the min available bandwidth
831	*
832	* @wm: watermark calculation data
833	*
834	* Calculate the min available bandwidth used for display (CIK).
835	* Used for display watermark bandwidth calculations
836	* Returns the min available bandwidth in MBytes/s
837	*/
838	static u32 dce_v10_0_available_bandwidth(struct dce10_wm_params *wm)
839	{
840	/* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
841	u32 dram_bandwidth = dce_v10_0_dram_bandwidth(wm);
842	u32 data_return_bandwidth = dce_v10_0_data_return_bandwidth(wm);
843	u32 dmif_req_bandwidth = dce_v10_0_dmif_request_bandwidth(wm);
844
845	return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
846	}
847
848	/**
849	* dce_v10_0_average_bandwidth - get the average available bandwidth
850	*
851	* @wm: watermark calculation data
852	*
853	* Calculate the average available bandwidth used for display (CIK).
854	* Used for display watermark bandwidth calculations
855	* Returns the average available bandwidth in MBytes/s
856	*/
857	static u32 dce_v10_0_average_bandwidth(struct dce10_wm_params *wm)
858	{
859	/* Calculate the display mode Average Bandwidth
860	* DisplayMode should contain the source and destination dimensions,
861	* timing, etc.
862	*/
863	fixed20_12 bpp;
864	fixed20_12 line_time;
865	fixed20_12 src_width;
866	fixed20_12 bandwidth;
867	fixed20_12 a;
868
869	a.full = dfixed_const(1000);
870	line_time.full = dfixed_const(wm->active_time + wm->blank_time);
871	line_time.full = dfixed_div(A: line_time, B: a);
872	bpp.full = dfixed_const(wm->bytes_per_pixel);
873	src_width.full = dfixed_const(wm->src_width);
874	bandwidth.full = dfixed_mul(src_width, bpp);
875	bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
876	bandwidth.full = dfixed_div(A: bandwidth, B: line_time);
877
878	return dfixed_trunc(bandwidth);
879	}
880
881	/**
882	* dce_v10_0_latency_watermark - get the latency watermark
883	*
884	* @wm: watermark calculation data
885	*
886	* Calculate the latency watermark (CIK).
887	* Used for display watermark bandwidth calculations
888	* Returns the latency watermark in ns
889	*/
890	static u32 dce_v10_0_latency_watermark(struct dce10_wm_params *wm)
891	{
892	/* First calculate the latency in ns */
893	u32 mc_latency = 2000; /* 2000 ns. */
894	u32 available_bandwidth = dce_v10_0_available_bandwidth(wm);
895	u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
896	u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
897	u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
898	u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
899	(wm->num_heads * cursor_line_pair_return_time);
900	u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
901	u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
902	u32 tmp, dmif_size = 12288;
903	fixed20_12 a, b, c;
904
905	if (wm->num_heads == 0)
906	return 0;
907
908	a.full = dfixed_const(2);
909	b.full = dfixed_const(1);
910	if ((wm->vsc.full > a.full) ||
911	((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
912	(wm->vtaps >= 5) ||
913	((wm->vsc.full >= a.full) && wm->interlaced))
914	max_src_lines_per_dst_line = 4;
915	else
916	max_src_lines_per_dst_line = 2;
917
918	a.full = dfixed_const(available_bandwidth);
919	b.full = dfixed_const(wm->num_heads);
920	a.full = dfixed_div(A: a, B: b);
921	tmp = div_u64(dividend: (u64) dmif_size * (u64) wm->disp_clk, divisor: mc_latency + 512);
922	tmp = min(dfixed_trunc(a), tmp);
923
924	lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
925
926	a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
927	b.full = dfixed_const(1000);
928	c.full = dfixed_const(lb_fill_bw);
929	b.full = dfixed_div(A: c, B: b);
930	a.full = dfixed_div(A: a, B: b);
931	line_fill_time = dfixed_trunc(a);
932
933	if (line_fill_time < wm->active_time)
934	return latency;
935	else
936	return latency + (line_fill_time - wm->active_time);
937
938	}
939
940	/**
941	* dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display - check
942	* average and available dram bandwidth
943	*
944	* @wm: watermark calculation data
945	*
946	* Check if the display average bandwidth fits in the display
947	* dram bandwidth (CIK).
948	* Used for display watermark bandwidth calculations
949	* Returns true if the display fits, false if not.
950	*/
951	static bool dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm)
952	{
953	if (dce_v10_0_average_bandwidth(wm) <=
954	(dce_v10_0_dram_bandwidth_for_display(wm) / wm->num_heads))
955	return true;
956	else
957	return false;
958	}
959
960	/**
961	* dce_v10_0_average_bandwidth_vs_available_bandwidth - check
962	* average and available bandwidth
963	*
964	* @wm: watermark calculation data
965	*
966	* Check if the display average bandwidth fits in the display
967	* available bandwidth (CIK).
968	* Used for display watermark bandwidth calculations
969	* Returns true if the display fits, false if not.
970	*/
971	static bool dce_v10_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm)
972	{
973	if (dce_v10_0_average_bandwidth(wm) <=
974	(dce_v10_0_available_bandwidth(wm) / wm->num_heads))
975	return true;
976	else
977	return false;
978	}
979
980	/**
981	* dce_v10_0_check_latency_hiding - check latency hiding
982	*
983	* @wm: watermark calculation data
984	*
985	* Check latency hiding (CIK).
986	* Used for display watermark bandwidth calculations
987	* Returns true if the display fits, false if not.
988	*/
989	static bool dce_v10_0_check_latency_hiding(struct dce10_wm_params *wm)
990	{
991	u32 lb_partitions = wm->lb_size / wm->src_width;
992	u32 line_time = wm->active_time + wm->blank_time;
993	u32 latency_tolerant_lines;
994	u32 latency_hiding;
995	fixed20_12 a;
996
997	a.full = dfixed_const(1);
998	if (wm->vsc.full > a.full)
999	latency_tolerant_lines = 1;
1000	else {
1001	if (lb_partitions <= (wm->vtaps + 1))
1002	latency_tolerant_lines = 1;
1003	else
1004	latency_tolerant_lines = 2;
1005	}
1006
1007	latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
1008
1009	if (dce_v10_0_latency_watermark(wm) <= latency_hiding)
1010	return true;
1011	else
1012	return false;
1013	}
1014
1015	/**
1016	* dce_v10_0_program_watermarks - program display watermarks
1017	*
1018	* @adev: amdgpu_device pointer
1019	* @amdgpu_crtc: the selected display controller
1020	* @lb_size: line buffer size
1021	* @num_heads: number of display controllers in use
1022	*
1023	* Calculate and program the display watermarks for the
1024	* selected display controller (CIK).
1025	*/
1026	static void dce_v10_0_program_watermarks(struct amdgpu_device *adev,
1027	struct amdgpu_crtc *amdgpu_crtc,
1028	u32 lb_size, u32 num_heads)
1029	{
1030	struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
1031	struct dce10_wm_params wm_low, wm_high;
1032	u32 active_time;
1033	u32 line_time = 0;
1034	u32 latency_watermark_a = 0, latency_watermark_b = 0;
1035	u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
1036
1037	if (amdgpu_crtc->base.enabled && num_heads && mode) {
1038	active_time = (u32) div_u64(dividend: (u64)mode->crtc_hdisplay * 1000000,
1039	divisor: (u32)mode->clock);
1040	line_time = (u32) div_u64(dividend: (u64)mode->crtc_htotal * 1000000,
1041	divisor: (u32)mode->clock);
1042	line_time = min_t(u32, line_time, 65535);
1043
1044	/* watermark for high clocks */
1045	if (adev->pm.dpm_enabled) {
1046	wm_high.yclk =
1047	amdgpu_dpm_get_mclk(adev, low: false) * 10;
1048	wm_high.sclk =
1049	amdgpu_dpm_get_sclk(adev, low: false) * 10;
1050	} else {
1051	wm_high.yclk = adev->pm.current_mclk * 10;
1052	wm_high.sclk = adev->pm.current_sclk * 10;
1053	}
1054
1055	wm_high.disp_clk = mode->clock;
1056	wm_high.src_width = mode->crtc_hdisplay;
1057	wm_high.active_time = active_time;
1058	wm_high.blank_time = line_time - wm_high.active_time;
1059	wm_high.interlaced = false;
1060	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1061	wm_high.interlaced = true;
1062	wm_high.vsc = amdgpu_crtc->vsc;
1063	wm_high.vtaps = 1;
1064	if (amdgpu_crtc->rmx_type != RMX_OFF)
1065	wm_high.vtaps = 2;
1066	wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1067	wm_high.lb_size = lb_size;
1068	wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1069	wm_high.num_heads = num_heads;
1070
1071	/* set for high clocks */
1072	latency_watermark_a = min_t(u32, dce_v10_0_latency_watermark(&wm_high), 65535);
1073
1074	/* possibly force display priority to high */
1075	/* should really do this at mode validation time... */
1076	if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(wm: &wm_high) ||
1077	!dce_v10_0_average_bandwidth_vs_available_bandwidth(wm: &wm_high) ||
1078	!dce_v10_0_check_latency_hiding(wm: &wm_high) ||
1079	(adev->mode_info.disp_priority == 2)) {
1080	DRM_DEBUG_KMS("force priority to high\n");
1081	}
1082
1083	/* watermark for low clocks */
1084	if (adev->pm.dpm_enabled) {
1085	wm_low.yclk =
1086	amdgpu_dpm_get_mclk(adev, low: true) * 10;
1087	wm_low.sclk =
1088	amdgpu_dpm_get_sclk(adev, low: true) * 10;
1089	} else {
1090	wm_low.yclk = adev->pm.current_mclk * 10;
1091	wm_low.sclk = adev->pm.current_sclk * 10;
1092	}
1093
1094	wm_low.disp_clk = mode->clock;
1095	wm_low.src_width = mode->crtc_hdisplay;
1096	wm_low.active_time = active_time;
1097	wm_low.blank_time = line_time - wm_low.active_time;
1098	wm_low.interlaced = false;
1099	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1100	wm_low.interlaced = true;
1101	wm_low.vsc = amdgpu_crtc->vsc;
1102	wm_low.vtaps = 1;
1103	if (amdgpu_crtc->rmx_type != RMX_OFF)
1104	wm_low.vtaps = 2;
1105	wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1106	wm_low.lb_size = lb_size;
1107	wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1108	wm_low.num_heads = num_heads;
1109
1110	/* set for low clocks */
1111	latency_watermark_b = min_t(u32, dce_v10_0_latency_watermark(&wm_low), 65535);
1112
1113	/* possibly force display priority to high */
1114	/* should really do this at mode validation time... */
1115	if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(wm: &wm_low) ||
1116	!dce_v10_0_average_bandwidth_vs_available_bandwidth(wm: &wm_low) ||
1117	!dce_v10_0_check_latency_hiding(wm: &wm_low) ||
1118	(adev->mode_info.disp_priority == 2)) {
1119	DRM_DEBUG_KMS("force priority to high\n");
1120	}
1121	lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
1122	}
1123
1124	/* select wm A */
1125	wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1126	tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);
1127	WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1128	tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1129	tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a);
1130	tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1131	WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1132	/* select wm B */
1133	tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);
1134	WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1135	tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1136	tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b);
1137	tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1138	WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1139	/* restore original selection */
1140	WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1141
1142	/* save values for DPM */
1143	amdgpu_crtc->line_time = line_time;
1144
1145	/* Save number of lines the linebuffer leads before the scanout */
1146	amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
1147	}
1148
1149	/**
1150	* dce_v10_0_bandwidth_update - program display watermarks
1151	*
1152	* @adev: amdgpu_device pointer
1153	*
1154	* Calculate and program the display watermarks and line
1155	* buffer allocation (CIK).
1156	*/
1157	static void dce_v10_0_bandwidth_update(struct amdgpu_device *adev)
1158	{
1159	struct drm_display_mode *mode = NULL;
1160	u32 num_heads = 0, lb_size;
1161	int i;
1162
1163	amdgpu_display_update_priority(adev);
1164
1165	for (i = 0; i < adev->mode_info.num_crtc; i++) {
1166	if (adev->mode_info.crtcs[i]->base.enabled)
1167	num_heads++;
1168	}
1169	for (i = 0; i < adev->mode_info.num_crtc; i++) {
1170	mode = &adev->mode_info.crtcs[i]->base.mode;
1171	lb_size = dce_v10_0_line_buffer_adjust(adev, amdgpu_crtc: adev->mode_info.crtcs[i], mode);
1172	dce_v10_0_program_watermarks(adev, amdgpu_crtc: adev->mode_info.crtcs[i],
1173	lb_size, num_heads);
1174	}
1175	}
1176
1177	static void dce_v10_0_audio_get_connected_pins(struct amdgpu_device *adev)
1178	{
1179	int i;
1180	u32 offset, tmp;
1181
1182	for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1183	offset = adev->mode_info.audio.pin[i].offset;
1184	tmp = RREG32_AUDIO_ENDPT(offset,
1185	ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1186	if (((tmp &
1187	AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1188	AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1189	adev->mode_info.audio.pin[i].connected = false;
1190	else
1191	adev->mode_info.audio.pin[i].connected = true;
1192	}
1193	}
1194
1195	static struct amdgpu_audio_pin *dce_v10_0_audio_get_pin(struct amdgpu_device *adev)
1196	{
1197	int i;
1198
1199	dce_v10_0_audio_get_connected_pins(adev);
1200
1201	for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1202	if (adev->mode_info.audio.pin[i].connected)
1203	return &adev->mode_info.audio.pin[i];
1204	}
1205	DRM_ERROR("No connected audio pins found!\n");
1206	return NULL;
1207	}
1208
1209	static void dce_v10_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1210	{
1211	struct amdgpu_device *adev = drm_to_adev(ddev: encoder->dev);
1212	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1213	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1214	u32 tmp;
1215
1216	if (!dig || !dig->afmt || !dig->afmt->pin)
1217	return;
1218
1219	tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset);
1220	tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);
1221	WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp);
1222	}
1223
1224	static void dce_v10_0_audio_write_latency_fields(struct drm_encoder *encoder,
1225	struct drm_display_mode *mode)
1226	{
1227	struct drm_device *dev = encoder->dev;
1228	struct amdgpu_device *adev = drm_to_adev(ddev: dev);
1229	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1230	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1231	struct drm_connector *connector;
1232	struct drm_connector_list_iter iter;
1233	struct amdgpu_connector *amdgpu_connector = NULL;
1234	u32 tmp;
1235	int interlace = 0;
1236
1237	if (!dig || !dig->afmt || !dig->afmt->pin)
1238	return;
1239
1240	drm_connector_list_iter_begin(dev, iter: &iter);
1241	drm_for_each_connector_iter(connector, &iter) {
1242	if (connector->encoder == encoder) {
1243	amdgpu_connector = to_amdgpu_connector(connector);
1244	break;
1245	}
1246	}
1247	drm_connector_list_iter_end(iter: &iter);
1248
1249	if (!amdgpu_connector) {
1250	DRM_ERROR("Couldn't find encoder's connector\n");
1251	return;
1252	}
1253
1254	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1255	interlace = 1;
1256	if (connector->latency_present[interlace]) {
1257	tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1258	VIDEO_LIPSYNC, connector->video_latency[interlace]);
1259	tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1260	AUDIO_LIPSYNC, connector->audio_latency[interlace]);
1261	} else {
1262	tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1263	VIDEO_LIPSYNC, 0);
1264	tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1265	AUDIO_LIPSYNC, 0);
1266	}
1267	WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1268	ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1269	}
1270
1271	static void dce_v10_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1272	{
1273	struct drm_device *dev = encoder->dev;
1274	struct amdgpu_device *adev = drm_to_adev(ddev: dev);
1275	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1276	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1277	struct drm_connector *connector;
1278	struct drm_connector_list_iter iter;
1279	struct amdgpu_connector *amdgpu_connector = NULL;
1280	u32 tmp;
1281	u8 *sadb = NULL;
1282	int sad_count;
1283
1284	if (!dig || !dig->afmt || !dig->afmt->pin)
1285	return;
1286
1287	drm_connector_list_iter_begin(dev, iter: &iter);
1288	drm_for_each_connector_iter(connector, &iter) {
1289	if (connector->encoder == encoder) {
1290	amdgpu_connector = to_amdgpu_connector(connector);
1291	break;
1292	}
1293	}
1294	drm_connector_list_iter_end(iter: &iter);
1295
1296	if (!amdgpu_connector) {
1297	DRM_ERROR("Couldn't find encoder's connector\n");
1298	return;
1299	}
1300
1301	sad_count = drm_edid_to_speaker_allocation(edid: amdgpu_connector->edid, sadb: &sadb);
1302	if (sad_count < 0) {
1303	DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1304	sad_count = 0;
1305	}
1306
1307	/* program the speaker allocation */
1308	tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1309	ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1310	tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1311	DP_CONNECTION, 0);
1312	/* set HDMI mode */
1313	tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1314	HDMI_CONNECTION, 1);
1315	if (sad_count)
1316	tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1317	SPEAKER_ALLOCATION, sadb[0]);
1318	else
1319	tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1320	SPEAKER_ALLOCATION, 5); /* stereo */
1321	WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1322	ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1323
1324	kfree(objp: sadb);
1325	}
1326
1327	static void dce_v10_0_audio_write_sad_regs(struct drm_encoder *encoder)
1328	{
1329	struct drm_device *dev = encoder->dev;
1330	struct amdgpu_device *adev = drm_to_adev(ddev: dev);
1331	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1332	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1333	struct drm_connector *connector;
1334	struct drm_connector_list_iter iter;
1335	struct amdgpu_connector *amdgpu_connector = NULL;
1336	struct cea_sad *sads;
1337	int i, sad_count;
1338
1339	static const u16 eld_reg_to_type[][2] = {
1340	{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1341	{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1342	{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1343	{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1344	{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1345	{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1346	{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1347	{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1348	{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1349	{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1350	{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1351	{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1352	};
1353
1354	if (!dig || !dig->afmt || !dig->afmt->pin)
1355	return;
1356
1357	drm_connector_list_iter_begin(dev, iter: &iter);
1358	drm_for_each_connector_iter(connector, &iter) {
1359	if (connector->encoder == encoder) {
1360	amdgpu_connector = to_amdgpu_connector(connector);
1361	break;
1362	}
1363	}
1364	drm_connector_list_iter_end(iter: &iter);
1365
1366	if (!amdgpu_connector) {
1367	DRM_ERROR("Couldn't find encoder's connector\n");
1368	return;
1369	}
1370
1371	sad_count = drm_edid_to_sad(edid: amdgpu_connector->edid, sads: &sads);
1372	if (sad_count < 0)
1373	DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1374	if (sad_count <= 0)
1375	return;
1376	BUG_ON(!sads);
1377
1378	for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1379	u32 tmp = 0;
1380	u8 stereo_freqs = 0;
1381	int max_channels = -1;
1382	int j;
1383
1384	for (j = 0; j < sad_count; j++) {
1385	struct cea_sad *sad = &sads[j];
1386
1387	if (sad->format == eld_reg_to_type[i][1]) {
1388	if (sad->channels > max_channels) {
1389	tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1390	MAX_CHANNELS, sad->channels);
1391	tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1392	DESCRIPTOR_BYTE_2, sad->byte2);
1393	tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1394	SUPPORTED_FREQUENCIES, sad->freq);
1395	max_channels = sad->channels;
1396	}
1397
1398	if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1399	stereo_freqs |= sad->freq;
1400	else
1401	break;
1402	}
1403	}
1404
1405	tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1406	SUPPORTED_FREQUENCIES_STEREO, stereo_freqs);
1407	WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);
1408	}
1409
1410	kfree(objp: sads);
1411	}
1412
1413	static void dce_v10_0_audio_enable(struct amdgpu_device *adev,
1414	struct amdgpu_audio_pin *pin,
1415	bool enable)
1416	{
1417	if (!pin)
1418	return;
1419
1420	WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1421	enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1422	}
1423
1424	static const u32 pin_offsets[] = {
1425	AUD0_REGISTER_OFFSET,
1426	AUD1_REGISTER_OFFSET,
1427	AUD2_REGISTER_OFFSET,
1428	AUD3_REGISTER_OFFSET,
1429	AUD4_REGISTER_OFFSET,
1430	AUD5_REGISTER_OFFSET,
1431	AUD6_REGISTER_OFFSET,
1432	};
1433
1434	static int dce_v10_0_audio_init(struct amdgpu_device *adev)
1435	{
1436	int i;
1437
1438	if (!amdgpu_audio)
1439	return 0;
1440
1441	adev->mode_info.audio.enabled = true;
1442
1443	adev->mode_info.audio.num_pins = 7;
1444
1445	for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1446	adev->mode_info.audio.pin[i].channels = -1;
1447	adev->mode_info.audio.pin[i].rate = -1;
1448	adev->mode_info.audio.pin[i].bits_per_sample = -1;
1449	adev->mode_info.audio.pin[i].status_bits = 0;
1450	adev->mode_info.audio.pin[i].category_code = 0;
1451	adev->mode_info.audio.pin[i].connected = false;
1452	adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1453	adev->mode_info.audio.pin[i].id = i;
1454	/* disable audio. it will be set up later */
1455	/* XXX remove once we switch to ip funcs */
1456	dce_v10_0_audio_enable(adev, pin: &adev->mode_info.audio.pin[i], enable: false);
1457	}
1458
1459	return 0;
1460	}
1461
1462	static void dce_v10_0_audio_fini(struct amdgpu_device *adev)
1463	{
1464	if (!amdgpu_audio)
1465	return;
1466
1467	if (!adev->mode_info.audio.enabled)
1468	return;
1469
1470	adev->mode_info.audio.enabled = false;
1471	}
1472
1473	/*
1474	* update the N and CTS parameters for a given pixel clock rate
1475	*/
1476	static void dce_v10_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1477	{
1478	struct drm_device *dev = encoder->dev;
1479	struct amdgpu_device *adev = drm_to_adev(ddev: dev);
1480	struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1481	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1482	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1483	u32 tmp;
1484
1485	tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
1486	tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
1487	WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
1488	tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
1489	tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
1490	WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
1491
1492	tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
1493	tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
1494	WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
1495	tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
1496	tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
1497	WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
1498
1499	tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
1500	tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
1501	WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
1502	tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
1503	tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
1504	WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
1505
1506	}
1507
1508	/*
1509	* build a HDMI Video Info Frame
1510	*/
1511	static void dce_v10_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1512	void *buffer, size_t size)
1513	{
1514	struct drm_device *dev = encoder->dev;
1515	struct amdgpu_device *adev = drm_to_adev(ddev: dev);
1516	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1517	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1518	uint8_t *frame = buffer + 3;
1519	uint8_t *header = buffer;
1520
1521	WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,
1522	frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1523	WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,
1524	frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1525	WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,
1526	frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1527	WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,
1528	frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1529	}
1530
1531	static void dce_v10_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1532	{
1533	struct drm_device *dev = encoder->dev;
1534	struct amdgpu_device *adev = drm_to_adev(ddev: dev);
1535	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1536	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1537	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1538	u32 dto_phase = 24 * 1000;
1539	u32 dto_modulo = clock;
1540	u32 tmp;
1541
1542	if (!dig || !dig->afmt)
1543	return;
1544
1545	/* XXX two dtos; generally use dto0 for hdmi */
1546	/* Express [24MHz / target pixel clock] as an exact rational
1547	* number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
1548	* is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1549	*/
1550	tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
1551	tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,
1552	amdgpu_crtc->crtc_id);
1553	WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
1554	WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1555	WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1556	}
1557
1558	/*
1559	* update the info frames with the data from the current display mode
1560	*/
1561	static void dce_v10_0_afmt_setmode(struct drm_encoder *encoder,
1562	struct drm_display_mode *mode)
1563	{
1564	struct drm_device *dev = encoder->dev;
1565	struct amdgpu_device *adev = drm_to_adev(ddev: dev);
1566	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1567	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1568	struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1569	u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1570	struct hdmi_avi_infoframe frame;
1571	ssize_t err;
1572	u32 tmp;
1573	int bpc = 8;
1574
1575	if (!dig || !dig->afmt)
1576	return;
1577
1578	/* Silent, r600_hdmi_enable will raise WARN for us */
1579	if (!dig->afmt->enabled)
1580	return;
1581
1582	/* hdmi deep color mode general control packets setup, if bpc > 8 */
1583	if (encoder->crtc) {
1584	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1585	bpc = amdgpu_crtc->bpc;
1586	}
1587
1588	/* disable audio prior to setting up hw */
1589	dig->afmt->pin = dce_v10_0_audio_get_pin(adev);
1590	dce_v10_0_audio_enable(adev, pin: dig->afmt->pin, enable: false);
1591
1592	dce_v10_0_audio_set_dto(encoder, clock: mode->clock);
1593
1594	tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1595	tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
1596	WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */
1597
1598	WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000);
1599
1600	tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset);
1601	switch (bpc) {
1602	case 0:
1603	case 6:
1604	case 8:
1605	case 16:
1606	default:
1607	tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);
1608	tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
1609	DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1610	connector->name, bpc);
1611	break;
1612	case 10:
1613	tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1614	tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);
1615	DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1616	connector->name);
1617	break;
1618	case 12:
1619	tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1620	tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);
1621	DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1622	connector->name);
1623	break;
1624	}
1625	WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp);
1626
1627	tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1628	tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */
1629	tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */
1630	tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */
1631	WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
1632
1633	tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1634	/* enable audio info frames (frames won't be set until audio is enabled) */
1635	tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
1636	/* required for audio info values to be updated */
1637	tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
1638	WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1639
1640	tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
1641	/* required for audio info values to be updated */
1642	tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1643	WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1644
1645	tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1646	/* anything other than 0 */
1647	tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);
1648	WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1649
1650	WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */
1651
1652	tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1653	/* set the default audio delay */
1654	tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
1655	/* should be suffient for all audio modes and small enough for all hblanks */
1656	tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
1657	WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1658
1659	tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1660	/* allow 60958 channel status fields to be updated */
1661	tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1662	WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1663
1664	tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
1665	if (bpc > 8)
1666	/* clear SW CTS value */
1667	tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
1668	else
1669	/* select SW CTS value */
1670	tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
1671	/* allow hw to sent ACR packets when required */
1672	tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
1673	WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
1674
1675	dce_v10_0_afmt_update_ACR(encoder, clock: mode->clock);
1676
1677	tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);
1678	tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
1679	WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);
1680
1681	tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);
1682	tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1683	WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);
1684
1685	tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);
1686	tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
1687	tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
1688	tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
1689	tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
1690	tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
1691	tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1692	WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);
1693
1694	dce_v10_0_audio_write_speaker_allocation(encoder);
1695
1696	WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset,
1697	(0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1698
1699	dce_v10_0_afmt_audio_select_pin(encoder);
1700	dce_v10_0_audio_write_sad_regs(encoder);
1701	dce_v10_0_audio_write_latency_fields(encoder, mode);
1702
1703	err = drm_hdmi_avi_infoframe_from_display_mode(frame: &frame, connector, mode);
1704	if (err < 0) {
1705	DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1706	return;
1707	}
1708
1709	err = hdmi_avi_infoframe_pack(frame: &frame, buffer, size: sizeof(buffer));
1710	if (err < 0) {
1711	DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1712	return;
1713	}
1714
1715	dce_v10_0_afmt_update_avi_infoframe(encoder, buffer, size: sizeof(buffer));
1716
1717	tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1718	/* enable AVI info frames */
1719	tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
1720	/* required for audio info values to be updated */
1721	tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
1722	WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1723
1724	tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1725	tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
1726	WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1727
1728	tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1729	/* send audio packets */
1730	tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
1731	WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1732
1733	WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF);
1734	WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF);
1735	WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001);
1736	WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001);
1737
1738	/* enable audio after to setting up hw */
1739	dce_v10_0_audio_enable(adev, pin: dig->afmt->pin, enable: true);
1740	}
1741
1742	static void dce_v10_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1743	{
1744	struct drm_device *dev = encoder->dev;
1745	struct amdgpu_device *adev = drm_to_adev(ddev: dev);
1746	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1747	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1748
1749	if (!dig || !dig->afmt)
1750	return;
1751
1752	/* Silent, r600_hdmi_enable will raise WARN for us */
1753	if (enable && dig->afmt->enabled)
1754	return;
1755	if (!enable && !dig->afmt->enabled)
1756	return;
1757
1758	if (!enable && dig->afmt->pin) {
1759	dce_v10_0_audio_enable(adev, pin: dig->afmt->pin, enable: false);
1760	dig->afmt->pin = NULL;
1761	}
1762
1763	dig->afmt->enabled = enable;
1764
1765	DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1766	enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1767	}
1768
1769	static int dce_v10_0_afmt_init(struct amdgpu_device *adev)
1770	{
1771	int i;
1772
1773	for (i = 0; i < adev->mode_info.num_dig; i++)
1774	adev->mode_info.afmt[i] = NULL;
1775
1776	/* DCE10 has audio blocks tied to DIG encoders */
1777	for (i = 0; i < adev->mode_info.num_dig; i++) {
1778	adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1779	if (adev->mode_info.afmt[i]) {
1780	adev->mode_info.afmt[i]->offset = dig_offsets[i];
1781	adev->mode_info.afmt[i]->id = i;
1782	} else {
1783	int j;
1784	for (j = 0; j < i; j++) {
1785	kfree(objp: adev->mode_info.afmt[j]);
1786	adev->mode_info.afmt[j] = NULL;
1787	}
1788	return -ENOMEM;
1789	}
1790	}
1791	return 0;
1792	}
1793
1794	static void dce_v10_0_afmt_fini(struct amdgpu_device *adev)
1795	{
1796	int i;
1797
1798	for (i = 0; i < adev->mode_info.num_dig; i++) {
1799	kfree(objp: adev->mode_info.afmt[i]);
1800	adev->mode_info.afmt[i] = NULL;
1801	}
1802	}
1803
1804	static const u32 vga_control_regs[6] = {
1805	mmD1VGA_CONTROL,
1806	mmD2VGA_CONTROL,
1807	mmD3VGA_CONTROL,
1808	mmD4VGA_CONTROL,
1809	mmD5VGA_CONTROL,
1810	mmD6VGA_CONTROL,
1811	};
1812
1813	static void dce_v10_0_vga_enable(struct drm_crtc *crtc, bool enable)
1814	{
1815	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1816	struct drm_device *dev = crtc->dev;
1817	struct amdgpu_device *adev = drm_to_adev(ddev: dev);
1818	u32 vga_control;
1819
1820	vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
1821	if (enable)
1822	WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
1823	else
1824	WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
1825	}
1826
1827	static void dce_v10_0_grph_enable(struct drm_crtc *crtc, bool enable)
1828	{
1829	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1830	struct drm_device *dev = crtc->dev;
1831	struct amdgpu_device *adev = drm_to_adev(ddev: dev);
1832
1833	if (enable)
1834	WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
1835	else
1836	WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
1837	}
1838
1839	static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc,
1840	struct drm_framebuffer *fb,
1841	int x, int y, int atomic)
1842	{
1843	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1844	struct drm_device *dev = crtc->dev;
1845	struct amdgpu_device *adev = drm_to_adev(ddev: dev);
1846	struct drm_framebuffer *target_fb;
1847	struct drm_gem_object *obj;
1848	struct amdgpu_bo *abo;
1849	uint64_t fb_location, tiling_flags;
1850	uint32_t fb_format, fb_pitch_pixels;
1851	u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE);
1852	u32 pipe_config;
1853	u32 tmp, viewport_w, viewport_h;
1854	int r;
1855	bool bypass_lut = false;
1856
1857	/* no fb bound */
1858	if (!atomic && !crtc->primary->fb) {
1859	DRM_DEBUG_KMS("No FB bound\n");
1860	return 0;
1861	}
1862
1863	if (atomic)
1864	target_fb = fb;
1865	else
1866	target_fb = crtc->primary->fb;
1867
1868	/* If atomic, assume fb object is pinned & idle & fenced and
1869	* just update base pointers
1870	*/
1871	obj = target_fb->obj[0];
1872	abo = gem_to_amdgpu_bo(obj);
1873	r = amdgpu_bo_reserve(bo: abo, no_intr: false);
1874	if (unlikely(r != 0))
1875	return r;
1876
1877	if (!atomic) {
1878	abo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
1879	r = amdgpu_bo_pin(bo: abo, AMDGPU_GEM_DOMAIN_VRAM);
1880	if (unlikely(r != 0)) {
1881	amdgpu_bo_unreserve(bo: abo);
1882	return -EINVAL;
1883	}
1884	}
1885	fb_location = amdgpu_bo_gpu_offset(bo: abo);
1886
1887	amdgpu_bo_get_tiling_flags(bo: abo, tiling_flags: &tiling_flags);
1888	amdgpu_bo_unreserve(bo: abo);
1889
1890	pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1891
1892	switch (target_fb->format->format) {
1893	case DRM_FORMAT_C8:
1894	fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0);
1895	fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1896	break;
1897	case DRM_FORMAT_XRGB4444:
1898	case DRM_FORMAT_ARGB4444:
1899	fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1900	fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2);
1901	#ifdef __BIG_ENDIAN
1902	fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1903	ENDIAN_8IN16);
1904	#endif
1905	break;
1906	case DRM_FORMAT_XRGB1555:
1907	case DRM_FORMAT_ARGB1555:
1908	fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1909	fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1910	#ifdef __BIG_ENDIAN
1911	fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1912	ENDIAN_8IN16);
1913	#endif
1914	break;
1915	case DRM_FORMAT_BGRX5551:
1916	case DRM_FORMAT_BGRA5551:
1917	fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1918	fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5);
1919	#ifdef __BIG_ENDIAN
1920	fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1921	ENDIAN_8IN16);
1922	#endif
1923	break;
1924	case DRM_FORMAT_RGB565:
1925	fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1926	fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
1927	#ifdef __BIG_ENDIAN
1928	fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1929	ENDIAN_8IN16);
1930	#endif
1931	break;
1932	case DRM_FORMAT_XRGB8888:
1933	case DRM_FORMAT_ARGB8888:
1934	fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
1935	fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1936	#ifdef __BIG_ENDIAN
1937	fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1938	ENDIAN_8IN32);
1939	#endif
1940	break;
1941	case DRM_FORMAT_XRGB2101010:
1942	case DRM_FORMAT_ARGB2101010:
1943	fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
1944	fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
1945	#ifdef __BIG_ENDIAN
1946	fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1947	ENDIAN_8IN32);
1948	#endif
1949	/* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1950	bypass_lut = true;
1951	break;
1952	case DRM_FORMAT_BGRX1010102:
1953	case DRM_FORMAT_BGRA1010102:
1954	fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
1955	fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4);
1956	#ifdef __BIG_ENDIAN
1957	fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1958	ENDIAN_8IN32);
1959	#endif
1960	/* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1961	bypass_lut = true;
1962	break;
1963	case DRM_FORMAT_XBGR8888:
1964	case DRM_FORMAT_ABGR8888:
1965	fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
1966	fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1967	fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_RED_CROSSBAR, 2);
1968	fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_BLUE_CROSSBAR, 2);
1969	#ifdef __BIG_ENDIAN
1970	fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1971	ENDIAN_8IN32);
1972	#endif
1973	break;
1974	default:
1975	DRM_ERROR("Unsupported screen format %p4cc\n",
1976	&target_fb->format->format);
1977	return -EINVAL;
1978	}
1979
1980	if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
1981	unsigned bankw, bankh, mtaspect, tile_split, num_banks;
1982
1983	bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
1984	bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
1985	mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
1986	tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
1987	num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
1988
1989	fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks);
1990	fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
1991	ARRAY_2D_TILED_THIN1);
1992	fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT,
1993	tile_split);
1994	fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw);
1995	fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh);
1996	fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT,
1997	mtaspect);
1998	fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE,
1999	ADDR_SURF_MICRO_TILING_DISPLAY);
2000	} else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
2001	fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2002	ARRAY_1D_TILED_THIN1);
2003	}
2004
2005	fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG,
2006	pipe_config);
2007
2008	dce_v10_0_vga_enable(crtc, enable: false);
2009
2010	/* Make sure surface address is updated at vertical blank rather than
2011	* horizontal blank
2012	*/
2013	tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
2014	tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
2015	GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);
2016	WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2017
2018	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2019	upper_32_bits(fb_location));
2020	WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2021	upper_32_bits(fb_location));
2022	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2023	(u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
2024	WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2025	(u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
2026	WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
2027	WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
2028
2029	/*
2030	* The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2031	* for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2032	* retain the full precision throughout the pipeline.
2033	*/
2034	tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset);
2035	if (bypass_lut)
2036	tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1);
2037	else
2038	tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0);
2039	WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp);
2040
2041	if (bypass_lut)
2042	DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2043
2044	WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
2045	WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
2046	WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
2047	WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
2048	WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
2049	WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
2050
2051	fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0];
2052	WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
2053
2054	dce_v10_0_grph_enable(crtc, enable: true);
2055
2056	WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
2057	target_fb->height);
2058
2059	x &= ~3;
2060	y &= ~1;
2061	WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
2062	(x << 16) | y);
2063	viewport_w = crtc->mode.hdisplay;
2064	viewport_h = (crtc->mode.vdisplay + 1) & ~1;
2065	WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2066	(viewport_w << 16) | viewport_h);
2067
2068	/* set pageflip to happen anywhere in vblank interval */
2069	WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
2070
2071	if (!atomic && fb && fb != crtc->primary->fb) {
2072	abo = gem_to_amdgpu_bo(fb->obj[0]);
2073	r = amdgpu_bo_reserve(bo: abo, no_intr: true);
2074	if (unlikely(r != 0))
2075	return r;
2076	amdgpu_bo_unpin(bo: abo);
2077	amdgpu_bo_unreserve(bo: abo);
2078	}
2079
2080	/* Bytes per pixel may have changed */
2081	dce_v10_0_bandwidth_update(adev);
2082
2083	return 0;
2084	}
2085
2086	static void dce_v10_0_set_interleave(struct drm_crtc *crtc,
2087	struct drm_display_mode *mode)
2088	{
2089	struct drm_device *dev = crtc->dev;
2090	struct amdgpu_device *adev = drm_to_adev(ddev: dev);
2091	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2092	u32 tmp;
2093
2094	tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset);
2095	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2096	tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1);
2097	else
2098	tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0);
2099	WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp);
2100	}
2101
2102	static void dce_v10_0_crtc_load_lut(struct drm_crtc *crtc)
2103	{
2104	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2105	struct drm_device *dev = crtc->dev;
2106	struct amdgpu_device *adev = drm_to_adev(ddev: dev);
2107	u16 *r, *g, *b;
2108	int i;
2109	u32 tmp;
2110
2111	DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2112
2113	tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2114	tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0);
2115	tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_OVL_MODE, 0);
2116	WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2117
2118	tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset);
2119	tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
2120	WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2121
2122	tmp = RREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset);
2123	tmp = REG_SET_FIELD(tmp, PRESCALE_OVL_CONTROL, OVL_PRESCALE_BYPASS, 1);
2124	WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2125
2126	tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2127	tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
2128	tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, OVL_INPUT_GAMMA_MODE, 0);
2129	WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2130
2131	WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2132
2133	WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2134	WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2135	WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2136
2137	WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2138	WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2139	WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2140
2141	WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2142	WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2143
2144	WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2145	r = crtc->gamma_store;
2146	g = r + crtc->gamma_size;
2147	b = g + crtc->gamma_size;
2148	for (i = 0; i < 256; i++) {
2149	WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2150	((*r++ & 0xffc0) << 14) |
2151	((*g++ & 0xffc0) << 4) |
2152	(*b++ >> 6));
2153	}
2154
2155	tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2156	tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0);
2157	tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, OVL_DEGAMMA_MODE, 0);
2158	tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0);
2159	WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2160
2161	tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset);
2162	tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0);
2163	tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, OVL_GAMUT_REMAP_MODE, 0);
2164	WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2165
2166	tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2167	tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0);
2168	tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, OVL_REGAMMA_MODE, 0);
2169	WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2170
2171	tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2172	tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0);
2173	tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_OVL_MODE, 0);
2174	WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2175
2176	/* XXX match this to the depth of the crtc fmt block, move to modeset? */
2177	WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0);
2178	/* XXX this only needs to be programmed once per crtc at startup,
2179	* not sure where the best place for it is
2180	*/
2181	tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset);
2182	tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1);
2183	WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2184	}
2185
2186	static int dce_v10_0_pick_dig_encoder(struct drm_encoder *encoder)
2187	{
2188	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2189	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2190
2191	switch (amdgpu_encoder->encoder_id) {
2192	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2193	if (dig->linkb)
2194	return 1;
2195	else
2196	return 0;
2197	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2198	if (dig->linkb)
2199	return 3;
2200	else
2201	return 2;
2202	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2203	if (dig->linkb)
2204	return 5;
2205	else
2206	return 4;
2207	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2208	return 6;
2209	default:
2210	DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2211	return 0;
2212	}
2213	}
2214
2215	/**
2216	* dce_v10_0_pick_pll - Allocate a PPLL for use by the crtc.
2217	*
2218	* @crtc: drm crtc
2219	*
2220	* Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2221	* a single PPLL can be used for all DP crtcs/encoders. For non-DP
2222	* monitors a dedicated PPLL must be used. If a particular board has
2223	* an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2224	* as there is no need to program the PLL itself. If we are not able to
2225	* allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2226	* avoid messing up an existing monitor.
2227	*
2228	* Asic specific PLL information
2229	*
2230	* DCE 10.x
2231	* Tonga
2232	* - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2233	* CI
2234	* - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2235	*
2236	*/
2237	static u32 dce_v10_0_pick_pll(struct drm_crtc *crtc)
2238	{
2239	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2240	struct drm_device *dev = crtc->dev;
2241	struct amdgpu_device *adev = drm_to_adev(ddev: dev);
2242	u32 pll_in_use;
2243	int pll;
2244
2245	if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2246	if (adev->clock.dp_extclk)
2247	/* skip PPLL programming if using ext clock */
2248	return ATOM_PPLL_INVALID;
2249	else {
2250	/* use the same PPLL for all DP monitors */
2251	pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2252	if (pll != ATOM_PPLL_INVALID)
2253	return pll;
2254	}
2255	} else {
2256	/* use the same PPLL for all monitors with the same clock */
2257	pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2258	if (pll != ATOM_PPLL_INVALID)
2259	return pll;
2260	}
2261
2262	/* DCE10 has PPLL0, PPLL1, and PPLL2 */
2263	pll_in_use = amdgpu_pll_get_use_mask(crtc);
2264	if (!(pll_in_use & (1 << ATOM_PPLL2)))
2265	return ATOM_PPLL2;
2266	if (!(pll_in_use & (1 << ATOM_PPLL1)))
2267	return ATOM_PPLL1;
2268	if (!(pll_in_use & (1 << ATOM_PPLL0)))
2269	return ATOM_PPLL0;
2270	DRM_ERROR("unable to allocate a PPLL\n");
2271	return ATOM_PPLL_INVALID;
2272	}
2273
2274	static void dce_v10_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2275	{
2276	struct amdgpu_device *adev = drm_to_adev(ddev: crtc->dev);
2277	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2278	uint32_t cur_lock;
2279
2280	cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2281	if (lock)
2282	cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1);
2283	else
2284	cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0);
2285	WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2286	}
2287
2288	static void dce_v10_0_hide_cursor(struct drm_crtc *crtc)
2289	{
2290	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2291	struct amdgpu_device *adev = drm_to_adev(ddev: crtc->dev);
2292	u32 tmp;
2293
2294	tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2295	tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);
2296	WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2297	}
2298
2299	static void dce_v10_0_show_cursor(struct drm_crtc *crtc)
2300	{
2301	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2302	struct amdgpu_device *adev = drm_to_adev(ddev: crtc->dev);
2303	u32 tmp;
2304
2305	WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2306	upper_32_bits(amdgpu_crtc->cursor_addr));
2307	WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2308	lower_32_bits(amdgpu_crtc->cursor_addr));
2309
2310	tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2311	tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);
2312	tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);
2313	WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2314	}
2315
2316	static int dce_v10_0_cursor_move_locked(struct drm_crtc *crtc,
2317	int x, int y)
2318	{
2319	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2320	struct amdgpu_device *adev = drm_to_adev(ddev: crtc->dev);
2321	int xorigin = 0, yorigin = 0;
2322
2323	amdgpu_crtc->cursor_x = x;
2324	amdgpu_crtc->cursor_y = y;
2325
2326	/* avivo cursor are offset into the total surface */
2327	x += crtc->x;
2328	y += crtc->y;
2329	DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2330
2331	if (x < 0) {
2332	xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2333	x = 0;
2334	}
2335	if (y < 0) {
2336	yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2337	y = 0;
2338	}
2339
2340	WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2341	WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2342	WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2343	((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2344
2345	return 0;
2346	}
2347
2348	static int dce_v10_0_crtc_cursor_move(struct drm_crtc *crtc,
2349	int x, int y)
2350	{
2351	int ret;
2352
2353	dce_v10_0_lock_cursor(crtc, lock: true);
2354	ret = dce_v10_0_cursor_move_locked(crtc, x, y);
2355	dce_v10_0_lock_cursor(crtc, lock: false);
2356
2357	return ret;
2358	}
2359
2360	static int dce_v10_0_crtc_cursor_set2(struct drm_crtc *crtc,
2361	struct drm_file *file_priv,
2362	uint32_t handle,
2363	uint32_t width,
2364	uint32_t height,
2365	int32_t hot_x,
2366	int32_t hot_y)
2367	{
2368	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2369	struct drm_gem_object *obj;
2370	struct amdgpu_bo *aobj;
2371	int ret;
2372
2373	if (!handle) {
2374	/* turn off cursor */
2375	dce_v10_0_hide_cursor(crtc);
2376	obj = NULL;
2377	goto unpin;
2378	}
2379
2380	if ((width > amdgpu_crtc->max_cursor_width) ||
2381	(height > amdgpu_crtc->max_cursor_height)) {
2382	DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2383	return -EINVAL;
2384	}
2385
2386	obj = drm_gem_object_lookup(filp: file_priv, handle);
2387	if (!obj) {
2388	DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2389	return -ENOENT;
2390	}
2391
2392	aobj = gem_to_amdgpu_bo(obj);
2393	ret = amdgpu_bo_reserve(bo: aobj, no_intr: false);
2394	if (ret != 0) {
2395	drm_gem_object_put(obj);
2396	return ret;
2397	}
2398
2399	aobj->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
2400	ret = amdgpu_bo_pin(bo: aobj, AMDGPU_GEM_DOMAIN_VRAM);
2401	amdgpu_bo_unreserve(bo: aobj);
2402	if (ret) {
2403	DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2404	drm_gem_object_put(obj);
2405	return ret;
2406	}
2407	amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(bo: aobj);
2408
2409	dce_v10_0_lock_cursor(crtc, lock: true);
2410
2411	if (width != amdgpu_crtc->cursor_width ||
2412	height != amdgpu_crtc->cursor_height ||
2413	hot_x != amdgpu_crtc->cursor_hot_x ||
2414	hot_y != amdgpu_crtc->cursor_hot_y) {
2415	int x, y;
2416
2417	x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2418	y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2419
2420	dce_v10_0_cursor_move_locked(crtc, x, y);
2421
2422	amdgpu_crtc->cursor_width = width;
2423	amdgpu_crtc->cursor_height = height;
2424	amdgpu_crtc->cursor_hot_x = hot_x;
2425	amdgpu_crtc->cursor_hot_y = hot_y;
2426	}
2427
2428	dce_v10_0_show_cursor(crtc);
2429	dce_v10_0_lock_cursor(crtc, lock: false);
2430
2431	unpin:
2432	if (amdgpu_crtc->cursor_bo) {
2433	struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2434	ret = amdgpu_bo_reserve(bo: aobj, no_intr: true);
2435	if (likely(ret == 0)) {
2436	amdgpu_bo_unpin(bo: aobj);
2437	amdgpu_bo_unreserve(bo: aobj);
2438	}
2439	drm_gem_object_put(obj: amdgpu_crtc->cursor_bo);
2440	}
2441
2442	amdgpu_crtc->cursor_bo = obj;
2443	return 0;
2444	}
2445
2446	static void dce_v10_0_cursor_reset(struct drm_crtc *crtc)
2447	{
2448	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2449
2450	if (amdgpu_crtc->cursor_bo) {
2451	dce_v10_0_lock_cursor(crtc, lock: true);
2452
2453	dce_v10_0_cursor_move_locked(crtc, x: amdgpu_crtc->cursor_x,
2454	y: amdgpu_crtc->cursor_y);
2455
2456	dce_v10_0_show_cursor(crtc);
2457
2458	dce_v10_0_lock_cursor(crtc, lock: false);
2459	}
2460	}
2461
2462	static int dce_v10_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2463	u16 *blue, uint32_t size,
2464	struct drm_modeset_acquire_ctx *ctx)
2465	{
2466	dce_v10_0_crtc_load_lut(crtc);
2467
2468	return 0;
2469	}
2470
2471	static void dce_v10_0_crtc_destroy(struct drm_crtc *crtc)
2472	{
2473	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2474
2475	drm_crtc_cleanup(crtc);
2476	kfree(objp: amdgpu_crtc);
2477	}
2478
2479	static const struct drm_crtc_funcs dce_v10_0_crtc_funcs = {
2480	.cursor_set2 = dce_v10_0_crtc_cursor_set2,
2481	.cursor_move = dce_v10_0_crtc_cursor_move,
2482	.gamma_set = dce_v10_0_crtc_gamma_set,
2483	.set_config = amdgpu_display_crtc_set_config,
2484	.destroy = dce_v10_0_crtc_destroy,
2485	.page_flip_target = amdgpu_display_crtc_page_flip_target,
2486	.get_vblank_counter = amdgpu_get_vblank_counter_kms,
2487	.enable_vblank = amdgpu_enable_vblank_kms,
2488	.disable_vblank = amdgpu_disable_vblank_kms,
2489	.get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
2490	};
2491
2492	static void dce_v10_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2493	{
2494	struct drm_device *dev = crtc->dev;
2495	struct amdgpu_device *adev = drm_to_adev(ddev: dev);
2496	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2497	unsigned type;
2498
2499	switch (mode) {
2500	case DRM_MODE_DPMS_ON:
2501	amdgpu_crtc->enabled = true;
2502	amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2503	dce_v10_0_vga_enable(crtc, enable: true);
2504	amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2505	dce_v10_0_vga_enable(crtc, enable: false);
2506	/* Make sure VBLANK and PFLIP interrupts are still enabled */
2507	type = amdgpu_display_crtc_idx_to_irq_type(adev,
2508	crtc: amdgpu_crtc->crtc_id);
2509	amdgpu_irq_update(adev, src: &adev->crtc_irq, type);
2510	amdgpu_irq_update(adev, src: &adev->pageflip_irq, type);
2511	drm_crtc_vblank_on(crtc);
2512	dce_v10_0_crtc_load_lut(crtc);
2513	break;
2514	case DRM_MODE_DPMS_STANDBY:
2515	case DRM_MODE_DPMS_SUSPEND:
2516	case DRM_MODE_DPMS_OFF:
2517	drm_crtc_vblank_off(crtc);
2518	if (amdgpu_crtc->enabled) {
2519	dce_v10_0_vga_enable(crtc, enable: true);
2520	amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2521	dce_v10_0_vga_enable(crtc, enable: false);
2522	}
2523	amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2524	amdgpu_crtc->enabled = false;
2525	break;
2526	}
2527	/* adjust pm to dpms */
2528	amdgpu_dpm_compute_clocks(adev);
2529	}
2530
2531	static void dce_v10_0_crtc_prepare(struct drm_crtc *crtc)
2532	{
2533	/* disable crtc pair power gating before programming */
2534	amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2535	amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2536	dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2537	}
2538
2539	static void dce_v10_0_crtc_commit(struct drm_crtc *crtc)
2540	{
2541	dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2542	amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2543	}
2544
2545	static void dce_v10_0_crtc_disable(struct drm_crtc *crtc)
2546	{
2547	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2548	struct drm_device *dev = crtc->dev;
2549	struct amdgpu_device *adev = drm_to_adev(ddev: dev);
2550	struct amdgpu_atom_ss ss;
2551	int i;
2552
2553	dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2554	if (crtc->primary->fb) {
2555	int r;
2556	struct amdgpu_bo *abo;
2557
2558	abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]);
2559	r = amdgpu_bo_reserve(bo: abo, no_intr: true);
2560	if (unlikely(r))
2561	DRM_ERROR("failed to reserve abo before unpin\n");
2562	else {
2563	amdgpu_bo_unpin(bo: abo);
2564	amdgpu_bo_unreserve(bo: abo);
2565	}
2566	}
2567	/* disable the GRPH */
2568	dce_v10_0_grph_enable(crtc, enable: false);
2569
2570	amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2571
2572	for (i = 0; i < adev->mode_info.num_crtc; i++) {
2573	if (adev->mode_info.crtcs[i] &&
2574	adev->mode_info.crtcs[i]->enabled &&
2575	i != amdgpu_crtc->crtc_id &&
2576	amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2577	/* one other crtc is using this pll don't turn
2578	* off the pll
2579	*/
2580	goto done;
2581	}
2582	}
2583
2584	switch (amdgpu_crtc->pll_id) {
2585	case ATOM_PPLL0:
2586	case ATOM_PPLL1:
2587	case ATOM_PPLL2:
2588	/* disable the ppll */
2589	amdgpu_atombios_crtc_program_pll(crtc, crtc_id: amdgpu_crtc->crtc_id, pll_id: amdgpu_crtc->pll_id,
2590	encoder_mode: 0, encoder_id: 0, ATOM_DISABLE, ref_div: 0, fb_div: 0, frac_fb_div: 0, post_div: 0, bpc: 0, ss_enabled: false, ss: &ss);
2591	break;
2592	default:
2593	break;
2594	}
2595	done:
2596	amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2597	amdgpu_crtc->adjusted_clock = 0;
2598	amdgpu_crtc->encoder = NULL;
2599	amdgpu_crtc->connector = NULL;
2600	}
2601
2602	static int dce_v10_0_crtc_mode_set(struct drm_crtc *crtc,
2603	struct drm_display_mode *mode,
2604	struct drm_display_mode *adjusted_mode,
2605	int x, int y, struct drm_framebuffer *old_fb)
2606	{
2607	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2608
2609	if (!amdgpu_crtc->adjusted_clock)
2610	return -EINVAL;
2611
2612	amdgpu_atombios_crtc_set_pll(crtc, mode: adjusted_mode);
2613	amdgpu_atombios_crtc_set_dtd_timing(crtc, mode: adjusted_mode);
2614	dce_v10_0_crtc_do_set_base(crtc, fb: old_fb, x, y, atomic: 0);
2615	amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2616	amdgpu_atombios_crtc_scaler_setup(crtc);
2617	dce_v10_0_cursor_reset(crtc);
2618	/* update the hw version fpr dpm */
2619	amdgpu_crtc->hw_mode = *adjusted_mode;
2620
2621	return 0;
2622	}
2623
2624	static bool dce_v10_0_crtc_mode_fixup(struct drm_crtc *crtc,
2625	const struct drm_display_mode *mode,
2626	struct drm_display_mode *adjusted_mode)
2627	{
2628	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2629	struct drm_device *dev = crtc->dev;
2630	struct drm_encoder *encoder;
2631
2632	/* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2633	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2634	if (encoder->crtc == crtc) {
2635	amdgpu_crtc->encoder = encoder;
2636	amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2637	break;
2638	}
2639	}
2640	if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2641	amdgpu_crtc->encoder = NULL;
2642	amdgpu_crtc->connector = NULL;
2643	return false;
2644	}
2645	if (!amdgpu_display_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2646	return false;
2647	if (amdgpu_atombios_crtc_prepare_pll(crtc, mode: adjusted_mode))
2648	return false;
2649	/* pick pll */
2650	amdgpu_crtc->pll_id = dce_v10_0_pick_pll(crtc);
2651	/* if we can't get a PPLL for a non-DP encoder, fail */
2652	if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2653	!ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2654	return false;
2655
2656	return true;
2657	}
2658
2659	static int dce_v10_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2660	struct drm_framebuffer *old_fb)
2661	{
2662	return dce_v10_0_crtc_do_set_base(crtc, fb: old_fb, x, y, atomic: 0);
2663	}
2664
2665	static int dce_v10_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2666	struct drm_framebuffer *fb,
2667	int x, int y, enum mode_set_atomic state)
2668	{
2669	return dce_v10_0_crtc_do_set_base(crtc, fb, x, y, atomic: 1);
2670	}
2671
2672	static const struct drm_crtc_helper_funcs dce_v10_0_crtc_helper_funcs = {
2673	.dpms = dce_v10_0_crtc_dpms,
2674	.mode_fixup = dce_v10_0_crtc_mode_fixup,
2675	.mode_set = dce_v10_0_crtc_mode_set,
2676	.mode_set_base = dce_v10_0_crtc_set_base,
2677	.mode_set_base_atomic = dce_v10_0_crtc_set_base_atomic,
2678	.prepare = dce_v10_0_crtc_prepare,
2679	.commit = dce_v10_0_crtc_commit,
2680	.disable = dce_v10_0_crtc_disable,
2681	.get_scanout_position = amdgpu_crtc_get_scanout_position,
2682	};
2683
2684	static void dce_v10_0_panic_flush(struct drm_plane *plane)
2685	{
2686	struct drm_framebuffer *fb;
2687	struct amdgpu_crtc *amdgpu_crtc;
2688	struct amdgpu_device *adev;
2689	uint32_t fb_format;
2690
2691	if (!plane->fb)
2692	return;
2693
2694	fb = plane->fb;
2695	amdgpu_crtc = to_amdgpu_crtc(plane->crtc);
2696	adev = drm_to_adev(ddev: fb->dev);
2697
2698	/* Disable DC tiling */
2699	fb_format = RREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset);
2700	fb_format &= ~GRPH_CONTROL__GRPH_ARRAY_MODE_MASK;
2701	WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
2702
2703	}
2704
2705	static const struct drm_plane_helper_funcs dce_v10_0_drm_primary_plane_helper_funcs = {
2706	.get_scanout_buffer = amdgpu_display_get_scanout_buffer,
2707	.panic_flush = dce_v10_0_panic_flush,
2708	};
2709
2710	static int dce_v10_0_crtc_init(struct amdgpu_device *adev, int index)
2711	{
2712	struct amdgpu_crtc *amdgpu_crtc;
2713
2714	amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2715	(AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2716	if (amdgpu_crtc == NULL)
2717	return -ENOMEM;
2718
2719	drm_crtc_init(dev: adev_to_drm(adev), crtc: &amdgpu_crtc->base, funcs: &dce_v10_0_crtc_funcs);
2720
2721	drm_mode_crtc_set_gamma_size(crtc: &amdgpu_crtc->base, gamma_size: 256);
2722	amdgpu_crtc->crtc_id = index;
2723	adev->mode_info.crtcs[index] = amdgpu_crtc;
2724
2725	amdgpu_crtc->max_cursor_width = 128;
2726	amdgpu_crtc->max_cursor_height = 128;
2727	adev_to_drm(adev)->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2728	adev_to_drm(adev)->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2729
2730	switch (amdgpu_crtc->crtc_id) {
2731	case 0:
2732	default:
2733	amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET;
2734	break;
2735	case 1:
2736	amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET;
2737	break;
2738	case 2:
2739	amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET;
2740	break;
2741	case 3:
2742	amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET;
2743	break;
2744	case 4:
2745	amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET;
2746	break;
2747	case 5:
2748	amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET;
2749	break;
2750	}
2751
2752	amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2753	amdgpu_crtc->adjusted_clock = 0;
2754	amdgpu_crtc->encoder = NULL;
2755	amdgpu_crtc->connector = NULL;
2756	drm_crtc_helper_add(crtc: &amdgpu_crtc->base, funcs: &dce_v10_0_crtc_helper_funcs);
2757	drm_plane_helper_add(plane: amdgpu_crtc->base.primary, funcs: &dce_v10_0_drm_primary_plane_helper_funcs);
2758
2759	return 0;
2760	}
2761
2762	static int dce_v10_0_early_init(struct amdgpu_ip_block *ip_block)
2763	{
2764	struct amdgpu_device *adev = ip_block->adev;
2765
2766	adev->audio_endpt_rreg = &dce_v10_0_audio_endpt_rreg;
2767	adev->audio_endpt_wreg = &dce_v10_0_audio_endpt_wreg;
2768
2769	dce_v10_0_set_display_funcs(adev);
2770
2771	adev->mode_info.num_crtc = dce_v10_0_get_num_crtc(adev);
2772
2773	switch (adev->asic_type) {
2774	case CHIP_FIJI:
2775	case CHIP_TONGA:
2776	adev->mode_info.num_hpd = 6;
2777	adev->mode_info.num_dig = 7;
2778	break;
2779	default:
2780	/* FIXME: not supported yet */
2781	return -EINVAL;
2782	}
2783
2784	dce_v10_0_set_irq_funcs(adev);
2785
2786	return 0;
2787	}
2788
2789	static int dce_v10_0_sw_init(struct amdgpu_ip_block *ip_block)
2790	{
2791	int r, i;
2792	struct amdgpu_device *adev = ip_block->adev;
2793
2794	for (i = 0; i < adev->mode_info.num_crtc; i++) {
2795	r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, src_id: i + 1, source: &adev->crtc_irq);
2796	if (r)
2797	return r;
2798	}
2799
2800	for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; i < 20; i += 2) {
2801	r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, src_id: i, source: &adev->pageflip_irq);
2802	if (r)
2803	return r;
2804	}
2805
2806	/* HPD hotplug */
2807	r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, source: &adev->hpd_irq);
2808	if (r)
2809	return r;
2810
2811	adev_to_drm(adev)->mode_config.funcs = &amdgpu_mode_funcs;
2812
2813	adev_to_drm(adev)->mode_config.async_page_flip = true;
2814
2815	adev_to_drm(adev)->mode_config.max_width = 16384;
2816	adev_to_drm(adev)->mode_config.max_height = 16384;
2817
2818	adev_to_drm(adev)->mode_config.preferred_depth = 24;
2819	adev_to_drm(adev)->mode_config.prefer_shadow = 1;
2820
2821	adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true;
2822
2823	r = amdgpu_display_modeset_create_props(adev);
2824	if (r)
2825	return r;
2826
2827	adev_to_drm(adev)->mode_config.max_width = 16384;
2828	adev_to_drm(adev)->mode_config.max_height = 16384;
2829
2830	/* allocate crtcs */
2831	for (i = 0; i < adev->mode_info.num_crtc; i++) {
2832	r = dce_v10_0_crtc_init(adev, index: i);
2833	if (r)
2834	return r;
2835	}
2836
2837	if (amdgpu_atombios_get_connector_info_from_object_table(adev))
2838	amdgpu_display_print_display_setup(dev: adev_to_drm(adev));
2839	else
2840	return -EINVAL;
2841
2842	/* setup afmt */
2843	r = dce_v10_0_afmt_init(adev);
2844	if (r)
2845	return r;
2846
2847	r = dce_v10_0_audio_init(adev);
2848	if (r)
2849	return r;
2850
2851	/* Disable vblank IRQs aggressively for power-saving */
2852	/* XXX: can this be enabled for DC? */
2853	adev_to_drm(adev)->vblank_disable_immediate = true;
2854
2855	r = drm_vblank_init(dev: adev_to_drm(adev), num_crtcs: adev->mode_info.num_crtc);
2856	if (r)
2857	return r;
2858
2859	INIT_DELAYED_WORK(&adev->hotplug_work,
2860	amdgpu_display_hotplug_work_func);
2861
2862	drm_kms_helper_poll_init(dev: adev_to_drm(adev));
2863
2864	adev->mode_info.mode_config_initialized = true;
2865	return 0;
2866	}
2867
2868	static int dce_v10_0_sw_fini(struct amdgpu_ip_block *ip_block)
2869	{
2870	struct amdgpu_device *adev = ip_block->adev;
2871
2872	drm_edid_free(drm_edid: adev->mode_info.bios_hardcoded_edid);
2873
2874	drm_kms_helper_poll_fini(dev: adev_to_drm(adev));
2875
2876	dce_v10_0_audio_fini(adev);
2877
2878	dce_v10_0_afmt_fini(adev);
2879
2880	drm_mode_config_cleanup(dev: adev_to_drm(adev));
2881	adev->mode_info.mode_config_initialized = false;
2882
2883	return 0;
2884	}
2885
2886	static int dce_v10_0_hw_init(struct amdgpu_ip_block *ip_block)
2887	{
2888	int i;
2889	struct amdgpu_device *adev = ip_block->adev;
2890
2891	dce_v10_0_init_golden_registers(adev);
2892
2893	/* disable vga render */
2894	dce_v10_0_set_vga_render_state(adev, render: false);
2895	/* init dig PHYs, disp eng pll */
2896	amdgpu_atombios_encoder_init_dig(adev);
2897	amdgpu_atombios_crtc_set_disp_eng_pll(adev, dispclk: adev->clock.default_dispclk);
2898
2899	/* initialize hpd */
2900	dce_v10_0_hpd_init(adev);
2901
2902	for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2903	dce_v10_0_audio_enable(adev, pin: &adev->mode_info.audio.pin[i], enable: false);
2904	}
2905
2906	dce_v10_0_pageflip_interrupt_init(adev);
2907
2908	return 0;
2909	}
2910
2911	static int dce_v10_0_hw_fini(struct amdgpu_ip_block *ip_block)
2912	{
2913	int i;
2914	struct amdgpu_device *adev = ip_block->adev;
2915
2916	dce_v10_0_hpd_fini(adev);
2917
2918	for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2919	dce_v10_0_audio_enable(adev, pin: &adev->mode_info.audio.pin[i], enable: false);
2920	}
2921
2922	dce_v10_0_pageflip_interrupt_fini(adev);
2923
2924	flush_delayed_work(dwork: &adev->hotplug_work);
2925
2926	return 0;
2927	}
2928
2929	static int dce_v10_0_suspend(struct amdgpu_ip_block *ip_block)
2930	{
2931	struct amdgpu_device *adev = ip_block->adev;
2932	int r;
2933
2934	r = amdgpu_display_suspend_helper(adev);
2935	if (r)
2936	return r;
2937
2938	adev->mode_info.bl_level =
2939	amdgpu_atombios_encoder_get_backlight_level_from_reg(adev);
2940
2941	return dce_v10_0_hw_fini(ip_block);
2942	}
2943
2944	static int dce_v10_0_resume(struct amdgpu_ip_block *ip_block)
2945	{
2946	struct amdgpu_device *adev = ip_block->adev;
2947	int ret;
2948
2949	amdgpu_atombios_encoder_set_backlight_level_to_reg(adev,
2950	backlight_level: adev->mode_info.bl_level);
2951
2952	ret = dce_v10_0_hw_init(ip_block);
2953
2954	/* turn on the BL */
2955	if (adev->mode_info.bl_encoder) {
2956	u8 bl_level = amdgpu_display_backlight_get_level(adev,
2957	adev->mode_info.bl_encoder);
2958	amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
2959	bl_level);
2960	}
2961	if (ret)
2962	return ret;
2963
2964	return amdgpu_display_resume_helper(adev);
2965	}
2966
2967	static bool dce_v10_0_is_idle(struct amdgpu_ip_block *ip_block)
2968	{
2969	return true;
2970	}
2971
2972	static bool dce_v10_0_check_soft_reset(struct amdgpu_ip_block *ip_block)
2973	{
2974	struct amdgpu_device *adev = ip_block->adev;
2975
2976	return dce_v10_0_is_display_hung(adev);
2977	}
2978
2979	static int dce_v10_0_soft_reset(struct amdgpu_ip_block *ip_block)
2980	{
2981	u32 srbm_soft_reset = 0, tmp;
2982	struct amdgpu_device *adev = ip_block->adev;
2983
2984	if (dce_v10_0_is_display_hung(adev))
2985	srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
2986
2987	if (srbm_soft_reset) {
2988	tmp = RREG32(mmSRBM_SOFT_RESET);
2989	tmp |= srbm_soft_reset;
2990	dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
2991	WREG32(mmSRBM_SOFT_RESET, tmp);
2992	tmp = RREG32(mmSRBM_SOFT_RESET);
2993
2994	udelay(usec: 50);
2995
2996	tmp &= ~srbm_soft_reset;
2997	WREG32(mmSRBM_SOFT_RESET, tmp);
2998	tmp = RREG32(mmSRBM_SOFT_RESET);
2999
3000	/* Wait a little for things to settle down */
3001	udelay(usec: 50);
3002	}
3003	return 0;
3004	}
3005
3006	static void dce_v10_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
3007	int crtc,
3008	enum amdgpu_interrupt_state state)
3009	{
3010	u32 lb_interrupt_mask;
3011
3012	if (crtc >= adev->mode_info.num_crtc) {
3013	DRM_DEBUG("invalid crtc %d\n", crtc);
3014	return;
3015	}
3016
3017	switch (state) {
3018	case AMDGPU_IRQ_STATE_DISABLE:
3019	lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3020	lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3021	VBLANK_INTERRUPT_MASK, 0);
3022	WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3023	break;
3024	case AMDGPU_IRQ_STATE_ENABLE:
3025	lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3026	lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3027	VBLANK_INTERRUPT_MASK, 1);
3028	WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3029	break;
3030	default:
3031	break;
3032	}
3033	}
3034
3035	static void dce_v10_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
3036	int crtc,
3037	enum amdgpu_interrupt_state state)
3038	{
3039	u32 lb_interrupt_mask;
3040
3041	if (crtc >= adev->mode_info.num_crtc) {
3042	DRM_DEBUG("invalid crtc %d\n", crtc);
3043	return;
3044	}
3045
3046	switch (state) {
3047	case AMDGPU_IRQ_STATE_DISABLE:
3048	lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3049	lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3050	VLINE_INTERRUPT_MASK, 0);
3051	WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3052	break;
3053	case AMDGPU_IRQ_STATE_ENABLE:
3054	lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3055	lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3056	VLINE_INTERRUPT_MASK, 1);
3057	WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3058	break;
3059	default:
3060	break;
3061	}
3062	}
3063
3064	static int dce_v10_0_set_hpd_irq_state(struct amdgpu_device *adev,
3065	struct amdgpu_irq_src *source,
3066	unsigned hpd,
3067	enum amdgpu_interrupt_state state)
3068	{
3069	u32 tmp;
3070
3071	if (hpd >= adev->mode_info.num_hpd) {
3072	DRM_DEBUG("invalid hpd %d\n", hpd);
3073	return 0;
3074	}
3075
3076	switch (state) {
3077	case AMDGPU_IRQ_STATE_DISABLE:
3078	tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3079	tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
3080	WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3081	break;
3082	case AMDGPU_IRQ_STATE_ENABLE:
3083	tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3084	tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1);
3085	WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3086	break;
3087	default:
3088	break;
3089	}
3090
3091	return 0;
3092	}
3093
3094	static int dce_v10_0_set_crtc_irq_state(struct amdgpu_device *adev,
3095	struct amdgpu_irq_src *source,
3096	unsigned type,
3097	enum amdgpu_interrupt_state state)
3098	{
3099	switch (type) {
3100	case AMDGPU_CRTC_IRQ_VBLANK1:
3101	dce_v10_0_set_crtc_vblank_interrupt_state(adev, crtc: 0, state);
3102	break;
3103	case AMDGPU_CRTC_IRQ_VBLANK2:
3104	dce_v10_0_set_crtc_vblank_interrupt_state(adev, crtc: 1, state);
3105	break;
3106	case AMDGPU_CRTC_IRQ_VBLANK3:
3107	dce_v10_0_set_crtc_vblank_interrupt_state(adev, crtc: 2, state);
3108	break;
3109	case AMDGPU_CRTC_IRQ_VBLANK4:
3110	dce_v10_0_set_crtc_vblank_interrupt_state(adev, crtc: 3, state);
3111	break;
3112	case AMDGPU_CRTC_IRQ_VBLANK5:
3113	dce_v10_0_set_crtc_vblank_interrupt_state(adev, crtc: 4, state);
3114	break;
3115	case AMDGPU_CRTC_IRQ_VBLANK6:
3116	dce_v10_0_set_crtc_vblank_interrupt_state(adev, crtc: 5, state);
3117	break;
3118	case AMDGPU_CRTC_IRQ_VLINE1:
3119	dce_v10_0_set_crtc_vline_interrupt_state(adev, crtc: 0, state);
3120	break;
3121	case AMDGPU_CRTC_IRQ_VLINE2:
3122	dce_v10_0_set_crtc_vline_interrupt_state(adev, crtc: 1, state);
3123	break;
3124	case AMDGPU_CRTC_IRQ_VLINE3:
3125	dce_v10_0_set_crtc_vline_interrupt_state(adev, crtc: 2, state);
3126	break;
3127	case AMDGPU_CRTC_IRQ_VLINE4:
3128	dce_v10_0_set_crtc_vline_interrupt_state(adev, crtc: 3, state);
3129	break;
3130	case AMDGPU_CRTC_IRQ_VLINE5:
3131	dce_v10_0_set_crtc_vline_interrupt_state(adev, crtc: 4, state);
3132	break;
3133	case AMDGPU_CRTC_IRQ_VLINE6:
3134	dce_v10_0_set_crtc_vline_interrupt_state(adev, crtc: 5, state);
3135	break;
3136	default:
3137	break;
3138	}
3139	return 0;
3140	}
3141
3142	static int dce_v10_0_set_pageflip_irq_state(struct amdgpu_device *adev,
3143	struct amdgpu_irq_src *src,
3144	unsigned type,
3145	enum amdgpu_interrupt_state state)
3146	{
3147	u32 reg;
3148
3149	if (type >= adev->mode_info.num_crtc) {
3150	DRM_ERROR("invalid pageflip crtc %d\n", type);
3151	return -EINVAL;
3152	}
3153
3154	reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
3155	if (state == AMDGPU_IRQ_STATE_DISABLE)
3156	WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3157	reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3158	else
3159	WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3160	reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3161
3162	return 0;
3163	}
3164
3165	static int dce_v10_0_pageflip_irq(struct amdgpu_device *adev,
3166	struct amdgpu_irq_src *source,
3167	struct amdgpu_iv_entry *entry)
3168	{
3169	unsigned long flags;
3170	unsigned crtc_id;
3171	struct amdgpu_crtc *amdgpu_crtc;
3172	struct amdgpu_flip_work *works;
3173
3174	crtc_id = (entry->src_id - 8) >> 1;
3175	amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3176
3177	if (crtc_id >= adev->mode_info.num_crtc) {
3178	DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3179	return -EINVAL;
3180	}
3181
3182	if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3183	GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3184	WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3185	GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
3186
3187	/* IRQ could occur when in initial stage */
3188	if (amdgpu_crtc == NULL)
3189	return 0;
3190
3191	spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
3192	works = amdgpu_crtc->pflip_works;
3193	if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
3194	DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3195	"AMDGPU_FLIP_SUBMITTED(%d)\n",
3196	amdgpu_crtc->pflip_status,
3197	AMDGPU_FLIP_SUBMITTED);
3198	spin_unlock_irqrestore(lock: &adev_to_drm(adev)->event_lock, flags);
3199	return 0;
3200	}
3201
3202	/* page flip completed. clean up */
3203	amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3204	amdgpu_crtc->pflip_works = NULL;
3205
3206	/* wakeup usersapce */
3207	if (works->event)
3208	drm_crtc_send_vblank_event(crtc: &amdgpu_crtc->base, e: works->event);
3209
3210	spin_unlock_irqrestore(lock: &adev_to_drm(adev)->event_lock, flags);
3211
3212	drm_crtc_vblank_put(crtc: &amdgpu_crtc->base);
3213	schedule_work(work: &works->unpin_work);
3214
3215	return 0;
3216	}
3217
3218	static void dce_v10_0_hpd_int_ack(struct amdgpu_device *adev,
3219	int hpd)
3220	{
3221	u32 tmp;
3222
3223	if (hpd >= adev->mode_info.num_hpd) {
3224	DRM_DEBUG("invalid hpd %d\n", hpd);
3225	return;
3226	}
3227
3228	tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3229	tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1);
3230	WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3231	}
3232
3233	static void dce_v10_0_crtc_vblank_int_ack(struct amdgpu_device *adev,
3234	int crtc)
3235	{
3236	u32 tmp;
3237
3238	if (crtc >= adev->mode_info.num_crtc) {
3239	DRM_DEBUG("invalid crtc %d\n", crtc);
3240	return;
3241	}
3242
3243	tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]);
3244	tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1);
3245	WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp);
3246	}
3247
3248	static void dce_v10_0_crtc_vline_int_ack(struct amdgpu_device *adev,
3249	int crtc)
3250	{
3251	u32 tmp;
3252
3253	if (crtc >= adev->mode_info.num_crtc) {
3254	DRM_DEBUG("invalid crtc %d\n", crtc);
3255	return;
3256	}
3257
3258	tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]);
3259	tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1);
3260	WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp);
3261	}
3262
3263	static int dce_v10_0_crtc_irq(struct amdgpu_device *adev,
3264	struct amdgpu_irq_src *source,
3265	struct amdgpu_iv_entry *entry)
3266	{
3267	unsigned crtc = entry->src_id - 1;
3268	uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3269	unsigned int irq_type = amdgpu_display_crtc_idx_to_irq_type(adev, crtc);
3270
3271	switch (entry->src_data[0]) {
3272	case 0: /* vblank */
3273	if (disp_int & interrupt_status_offsets[crtc].vblank)
3274	dce_v10_0_crtc_vblank_int_ack(adev, crtc);
3275	else
3276	DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3277
3278	if (amdgpu_irq_enabled(adev, src: source, type: irq_type)) {
3279	drm_handle_vblank(dev: adev_to_drm(adev), pipe: crtc);
3280	}
3281	DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3282
3283	break;
3284	case 1: /* vline */
3285	if (disp_int & interrupt_status_offsets[crtc].vline)
3286	dce_v10_0_crtc_vline_int_ack(adev, crtc);
3287	else
3288	DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3289
3290	DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3291
3292	break;
3293	default:
3294	DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
3295	break;
3296	}
3297
3298	return 0;
3299	}
3300
3301	static int dce_v10_0_hpd_irq(struct amdgpu_device *adev,
3302	struct amdgpu_irq_src *source,
3303	struct amdgpu_iv_entry *entry)
3304	{
3305	uint32_t disp_int, mask;
3306	unsigned hpd;
3307
3308	if (entry->src_data[0] >= adev->mode_info.num_hpd) {
3309	DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
3310	return 0;
3311	}
3312
3313	hpd = entry->src_data[0];
3314	disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3315	mask = interrupt_status_offsets[hpd].hpd;
3316
3317	if (disp_int & mask) {
3318	dce_v10_0_hpd_int_ack(adev, hpd);
3319	schedule_delayed_work(dwork: &adev->hotplug_work, delay: 0);
3320	DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3321	}
3322
3323	return 0;
3324	}
3325
3326	static int dce_v10_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
3327	enum amd_clockgating_state state)
3328	{
3329	return 0;
3330	}
3331
3332	static int dce_v10_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
3333	enum amd_powergating_state state)
3334	{
3335	return 0;
3336	}
3337
3338	static const struct amd_ip_funcs dce_v10_0_ip_funcs = {
3339	.name = "dce_v10_0",
3340	.early_init = dce_v10_0_early_init,
3341	.sw_init = dce_v10_0_sw_init,
3342	.sw_fini = dce_v10_0_sw_fini,
3343	.hw_init = dce_v10_0_hw_init,
3344	.hw_fini = dce_v10_0_hw_fini,
3345	.suspend = dce_v10_0_suspend,
3346	.resume = dce_v10_0_resume,
3347	.is_idle = dce_v10_0_is_idle,
3348	.check_soft_reset = dce_v10_0_check_soft_reset,
3349	.soft_reset = dce_v10_0_soft_reset,
3350	.set_clockgating_state = dce_v10_0_set_clockgating_state,
3351	.set_powergating_state = dce_v10_0_set_powergating_state,
3352	};
3353
3354	static void
3355	dce_v10_0_encoder_mode_set(struct drm_encoder *encoder,
3356	struct drm_display_mode *mode,
3357	struct drm_display_mode *adjusted_mode)
3358	{
3359	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3360
3361	amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3362
3363	/* need to call this here rather than in prepare() since we need some crtc info */
3364	amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3365
3366	/* set scaler clears this on some chips */
3367	dce_v10_0_set_interleave(crtc: encoder->crtc, mode);
3368
3369	if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3370	dce_v10_0_afmt_enable(encoder, enable: true);
3371	dce_v10_0_afmt_setmode(encoder, mode: adjusted_mode);
3372	}
3373	}
3374
3375	static void dce_v10_0_encoder_prepare(struct drm_encoder *encoder)
3376	{
3377	struct amdgpu_device *adev = drm_to_adev(ddev: encoder->dev);
3378	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3379	struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3380
3381	if ((amdgpu_encoder->active_device &
3382	(ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3383	(amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3384	ENCODER_OBJECT_ID_NONE)) {
3385	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3386	if (dig) {
3387	dig->dig_encoder = dce_v10_0_pick_dig_encoder(encoder);
3388	if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3389	dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3390	}
3391	}
3392
3393	amdgpu_atombios_scratch_regs_lock(adev, lock: true);
3394
3395	if (connector) {
3396	struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3397
3398	/* select the clock/data port if it uses a router */
3399	if (amdgpu_connector->router.cd_valid)
3400	amdgpu_i2c_router_select_cd_port(connector: amdgpu_connector);
3401
3402	/* turn eDP panel on for mode set */
3403	if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3404	amdgpu_atombios_encoder_set_edp_panel_power(connector,
3405	ATOM_TRANSMITTER_ACTION_POWER_ON);
3406	}
3407
3408	/* this is needed for the pll/ss setup to work correctly in some cases */
3409	amdgpu_atombios_encoder_set_crtc_source(encoder);
3410	/* set up the FMT blocks */
3411	dce_v10_0_program_fmt(encoder);
3412	}
3413
3414	static void dce_v10_0_encoder_commit(struct drm_encoder *encoder)
3415	{
3416	struct drm_device *dev = encoder->dev;
3417	struct amdgpu_device *adev = drm_to_adev(ddev: dev);
3418
3419	/* need to call this here as we need the crtc set up */
3420	amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3421	amdgpu_atombios_scratch_regs_lock(adev, lock: false);
3422	}
3423
3424	static void dce_v10_0_encoder_disable(struct drm_encoder *encoder)
3425	{
3426	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3427	struct amdgpu_encoder_atom_dig *dig;
3428
3429	amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3430
3431	if (amdgpu_atombios_encoder_is_digital(encoder)) {
3432	if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3433	dce_v10_0_afmt_enable(encoder, enable: false);
3434	dig = amdgpu_encoder->enc_priv;
3435	dig->dig_encoder = -1;
3436	}
3437	amdgpu_encoder->active_device = 0;
3438	}
3439
3440	/* these are handled by the primary encoders */
3441	static void dce_v10_0_ext_prepare(struct drm_encoder *encoder)
3442	{
3443
3444	}
3445
3446	static void dce_v10_0_ext_commit(struct drm_encoder *encoder)
3447	{
3448
3449	}
3450
3451	static void
3452	dce_v10_0_ext_mode_set(struct drm_encoder *encoder,
3453	struct drm_display_mode *mode,
3454	struct drm_display_mode *adjusted_mode)
3455	{
3456
3457	}
3458
3459	static void dce_v10_0_ext_disable(struct drm_encoder *encoder)
3460	{
3461
3462	}
3463
3464	static void
3465	dce_v10_0_ext_dpms(struct drm_encoder *encoder, int mode)
3466	{
3467
3468	}
3469
3470	static const struct drm_encoder_helper_funcs dce_v10_0_ext_helper_funcs = {
3471	.dpms = dce_v10_0_ext_dpms,
3472	.prepare = dce_v10_0_ext_prepare,
3473	.mode_set = dce_v10_0_ext_mode_set,
3474	.commit = dce_v10_0_ext_commit,
3475	.disable = dce_v10_0_ext_disable,
3476	/* no detect for TMDS/LVDS yet */
3477	};
3478
3479	static const struct drm_encoder_helper_funcs dce_v10_0_dig_helper_funcs = {
3480	.dpms = amdgpu_atombios_encoder_dpms,
3481	.mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3482	.prepare = dce_v10_0_encoder_prepare,
3483	.mode_set = dce_v10_0_encoder_mode_set,
3484	.commit = dce_v10_0_encoder_commit,
3485	.disable = dce_v10_0_encoder_disable,
3486	.detect = amdgpu_atombios_encoder_dig_detect,
3487	};
3488
3489	static const struct drm_encoder_helper_funcs dce_v10_0_dac_helper_funcs = {
3490	.dpms = amdgpu_atombios_encoder_dpms,
3491	.mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3492	.prepare = dce_v10_0_encoder_prepare,
3493	.mode_set = dce_v10_0_encoder_mode_set,
3494	.commit = dce_v10_0_encoder_commit,
3495	.detect = amdgpu_atombios_encoder_dac_detect,
3496	};
3497
3498	static void dce_v10_0_encoder_destroy(struct drm_encoder *encoder)
3499	{
3500	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3501	if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3502	amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3503	kfree(objp: amdgpu_encoder->enc_priv);
3504	drm_encoder_cleanup(encoder);
3505	kfree(objp: amdgpu_encoder);
3506	}
3507
3508	static const struct drm_encoder_funcs dce_v10_0_encoder_funcs = {
3509	.destroy = dce_v10_0_encoder_destroy,
3510	};
3511
3512	static void dce_v10_0_encoder_add(struct amdgpu_device *adev,
3513	uint32_t encoder_enum,
3514	uint32_t supported_device,
3515	u16 caps)
3516	{
3517	struct drm_device *dev = adev_to_drm(adev);
3518	struct drm_encoder *encoder;
3519	struct amdgpu_encoder *amdgpu_encoder;
3520
3521	/* see if we already added it */
3522	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3523	amdgpu_encoder = to_amdgpu_encoder(encoder);
3524	if (amdgpu_encoder->encoder_enum == encoder_enum) {
3525	amdgpu_encoder->devices |= supported_device;
3526	return;
3527	}
3528
3529	}
3530
3531	/* add a new one */
3532	amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3533	if (!amdgpu_encoder)
3534	return;
3535
3536	encoder = &amdgpu_encoder->base;
3537	switch (adev->mode_info.num_crtc) {
3538	case 1:
3539	encoder->possible_crtcs = 0x1;
3540	break;
3541	case 2:
3542	default:
3543	encoder->possible_crtcs = 0x3;
3544	break;
3545	case 4:
3546	encoder->possible_crtcs = 0xf;
3547	break;
3548	case 6:
3549	encoder->possible_crtcs = 0x3f;
3550	break;
3551	}
3552
3553	amdgpu_encoder->enc_priv = NULL;
3554
3555	amdgpu_encoder->encoder_enum = encoder_enum;
3556	amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3557	amdgpu_encoder->devices = supported_device;
3558	amdgpu_encoder->rmx_type = RMX_OFF;
3559	amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3560	amdgpu_encoder->is_ext_encoder = false;
3561	amdgpu_encoder->caps = caps;
3562
3563	switch (amdgpu_encoder->encoder_id) {
3564	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3565	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3566	drm_encoder_init(dev, encoder, funcs: &dce_v10_0_encoder_funcs,
3567	DRM_MODE_ENCODER_DAC, NULL);
3568	drm_encoder_helper_add(encoder, funcs: &dce_v10_0_dac_helper_funcs);
3569	break;
3570	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3571	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3572	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3573	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3574	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3575	if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3576	amdgpu_encoder->rmx_type = RMX_FULL;
3577	drm_encoder_init(dev, encoder, funcs: &dce_v10_0_encoder_funcs,
3578	DRM_MODE_ENCODER_LVDS, NULL);
3579	amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(encoder: amdgpu_encoder);
3580	} else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3581	drm_encoder_init(dev, encoder, funcs: &dce_v10_0_encoder_funcs,
3582	DRM_MODE_ENCODER_DAC, NULL);
3583	amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3584	} else {
3585	drm_encoder_init(dev, encoder, funcs: &dce_v10_0_encoder_funcs,
3586	DRM_MODE_ENCODER_TMDS, NULL);
3587	amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3588	}
3589	drm_encoder_helper_add(encoder, funcs: &dce_v10_0_dig_helper_funcs);
3590	break;
3591	case ENCODER_OBJECT_ID_SI170B:
3592	case ENCODER_OBJECT_ID_CH7303:
3593	case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3594	case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3595	case ENCODER_OBJECT_ID_TITFP513:
3596	case ENCODER_OBJECT_ID_VT1623:
3597	case ENCODER_OBJECT_ID_HDMI_SI1930:
3598	case ENCODER_OBJECT_ID_TRAVIS:
3599	case ENCODER_OBJECT_ID_NUTMEG:
3600	/* these are handled by the primary encoders */
3601	amdgpu_encoder->is_ext_encoder = true;
3602	if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3603	drm_encoder_init(dev, encoder, funcs: &dce_v10_0_encoder_funcs,
3604	DRM_MODE_ENCODER_LVDS, NULL);
3605	else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3606	drm_encoder_init(dev, encoder, funcs: &dce_v10_0_encoder_funcs,
3607	DRM_MODE_ENCODER_DAC, NULL);
3608	else
3609	drm_encoder_init(dev, encoder, funcs: &dce_v10_0_encoder_funcs,
3610	DRM_MODE_ENCODER_TMDS, NULL);
3611	drm_encoder_helper_add(encoder, funcs: &dce_v10_0_ext_helper_funcs);
3612	break;
3613	}
3614	}
3615
3616	static const struct amdgpu_display_funcs dce_v10_0_display_funcs = {
3617	.bandwidth_update = &dce_v10_0_bandwidth_update,
3618	.vblank_get_counter = &dce_v10_0_vblank_get_counter,
3619	.backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3620	.backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3621	.hpd_sense = &dce_v10_0_hpd_sense,
3622	.hpd_set_polarity = &dce_v10_0_hpd_set_polarity,
3623	.hpd_get_gpio_reg = &dce_v10_0_hpd_get_gpio_reg,
3624	.page_flip = &dce_v10_0_page_flip,
3625	.page_flip_get_scanoutpos = &dce_v10_0_crtc_get_scanoutpos,
3626	.add_encoder = &dce_v10_0_encoder_add,
3627	.add_connector = &amdgpu_connector_add,
3628	};
3629
3630	static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev)
3631	{
3632	adev->mode_info.funcs = &dce_v10_0_display_funcs;
3633	}
3634
3635	static const struct amdgpu_irq_src_funcs dce_v10_0_crtc_irq_funcs = {
3636	.set = dce_v10_0_set_crtc_irq_state,
3637	.process = dce_v10_0_crtc_irq,
3638	};
3639
3640	static const struct amdgpu_irq_src_funcs dce_v10_0_pageflip_irq_funcs = {
3641	.set = dce_v10_0_set_pageflip_irq_state,
3642	.process = dce_v10_0_pageflip_irq,
3643	};
3644
3645	static const struct amdgpu_irq_src_funcs dce_v10_0_hpd_irq_funcs = {
3646	.set = dce_v10_0_set_hpd_irq_state,
3647	.process = dce_v10_0_hpd_irq,
3648	};
3649
3650	static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev)
3651	{
3652	if (adev->mode_info.num_crtc > 0)
3653	adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc;
3654	else
3655	adev->crtc_irq.num_types = 0;
3656	adev->crtc_irq.funcs = &dce_v10_0_crtc_irq_funcs;
3657
3658	adev->pageflip_irq.num_types = adev->mode_info.num_crtc;
3659	adev->pageflip_irq.funcs = &dce_v10_0_pageflip_irq_funcs;
3660
3661	adev->hpd_irq.num_types = adev->mode_info.num_hpd;
3662	adev->hpd_irq.funcs = &dce_v10_0_hpd_irq_funcs;
3663	}
3664
3665	const struct amdgpu_ip_block_version dce_v10_0_ip_block = {
3666	.type = AMD_IP_BLOCK_TYPE_DCE,
3667	.major = 10,
3668	.minor = 0,
3669	.rev = 0,
3670	.funcs = &dce_v10_0_ip_funcs,
3671	};
3672
3673	const struct amdgpu_ip_block_version dce_v10_1_ip_block = {
3674	.type = AMD_IP_BLOCK_TYPE_DCE,
3675	.major = 10,
3676	.minor = 1,
3677	.rev = 0,
3678	.funcs = &dce_v10_0_ip_funcs,
3679	};
3680