Update mvdr_beamforming FPGA design with code to support real IO Pipes#476
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…82a62 on gitlab.devtools.intel.com:29418/hld-das/oneapi_streaming.git
…eb872 on gitlab.devtools.intel.com:29418/hld-das/oneapi_streaming.git
…now 480 MHz with a single while(1) loop with II 1. Code still needs some cleanup.
Rewrote transpose kernel to eliminate fmax bottleneck, and ran clang-format on all files.
…t num_matricies <= 0 to mean use the default value (currently 1024). Updated the .vcxproj.user file to use the new command line argument format. Updated the .vcxproj file with the correct list of source files.
…design) Waiting for respond from Josh about the TODO section.
README updates for real IO pipe version
Signed-off-by: mtucker <mike.d.b.tucker@intel.com>
Increased depth of xrx data pipe to improve throughput
JoeOster
previously approved these changes
Apr 19, 2021
pmpeter1
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Apr 19, 2021
pmpeter1
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Overall good. Some questions on "k_" prefix variables for consistent naming.
pmpeter1
requested changes
Apr 21, 2021
Signed-off-by: mtucker <mike.d.b.tucker@intel.com>
Signed-off-by: mtucker <mike.d.b.tucker@intel.com>
pmpeter1
approved these changes
Apr 21, 2021
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Description
The mvdr_beamforming design is intended to illustrate how to create a design that uses IO Pipes for streaming. The design has two modes of operation, one which uses 'fake' IO pipes where data is transferred to/from host memory, and one which uses real IO pipes.
Since the BSP with real IO pipes is not available in the dev cloud, the real IO pipes version of the code requires obtaining a suitable board and BSP from Intel PSG CEG. Explanations of all of this are provided in the readme file.
Other changes included in this PR:
Type of change
How Has This Been Tested?
Tested with PSG HLD team regression test infrastructure against SYCL 2021.2 release code.
Tested emulation and report generation compiles.
Tested fpga generation compiles and tested result in real hardware.