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TST: fix POWER VSX feature mapping #30801

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Merged
charris merged 6 commits into from
Mar 26, 2026
+33 −1
Merged

TST: fix POWER VSX feature mapping #30801

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0576d7c
fix POWER VSX test feature mapping
abslock128w Feb 8, 2026
4f671d8
treat VSX as baseline in CPU feature tests
abslock128w Feb 8, 2026
e9376e8
fix POWER VSX feature detection using platform inference
abslock128w Feb 8, 2026
330acf0
Black space formatting
abslock128w Feb 9, 2026
2d95860
removed the one trailing space i fogot about+_+
abslock128w Feb 11, 2026
0c4124b
Update test_cpu_features.py
abslock128w Feb 12, 2026
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Black space formatting
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@abslock128w
abslock128w authored Feb 9, 2026
commit 330acf08d9f260a0e52eeba8bd2abcb1e4d7c11a
12 changes: 6 additions & 6 deletions numpy/_core/tests/test_cpu_features.py
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Original file line number Diff line number Diff line change
Expand Up @@ -388,16 +388,16 @@ def load_flags(self):
class Test_POWER_Features(AbstractTest):
features = ["VSX", "VSX2", "VSX3", "VSX4"]
features_map = {
"VSX": "ARCH_2_06",
"VSX2": "ARCH_2_07",
"VSX3": "ARCH_3_00",
"VSX": "ARCH_2_06",
"VSX2": "ARCH_2_07",
"VSX3": "ARCH_3_00",
"VSX4": "ARCH_3_1B"
}

def load_flags(self):
self.load_flags_auxv()
platform = self._get_platform()

if platform:
power_match = re.search(r'power(\d+)', platform, re.IGNORECASE)
if power_match:
Expand All @@ -410,8 +410,8 @@ def load_flags(self):
self.features_flags.add("ARCH_3_00")
if power_gen >= 10:
self.features_flags.add("ARCH_3_1B")
def _get_platform(self):

def _get_platform(self):
"""Get the AT_PLATFORM value from AUXV"""
try:
auxv = subprocess.check_output(['/bin/true'], env={"LD_SHOW_AUXV": "1"})
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