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deps: V8: backport 77599ffe0a74
Original commit message:

    [riscv64] Add block before LoadAddress

    fix node.js DCHECK failed
    issue: riscv-collab/v8#514

    Change-Id: I07f40e6aca05be3eb7304a43235185fd40ebc1f2
    Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3260979
    Reviewed-by: ji qiu <qiuji@iscas.ac.cn>
    Commit-Queue: ji qiu <qiuji@iscas.ac.cn>
    Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
    Cr-Commit-Position: refs/heads/main@{#77750}

Refs: v8/v8@77599ffe0a74
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luyahan committed Jan 17, 2022
commit f18bb63439fdff1c4a517276277ec16e7026ef99
2 changes: 1 addition & 1 deletion common.gypi
Original file line number Diff line number Diff line change
Expand Up @@ -36,7 +36,7 @@

# Reset this number to 0 on major V8 upgrades.
# Increment by one for each non-official patch applied to deps/v8.
'v8_embedder_string': '-node.18',
'v8_embedder_string': '-node.19',

##### V8 defaults for Node.js #####

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Original file line number Diff line number Diff line change
Expand Up @@ -438,6 +438,7 @@ void BaselineAssembler::Switch(Register reg, int case_value_base,
DCHECK(is_int32(imm64));
int32_t Hi20 = (((int32_t)imm64 + 0x800) >> 12);
int32_t Lo12 = (int32_t)imm64 << 20 >> 20;
__ BlockTrampolinePoolFor(2);
__ auipc(temp, Hi20); // Read PC + Hi20 into t6
__ addi(temp, temp, Lo12); // jump PC + Hi20 + Lo12

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1 change: 1 addition & 0 deletions deps/v8/src/codegen/riscv64/macro-assembler-riscv64.cc
Original file line number Diff line number Diff line change
Expand Up @@ -3485,6 +3485,7 @@ void TurboAssembler::LoadAddress(Register dst, Label* target,
if (CalculateOffset(target, &offset, OffsetSize::kOffset32)) {
int32_t Hi20 = (((int32_t)offset + 0x800) >> 12);
int32_t Lo12 = (int32_t)offset << 20 >> 20;
BlockTrampolinePoolScope block_trampoline_pool(this);
auipc(dst, Hi20);
addi(dst, dst, Lo12);
} else {
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