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Add Seeed XIAO ESP32C3, ESP32C5 and ESP32S3 (PLUS) boards#19368

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Add Seeed XIAO ESP32C3, ESP32C5 and ESP32S3 (PLUS) boards#19368
pavelrevak wants to merge 4 commits into
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@pavelrevak pavelrevak commented Jun 22, 2026 •
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Summary

Adds board definitions for three Seeed XIAO ESP32 variants: XIAO ESP32C3, XIAO ESP32C5, XIAO ESP32S3 and XIAO ESP32S3 PLUS.

These follow the style of the merged SEEED_XIAO_ESP32C6 (#18958) and the
review feedback on earlier attempts (#12042, #17795, #17796): pin names are
defined in pins.csv, the board uses the include(...common.cmake) style,
and the REPL is left on the native USB interface so that UART0 stays free
for the application.

  • XIAO ESP32C3 - 4MB flash.
  • XIAO ESP32C5 - 8MB flash, 8MB quad SPIRAM.
  • XIAO ESP32S3 - 8MB flash, 8MB octal SPIRAM.
  • XIAO ESP32S3 PLUS - 16MB flash, 8MB octal SPIRAM.

@projectgus invited a fresh PR for XIAO S3/C3 support in #12042 — here it is,
adapted from the C6 template as suggested.

Testing

Built with ESP-IDF v5.5.4 for all three boards.

  • XIAO ESP32C3 - flashed and tested on hardware: REPL over native USB
    Serial/JTAG, pin mapping (matches the earlier esp32/boards/SEEED_XIAO_ESP32_C3: Add new board definition. #17795 PR).
  • XIAO ESP32C5 - builds successfully, but not tested on hardware (I don't have the board).
    The pin mapping is based on the Seeed documentation; happy to adjust if
    someone can verify it on real hardware.
  • XIAO ESP32S3 - flashed and tested on hardware: REPL over native USB,
    GPIO/pin mapping, I2C and SPI defaults, and a microSD card on the Sense
    expansion board (SPI mode).
  • XIAO ESP32S3 Plus — builds successfully, but not tested on hardware
    (I don't have the board). The pin mapping is confirmed against two sources:
    the official espressif/arduino-esp32 variant header
    (variants/XIAO_ESP32S3_Plus/pins_arduino.h) and the Seeed pinout table.

Generative AI

I used generative AI tools when creating this PR, but a human has checked the
code and is responsible for the code and the description above.

@pavelrevak pavelrevak changed the title Xiao esp32 Add Seeed XIAO ESP32S3, ESP32C3 and ESP32C5 boards Jun 22, 2026
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github-actions Bot commented Jun 22, 2026 •
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Code size report:

Reference:  tools/mpy_ld.py: Allow overriding the internal MPY file name. [b49f098]
Comparison: esp32/boards/SEEED_XIAO_ESP32S3_PLUS: Add new board definition. [merge of 648418a]
  mpy-cross:    +0 +0.000% 
   bare-arm:    +0 +0.000% 
minimal x86:    +0 +0.000% 
   unix x64:    +0 +0.000% standard
      stm32:    +0 +0.000% PYBV10
      esp32:    +0 +0.000% ESP32_GENERIC
     mimxrt:    +0 +0.000% TEENSY40
        rp2:    +0 +0.000% RPI_PICO_W
       samd:    +0 +0.000% ADAFRUIT_ITSYBITSY_M4_EXPRESS
  qemu rv32:    +0 +0.000% VIRT_RV32

@pavelrevak pavelrevak changed the title Add Seeed XIAO ESP32S3, ESP32C3 and ESP32C5 boards Add Seeed XIAO ESP32S3 (PLUS), ESP32C3 and ESP32C5 boards Jun 22, 2026
@pavelrevak pavelrevak changed the title Add Seeed XIAO ESP32S3 (PLUS), ESP32C3 and ESP32C5 boards Add Seeed XIAO ESP32C3, ESP32C5 and ESP32S3 (PLUS) boards Jun 22, 2026
@pavelrevak
esp32/boards/SEEED_XIAO_ESP32C3: Add new board definition.
76dc171 
Add a board definition for the Seeed Studio XIAO ESP32C3
(ESP32-C3 with 4MB flash).
The REPL is on the native USB Serial/JTAG interface,
leaving UART0 free for the application.

Signed-off-by: Pavel Revak <pavelrevak@gmail.com>
@pavelrevak
esp32/boards/SEEED_XIAO_ESP32C5: Add new board definition.
e381661 
Add a board definition for the Seeed Studio XIAO ESP32C5
(ESP32-C5 with 8MB flash and 8MB quad SPIRAM).
The REPL is on the native USB Serial/JTAG interface,
leaving UART0 free for the application.

Signed-off-by: Pavel Revak <pavelrevak@gmail.com>
@pavelrevak
esp32/boards/SEEED_XIAO_ESP32S3: Add new board definition.
f11cd1f 
Add a board definition for the Seeed Studio XIAO ESP32S3
(ESP32-S3 with 8MB flash and 8MB octal SPIRAM).
The REPL is on the native USB interface, leaving UART0 free
for the application.

Signed-off-by: Pavel Revak <pavelrevak@gmail.com>
@pavelrevak
esp32/boards/SEEED_XIAO_ESP32S3_PLUS: Add new board definition.
648418a 
Add a board definition for the Seeed Studio XIAO ESP32S3 Plus
(ESP32-S3 with 16MB flash and 8MB octal SPIRAM,
exposing extra GPIO pins D11-D19).
The REPL is on the native USB interface,
leaving UART0 free for the application.

Signed-off-by: Pavel Revak <pavelrevak@gmail.com>
@dpgeorge dpgeorge added port-esp32 board-definition New or updated board definition files. Combine with a port- label. labels Jun 23, 2026
@dpgeorge

dpgeorge commented Jun 23, 2026

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Thanks for the PR.

I suggest to combine the PLUS board with the standard board, so there would be just SEEED_XIAO_ESP32S3 and that firmware would work on both standard and plus boards.

The differences that plus adds are:

  • more flash (but flash size is auto-detected anyway, so doesn't need a config option)
  • 9 extra pins (can include these pins in pins.csv without harming the standard board)

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@pavelrevak @dpgeorge