Summary

The stm32 port already supports machine.WDT(), which accesses the IWDG peripheral (independent watchdog).

This PR adds support for the STM32 WWDG peripheral (windowed watchdog), through the same, standard machine.WDT() class interface. It's accessed as peripheral id=1.

So now it's possible to have 2 watchdogs, like this:

import machine

w1 = machine.WDT(timeout=5000)  # IWDG
w2 = machine.WDT(1, timeout=100)  #WWDG
w1.feed()
w2.feed()

The maximum timeout is quite limited on this watchdog due to the limited prescaler values, for example:

• STM32F4 at 168MHz: 49ms max timeout (at 96MHz it's 87ms max)
• STM32F7 at 216MHz: 38ms max timeout
• STM32N6 at 800MHz: 167ms max timeout
• STM32WB at 64MHz: 524ms max timeout

So it needs to be used with care.

Testing

Tested on:

• PYBV10
• PYB_SF6
• NUCLEO_WB55
• OPENMV_N6

Trade-offs and Alternatives

The hardest decision here is how to name/access the peripherals. All existing ports have only one watchdog exposed, and it's the default when you do machine.WDT() -- that's equivalent to machine.WDT(0).

But now with more than one watchdog, how to name them? The stm32 datasheets call them IWDG and WWDG on everything except H7 which has two of each: IWDG1, IWDG2, WWDG1 and WWDG2 (only IWDG1/WWDG1 are currently implemented on H7).

Note that mimxrt also has multiple watchdogs: WDOG1, WDOG2 (and WDOG3 if it exists on the MCU). Currently only WDOG1 is exposed (as machine.WDT(0)).

To be consistent with other stm32 peripheral naming, the IWDG1/IWDG2 should probably be accessed via id=1 and id=2 respectively. Then WWDG1/WWDG2 could be id=3 and id=4... although that's not very intuitive. Instead they could be named by a string like machine.WDT("WWDG1") etc. The default machine.WDT() would still access IWDG(1), but I guess it should also be available via the string "IWDG"/"IWDG1".

Generative AI

Not used.