Summary

Fixes #19010. Follow-up to PR #19140 which fixed this bug on stm32, and this PR is to fix the same bug on mimxrt.

This PR has some overlap with #18451, I apologise that I haven't looked super closely at that PR yet.

First commit is to add a test:

• Adapts the sdcard_dma_align.py test from stm32: Fix cache corruption on unaligned SDCard reads #19140 so it now works on mimxrt as well. This test relies on a high frequency timer interrupt where the CPU reads/writes memory throughout the SD transfer. It's a little less effective on mimxrt because the max timer frequency is only 1kHz - however it still seemed able to trigger the bug.

Then the fix:

• Disable DMA if the buffer is not DCache aligned. This is to prevent corruption caused by CPU writes to the same cache line as the start or end of the buffer. The SDCard block API doesn't return until the operation is done, so disabling DMA shouldn't have much impact apart from a small power consumption increase.
• Invalidate DCache for the DMA buffer region after the transfer completes. This avoids stale cache lines if the CPU has read into the cache while the transfer was in progress (including due to a speculative read). The cache is already correctly cleaned before the transfer (this happens in the NXP driver layer).

Testing

• Tested sdcard_dma_align.py before and after the fix on TEENSY41 & MIMXRT1050. Both boards fail without the fix, and pass with the fix. (An interesting note, the first part of the fix - disabling DMA - doesn't seem to be necessary to pass the test on MIMXRT1050, even running a high number of repeats. I think this is because the interrupts only trigger at 1kHz so it's very hard to have one trigger while the start or end cache line is being read, and the driver itself disables DMA internally if a buffer isn't 4-byte aligned so we're aiming for a very small target. This change was, however, very necessary for the test to pass on the Teensy - not entirely sure what the difference is there.)
• Did a special test run where I multiplied the REPEATS value by 30 on both boards, checked these extended ~20 minute test runs also pass with the fix applied.
• Ran the updated test on PYBD_SF6 to ensure it still works on stm32 port (it does).

Trade-offs and Alternatives

• As discussed in stm32: Fix cache corruption on unaligned SDCard reads #19140, it's not viable to always ensure a DMA buffer is aligned to DCache. Some kind of workaround or special case handler is needed.
• By disabling DMA like this it may be harder to swap to a non-blocking API, as is being trialled in mimxrt: Fix SD card deadlock and implement proper timeout handling. #18451.
• It might be possible to fix this using the same dma_protect_rx_region() method that we used on stm32 instead, however (a) that method doesn't scale to multiple concurrent DMA transfers, and (b) I couldn't actually figure out where the MPU is configured on mimxrt! (Although I didn't look for that long.)
• There is support to submit a table of multiple DMA descriptors for a single transfer in the NXP USDHC driver, but it looks like the driver has been designed only for a very specific use case where the descriptors are updated dynamically during the transfer(!) We could maybe write our own USDHC driver so we could chain small aligned "head" and "tail" transfers with a large aligned transfer in the middle, but it would be a lot of work and possibly we'd be the first people to try and use the NXP DMA hardware in this way (which makes me nervous).

Generative AI

I did not use generative AI tools when creating this PR.