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esp32: Enable SPIRAM & disable free_ram optimisation for ESP32_GENERIC_C5.#19303

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esp32: Enable SPIRAM & disable free_ram optimisation for ESP32_GENERIC_C5.#19303
projectgus wants to merge 4 commits into
micropython:masterfrom
projectgus:feature/esp32c5_spiram

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@projectgus projectgus commented Jun 4, 2026

Summary

Inspired by this discussion: https://github.com/orgs/micropython/discussions/19302

Ended up making five changes:

  • Removed the sdkconfig.free_ram from the ESP32-C5, which was added with initial support in seeed_xiao_esp32c5 support (IDF v5.5) #17912. ESP32-C5 has similar internal RAM size to the ESP32-C3 & C6, so it doesn't really need this RAM optimisation which was added for C2. .The C5 is also a Wifi-6 chip, so the reduced-performance-for-more-free-RAM trade-off isn't as obvious.
  • Added SPIRAM to the default ESP32_GENERIC_C5 board. Similar to S2 and S3, the idea is that missing SPIRAM will be ignored at boot.
  • Removed two three chip-specific settings from sdkconfig.spiram_sx, as they weren't needed (they were the defaults in ESP-IDF, already.)
  • Changed SPARKFUN_THINGPLUS_ESP32C5 board to not include spiram config, as now part of the common C5 config.
  • Renamed the sdkconfig.spiram_* configs to better document what they are now.

Testing

I have a ESP32-C5-DevKitC-1 board which I did not realise had PSRAM installed(!), so compared binary size and free memory on this board:

Version Binary Size gc.free_mem()
master 1854032 225936
with sdkconfig.free_ram removed 1876528 (+22KB) 189408 (-36KB)[*]
with sdkconfig.spiram_sx added (this PR) 1883744 (+30KB) 4125664

[*] This seems like a big drop, but gc.mem_free() on ESP32_GENERIC_C3 is 174528 so the C5 still has more free RAM than C3 (and C3 doesn't use sdkconfig.free_ram.)


  • Flashed both an S2 and an S3 board with this PR's firmware, verified PSRAM still detects OK.
  • It would be good to also test a C5 board without PSRAM, but I do not have one.

This work was funded through GitHub sponsors

Trade-offs and Alternatives

  • Could leave sdkconfig.free_ram enabled here (especially if we can't demonstrate any performance regression), but if so we should consider enabling it for some other boards as well.
  • Eventually we might want to rename sdkconfig.spiram to sdkconfig.spiram_esp32 and sdkconfig.spiram_sx to sdkconfig.spiram, or something like this. Decided to keep as-is for this PR.

Generative AI

I did not use generative AI tools when creating this PR.

@projectgus projectgus force-pushed the feature/esp32c5_spiram branch from 97151d3 to 8711aca Compare June 4, 2026 01:07
Comment thread ports/esp32/boards/SPARKFUN_THINGPLUS_ESP32C5/mpconfigboard.cmake Outdated
@projectgus projectgus requested a review from dpgeorge June 4, 2026 01:09
@projectgus projectgus changed the title esp32: Enable SPIRAM for ESP32_GENERIC_C5 board. esp32: Enable SPIRAM & disable free_ram optimisation for ESP32_GENERIC_C5. Jun 4, 2026
@projectgus projectgus force-pushed the feature/esp32c5_spiram branch 2 times, most recently from fc532b1 to 6c48af8 Compare June 4, 2026 01:12
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github-actions Bot commented Jun 4, 2026

Code size report:

Reference:  mimxrt: Mark boards with no TinyUF2 bootloader support. [75555f4]
Comparison: esp32: Rename the sdkconfig.spiram_xxx config snippets. [merge of 3f5247a]
  mpy-cross:    +0 +0.000% 
   bare-arm:    +0 +0.000% 
minimal x86:    +0 +0.000% 
   unix x64:    +0 +0.000% standard
      stm32:    +0 +0.000% PYBV10
      esp32:    +0 +0.000% ESP32_GENERIC
     mimxrt:    +0 +0.000% TEENSY40
        rp2:    +0 +0.000% RPI_PICO_W
       samd:    +0 +0.000% ADAFRUIT_ITSYBITSY_M4_EXPRESS
  qemu rv32:    +0 +0.000% VIRT_RV32

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dpgeorge commented Jun 4, 2026

I don't have a C5 board, but can test on S2 and S3.

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I don't have a C5 board, but can test on S2 and S3.

FWIW I've tested those already (for boards with PSRAM), and the sdkconfig ends up identical so there shouldn't be much risk of a regression there.

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dpgeorge commented Jun 4, 2026

  • Eventually we might want to rename sdkconfig.spiram to sdkconfig.spiram_esp32 and sdkconfig.spiram_sx to sdkconfig.spiram, or something like this

Would it be better to rename sdkconfig.spiram_sx to sdkconfig.spiram_quad? I think the "sx" means "S2" or "S3", but now that it's also used for C5 it might be best to rename it.

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dpgeorge commented Jun 4, 2026

FWIW I've tested those already (for boards with PSRAM), and the sdkconfig ends up identical so there shouldn't be much risk of a regression there.

OK, I won't test these boards. Idential sdkconfig is enough!

@projectgus

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These are already the ESP-IDF defaults.

This work was funded through GitHub Sponsors.

Signed-off-by: Angus Gratton <angus@redyak.com.au>
This was added with C5 support in 30c74fc, but probably
unnecessary for C5 which has closer total internal RAM to C3 and C6,
compared to C2 which is the chip this was added for.

This work was funded through GitHub Sponsors.

Signed-off-by: Angus Gratton <angus@redyak.com.au>
Similar to S2 & S3, it should be OK to detect at boot
if present or not.

This work was funded through GitHub Sponsors.

Signed-off-by: Angus Gratton <angus@redyak.com.au>
@projectgus projectgus force-pushed the feature/esp32c5_spiram branch from 6c48af8 to ba63266 Compare June 4, 2026 07:28
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  • Eventually we might want to rename sdkconfig.spiram to sdkconfig.spiram_esp32 and sdkconfig.spiram_sx to sdkconfig.spiram, or something like this

Would it be better to rename sdkconfig.spiram_sx to sdkconfig.spiram_quad? I think the "sx" means "S2" or "S3", but now that it's also used for C5 it might be best to rename it.

Makes sense, do you want me to do it in this PR?

Have applied that change in this PR. Thanks to #18873 it's a pretty small change. Re-built all boards, and checked S2 & S3 generic board sdkconfigs again.

They now more correctly describe what they each do.

This work was funded through GitHub Sponsors.

Signed-off-by: Angus Gratton <angus@redyak.com.au>
@projectgus projectgus force-pushed the feature/esp32c5_spiram branch from ba63266 to 3f5247a Compare June 4, 2026 07:53
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Josverl commented Jun 4, 2026

Tested on DOIT ESP32-C5 (ESPC532 H4) devboard that has no PSRAM

  • It correctly does not detect PSRAM.
>>> machine.reset()
ESP-ROM:esp32c5-eco2-20250121
Build:Jan 21 2025
rst:0xc (SW_CPU),boot:0x18 (SPI_FAST_FLASH_BOOT)
Core0 Saved PC:0x40813cc4
SPI mode:DIO, clock div:1
load:0x408556b0,len:0xdfc
load:0x4084bba0,len:0xc70
load:0x4084e5a0,len:0x2ee8
entry 0x4084bba0
E (433) quad_psram: PSRAM chip is not connected, or wrong PSRAM line mode
E (434) esp_psram: PSRAM enabled but initialization failed. Bailing out.
E cpu_start: Failed to init external RAM; continuing without it.
E (441) quad_psram: PSRAM chip is not connected, or wrong PSRAM line mode
E (447) esp_psram: PSRAM enabled but initialization failed. Bailing out.
MicroPython v1.29.0-preview.349.g3f5247a5c9 on 2026-06-04; ESP32C5 module with ESP32-C5
Type "help()" for more information.
>>>
  • python3 run-tests.py -t a0

    • 2 tests failed: extmod/time_ms_us.py extmod/time_res.py
     timeout waiting for first EOF reception
     CRASH
    
    • Im not sure if these are related - the same tests also crash on v1.28.0 :-(
Crashdumps

(.venv) PS C:\dev\micropython\tests> mpremote run extmod/time_res.py

A fatal error occurred. The crash dump printed below may be used to help
determine what caused it. If you are not already running the most recent
version of MicroPython, consider upgrading. New versions often fix bugs.

To learn more about how to debug and/or report this crash visit the wiki
page at: https://github.com/micropython/micropython/wiki/ESP32-debugging

MPY version : v1.29.0-preview.349.g3f5247a5c9 on 2026-06-04
IDF version : v5.5.2
Machine     : ESP32C5 module with ESP32-C5

Guru Meditation Error: Core  0 panic'ed (Illegal instruction). Exception was unhandled.

Core  0 register dump:
MEPC    : 0x420482ea  RA      : 0x4080486e  SP      : 0x4082d810  GP      : 0x4081ac04
TP      : 0x4082db70  T0      : 0x40038640  T1      : 0x408153a8  T2      : 0x00000007
S0/FP   : 0x4082e8a0  S1      : 0x42193440  A0      : 0x00000000  A1      : 0x00000000
A2      : 0x00000000  A3      : 0x00000000  A4      : 0x00000000  A5      : 0x420482ea
A6      : 0x00000000  A7      : 0x00000000  S2      : 0x4082e90c  S3      : 0x00000001
S4      : 0x4082f610  S5      : 0x4082e908  S6      : 0x00000000  S7      : 0x00000008
S8      : 0x4082f848  S9      : 0x4082e8c4  S10     : 0x4082f849  S11     : 0x4082f827
T3      : 0x4082db80  T4      : 0x00000002  T5      : 0x4082ec12  T6      : 0x00000000
MSTATUS : 0x00001881  MTVEC   : 0x40800003  MCAUSE  : 0x00000002  MTVAL   : 0x7e202573
MHARTID : 0x00000000

Stack memory:
4082d810: 0x62696c2f 0x6d69742f 0x00000000 0x00000000 0x00000000 0x4082ee74 0x4082e950 0x4082e90c
4082d830: 0x00000015 0x4082ee74 0x00000008 0x00000001 0x4082d920 0x4082ecb0 0x408037f8 0x4082e8a0
4082d850: 0x4082ecb0 0x4082e90c 0x00000001 0x00000005 0x4082e908 0x4082f620 0x00000008 0x00000001
4082d870: 0x4082f802 0x4082f5ea 0x00000000 0x4082d810 0x4082f7e0 0x00000003 0x00000001 0x4082d9b0
4082d890: 0x4082f5ea 0x4082d9b4 0x00000078 0x00000016 0x4082d9b8 0x00000000 0x00000000 0x4081fe24
4082d8b0: 0x00000064 0x4082e8a0 0x4082d8f0 0x42034f98 0x4082d9cc 0x42193440 0x4082f5e9 0x00000006
4082d8d0: 0x00000000 0x4082d9c8 0x4082f610 0x4081fe24 0x4082d9cc 0x42193440 0x4082d9a0 0x4080486e
4082d8f0: 0x00000006 0x00000005 0x4082eeb8 0x00000000 0x000000e9 0x00000000 0x4082da38 0x4082d9c0
4082d910: 0x0000001f 0x4082f400 0x4082e950 0x4205c59e 0x4082da40 0x4082f400 0x408037f8 0x4082d9a0
4082d930: 0x4082d9a0 0x4082d9cc 0x4081fe24 0x00000000 0x4082d9c8 0x00000000 0x00000006 0x00000040
4082d950: 0x00000001 0x00000000 0x00000000 0x4082d8f0 0x4082ef20 0x00000001 0x4082e650 0x00000000
4082d970: 0x00000000 0x00000001 0x00000040 0x00000006 0x00000000 0x00000000 0x00000000 0x4081fe24
4082d990: 0x00000000 0x4082d9a0 0x4082da10 0x42034f98 0x4082e680 0x4082f5e8 0x4082d9b0 0x00000006
4082d9b0: 0x4081fe24 0x4082e6e0 0x00000006 0x00000000 0x00000000 0x00000000 0x00000000 0x4082f5c8
4082d9d0: 0x4082d9b0 0x00000000 0x4082da10 0x42034f14 0x4082f5b0 0x4082e650 0x00000080 0x00000004
4082d9f0: 0x00000003 0x00000005 0x000000e9 0x00000001 0x00000001 0x00000000 0x4082e680 0x4204d010
4082da10: 0x40825000 0x40825000 0x00000000 0x40825000 0x4082daac 0x4204cf32 0x4204d128 0x00000000
4082da30: 0x42177000 0x00000005 0x4082ef20 0x00000000 0x00000000 0x00000000 0x4204cfcc 0x4082dab4
4082da50: 0x00000041 0x42173000 0x00000001 0x42177000 0x00000005 0x00000003 0x00000004 0x00000080
4082da70: 0x00000001 0x00000000 0x00000000 0x4082da10 0x42173000 0x4082daa8 0x42177000 0x00000041
4082da90: 0x42173000 0x00000001 0x00000002 0x4204d22e 0x00000000 0x00000000 0x42010080 0x00802801
4082dab0: 0x0000005a 0x4082daac 0x4204cf32 0x4204d128 0x00000020 0x00000002 0x4082e630 0x4081fd00
4082dad0: 0x00000001 0x00000000 0x4081fdc8 0x40825000 0x4202c000 0x42173000 0x40820000 0x4202c5b8
4082daf0: 0x4083db80 0x00003c00 0x4082db80 0x4202c770 0x00000000 0x00000000 0x00000000 0x00000000
4082db10: 0x00000000 0x00000000 0x00000000 0x4082db00 0x00000000 0x00000000 0x00000000 0x00000000
4082db30: 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
4082db50: 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5
4082db70: 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0x00010000 0x55555559 0xaaaaaa56 0x6aaa5aaa 0xaa966aaa
4082db90: 0x565aaaaa 0x55555555 0xa5569555 0x569aaa9a 0x55555695 0xaaaa6aaa 0x5695569a 0x95555555
4082dbb0: 0x00001a9a 0x00000000 0x00009000 0x00000000 0xaa400000 0x0000002a 0xa9000000 0x00000000
4082dbd0: 0x02a66a40 0xaaaa4000 0xaaaa9aaa 0x00002aaa 0x00000000 0x00000000 0x00000000 0x00000000
4082dbf0: 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000



ELF file SHA256: 6e2975c06

Rebooting...
ESP-ROM:esp32c5-eco2-20250121
Build:Jan 21 2025
rst:0xc (SW_CPU),boot:0x79 (SPI_FAST_FLASH_BOOT)
Core0 Saved PC:0x40813cc4
SPI mode:DIO, clock div:1
load:0x408556b0,len:0xdfc
load:0x4084bba0,len:0xc70
load:0x4084e5a0,len:0x2ee8
entry 0x4084bba0
E (433) quad_psram: PSRAM chip is not connected, or wrong PSRAM line mode
E (434) esp_psram: PSRAM enabled but initialization failed. Bailing out.
E cpu_start: Failed to init external RAM; continuing without it.
E (441) quad_psram: PSRAM chip is not connected, or wrong PSRAM line mode
E (447) esp_psram: PSRAM enabled but initialization failed. Bailing out.
MicroPython v1.29.0-preview.349.g3f5247a5c9 on 2026-06-04; ESP32C5 module with ESP32-C5
Type "help()" for more information.
>>>

 mpremote run extmod/time_ms_us.py
True
True

A fatal error occurred. The crash dump printed below may be used to help
determine what caused it. If you are not already running the most recent
version of MicroPython, consider upgrading. New versions often fix bugs.

To learn more about how to debug and/or report this crash visit the wiki
page at: https://github.com/micropython/micropython/wiki/ESP32-debugging

MPY version : v1.29.0-preview.349.g3f5247a5c9 on 2026-06-04
IDF version : v5.5.2
Machine     : ESP32C5 module with ESP32-C5

Guru Meditation Error: Core  0 panic'ed (Illegal instruction). Exception was unhandled.

Core  0 register dump:
MEPC    : 0x420482ea  RA      : 0x40804922  SP      : 0x4082d8e0  GP      : 0x4081ac04
TP      : 0x4082db70  T0      : 0x4001bd9a  T1      : 0x408153a8  T2      : 0xffffffff
S0/FP   : 0x4082d990  S1      : 0x42193440  A0      : 0x00000000  A1      : 0x00000000
A2      : 0x00000000  A3      : 0x00000000  A4      : 0x00000000  A5      : 0x420482ea
A6      : 0x600b1400  A7      : 0x00000000  S2      : 0x4082d9c0  S3      : 0x4081fe24
S4      : 0x4082e6c0  S5      : 0x4082d9bc  S6      : 0x00000000  S7      : 0x00000007
S8      : 0x4082f17b  S9      : 0x4082d9a4  S10     : 0x4082f17c  S11     : 0x4082d9a0
T3      : 0x00000000  T4      : 0x000096fd  T5      : 0x40825000  T6      : 0xffffffff
MSTATUS : 0x00001881  MTVEC   : 0x40800003  MCAUSE  : 0x00000002  MTVAL   : 0x7e202573
MHARTID : 0x00000000

Stack memory:
4082d8e0: 0x0000000c 0x4082d97c 0x4082f0f2 0x00000000 0x0000000c 0x0000000b 0x4082f088 0x4082d9b4
4082d900: 0x0000001b 0x00000000 0x4082da38 0x4082d97c 0x4082da40 0x4082e680 0x408037f8 0x4082d990
4082d920: 0x4082d990 0x4082d9c0 0x4081fe24 0x00000000 0x4082d9bc 0x00000000 0x00000007 0x00000050
4082d940: 0x00000001 0x00000000 0x00000000 0x4082d8e0 0x00000000 0x4082e650 0x4082e6e0 0x00000000
4082d960: 0x00000000 0x00000001 0x00000050 0x00000007 0x00000000 0x00000000 0x00000000 0x4081fe24
4082d980: 0x00000000 0x4082d990 0x4082da10 0x42034f98 0x4082e660 0x4082f17a 0x4082d9a0 0x00000007
4082d9a0: 0x4081fe24 0x4219553c 0x00000000 0x000003e9 0x0000000d 0x04b7f309 0x04b7f2fd 0x00000000
4082d9c0: 0x4082f0f8 0x4082d9a0 0x00000000 0x4205c42a 0x00000003 0x00000005 0x4082da10 0x42034f14
4082d9e0: 0x4082f0c0 0x4082e650 0x00000080 0x00000004 0x00000003 0x00000005 0x000000e9 0x00000001
4082da00: 0x00000001 0x00000000 0x4082e660 0x4204d010 0x40825000 0x40825000 0x00000000 0x40825000
4082da20: 0x4082daac 0x4204cf32 0x4204d128 0x00000000 0x42177000 0x00000005 0x4082f088 0x00000000
4082da40: 0x00000000 0x00000000 0x4204cfcc 0x4082dab4 0x00000041 0x42173000 0x00000001 0x42177000
4082da60: 0x00000005 0x00000003 0x00000004 0x00000080 0x00000001 0x00000000 0x00000000 0x4082da10
4082da80: 0x42173000 0x4082daa8 0x42177000 0x00000041 0x42173000 0x00000001 0x00000002 0x4204d22e
4082daa0: 0x00000000 0x00000000 0x42010080 0x00802801 0x00000054 0x4082daac 0x4204cf32 0x4204d128
4082dac0: 0x00000020 0x00000002 0x4082e630 0x4081fd00 0x00000001 0x00000000 0x4081fdc8 0x40825000
4082dae0: 0x4202c000 0x42173000 0x40820000 0x4202c5b8 0x4083db80 0x00003c00 0x4082db80 0x4202c770
4082db00: 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x4082db00
4082db20: 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
4082db40: 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
4082db60: 0x00000000 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0xa5a5a5a5 0x00010000
4082db80: 0x55555559 0xaaaaaa56 0x6aaa5aaa 0xaa966aaa 0x565aaaaa 0x02a40949 0x00000000 0x002aaa90
4082dba0: 0x00000000 0xaaa90000 0x002aaaa9 0x00000000 0x00000000 0x00000000 0x00000000 0xaaaaa900
4082dbc0: 0x0000000a 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
4082dbe0: 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
4082dc00: 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
4082dc20: 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
4082dc40: 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
4082dc60: 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
4082dc80: 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
4082dca0: 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
4082dcc0: 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000



ELF file SHA256: 6e2975c06

Rebooting...
ESP-ROM:esp32c5-eco2-20250121
Build:Jan 21 2025
rst:0xc (SW_CPU),boot:0x79 (SPI_FAST_FLASH_BOOT)
Core0 Saved PC:0x40813cc4
SPI mode:DIO, clock div:1
load:0x408556b0,len:0xdfc
load:0x4084bba0,len:0xc70
load:0x4084e5a0,len:0x2ee8
entry 0x4084bba0
E (433) quad_psram: PSRAM chip is not connected, or wrong PSRAM line mode
E (434) esp_psram: PSRAM enabled but initialization failed. Bailing out.
E cpu_start: Failed to init external RAM; continuing without it.
E (441) quad_psram: PSRAM chip is not connected, or wrong PSRAM line mode
E (447) esp_psram: PSRAM enabled but initialization failed. Bailing out.
MicroPython v1.29.0-preview.349.g3f5247a5c9 on 2026-06-04; ESP32C5 module with ESP32-C5
Type "help()" for more information.

board package chip Details

board on Ali

image

ESPC5-32 H4

https://www.lcsc.com/product-detail/C52139915.html
Module Type

Name Flash PSRAM Antenna
ESPC5-32E-H4 32M bit - U.FL
ESPC5-32E-H8R8 64M bit 64M bit U.FL
ESPC5-32E-H16R8 128M bit 64M bit U.FL
$ esptool flash-id
esptool v5.3.0
Connected to ESP32-C5 on /dev/ttyUSB0:
Chip type:          ESP32-C5 (revision v1.0)
Features:           Wi-Fi 6 (dual-band), BT 5 (LE), IEEE802.15.4, Single Core + LP Core, 240MHz
Crystal frequency:  48MHz
MAC:                d0:cf:13:ff:fe:ed:61:80
BASE MAC:           d0:cf:13:ed:61:80
MAC_EXT:            ff:fe

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3 participants