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Update mvdr_beamforming FPGA design with code to support real IO Pipes (oneapi-src#476)
* Copying all code from commit hash 88b0f05c90436359fa93fbfdd77a6f953ea82a62 on gitlab.devtools.intel.com:29418/hld-das/oneapi_streaming.git * Copying all code from commit hash f2269f9a6437eeab79155bb277ffd8ac3e1eb872 on gitlab.devtools.intel.com:29418/hld-das/oneapi_streaming.git * Added formatting comments prior to running clang-format * Ran clang-format with style=Google on all source files * Removed executable mode on all files. * Eliminated compile warnings from InputDemux. * Deleted unused files * Fixed a comment in InputDemux * Minor change in InputDemux to make code more readable and easy to maintain. * Rewrote Transpose kernel to eliminate FMAX bottleneck. Reported FMAX now 480 MHz with a single while(1) loop with II 1. Code still needs some cleanup. * Transpose code clean-up * Ran clang-format on Transpose.hpp * Assorted minor code clean-up based on review comments. * Code clean up. Removed some dead code and some TODO comments. * Updated command line argument parsing in mvdr_beamforming.cpp to treat num_matricies <= 0 to mean use the default value (currently 1024). Updated the .vcxproj.user file to use the new command line argument format. Updated the .vcxproj file with the correct list of source files. * Added sections to README about real IO pipes (loopback test and full design) Waiting for respond from Josh about the TODO section. * Small changes to README * README updates * README updates * Added message from Josh to README * Increased depth of xrx data pipe to try to improve throughput * Minor README cleanup Signed-off-by: mtucker <mike.d.b.tucker@intel.com> * Fixed casting from char to unsigned char in ForwardSubstitution.hpp Signed-off-by: mtucker <mike.d.b.tucker@intel.com> * Fix casting in Beamformer from char to unsigned char Signed-off-by: mtucker <mike.d.b.tucker@intel.com> Co-authored-by: tyoungsc <tanner.young-schultz@intel.com>
1 parent 0219db1 commit 01a7076

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‎DirectProgramming/DPC++FPGA/ReferenceDesigns/mvdr_beamforming/README.md‎

Lines changed: 83 additions & 39 deletions
Original file line numberDiff line numberDiff line change
@@ -122,62 +122,41 @@ You can compile and run this Reference Design in the Eclipse* IDE (in Linux*) an
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1. Run the sample on the FPGA emulator (the kernel executes on the CPU).
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```
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./mvdr_beamforming.fpga_emu --in=../data (Linux)
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./mvdr_beamforming.fpga_emu.exe --in=../data (Windows)
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./mvdr_beamforming.fpga_emu 1024 ../data . (Linux)
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./mvdr_beamforming.fpga_emu.exe 1024 ../data . (Windows)
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```
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2. Run the sample on the FPGA device.
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```
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./mvdr_beamforming.fpga --in=../data (Linux)
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./mvdr_beamforming.fpga 1024 ../data . (Linux)
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```
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### Application Parameters
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| Argument | Description
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|--- |---
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| `--in=<path to input>` | Specifies the directory that contains the input files (default=`../data`)
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| `--out=<path to output>` | Specifies the directory to produce output data to (default=`.`)
136+
| Argument Index | Description
137+
|--- |---
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| 0 | The number of matrices (default=`1024`)
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| 1 | The input directory (default=`../data`)
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| 2 | The output directory (default=`.`)
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### Example of Output
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You should see the following output in the console:
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```
146+
Matrices: 1024
147+
Input Directory: '../data'
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Output Directory: '.'
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Reading training data from '../data/A_real.txt and ../data/A_imag.txt
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Reading input data from ../data/X_real.txt and ../data/X_imag.txt
147-
Calculated sin(theta) values
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Launched MVDR kernels
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*** Basic single matrix and steering vectors test ***
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Launching consumer kernel
152-
Launching producer kernels
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Producer kernels finished
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Consumer kernels finished
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Writing output to ./out_real.txt and ./out_imag.txt
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Checking output data against ../data/small_expected_out_real.txt and ../data/small_expected_out_imag.txt
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Output data check succeeded
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*** Re-send single matrix test ***
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Re-sending Xrx and training data
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Producer kernels finished
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Consumer kernels finished
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Checking output data against ../data/small_expected_out_real.txt and ../data/small_expected_out_imag.txt
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Output data check succeeded
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*** Modify weight vectors test (expect data mismatch) ***
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Modifying and sending sin(theta) values
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Re-sending Xrx and training data two times
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Output data mismatched as expected
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Restoring original sin(theta)[0] value
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Re-sending Xrx and training data two times
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Checking output data against ../data/small_expected_out_real.txt and ../data/small_expected_out_imag.txt
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Output data check succeeded
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*** Launching throughput test of 1024 matrices ***
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Sensor inputs : 16
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Training matrix rows : 48
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Data rows per training matrix : 48
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Steering vectors : 25
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Throughput: 34.6133 matrices/second
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Throughput: 82.5219 matrices/second
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Checking output data against ../data/small_expected_out_real.txt and ../data/small_expected_out_imag.txt
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Output data check succeeded
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PASSED
@@ -188,23 +167,27 @@ PASSED
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### Source Code Breakdown
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| File | Description
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|:--- |:---
191-
|`mvdr_beamforming.cpp` | Contains the `main()` function and the top-level interfaces to the MVDR functions.
170+
|`mvdr_beamforming.cpp` | Contains the `main()` function and the top-level interfaces to the MVDR functions
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|`BackwardSubstitution.hpp` | Backward Substitution kernel
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|`Beamformer.hpp` | Beamformer kernel, multiplies input vectors by each weight vector to generate final output
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|`CalcWeights.hpp` | CalcWeights kernel, multiplies BackwardSubstitution output by steering vectors
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|`Constants.hpp` | Defines constants used throught the design, some can be overridden from the command line during compiliation
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|`FakeIOPipes.hpp` | Implements 'fake' IO pipes, which interface to the host
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|`ForwardSubstitution.hpp` | Forward Substitution kernel
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|`InputDemux.hpp` | InputDemux kernel, separates training and processing data
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|`mvdr_complex.hpp` | Definition of ComplexType, used throughout this design
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|`MVDR.hpp` | Function to launch all MVDR kernels and define the pipes that connect them together
200-
|`NullPipe.hpp` | Defines the NullPipe class which allows pipe interfaces on kernels to be unused
201-
|`pipe_array.hpp` | Header file containing the definition of an array of pipes.
202-
|`pipe_array_internal.hpp` | Helper for pipe_array.hpp.
180+
|`ParallelCopyArray.hpp` | Defines the ParallelCopyArray class, an array that supports unrolled copy / assign operations
181+
|`pipe_array.hpp` | Header file containing the definition of an array of pipes
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|`pipe_array_internal.hpp` | Helper for pipe_array.hpp
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|`PipeDuplicator.hpp` | Defines the PipeDuplicator class, creates multiple copies of a pipe for fan-out
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|`SteeringVectorGenerator.hpp` | SteeringVectorGenerator kernel, generates steering vectors based on data from the host
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|`StreamingQRD.hpp` | StreamingQRD kernel, performs Q-R Decompostion on a matrix
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|`Transpose.hpp` | Transpose kernel, reorders data for the StreamingQRD kernel
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|`Tuple.hpp` | A templated tuple that defines the NTuple class which is used for pipe interfaces
207-
|`UnrolledLoop.hpp` | A templated-based loop unroller that unrolls loops in the compiler front end
188+
|`udp_loopback_test.cpp` | Contains the `main()` function for the loopback test. This code is only relevant for use with real IO pipes
189+
|`UDP.hpp` | This code is **only** relevant for using the real IO pipes (i.e. not in the devcloud). This is discussed later in the [Using Real IO-pipes Section](#using-real-io-pipes)
190+
|`UnrolledLoop.hpp` | A templated-based loop unroller that unrolls loops in the compiler front end
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### MVDR Beamforming
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This reference design is built upon the **IO Streaming** code sample.
@@ -214,3 +197,64 @@ The images below show the dataflow in the MVDR beamforming design. The first ima
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<img src="processing_kernels_ideal.png" alt="processing_kernels_ideal" width="800"/>
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<img src="processing_kernels_fake.png" alt="processing_kernels_fake" width="800"/>
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200+
### Using Real IO-pipes
201+
This section describes how to build and run this reference design on a BSP with real IO pipes. The real IO pipes version does **not** work on Windows and requires a specific system setup and BSP.
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#### Getting access to the BSP
204+
This design requires a specific board support package (BSP) with a distinct hardware configuration. For access to this BSP or general customer support, submit a case through Intel&reg; Premier Support (IPS) or contact your Intel or Distribution Sales Representative.
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206+
#### Building the loopback test and Reference Design with real IO pipes
207+
Use the following commands to generate a Makefile for building both the loopback test and reference design:
208+
```
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mkdir build
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cd build
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212+
cmake .. -DREAL_IO_PIPES=1 -DFPGA_BOARD=pac_s10_usm_udp
213+
```
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215+
The `REAL_IO_PIPES` cmake flag defines a variable that is used *exclusively* in `mvdr_beamforming.cpp` to create a kernel system using real IO pipes, as opposed to the fake IO pipes described earlier in this document.
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217+
To build the loopback test, use the following command:
218+
```
219+
make udp_loopback_test
220+
```
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222+
To build the MVDR reference design, use the following command:
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```
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make fpga
225+
```
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227+
#### Running the loopback test and reference design with real IO pipes
228+
To run the loopback test, use the following command:
229+
```
230+
./udp_loopback_test.fpga 64:4C:36:00:2F:20 192.168.0.11 34543 255.255.255.0 94:40:C9:71:8D:10 192.168.0.10 34543 10000000
231+
```
232+
233+
| Argument Index | Description
234+
|--- |---
235+
| 1 | FPGA MAC Address
236+
| 2 | FPGA IP Address
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| 3 | FPGA UDP Port
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| 4 | FPGA Netmask
239+
| 5 | Host MAC Address
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| 6 | Host IP Address
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| 7 | Host UDP Port
242+
| 8 | Number of packets (optional, default=`100000000`)
243+
244+
To run the MVDR reference design with real IO pipes, use the following command:
245+
```
246+
./mvdr_beamforming.fpga 64:4C:36:00:2F:20 192.168.0.11 34543 255.255.255.0 94:40:C9:71:8D:10 192.168.0.10 34543 1024 ../data .
247+
```
248+
249+
| Argument Index | Description
250+
|--- |---
251+
| 1 | FPGA MAC Address
252+
| 2 | FPGA IP Address
253+
| 3 | FPGA UDP Port
254+
| 4 | FPGA Netmask
255+
| 5 | Host MAC Address
256+
| 6 | Host IP Address
257+
| 7 | Host UDP Port
258+
| 8 | The number of matrices (optional, default=`1024`)
259+
| 9 | The input directory (optional, default=`../data`)
260+
| 10 | The output directory (optional, default=`.`)

‎DirectProgramming/DPC++FPGA/ReferenceDesigns/mvdr_beamforming/mvdr_beamforming.vcxproj‎

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@@ -20,12 +20,13 @@
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<ClInclude Include="src\Constants.hpp" />
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<ClInclude Include="src\FakeIOPipes.hpp" />
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<ClInclude Include="src\ForwardSubstitution.hpp" />
23+
<ClInclude Include="src\InputDemux.hpp" />
2324
<ClInclude Include="src\mvdr_complex.hpp" />
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<ClInclude Include="src\MVDR.hpp" />
25-
<ClInclude Include="src\NullPipe.hpp" />
2626
<ClInclude Include="src\ParallelCopyArray.hpp" />
27-
<ClInclude Include="src\pipe_array_internal.hpp" />
2827
<ClInclude Include="src\pipe_array.hpp" />
28+
<ClInclude Include="src\pipe_array_internal.hpp" />
29+
<ClInclude Include="src\PipeDuplicator.hpp" />
2930
<ClInclude Include="src\SteeringVectorGenerator.hpp" />
3031
<ClInclude Include="src\StreamingQRD.hpp" />
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<ClInclude Include="src\Transpose.hpp" />

‎DirectProgramming/DPC++FPGA/ReferenceDesigns/mvdr_beamforming/mvdr_beamforming.vcxproj.user‎

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@@ -1,7 +1,7 @@
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<?xml version="1.0" encoding="utf-8"?>
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<Project ToolsVersion="15.0" xmlns="http://schemas.microsoft.com/developer/msbuild/2003">
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<PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Debug|x64'">
4-
<LocalDebuggerCommandArguments>--in=data</LocalDebuggerCommandArguments>
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<LocalDebuggerCommandArguments>0 ./data</LocalDebuggerCommandArguments>
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<DebuggerFlavor>WindowsLocalDebugger</DebuggerFlavor>
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</PropertyGroup>
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<PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Release|x64'">

‎DirectProgramming/DPC++FPGA/ReferenceDesigns/mvdr_beamforming/src/Beamformer.hpp‎

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@@ -75,16 +75,12 @@ event SubmitBeamformerKernel(
7575

7676
auto e = q.submit([&](handler& h) {
7777
h.single_task<BeamformerKernelName>([=] {
78-
// count the number of xrx vectors that have been processed with the
79-
// current weight vectors
80-
int xrx_vectors_processed = 0;
81-
8278
while (1) {
8379
CalcType weight_vectors[k_num_weight_vectors][kNumCalcTypePerVector];
8480

8581
// load the weight vectors to be used with the next set of Xrx vectors
86-
for (char vector_num = 0; vector_num < (char)k_num_weight_vectors;
87-
vector_num++) {
82+
for (unsigned char vector_num = 0;
83+
vector_num < (unsigned char)k_num_weight_vectors; vector_num++) {
8884
// weights are loaded in reverse order
8985
for (short i = kNumCalcTypePerVector - 1; i >= 0; i--) {
9086
for (short j = (short)k_unroll_factor - 1; j >= 0; j--) {
@@ -126,8 +122,8 @@ event SubmitBeamformerKernel(
126122
ComplexType result[k_num_weight_vectors];
127123

128124
// calculate an output vector for each weight vector
129-
for (char vector_num = 0; vector_num < (char)k_num_weight_vectors;
130-
vector_num++) {
125+
for (unsigned char vector_num = 0;
126+
vector_num < (unsigned char)k_num_weight_vectors; vector_num++) {
131127
// zero the accumulators
132128
UnrolledLoop<k_unroll_factor>([&](auto i) { accum_vector[i] = 0; });
133129

@@ -148,8 +144,8 @@ event SubmitBeamformerKernel(
148144

149145
} // end of for( vector_num... )
150146

151-
for (char vector_num = 0; vector_num < (char)k_num_weight_vectors;
152-
vector_num++) {
147+
for (unsigned char vector_num = 0;
148+
vector_num < (unsigned char)k_num_weight_vectors; vector_num++) {
153149
// send the result out
154150
DataOutPipe::write(result[vector_num]);
155151
}

‎DirectProgramming/DPC++FPGA/ReferenceDesigns/mvdr_beamforming/src/CMakeLists.txt‎

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Original file line numberDiff line numberDiff line change
@@ -28,6 +28,25 @@ if(WIN32)
2828
set(WIN_FLAG "/EHsc")
2929
endif()
3030

31+
# Allow the user to enable real IO pipes
32+
# e.g. cmake .. -DREAL_IO_PIPES=1
33+
if(REAL_IO_PIPES)
34+
set(REAL_IO_PIPES_FLAG "-DREAL_IO_PIPES")
35+
set(STREAMING_PIPE_WIDTH_FLAG "-DSTREAMING_PIPE_WIDTH=1")
36+
set(UDP_LINK_FLAGS "-luuid -lopae-c -lpthread")
37+
message(STATUS "Design is using real IO pipes")
38+
39+
# the real IO pipes version doesn't work on Windows, so error out
40+
if(WIN32)
41+
message(FATAL_ERROR "The real IO pipe design is only supported on Linux")
42+
endif()
43+
endif()
44+
45+
if(FLAT_COMPILE)
46+
message(STATUS "Doing a flat compile")
47+
set(FLAT_COMPILE_FLAG "-Xsbsp-flow=flat")
48+
endif()
49+
3150
# Allow the user to enable hardware profiling
3251
# Profiling can be enabled when running cmake by adding the flag -DPROFILE_HW=1
3352
# e.g. cmake .. -DPROFILE_HW=1
@@ -54,17 +73,23 @@ if(QRD_MIN_ITERATIONS)
5473
set(QRD_MIN_ITERATIONS_FLAG "-DQRD_MIN_ITERATIONS=${QRD_MIN_ITERATIONS}")
5574
endif()
5675

76+
# Allow the user to set the streaming pipe width for the input/output pipes
77+
# e.g. cmake .. -DSTREAMING_PIPE_WIDTH=2
78+
if(STREAMING_PIPE_WIDTH)
79+
set(STREAMING_PIPE_WIDTH_FLAG "-DSTREAMING_PIPE_WIDTH=${STREAMING_PIPE_WIDTH}")
80+
endif()
81+
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5883
# A DPC++ ahead-of-time (AoT) compile processes the device code in two stages.
5984
# 1. The "compile" stage compiles the device code to an intermediate representation (SPIR-V).
6085
# 2. The "link" stage invokes the compiler's FPGA backend before linking.
6186
# For this reason, FPGA backend flags must be passed as link flags in CMake.
62-
set(EMULATOR_COMPILE_FLAGS "${WIN_FLAG} -fintelfpga -fbracket-depth=512 ${ENABLE_USM} ${SENSOR_SIZE_FLAG} ${NUM_SENSORS_FLAG} ${QRD_MIN_ITERATIONS_FLAG} -DFPGA_EMULATOR")
87+
set(EMULATOR_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fintelfpga -fbracket-depth=512 ${ENABLE_USM} ${SENSOR_SIZE_FLAG} ${NUM_SENSORS_FLAG} ${QRD_MIN_ITERATIONS_FLAG} ${STREAMING_PIPE_WIDTH_FLAG} -DFPGA_EMULATOR")
6388
set(EMULATOR_LINK_FLAGS "-fintelfpga ${ENABLE_USM}")
64-
set(SIMULATOR_COMPILE_FLAGS "-fintelfpga -fbracket-depth=512 ${ENABLE_USM} ${SENSOR_SIZE_FLAG} ${NUM_SENSORS_FLAG} ${QRD_MIN_ITERATIONS_FLAG}")
89+
set(SIMULATOR_COMPILE_FLAGS "-Wall -fintelfpga -fbracket-depth=512 ${ENABLE_USM} ${SENSOR_SIZE_FLAG} ${NUM_SENSORS_FLAG} ${QRD_MIN_ITERATIONS_FLAG} ${STREAMING_PIPE_WIDTH_FLAG}")
6590
set(SIMULATOR_LINK_FLAGS "-fintelfpga -fbracket-depth=512 -Xssimulation -Xsghdl")
66-
set(HARDWARE_COMPILE_FLAGS "${WIN_FLAG} -fbracket-depth=512 -fintelfpga ${ENABLE_USM} ${SENSOR_SIZE_FLAG} ${NUM_SENSORS_FLAG} ${QRD_MIN_ITERATIONS_FLAG}")
67-
set(HARDWARE_LINK_FLAGS "-fintelfpga -Xshardware -fbracket-depth=512 ${PROFILE_FLAG} ${ENABLE_USM} ${SENSOR_SIZE_FLAG} ${NUM_SENSORS_FLAG} ${QRD_MIN_ITERATIONS_FLAG} -Xsparallel=2 -Xsboard=${FPGA_BOARD} ${USER_HARDWARE_FLAGS}")
91+
set(HARDWARE_COMPILE_FLAGS "-Wall ${WIN_FLAG} -fbracket-depth=512 -fintelfpga ${ENABLE_USM} ${SENSOR_SIZE_FLAG} ${NUM_SENSORS_FLAG} ${QRD_MIN_ITERATIONS_FLAG} ${REAL_IO_PIPES_FLAG} ${STREAMING_PIPE_WIDTH_FLAG}")
92+
set(HARDWARE_LINK_FLAGS "-fintelfpga -Xshardware -fbracket-depth=512 ${PROFILE_FLAG} -Xsparallel=2 -Xsboard=${FPGA_BOARD} ${USER_HARDWARE_FLAGS} ${UDP_LINK_FLAGS}")
6893
# use cmake -D USER_HARDWARE_FLAGS=<flags> to set extra flags for FPGA backend compilation
6994

7095
###############################################################################
@@ -124,3 +149,15 @@ set_target_properties(${FPGA_TARGET} PROPERTIES LINK_FLAGS "${HARDWARE_LINK_FLAG
124149
# The -reuse-exe flag enables rapid recompilation of host-only code changes.
125150
# See DPC++FPGA/GettingStarted/fast_recompile for details.
126151

152+
153+
###############################################################################
154+
# UDP Loopback test
155+
###############################################################################
156+
set(UDP_LOOPBACK_TARGET udp_loopback_test.fpga)
157+
set(UDP_LOOPBACK_COMPILE_FLAGS "-Wall -fintelfpga")
158+
set(UDP_LOOPBACK_LINK_FLAGS "-fintelfpga -Xshardware -Xsboard=${FPGA_BOARD} ${FLAT_COMPILE_FLAG} ${USER_HARDWARE_FLAGS} ${UDP_LINK_FLAGS}")
159+
add_executable(${UDP_LOOPBACK_TARGET} EXCLUDE_FROM_ALL udp_loopback_test.cpp)
160+
add_custom_target(udp_loopback_test DEPENDS ${UDP_LOOPBACK_TARGET})
161+
set_target_properties(${UDP_LOOPBACK_TARGET} PROPERTIES COMPILE_FLAGS "${UDP_LOOPBACK_COMPILE_FLAGS}")
162+
set_target_properties(${UDP_LOOPBACK_TARGET} PROPERTIES LINK_FLAGS "${UDP_LOOPBACK_LINK_FLAGS} -reuse-exe=${CMAKE_BINARY_DIR}/${UDP_LOOPBACK_TARGET}")
163+

‎DirectProgramming/DPC++FPGA/ReferenceDesigns/mvdr_beamforming/src/FakeIOPipes.hpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -232,8 +232,8 @@ class ConsumerImpl : public ProducerConsumerBaseImpl<Id, T, use_host_alloc> {
232232
auto kernel_ptr = BaseImpl::get_kernel_ptr();
233233

234234
// launch the kernel to read the output into device side global memory
235-
// NO-FORMAT comments are for clang-format
236235
auto kernel_event = q.submit([&](handler &h) {
236+
// NO-FORMAT comments are for clang-format
237237
h.single_task<KernelID>([=
238238
]() [[intel::kernel_args_restrict]] { // NO-FORMAT: Attribute
239239
kernel_ptr_type ptr(kernel_ptr);

‎DirectProgramming/DPC++FPGA/ReferenceDesigns/mvdr_beamforming/src/ForwardSubstitution.hpp‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -96,7 +96,7 @@ event SubmitForwardSubstitutionKernel(queue& q) {
9696
// receive new y_vectors if they are available
9797
// This odd loop is a fusion of two loops with different trip counts.
9898
short col = 0, row = 0, i = 0, j = 0;
99-
char vector_num = 0;
99+
unsigned char vector_num = 0;
100100
for (int iteration = 0; iteration < kLoadLoopIterations; iteration++) {
101101
// Load the L and LDiagRecip values
102102
if (iteration < kNumLElements) {
@@ -135,8 +135,8 @@ event SubmitForwardSubstitutionKernel(queue& q) {
135135
} // end of for(i...)
136136

137137
// Loop through all the y vectors
138-
for (char vector_num = 0; vector_num < (char)k_num_y_vectors;
139-
vector_num++) {
138+
for (unsigned char vector_num = 0;
139+
vector_num < (unsigned char)k_num_y_vectors; vector_num++) {
140140
// y_vector_intial contains the unmodified current y vector. y_vector
141141
// is used during processing. Splitting these two vectors allows
142142
// each to be implemented in a local memory with only one read and

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