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New FPGA reference design: ANR (oneapi-src#701)
* New FPGA reference design: ANR * Changes to address Peter's review: mostly formatting of constants and magic numbers.
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‎DirectProgramming/DPC++FPGA/ReferenceDesigns/anr/CMakeLists.txt‎

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if(UNIX)
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# Direct CMake to use dpcpp rather than the default C++ compiler/linker
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set(CMAKE_CXX_COMPILER dpcpp)
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else() # Windows
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# Force CMake to use dpcpp rather than the default C++ compiler/linker
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# (needed on Windows only)
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include (CMakeForceCompiler)
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CMAKE_FORCE_CXX_COMPILER (dpcpp IntelDPCPP)
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include (Platform/Windows-Clang)
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endif()
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cmake_minimum_required (VERSION 3.4)
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project(ANR CXX)
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set(CMAKE_ARCHIVE_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR})
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set(CMAKE_LIBRARY_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR})
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set(CMAKE_RUNTIME_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR})
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add_subdirectory (src)

‎DirectProgramming/DPC++FPGA/ReferenceDesigns/anr/License.txt‎

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Copyright Intel Corporation
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SPDX-License-Identifier: MIT
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https://opensource.org/licenses/MIT
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in all
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copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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SOFTWARE.
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‎DirectProgramming/DPC++FPGA/ReferenceDesigns/anr/README.md‎

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‎DirectProgramming/DPC++FPGA/ReferenceDesigns/anr/anr.sln‎

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Microsoft Visual Studio Solution File, Format Version 12.00
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# Visual Studio 15
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VisualStudioVersion = 15.0.28307.705
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MinimumVisualStudioVersion = 10.0.40219.1
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Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "anr", "anr.vcxproj", "{ACDE6B7A-6F9A-428E-B040-CEDC5B1E2C79}"
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EndProject
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Global
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GlobalSection(SolutionConfigurationPlatforms) = preSolution
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Debug|x64 = Debug|x64
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Release|x64 = Release|x64
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EndGlobalSection
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GlobalSection(ProjectConfigurationPlatforms) = postSolution
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{ACDE6B7A-6F9A-428E-B040-CEDC5B1E2C79}.Debug|x64.ActiveCfg = Debug|x64
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{ACDE6B7A-6F9A-428E-B040-CEDC5B1E2C79}.Debug|x64.Build.0 = Debug|x64
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{ACDE6B7A-6F9A-428E-B040-CEDC5B1E2C79}.Release|x64.ActiveCfg = Release|x64
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{ACDE6B7A-6F9A-428E-B040-CEDC5B1E2C79}.Release|x64.Build.0 = Release|x64
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EndGlobalSection
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GlobalSection(SolutionProperties) = preSolution
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HideSolutionNode = FALSE
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EndGlobalSection
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GlobalSection(ExtensibilityGlobals) = postSolution
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SolutionGuid = {97D1BD74-AAAB-4835-8F00-37A58B70871A}
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EndGlobalSection
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EndGlobal

‎DirectProgramming/DPC++FPGA/ReferenceDesigns/anr/anr.vcxproj‎

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<?xml version="1.0" encoding="utf-8"?>
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<Project DefaultTargets="Build" ToolsVersion="15.0" xmlns="http://schemas.microsoft.com/developer/msbuild/2003">
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<ProjectConfiguration Include="Debug|x64">
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<Configuration>Debug</Configuration>
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<Platform>x64</Platform>
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</ProjectConfiguration>
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<ProjectConfiguration Include="Release|x64">
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<Configuration>Release</Configuration>
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<Platform>x64</Platform>
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</ProjectConfiguration>
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</ItemGroup>
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<ItemGroup>
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<ClCompile Include="src\main.cpp" />
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</ItemGroup>
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<ItemGroup>
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<ClInclude Include="src\anr_params.hpp" />
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<ClInclude Include="src\anr.hpp" />
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<ClInclude Include="src\column_stencil.hpp" />
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<ClInclude Include="src\constants.hpp" />
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<ClInclude Include="src\data_bundle.hpp" />
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<ClInclude Include="src\dma_kernels.hpp" />
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<ClInclude Include="src\intensity_sigma_lut.hpp" />
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<ClInclude Include="src\mp_math.hpp" />
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<ClInclude Include="src\qfp_exp_lut.hpp" />
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<ClInclude Include="src\qfp_inv_lut.hpp" />
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<ClInclude Include="src\qfp.hpp" />
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<ClInclude Include="src\rom_base.hpp" />
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<ClInclude Include="src\row_stencil.hpp" />
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<ClInclude Include="src\shift_reg.hpp" />
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<ClInclude Include="src\unrolled_loop.hpp" />
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</ItemGroup>
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<ItemGroup>
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<None Include="README.md" />
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<WarningLevel>Level3</WarningLevel>
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<Optimization>Disabled</Optimization>
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<SDLCheck>true</SDLCheck>
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<ConformanceMode>true</ConformanceMode>
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<PrecompiledHeaderFile>pch.h</PrecompiledHeaderFile>
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<AdditionalIncludeDirectories>$(ONEAPI_ROOT)dev-utilities\latest\include</AdditionalIncludeDirectories>
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</ClCompile>
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<Link>
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<EnableFPGACompilationAhead>true</EnableFPGACompilationAhead>
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<AdditionalOptions>-DFPGA_EMULATOR -fconstexpr-steps=5084968 %(AdditionalOptions)</AdditionalOptions>
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‎DirectProgramming/DPC++FPGA/ReferenceDesigns/anr/anr_ip.png‎

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‎DirectProgramming/DPC++FPGA/ReferenceDesigns/anr/anr_system.png‎

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‎DirectProgramming/DPC++FPGA/ReferenceDesigns/anr/bayer.png‎

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‎DirectProgramming/DPC++FPGA/ReferenceDesigns/anr/bilateral_estimate.png‎

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‎DirectProgramming/DPC++FPGA/ReferenceDesigns/anr/conv.png‎

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