ARM: EXYNOS: Add USB HSIC device

This patch support to control USB HSIC of EXYNOS4, edited based on Samsung's GT-i9100 ICS Opensource Update7. Change-Id: Ifba33c6a5166abf3644794eee6abe528bd71f521 Signed-off-by: Dongjin Kim <dongjin.kim@agreeyamobility.net>
hardkernel · tobetter · Jul 30, 2012 · Jul 24, 2012 · Jul 13, 2012 · Jul 28, 2012
commit 6a590abbb4cfb886b8d484ccf405a812181c42eb
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
@@ -178,6 +178,11 @@ static struct map_desc exynos4_iodesc[] __initdata = {
 		.pfn		= __phys_to_pfn(EXYNOS4_PA_L2CC),
 		.length		= SZ_4K,
 		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S5P_VA_GPIO2,
+		.pfn		= __phys_to_pfn(EXYNOS4_PA_GPIO2),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
 	}, {
 		.virtual	= (unsigned long)S5P_VA_DMC0,
 		.pfn		= __phys_to_pfn(EXYNOS4_PA_DMC0),

diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h b/arch/arm/mach-exynos/include/mach/regs-pmu.h
@@ -185,6 +185,15 @@
 #define S5P_PMU_LCD1_CONF		S5P_PMUREG(0x3CA0)
 
 /* Only for EXYNOS4x12 */
+#define S5P_USB_PHY_CONTROL			S5P_PMUREG(0x0704)
+#define S5P_USB_PHY_ENABLE			(0x1 << 0)
+
+#define S5P_HSIC_1_PHY_CONTROL			S5P_PMUREG(0x0708)
+#define S5P_HSIC_1_PHY_ENABLE			(0x1 << 0)
+
+#define S5P_HSIC_2_PHY_CONTROL			S5P_PMUREG(0x070C)
+#define S5P_HSIC_2_PHY_ENABLE			(0x1 << 0)
+
 #define S5P_ISP_ARM_LOWPWR			S5P_PMUREG(0x1050)
 #define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR	S5P_PMUREG(0x1054)
 #define S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR	S5P_PMUREG(0x1058)
@@ -242,6 +251,9 @@
 
 #define EXYNOS5_SYS_WDTRESET					(1 << 20)
 
+#define EXYNOS5_USBDEV_PHY_CONTROL			S5P_PMUREG(0x0704)
+#define EXYNOS5_USBHOST_PHY_CONTROL			S5P_PMUREG(0x0708)
+
 #define EXYNOS5_ARM_CORE0_SYS_PWR_REG				S5P_PMUREG(0x1000)
 #define EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG		S5P_PMUREG(0x1004)
 #define EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG		S5P_PMUREG(0x1008)

diff --git a/arch/arm/mach-exynos/include/mach/regs-usb-phy.h b/arch/arm/mach-exynos/include/mach/regs-usb-phy.h
@@ -43,6 +43,43 @@
 #define EXYNOS4210_CLKSEL_12M		(0x2 << 0)
 #define EXYNOS4210_CLKSEL_24M		(0x3 << 0)
 
+#define EXYNOS4210_HSIC1_NORMAL_MASK            (0x3 << 11)
+#define EXYNOS4210_HSIC1_SLEEP                  (1 << 12)
+#define EXYNOS4210_HSIC1_FORCE_SUSPEND          (1 << 11)
+#define EXYNOS4210_HSIC0_NORMAL_MASK            (0x3 << 9)
+#define EXYNOS4210_HSIC0_SLEEP                  (1 << 10)
+#define EXYNOS4210_HSIC0_FORCE_SUSPEND          (1 << 9)
+
+#define EXYNOS4210_HOST_LINK_PORT_SWRST_MASK    (0xf << 6)
+#define EXYNOS4210_HOST_LINK_PORT2_SWRST        (1 << 9)
+#define EXYNOS4210_HOST_LINK_PORT1_SWRST        (1 << 8)
+#define EXYNOS4210_HOST_LINK_PORT0_SWRST        (1 << 7)
+#define EXYNOS4210_HOST_LINK_ALL_SWRST          (1 << 6)
+#define EXYNOS4210_PHY1_SWRST_MASK              (0x7 << 3)
+#define EXYNOS4210_PHY1_HSIC_SWRST              (1 << 5)
+#define EXYNOS4210_PHY1_STD_SWRST               (1 << 4)
+#define EXYNOS4210_PHY1_ALL_SWRST               (1 << 3)
+
+#define EXYNOS4X12_HSIC1_NORMAL_MASK		(0x7 << 12)
+#define EXYNOS4X12_HSIC1_SLEEP			(1 << 14)
+#define EXYNOS4X12_HSIC1_ANALOG_POWERDOWN	(1 << 13)
+#define EXYNOS4X12_HSIC1_FORCE_SUSPEND		(1 << 12)
+#define EXYNOS4X12_HSIC0_NORMAL_MASK		(0x7 << 9)
+#define EXYNOS4X12_HSIC0_SLEEP			(1 << 11)
+#define EXYNOS4X12_HSIC0_ANALOG_POWERDOWN	(1 << 10)
+#define EXYNOS4X12_HSIC0_FORCE_SUSPEND		(1 << 9)
+
+#define EXYNOS4X12_HOST_LINK_PORT_SWRST_MASK	(0xf << 7)
+#define EXYNOS4X12_HOST_LINK_PORT2_SWRST	(1 << 10)
+#define EXYNOS4X12_HOST_LINK_PORT1_SWRST	(1 << 9)
+#define EXYNOS4X12_HOST_LINK_PORT0_SWRST	(1 << 8)
+#define EXYNOS4X12_HOST_LINK_ALL_SWRST		(1 << 7)
+#define EXYNOS4X12_PHY1_SWRST_MASK		(0xf << 3)
+#define EXYNOS4X12_PHY1_HSIC1_SWRST		(1 << 6)
+#define EXYNOS4X12_PHY1_HSIC0_SWRST		(1 << 5)
+#define EXYNOS4X12_PHY1_SWRST			(1 << 4)
+#define EXYNOS4X12_HOST_PHY_SWRST		(1 << 3)
+
 #define EXYNOS4X12_CLKSEL_MASK		(0x7 << 0)
 #define EXYNOS4X12_CLKSEL_9600K		(0x0 << 0)
 #define EXYNOS4X12_CLKSEL_10M		(0x1 << 0)
@@ -71,4 +108,64 @@
 #define EXYNOS4_PHY1CON			EXYNOS4_HSOTG_PHYREG(0x34)
 #define FPENABLEN			(1 << 0)
 
+/* For Exynos5 */
+#define EXYNOS5_PHY_HOST_CTRL0                  EXYNOS4_HSOTG_PHYREG(0x00)
+#define HOST_CTRL0_PHYSWRSTALL                  (0x1 << 31)
+#define HOST_CTRL0_REFCLKSEL(val)               (val << 19)
+#define EXYNOS5_CLKSEL_50M                      (0x7)
+#define EXYNOS5_CLKSEL_24M                      (0x5)
+#define EXYNOS5_CLKSEL_20M                      (0x4)
+#define EXYNOS5_CLKSEL_19200K                   (0x3)
+#define EXYNOS5_CLKSEL_12M                      (0x2)
+#define EXYNOS5_CLKSEL_10M                      (0x1)
+#define EXYNOS5_CLKSEL_9600K                    (0x0)
+#define HOST_CTRL0_CLKSEL_SHIFT                 (16)
+#define HOST_CTRL0_FSEL_MASK                    (0x7 << 16)
+
+#define HOST_CTRL0_COMMONON_N                   (0x1 << 9)
+#define HOST_CTRL0_SIDDQ                        (0x1 << 6)
+#define HOST_CTRL0_FORCESLEEP                   (0x1 << 5)
+#define HOST_CTRL0_FORCESUSPEND                 (0x1 << 4)
+#define HOST_CTRL0_WORDINTERFACE                (0x1 << 3)
+#define HOST_CTRL0_UTMISWRST                    (0x1 << 2)
+#define HOST_CTRL0_LINKSWRST                    (0x1 << 1)
+#define HOST_CTRL0_PHYSWRST                     (0x1 << 0)
+
+#define EXYNOS5_PHY_HOST_TUNE0                  EXYNOS4_HSOTG_PHYREG(0x04)
+#define EXYNOS5_PHY_HOST_TEST0                  EXYNOS4_HSOTG_PHYREG(0x08)
+
+#define EXYNOS5_PHY_HSIC_CTRL1                  EXYNOS4_HSOTG_PHYREG(0x10)
+#define EXYNOS5_PHY_HSIC_CTRL2                  EXYNOS4_HSOTG_PHYREG(0x20)
+#define HSIC_CTRL_REFCLKSEL(val)                ((val&0x3) << 23)
+#define HSIC_CTRL_REFCLKDIV(val)                ((val&0x7f) << 16)
+#define HSIC_CTRL_SIDDQ                         (0x1 << 6)
+#define HSIC_CTRL_FORCESLEEP                    (0x1 << 5)
+#define HSIC_CTRL_FORCESUSPEND                  (0x1 << 4)
+#define HSIC_CTRL_WORDINTERFACE                 (0x1 << 3)
+#define HSIC_CTRL_UTMISWRST                     (0x1 << 2)
+#define HSIC_CTRL_PHYSWRST                      (0x1 << 0)
+
+#define EXYNOS5_PHY_HOST_EHCICTRL               EXYNOS4_HSOTG_PHYREG(0x30)
+#define EHCICTRL_ENAINCRXALIGN                  (0x1 << 29)
+#define EHCICTRL_ENAINCR4                       (0x1 << 28)
+#define EHCICTRL_ENAINCR8                       (0x1 << 27)
+#define EHCICTRL_ENAINCR16                      (0x1 << 26)
+
+#define EXYNOS5_PHY_HOST_OHCICTRL               EXYNOS4_HSOTG_PHYREG(0x34)
+
+#define EXYNOS5_PHY_OTG_SYS                     EXYNOS4_HSOTG_PHYREG(0x38)
+#define OTG_SYS_PHYLINK_SW_RESET                (0x1 << 14)
+#define OTG_SYS_LINK_SW_RST_UOTG                (0x1 << 13)
+#define OTG_SYS_PHY0_SW_RST                     (0x1 << 12)
+#define OTG_SYS_REF_CLK_SEL(val)                ((val&0x3) << 9)
+#define OTG_SYS_REF_CLK_SEL_MASK                (0x3 << 9)
+#define OTG_SYS_IP_PULLUP_UOTG                  (0x1 << 8)
+#define OTG_SYS_COMMON_ON                       (0x1 << 7)
+#define OTG_SYS_CLKSEL_SHIFT                    (4)
+#define OTG_SYS_CTRL0_FSEL_MASK                 (0x7 << 4)
+#define OTG_SYS_FORCE_SLEEP                     (0x1 << 3)
+#define OTG_SYS_OTGDISABLE                      (0x1 << 2)
+#define OTG_SYS_SIDDQ_UOTG                      (0x1 << 1)
+#define OTG_SYS_FORCE_SUSPEND                   (0x1 << 0)
+
 #endif /* __PLAT_S5P_REGS_USB_PHY_H */