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Pull requests: gem5/gem5

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Pull requests list

arch-riscv: fix vcompress.vm data corruption and tail policy
#3104 opened Apr 22, 2026 by amatabsc Contributor Loading…
scons: Raise minimum protoc version to 3.0.0 scons Scons. gem5's Build System
#3101 opened Apr 21, 2026 by MrJaxK Loading…
1
misc: add GitHub agentic workflow for labeling PRs and issues misc Anything outside of the current labeling categories
#3095 opened Apr 17, 2026 by erin-le Contributor Loading…
12
mem: addd SimpleMemory latency based on norm dist mem General Memory Systems (e.g., XBar, Packet)
#3088 opened Apr 15, 2026 by giactra Contributor Loading…
3
arch-riscv: Add support for Sv48 and Sv57 virtual memory systems arch-riscv The RISC-V ISA
#3086 opened Apr 14, 2026 by TommyWu-fdgkhdkgh Contributor Loading…
9
mem-ruby: add transition_no_stall mem-ruby Ruby caches, structures, and protocols
#3084 opened Apr 14, 2026 by giactra Contributor Loading…
2
cpu: Add AppleVirtCPU (KvmCPU equiv for Apple hosts) cpu General gem5 CPU code (e.g., `BaseCPU`)
#3076 opened Apr 13, 2026 by BobbyRBruce Member • Draft
2
cpu-o3: Fix stall when instruction has no capable FU cpu-o3 gem5's Out-Of-Order CPU
#3073 opened Apr 10, 2026 by powerjg Contributor Loading…
7
arch-riscv: Fix incorrect old_vd_idx for OPIVI vector instructions arch-riscv The RISC-V ISA
#3067 opened Apr 7, 2026 by amatabsc Contributor Loading…
1
arch-riscv: Add KVM support arch-riscv The RISC-V ISA cpu-kvm gem5's KVM CPU
#3053 opened Apr 1, 2026 by selimsandal Loading…
64
arch-x86: add MPK support arch-x86 The X86 ISA
#3051 opened Mar 31, 2026 by Schmitz48 Loading…
3
arch-riscv: Fix some vslideup instructions arch-riscv The RISC-V ISA
#3048 opened Mar 29, 2026 by EzElephant Loading…
cpu-o3: fix renameSrcRegs crash on InvalidRegClass src reg cpu-o3 gem5's Out-Of-Order CPU
#3042 opened Mar 27, 2026 by polpetras • Draft
1
4
cpu-o3: fix pinned reg assert on fault-induced squash cpu-o3 gem5's Out-Of-Order CPU
#3040 opened Mar 27, 2026 by polpetras Loading…
1
2
feat(riscv): Added support SV48 in pagetable_walker, SV48 is not supp… arch-riscv The RISC-V ISA
#3032 opened Mar 25, 2026 by NikitaRusanovskii Loading…
1
misc: Update to use c++20 misc Anything outside of the current labeling categories
#3028 opened Mar 24, 2026 by ylldummy Contributor Loading…
29
arch-x86: x87 FPU movfp/lfpimm micro-ops use wrong dataSize arch-x86 The X86 ISA
#3026 opened Mar 22, 2026 by hakan-demirli Loading…
1
cpu-o3: discard zero-byte LSQ requests to avoid DynInst leaks cpu-o3 gem5's Out-Of-Order CPU
#3022 opened Mar 20, 2026 by BobbyRBruce Member Loading…
15
arch-x86: Fix decoding of REX prefixes in invalid positions arch-x86 The X86 ISA
#3021 opened Mar 20, 2026 by jxors Loading…
1
6
misc: Proof of concept for bazel integration: DO NOT MERGE misc Anything outside of the current labeling categories
#3004 opened Mar 12, 2026 by powerjg Contributor • Draft
tests, arch-arm: Update arm fs tests to use obtain_resources arch-arm The ARM ISA tests gem5's Testing Infrastructure
#3003 opened Mar 11, 2026 by Harshil2107 Contributor Loading…
1
15
arch-x86: Revert " implement FSGSBASE" arch-x86 The X86 ISA
#2996 opened Mar 9, 2026 by BobbyRBruce Member • Draft
sim,python: Document and name the hypercall exit APIs python gem5's Python SimObject wrapping and infrastructure sim General gem5 Simulation Components
#2983 opened Mar 3, 2026 by BobbyRBruce Member • Draft
6
mem-ruby: add StashOnce*PoC and StashOnce* flow mem-ruby Ruby caches, structures, and protocols
#2975 opened Mar 2, 2026 by tsyw Loading…
5
build: replace SCons with CMake+Ninja and Bazel build systems misc Anything outside of the current labeling categories scons Scons. gem5's Build System
#2969 opened Feb 28, 2026 by SihaoLiu Loading…
23
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