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Pull requests list

fix(csr): fix the update logic of xepc and xtval module: backend Decode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuan module: frontend Bpu, Ftq, Ifu, ICache, IBuffer module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun module: top XSTop, XSTile, XSParameters, configs topic: functionality To introduce new function, e.g. new isa extensions, new components, bug fixes...
#5860 opened Apr 25, 2026 by sinceforYy Contributor • Draft
bump L2 [[fix_snp_block_cmoAll 8b180626] module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun note: submodule bump (PR) For maintainer: this bumps submodule, merge carefully
#5859 opened Apr 24, 2026 by yulightenyu Contributor • Draft
fix(Bitmap): cfs indexed with wrong truncated PPN in L2TLB module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun topic: functionality To introduce new function, e.g. new isa extensions, new components, bug fixes...
#5858 opened Apr 24, 2026 by yxtx1994 Contributor Loading…
1
fix(ftq): move the delay from mux to port module: frontend Bpu, Ftq, Ifu, ICache, IBuffer
#5857 opened Apr 23, 2026 by Yan-Muzi Contributor Loading…
fix(StoreQueue): fix cross16B handle of storeQueue module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun topic: functionality To introduce new function, e.g. new isa extensions, new components, bug fixes...
#5855 opened Apr 23, 2026 by weidingliu Member Loading…
5
1
area(tage): use SRAM to store usefulCtr module: frontend Bpu, Ftq, Ifu, ICache, IBuffer topic: area To reduce area comsuption
#5852 opened Apr 23, 2026 by TheKiteRunner24 Collaborator Loading…
4
20260423 release module: backend Decode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuan module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun module: tool non-RTL tools like difftest, gsim, XSpdb, Makefiles, scripts, CI/CD, etc. module: top XSTop, XSTile, XSParameters, configs note: submodule bump (PR) For maintainer: this bumps submodule, merge carefully
#5848 opened Apr 22, 2026 by good-circle Contributor • Draft
test 20260422 release module: backend Decode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuan module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun module: tool non-RTL tools like difftest, gsim, XSpdb, Makefiles, scripts, CI/CD, etc. module: top XSTop, XSTile, XSParameters, configs note: submodule bump (PR) For maintainer: this bumps submodule, merge carefully
#5844 opened Apr 22, 2026 by good-circle Contributor • Draft
timing(bpu): hoist MBTB attribute checks to S2 for timing module: frontend Bpu, Ftq, Ifu, ICache, IBuffer
#5842 opened Apr 22, 2026 by my-mayfly Collaborator Loading…
1
feat(CSR): support smcdeleg/ssccfg extension module: backend Decode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuan module: tool non-RTL tools like difftest, gsim, XSpdb, Makefiles, scripts, CI/CD, etc. module: top XSTop, XSTile, XSParameters, configs note: submodule bump (PR) For maintainer: this bumps submodule, merge carefully topic: functionality To introduce new function, e.g. new isa extensions, new components, bug fixes...
#5841 opened Apr 22, 2026 by wissygh Contributor • Draft
6
refactor(mem): move hardware prefetch from loadUnit to mainPipe module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun
#5839 opened Apr 22, 2026 by Ruomio • Draft
fix(XSNoCTop,DCache): fix X-state casused by missing initial value during reset module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun module: top XSTop, XSTile, XSParameters, configs topic: functionality To introduce new function, e.g. new isa extensions, new components, bug fixes...
#5838 opened Apr 21, 2026 by forever043 Contributor Loading…
Bump l2 add tx shadow module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun module: top XSTop, XSTile, XSParameters, configs note: submodule bump (PR) For maintainer: this bumps submodule, merge carefully
#5837 opened Apr 21, 2026 by yulightenyu Contributor • Draft
feat(constantin): add custom constantin file module: tool non-RTL tools like difftest, gsim, XSpdb, Makefiles, scripts, CI/CD, etc. module: utility RTL utility note: submodule bump (PR) For maintainer: this bumps submodule, merge carefully
#5836 opened Apr 20, 2026 by Maxpicca-Li Member Loading…
3 of 5 tasks
8
feat(VirtualStoreQueue): add support of pre-allocated storeQueue module: backend Decode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuan module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun module: top XSTop, XSTile, XSParameters, configs topic: functionality To introduce new function, e.g. new isa extensions, new components, bug fixes...
#5834 opened Apr 20, 2026 by weidingliu Member • Draft
1
test 20260417 release module: backend Decode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuan module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun module: tool non-RTL tools like difftest, gsim, XSpdb, Makefiles, scripts, CI/CD, etc. module: top XSTop, XSTile, XSParameters, configs note: submodule bump (PR) For maintainer: this bumps submodule, merge carefully
#5828 opened Apr 17, 2026 by good-circle Contributor • Draft
fix(LoadUnit): prefetch does not trigger an exception module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun
#5827 opened Apr 17, 2026 by Anzooooo Member • Draft
submodule(difftest): bump difftest for kmh-v3 module: tool non-RTL tools like difftest, gsim, XSpdb, Makefiles, scripts, CI/CD, etc. note: submodule bump (PR) For maintainer: this bumps submodule, merge carefully
#5826 opened Apr 17, 2026 by klin02 Member Loading…
1
submodule(difftest): bump difftest for kmh-v2 module: tool non-RTL tools like difftest, gsim, XSpdb, Makefiles, scripts, CI/CD, etc. note: submodule bump (PR) For maintainer: this bumps submodule, merge carefully
#5825 opened Apr 17, 2026 by klin02 Member Loading…
feat(CtrlUnit): add two regs for limiting addr range module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun
#5817 opened Apr 15, 2026 by Ruomio • Draft
Test for sbuffer size 16 -> 32 (and sbuffer threshold = 12) module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun module: top XSTop, XSTile, XSParameters, configs
#5816 opened Apr 15, 2026 by jlong299 Contributor Loading…
1
feat(dispatch): add switch to disable dispatch balance opt module: backend Decode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuan module: top XSTop, XSTile, XSParameters, configs
#5815 opened Apr 15, 2026 by xiaofeibao-xjtu Contributor Loading…
1
feat(missQueue, sbuffer): sbuffer releases the entry when miss accepted by mshr, and mshr provides st-ld forwarding module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun module: top XSTop, XSTile, XSParameters, configs
#5813 opened Apr 14, 2026 by jlong299 Contributor Loading…
7
tmp module: backend Decode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuan module: frontend Bpu, Ftq, Ifu, ICache, IBuffer module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun module: other ChiselAIA, IMSIC, CLINT, etc. module: tool non-RTL tools like difftest, gsim, XSpdb, Makefiles, scripts, CI/CD, etc. module: utility RTL utility note: submodule bump (PR) For maintainer: this bumps submodule, merge carefully
#5811 opened Apr 14, 2026 by Tang-Haojin Member • Draft
1
fix(LoadUnit): clear replay cause on matchInvalid writeback module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun topic: functionality To introduce new function, e.g. new isa extensions, new components, bug fixes...
#5810 opened Apr 14, 2026 by maxiaoran24 Loading…
1
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