| 1 | /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ |
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| 2 | /* Copyright(c) 2015-17 Intel Corporation. */ |
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| 3 | |
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| 4 | #ifndef __SDW_REGISTERS_H |
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| 5 | #define __SDW_REGISTERS_H |
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| 6 | |
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| 7 | #include <linux/bitfield.h> |
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| 8 | #include <linux/bits.h> |
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| 9 | |
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| 10 | /* |
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| 11 | * SDW registers as defined by MIPI 1.2 Spec |
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| 12 | */ |
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| 13 | #define SDW_REGADDR GENMASK(14, 0) |
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| 14 | #define SDW_SCP_ADDRPAGE2_MASK GENMASK(22, 15) |
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| 15 | #define SDW_SCP_ADDRPAGE1_MASK GENMASK(30, 23) |
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| 16 | |
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| 17 | #define SDW_REG_NO_PAGE 0x00008000 |
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| 18 | #define SDW_REG_OPTIONAL_PAGE 0x00010000 |
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| 19 | #define SDW_REG_MAX 0x48000000 |
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| 20 | |
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| 21 | #define SDW_DPN_SIZE 0x100 |
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| 22 | #define SDW_BANK1_OFFSET 0x10 |
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| 23 | |
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| 24 | /* |
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| 25 | * DP0 Interrupt register & bits |
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| 26 | * |
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| 27 | * Spec treats Status (RO) and Clear (WC) as separate but they are same |
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| 28 | * address, so treat as same register with WC. |
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| 29 | */ |
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| 30 | |
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| 31 | /* both INT and STATUS register are same */ |
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| 32 | #define SDW_DP0_INT 0x0 |
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| 33 | #define SDW_DP0_INTMASK 0x1 |
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| 34 | #define SDW_DP0_PORTCTRL 0x2 |
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| 35 | #define SDW_DP0_BLOCKCTRL1 0x3 |
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| 36 | #define SDW_DP0_PREPARESTATUS 0x4 |
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| 37 | #define SDW_DP0_PREPARECTRL 0x5 |
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| 38 | |
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| 39 | #define SDW_DP0_INT_TEST_FAIL BIT(0) |
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| 40 | #define SDW_DP0_INT_PORT_READY BIT(1) |
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| 41 | #define SDW_DP0_INT_BRA_FAILURE BIT(2) |
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| 42 | #define SDW_DP0_SDCA_CASCADE BIT(3) |
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| 43 | /* BIT(4) not allocated in SoundWire specification 1.2 */ |
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| 44 | #define SDW_DP0_INT_IMPDEF1 BIT(5) |
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| 45 | #define SDW_DP0_INT_IMPDEF2 BIT(6) |
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| 46 | #define SDW_DP0_INT_IMPDEF3 BIT(7) |
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| 47 | #define SDW_DP0_INTERRUPTS (SDW_DP0_INT_TEST_FAIL | \ |
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| 48 | SDW_DP0_INT_PORT_READY | \ |
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| 49 | SDW_DP0_INT_BRA_FAILURE | \ |
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| 50 | SDW_DP0_INT_IMPDEF1 | \ |
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| 51 | SDW_DP0_INT_IMPDEF2 | \ |
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| 52 | SDW_DP0_INT_IMPDEF3) |
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| 53 | |
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| 54 | #define SDW_DP0_PORTCTRL_DATAMODE GENMASK(3, 2) |
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| 55 | #define SDW_DP0_PORTCTRL_NXTINVBANK BIT(4) |
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| 56 | #define SDW_DP0_PORTCTRL_BPT_PAYLD GENMASK(7, 6) |
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| 57 | |
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| 58 | #define SDW_DP0_CHANNELEN 0x20 |
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| 59 | #define SDW_DP0_SAMPLECTRL1 0x22 |
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| 60 | #define SDW_DP0_SAMPLECTRL2 0x23 |
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| 61 | #define SDW_DP0_OFFSETCTRL1 0x24 |
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| 62 | #define SDW_DP0_OFFSETCTRL2 0x25 |
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| 63 | #define SDW_DP0_HCTRL 0x26 |
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| 64 | #define SDW_DP0_LANECTRL 0x28 |
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| 65 | |
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| 66 | /* Both INT and STATUS register are same */ |
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| 67 | #define SDW_SCP_INT1 0x40 |
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| 68 | #define SDW_SCP_INTMASK1 0x41 |
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| 69 | |
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| 70 | #define SDW_SCP_INT1_PARITY BIT(0) |
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| 71 | #define SDW_SCP_INT1_BUS_CLASH BIT(1) |
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| 72 | #define SDW_SCP_INT1_IMPL_DEF BIT(2) |
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| 73 | #define SDW_SCP_INT1_SCP2_CASCADE BIT(7) |
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| 74 | #define SDW_SCP_INT1_PORT0_3 GENMASK(6, 3) |
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| 75 | |
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| 76 | #define SDW_SCP_INTSTAT2 0x42 |
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| 77 | #define SDW_SCP_INTSTAT2_SCP3_CASCADE BIT(7) |
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| 78 | #define SDW_SCP_INTSTAT2_PORT4_10 GENMASK(6, 0) |
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| 79 | |
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| 80 | #define SDW_SCP_INTSTAT3 0x43 |
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| 81 | #define SDW_SCP_INTSTAT3_PORT11_14 GENMASK(3, 0) |
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| 82 | |
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| 83 | /* Number of interrupt status registers */ |
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| 84 | #define SDW_NUM_INT_STAT_REGISTERS 3 |
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| 85 | |
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| 86 | /* Number of interrupt clear registers */ |
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| 87 | #define SDW_NUM_INT_CLEAR_REGISTERS 1 |
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| 88 | |
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| 89 | #define SDW_SCP_CTRL 0x44 |
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| 90 | #define SDW_SCP_CTRL_CLK_STP_NOW BIT(1) |
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| 91 | #define SDW_SCP_CTRL_FORCE_RESET BIT(7) |
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| 92 | |
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| 93 | #define SDW_SCP_STAT 0x44 |
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| 94 | #define SDW_SCP_STAT_CLK_STP_NF BIT(0) |
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| 95 | #define SDW_SCP_STAT_HPHY_NOK BIT(5) |
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| 96 | #define SDW_SCP_STAT_CURR_BANK BIT(6) |
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| 97 | |
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| 98 | #define SDW_SCP_SYSTEMCTRL 0x45 |
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| 99 | #define SDW_SCP_SYSTEMCTRL_CLK_STP_PREP BIT(0) |
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| 100 | #define SDW_SCP_SYSTEMCTRL_CLK_STP_MODE BIT(2) |
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| 101 | #define SDW_SCP_SYSTEMCTRL_WAKE_UP_EN BIT(3) |
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| 102 | #define SDW_SCP_SYSTEMCTRL_HIGH_PHY BIT(4) |
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| 103 | |
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| 104 | #define SDW_SCP_SYSTEMCTRL_CLK_STP_MODE0 0 |
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| 105 | #define SDW_SCP_SYSTEMCTRL_CLK_STP_MODE1 BIT(2) |
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| 106 | |
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| 107 | #define SDW_SCP_DEVNUMBER 0x46 |
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| 108 | #define SDW_SCP_HIGH_PHY_CHECK 0x47 |
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| 109 | #define SDW_SCP_ADDRPAGE1 0x48 |
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| 110 | #define SDW_SCP_ADDRPAGE2 0x49 |
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| 111 | #define SDW_SCP_KEEPEREN 0x4A |
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| 112 | #define SDW_SCP_BANKDELAY 0x4B |
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| 113 | #define SDW_SCP_COMMIT 0x4C |
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| 114 | |
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| 115 | #define SDW_SCP_BUS_CLOCK_BASE 0x4D |
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| 116 | #define SDW_SCP_BASE_CLOCK_FREQ GENMASK(2, 0) |
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| 117 | #define SDW_SCP_BASE_CLOCK_UNKNOWN 0x0 |
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| 118 | #define SDW_SCP_BASE_CLOCK_19200000_HZ 0x1 |
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| 119 | #define SDW_SCP_BASE_CLOCK_24000000_HZ 0x2 |
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| 120 | #define SDW_SCP_BASE_CLOCK_24576000_HZ 0x3 |
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| 121 | #define SDW_SCP_BASE_CLOCK_22579200_HZ 0x4 |
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| 122 | #define SDW_SCP_BASE_CLOCK_32000000_HZ 0x5 |
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| 123 | #define SDW_SCP_BASE_CLOCK_RESERVED 0x6 |
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| 124 | #define SDW_SCP_BASE_CLOCK_IMP_DEF 0x7 |
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| 125 | |
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| 126 | /* 0x4E is not allocated in SoundWire specification 1.2 */ |
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| 127 | #define SDW_SCP_TESTMODE 0x4F |
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| 128 | #define SDW_SCP_DEVID_0 0x50 |
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| 129 | #define SDW_SCP_DEVID_1 0x51 |
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| 130 | #define SDW_SCP_DEVID_2 0x52 |
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| 131 | #define SDW_SCP_DEVID_3 0x53 |
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| 132 | #define SDW_SCP_DEVID_4 0x54 |
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| 133 | #define SDW_SCP_DEVID_5 0x55 |
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| 134 | |
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| 135 | /* Both INT and STATUS register are same */ |
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| 136 | #define SDW_SCP_SDCA_INT1 0x58 |
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| 137 | #define SDW_SCP_SDCA_INT_SDCA_0 BIT(0) |
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| 138 | #define SDW_SCP_SDCA_INT_SDCA_1 BIT(1) |
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| 139 | #define SDW_SCP_SDCA_INT_SDCA_2 BIT(2) |
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| 140 | #define SDW_SCP_SDCA_INT_SDCA_3 BIT(3) |
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| 141 | #define SDW_SCP_SDCA_INT_SDCA_4 BIT(4) |
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| 142 | #define SDW_SCP_SDCA_INT_SDCA_5 BIT(5) |
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| 143 | #define SDW_SCP_SDCA_INT_SDCA_6 BIT(6) |
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| 144 | #define SDW_SCP_SDCA_INT_SDCA_7 BIT(7) |
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| 145 | |
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| 146 | #define SDW_SCP_SDCA_INT2 0x59 |
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| 147 | #define SDW_SCP_SDCA_INT_SDCA_8 BIT(0) |
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| 148 | #define SDW_SCP_SDCA_INT_SDCA_9 BIT(1) |
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| 149 | #define SDW_SCP_SDCA_INT_SDCA_10 BIT(2) |
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| 150 | #define SDW_SCP_SDCA_INT_SDCA_11 BIT(3) |
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| 151 | #define SDW_SCP_SDCA_INT_SDCA_12 BIT(4) |
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| 152 | #define SDW_SCP_SDCA_INT_SDCA_13 BIT(5) |
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| 153 | #define SDW_SCP_SDCA_INT_SDCA_14 BIT(6) |
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| 154 | #define SDW_SCP_SDCA_INT_SDCA_15 BIT(7) |
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| 155 | |
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| 156 | #define SDW_SCP_SDCA_INT3 0x5A |
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| 157 | #define SDW_SCP_SDCA_INT_SDCA_16 BIT(0) |
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| 158 | #define SDW_SCP_SDCA_INT_SDCA_17 BIT(1) |
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| 159 | #define SDW_SCP_SDCA_INT_SDCA_18 BIT(2) |
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| 160 | #define SDW_SCP_SDCA_INT_SDCA_19 BIT(3) |
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| 161 | #define SDW_SCP_SDCA_INT_SDCA_20 BIT(4) |
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| 162 | #define SDW_SCP_SDCA_INT_SDCA_21 BIT(5) |
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| 163 | #define SDW_SCP_SDCA_INT_SDCA_22 BIT(6) |
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| 164 | #define SDW_SCP_SDCA_INT_SDCA_23 BIT(7) |
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| 165 | |
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| 166 | #define SDW_SCP_SDCA_INT4 0x5B |
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| 167 | #define SDW_SCP_SDCA_INT_SDCA_24 BIT(0) |
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| 168 | #define SDW_SCP_SDCA_INT_SDCA_25 BIT(1) |
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| 169 | #define SDW_SCP_SDCA_INT_SDCA_26 BIT(2) |
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| 170 | #define SDW_SCP_SDCA_INT_SDCA_27 BIT(3) |
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| 171 | #define SDW_SCP_SDCA_INT_SDCA_28 BIT(4) |
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| 172 | #define SDW_SCP_SDCA_INT_SDCA_29 BIT(5) |
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| 173 | #define SDW_SCP_SDCA_INT_SDCA_30 BIT(6) |
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| 174 | /* BIT(7) not allocated in SoundWire 1.2 specification */ |
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| 175 | |
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| 176 | #define SDW_SCP_SDCA_INTMASK1 0x5C |
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| 177 | #define SDW_SCP_SDCA_INTMASK_SDCA_0 BIT(0) |
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| 178 | #define SDW_SCP_SDCA_INTMASK_SDCA_1 BIT(1) |
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| 179 | #define SDW_SCP_SDCA_INTMASK_SDCA_2 BIT(2) |
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| 180 | #define SDW_SCP_SDCA_INTMASK_SDCA_3 BIT(3) |
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| 181 | #define SDW_SCP_SDCA_INTMASK_SDCA_4 BIT(4) |
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| 182 | #define SDW_SCP_SDCA_INTMASK_SDCA_5 BIT(5) |
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| 183 | #define SDW_SCP_SDCA_INTMASK_SDCA_6 BIT(6) |
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| 184 | #define SDW_SCP_SDCA_INTMASK_SDCA_7 BIT(7) |
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| 185 | |
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| 186 | #define SDW_SCP_SDCA_INTMASK2 0x5D |
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| 187 | #define SDW_SCP_SDCA_INTMASK_SDCA_8 BIT(0) |
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| 188 | #define SDW_SCP_SDCA_INTMASK_SDCA_9 BIT(1) |
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| 189 | #define SDW_SCP_SDCA_INTMASK_SDCA_10 BIT(2) |
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| 190 | #define SDW_SCP_SDCA_INTMASK_SDCA_11 BIT(3) |
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| 191 | #define SDW_SCP_SDCA_INTMASK_SDCA_12 BIT(4) |
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| 192 | #define SDW_SCP_SDCA_INTMASK_SDCA_13 BIT(5) |
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| 193 | #define SDW_SCP_SDCA_INTMASK_SDCA_14 BIT(6) |
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| 194 | #define SDW_SCP_SDCA_INTMASK_SDCA_15 BIT(7) |
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| 195 | |
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| 196 | #define SDW_SCP_SDCA_INTMASK3 0x5E |
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| 197 | #define SDW_SCP_SDCA_INTMASK_SDCA_16 BIT(0) |
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| 198 | #define SDW_SCP_SDCA_INTMASK_SDCA_17 BIT(1) |
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| 199 | #define SDW_SCP_SDCA_INTMASK_SDCA_18 BIT(2) |
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| 200 | #define SDW_SCP_SDCA_INTMASK_SDCA_19 BIT(3) |
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| 201 | #define SDW_SCP_SDCA_INTMASK_SDCA_20 BIT(4) |
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| 202 | #define SDW_SCP_SDCA_INTMASK_SDCA_21 BIT(5) |
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| 203 | #define SDW_SCP_SDCA_INTMASK_SDCA_22 BIT(6) |
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| 204 | #define SDW_SCP_SDCA_INTMASK_SDCA_23 BIT(7) |
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| 205 | |
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| 206 | #define SDW_SCP_SDCA_INTMASK4 0x5F |
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| 207 | #define SDW_SCP_SDCA_INTMASK_SDCA_24 BIT(0) |
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| 208 | #define SDW_SCP_SDCA_INTMASK_SDCA_25 BIT(1) |
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| 209 | #define SDW_SCP_SDCA_INTMASK_SDCA_26 BIT(2) |
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| 210 | #define SDW_SCP_SDCA_INTMASK_SDCA_27 BIT(3) |
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| 211 | #define SDW_SCP_SDCA_INTMASK_SDCA_28 BIT(4) |
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| 212 | #define SDW_SCP_SDCA_INTMASK_SDCA_29 BIT(5) |
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| 213 | #define SDW_SCP_SDCA_INTMASK_SDCA_30 BIT(6) |
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| 214 | /* BIT(7) not allocated in SoundWire 1.2 specification */ |
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| 215 | |
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| 216 | /* Banked Registers */ |
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| 217 | #define SDW_SCP_FRAMECTRL_B0 0x60 |
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| 218 | #define SDW_SCP_FRAMECTRL_B1 (0x60 + SDW_BANK1_OFFSET) |
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| 219 | #define SDW_SCP_NEXTFRAME_B0 0x61 |
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| 220 | #define SDW_SCP_NEXTFRAME_B1 (0x61 + SDW_BANK1_OFFSET) |
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| 221 | |
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| 222 | #define SDW_SCP_BUSCLOCK_SCALE_B0 0x62 |
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| 223 | #define SDW_SCP_BUSCLOCK_SCALE_B1 (0x62 + SDW_BANK1_OFFSET) |
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| 224 | #define SDW_SCP_CLOCK_SCALE GENMASK(3, 0) |
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| 225 | |
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| 226 | /* PHY registers - CTRL and STAT are the same address */ |
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| 227 | #define SDW_SCP_PHY_OUT_CTRL_0 0x80 |
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| 228 | #define SDW_SCP_PHY_OUT_CTRL_1 0x81 |
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| 229 | #define SDW_SCP_PHY_OUT_CTRL_2 0x82 |
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| 230 | #define SDW_SCP_PHY_OUT_CTRL_3 0x83 |
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| 231 | #define SDW_SCP_PHY_OUT_CTRL_4 0x84 |
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| 232 | #define SDW_SCP_PHY_OUT_CTRL_5 0x85 |
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| 233 | #define SDW_SCP_PHY_OUT_CTRL_6 0x86 |
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| 234 | #define SDW_SCP_PHY_OUT_CTRL_7 0x87 |
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| 235 | |
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| 236 | #define SDW_SCP_CAP_LOAD_CTRL GENMASK(2, 0) |
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| 237 | #define SDW_SCP_DRIVE_STRENGTH_CTRL GENMASK(5, 3) |
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| 238 | #define SDW_SCP_SLEW_TIME_CTRL GENMASK(7, 6) |
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| 239 | |
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| 240 | /* Both INT and STATUS register is same */ |
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| 241 | #define SDW_DPN_INT(n) (0x0 + SDW_DPN_SIZE * (n)) |
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| 242 | #define SDW_DPN_INTMASK(n) (0x1 + SDW_DPN_SIZE * (n)) |
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| 243 | #define SDW_DPN_PORTCTRL(n) (0x2 + SDW_DPN_SIZE * (n)) |
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| 244 | #define SDW_DPN_BLOCKCTRL1(n) (0x3 + SDW_DPN_SIZE * (n)) |
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| 245 | #define SDW_DPN_PREPARESTATUS(n) (0x4 + SDW_DPN_SIZE * (n)) |
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| 246 | #define SDW_DPN_PREPARECTRL(n) (0x5 + SDW_DPN_SIZE * (n)) |
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| 247 | |
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| 248 | #define SDW_DPN_INT_TEST_FAIL BIT(0) |
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| 249 | #define SDW_DPN_INT_PORT_READY BIT(1) |
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| 250 | #define SDW_DPN_INT_IMPDEF1 BIT(5) |
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| 251 | #define SDW_DPN_INT_IMPDEF2 BIT(6) |
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| 252 | #define SDW_DPN_INT_IMPDEF3 BIT(7) |
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| 253 | #define SDW_DPN_INTERRUPTS (SDW_DPN_INT_TEST_FAIL | \ |
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| 254 | SDW_DPN_INT_PORT_READY | \ |
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| 255 | SDW_DPN_INT_IMPDEF1 | \ |
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| 256 | SDW_DPN_INT_IMPDEF2 | \ |
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| 257 | SDW_DPN_INT_IMPDEF3) |
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| 258 | |
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| 259 | #define SDW_DPN_PORTCTRL_FLOWMODE GENMASK(1, 0) |
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| 260 | #define SDW_DPN_PORTCTRL_DATAMODE GENMASK(3, 2) |
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| 261 | #define SDW_DPN_PORTCTRL_NXTINVBANK BIT(4) |
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| 262 | |
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| 263 | #define SDW_DPN_BLOCKCTRL1_WDLEN GENMASK(5, 0) |
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| 264 | |
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| 265 | #define SDW_DPN_PREPARECTRL_CH_PREP GENMASK(7, 0) |
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| 266 | |
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| 267 | #define SDW_DPN_CHANNELEN_B0(n) (0x20 + SDW_DPN_SIZE * (n)) |
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| 268 | #define SDW_DPN_CHANNELEN_B1(n) (0x30 + SDW_DPN_SIZE * (n)) |
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| 269 | |
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| 270 | #define SDW_DPN_BLOCKCTRL2_B0(n) (0x21 + SDW_DPN_SIZE * (n)) |
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| 271 | #define SDW_DPN_BLOCKCTRL2_B1(n) (0x31 + SDW_DPN_SIZE * (n)) |
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| 272 | |
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| 273 | #define SDW_DPN_SAMPLECTRL1_B0(n) (0x22 + SDW_DPN_SIZE * (n)) |
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| 274 | #define SDW_DPN_SAMPLECTRL1_B1(n) (0x32 + SDW_DPN_SIZE * (n)) |
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| 275 | |
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| 276 | #define SDW_DPN_SAMPLECTRL2_B0(n) (0x23 + SDW_DPN_SIZE * (n)) |
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| 277 | #define SDW_DPN_SAMPLECTRL2_B1(n) (0x33 + SDW_DPN_SIZE * (n)) |
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| 278 | |
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| 279 | #define SDW_DPN_OFFSETCTRL1_B0(n) (0x24 + SDW_DPN_SIZE * (n)) |
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| 280 | #define SDW_DPN_OFFSETCTRL1_B1(n) (0x34 + SDW_DPN_SIZE * (n)) |
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| 281 | |
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| 282 | #define SDW_DPN_OFFSETCTRL2_B0(n) (0x25 + SDW_DPN_SIZE * (n)) |
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| 283 | #define SDW_DPN_OFFSETCTRL2_B1(n) (0x35 + SDW_DPN_SIZE * (n)) |
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| 284 | |
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| 285 | #define SDW_DPN_HCTRL_B0(n) (0x26 + SDW_DPN_SIZE * (n)) |
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| 286 | #define SDW_DPN_HCTRL_B1(n) (0x36 + SDW_DPN_SIZE * (n)) |
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| 287 | |
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| 288 | #define SDW_DPN_BLOCKCTRL3_B0(n) (0x27 + SDW_DPN_SIZE * (n)) |
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| 289 | #define SDW_DPN_BLOCKCTRL3_B1(n) (0x37 + SDW_DPN_SIZE * (n)) |
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| 290 | |
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| 291 | #define SDW_DPN_LANECTRL_B0(n) (0x28 + SDW_DPN_SIZE * (n)) |
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| 292 | #define SDW_DPN_LANECTRL_B1(n) (0x38 + SDW_DPN_SIZE * (n)) |
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| 293 | |
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| 294 | #define SDW_DPN_SAMPLECTRL_LOW GENMASK(7, 0) |
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| 295 | #define SDW_DPN_SAMPLECTRL_HIGH GENMASK(15, 8) |
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| 296 | |
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| 297 | #define SDW_DPN_HCTRL_HSTART GENMASK(7, 4) |
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| 298 | #define SDW_DPN_HCTRL_HSTOP GENMASK(3, 0) |
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| 299 | |
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| 300 | #define SDW_NUM_CASC_PORT_INTSTAT1 4 |
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| 301 | #define SDW_CASC_PORT_START_INTSTAT1 0 |
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| 302 | #define SDW_CASC_PORT_MASK_INTSTAT1 0x8 |
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| 303 | #define SDW_CASC_PORT_REG_OFFSET_INTSTAT1 0x0 |
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| 304 | |
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| 305 | #define SDW_NUM_CASC_PORT_INTSTAT2 7 |
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| 306 | #define SDW_CASC_PORT_START_INTSTAT2 4 |
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| 307 | #define SDW_CASC_PORT_MASK_INTSTAT2 1 |
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| 308 | #define SDW_CASC_PORT_REG_OFFSET_INTSTAT2 1 |
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| 309 | |
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| 310 | #define SDW_NUM_CASC_PORT_INTSTAT3 4 |
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| 311 | #define SDW_CASC_PORT_START_INTSTAT3 11 |
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| 312 | #define SDW_CASC_PORT_MASK_INTSTAT3 1 |
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| 313 | #define SDW_CASC_PORT_REG_OFFSET_INTSTAT3 2 |
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| 314 | |
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| 315 | /* |
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| 316 | * v1.2 device - SDCA address mapping |
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| 317 | * |
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| 318 | * Spec definition |
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| 319 | * Bits Contents |
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| 320 | * 31 0 (required by addressing range) |
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| 321 | * 30:26 0b10000 (Control Prefix) |
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| 322 | * 25 0 (Reserved) |
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| 323 | * 24:22 Function Number [2:0] |
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| 324 | * 21 Entity[6] |
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| 325 | * 20:19 Control Selector[5:4] |
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| 326 | * 18 0 (Reserved) |
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| 327 | * 17:15 Control Number[5:3] |
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| 328 | * 14 Next |
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| 329 | * 13 MBQ |
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| 330 | * 12:7 Entity[5:0] |
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| 331 | * 6:3 Control Selector[3:0] |
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| 332 | * 2:0 Control Number[2:0] |
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| 333 | */ |
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| 334 | |
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| 335 | #define SDW_SDCA_CTL(fun, ent, ctl, ch) (BIT(30) | \ |
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| 336 | (((fun) & GENMASK(2, 0)) << 22) | \ |
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| 337 | (((ent) & BIT(6)) << 15) | \ |
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| 338 | (((ent) & GENMASK(5, 0)) << 7) | \ |
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| 339 | (((ctl) & GENMASK(5, 4)) << 15) | \ |
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| 340 | (((ctl) & GENMASK(3, 0)) << 3) | \ |
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| 341 | (((ch) & GENMASK(5, 3)) << 12) | \ |
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| 342 | ((ch) & GENMASK(2, 0))) |
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| 343 | |
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| 344 | #define SDW_SDCA_CTL_FUNC(reg) FIELD_GET(GENMASK(24, 22), (reg)) |
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| 345 | #define SDW_SDCA_CTL_ENT(reg) ((FIELD_GET(BIT(21), (reg)) << 6) | \ |
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| 346 | FIELD_GET(GENMASK(12, 7), (reg))) |
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| 347 | #define SDW_SDCA_CTL_CSEL(reg) ((FIELD_GET(GENMASK(20, 19), (reg)) << 4) | \ |
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| 348 | FIELD_GET(GENMASK(6, 3), (reg))) |
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| 349 | #define SDW_SDCA_CTL_CNUM(reg) ((FIELD_GET(GENMASK(17, 15), (reg)) << 3) | \ |
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| 350 | FIELD_GET(GENMASK(2, 0), (reg))) |
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| 351 | |
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| 352 | #define SDW_SDCA_MBQ_CTL(reg) ((reg) | BIT(13)) |
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| 353 | #define SDW_SDCA_NEXT_CTL(reg) ((reg) | BIT(14)) |
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| 354 | |
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| 355 | /* Check the reserved and fixed bits in address */ |
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| 356 | #define SDW_SDCA_VALID_CTL(reg) (((reg) & (GENMASK(31, 25) | BIT(18) | BIT(13))) == BIT(30)) |
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| 357 | |
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| 358 | #define SDW_SDCA_MAX_REGISTER 0x47FFFFFF |
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| 359 | |
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| 360 | #endif /* __SDW_REGISTERS_H */ |
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| 361 | |
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