| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* |
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| 3 | * Copyright (c) 2024 MediaTek Inc. |
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| 4 | * Copyright (c) 2025 Collabora Ltd |
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| 5 | */ |
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| 6 | |
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| 7 | #include <linux/bits.h> |
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| 8 | |
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| 9 | #ifndef __LINUX_REGULATOR_MT6363_H |
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| 10 | #define __LINUX_REGULATOR_MT6363_H |
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| 11 | |
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| 12 | /* Register */ |
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| 13 | #define MT6363_TOP_TRAP 0x6 |
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| 14 | #define MT6363_TOP_TMA_KEY_L 0x36e |
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| 15 | #define MT6363_RG_BUCK0_EN_ADDR 0x210 |
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| 16 | #define MT6363_RG_BUCK_VS2_EN_BIT 0 |
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| 17 | #define MT6363_RG_BUCK_VBUCK1_EN_BIT 1 |
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| 18 | #define MT6363_RG_BUCK_VBUCK2_EN_BIT 2 |
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| 19 | #define MT6363_RG_BUCK_VBUCK3_EN_BIT 3 |
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| 20 | #define MT6363_RG_BUCK_VBUCK4_EN_BIT 4 |
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| 21 | #define MT6363_RG_BUCK_VBUCK5_EN_BIT 5 |
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| 22 | #define MT6363_RG_BUCK_VBUCK6_EN_BIT 6 |
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| 23 | #define MT6363_RG_BUCK_VBUCK7_EN_BIT 7 |
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| 24 | #define MT6363_RG_BUCK1_EN_ADDR 0x213 |
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| 25 | #define MT6363_RG_BUCK_VS1_EN_BIT 0 |
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| 26 | #define MT6363_RG_BUCK_VS3_EN_BIT 1 |
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| 27 | #define MT6363_RG_LDO_VSRAM_DIGRF_EN_BIT 4 |
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| 28 | #define MT6363_RG_LDO_VSRAM_MDFE_EN_BIT 5 |
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| 29 | #define MT6363_RG_LDO_VSRAM_MODEM_EN_BIT 6 |
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| 30 | #define MT6363_RG_BUCK0_LP_ADDR 0x216 |
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| 31 | #define MT6363_RG_BUCK_VS2_LP_BIT 0 |
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| 32 | #define MT6363_RG_BUCK_VBUCK1_LP_BIT 1 |
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| 33 | #define MT6363_RG_BUCK_VBUCK2_LP_BIT 2 |
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| 34 | #define MT6363_RG_BUCK_VBUCK3_LP_BIT 3 |
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| 35 | #define MT6363_RG_BUCK_VBUCK4_LP_BIT 4 |
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| 36 | #define MT6363_RG_BUCK_VBUCK5_LP_BIT 5 |
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| 37 | #define MT6363_RG_BUCK_VBUCK6_LP_BIT 6 |
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| 38 | #define MT6363_RG_BUCK_VBUCK7_LP_BIT 7 |
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| 39 | #define MT6363_RG_BUCK1_LP_ADDR 0x219 |
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| 40 | #define MT6363_RG_BUCK_VS1_LP_BIT 0 |
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| 41 | #define MT6363_RG_BUCK_VS3_LP_BIT 1 |
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| 42 | #define MT6363_RG_LDO_VSRAM_DIGRF_LP_BIT 4 |
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| 43 | #define MT6363_RG_LDO_VSRAM_MDFE_LP_BIT 5 |
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| 44 | #define MT6363_RG_LDO_VSRAM_MODEM_LP_BIT 6 |
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| 45 | #define MT6363_RG_BUCK_VS2_VOSEL_ADDR 0x21c |
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| 46 | #define MT6363_RG_BUCK_VS2_VOSEL_MASK GENMASK(7, 0) |
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| 47 | #define MT6363_RG_BUCK_VBUCK1_VOSEL_ADDR 0x21d |
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| 48 | #define MT6363_RG_BUCK_VBUCK1_VOSEL_MASK GENMASK(7, 0) |
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| 49 | #define MT6363_RG_BUCK_VBUCK2_VOSEL_ADDR 0x21e |
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| 50 | #define MT6363_RG_BUCK_VBUCK2_VOSEL_MASK GENMASK(7, 0) |
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| 51 | #define MT6363_RG_BUCK_VBUCK3_VOSEL_ADDR 0x21f |
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| 52 | #define MT6363_RG_BUCK_VBUCK3_VOSEL_MASK GENMASK(7, 0) |
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| 53 | #define MT6363_RG_BUCK_VBUCK4_VOSEL_ADDR 0x220 |
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| 54 | #define MT6363_RG_BUCK_VBUCK4_VOSEL_MASK GENMASK(7, 0) |
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| 55 | #define MT6363_RG_BUCK_VBUCK5_VOSEL_ADDR 0x221 |
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| 56 | #define MT6363_RG_BUCK_VBUCK5_VOSEL_MASK GENMASK(7, 0) |
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| 57 | #define MT6363_RG_BUCK_VBUCK6_VOSEL_ADDR 0x222 |
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| 58 | #define MT6363_RG_BUCK_VBUCK6_VOSEL_MASK GENMASK(7, 0) |
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| 59 | #define MT6363_RG_BUCK_VBUCK7_VOSEL_ADDR 0x223 |
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| 60 | #define MT6363_RG_BUCK_VBUCK7_VOSEL_MASK GENMASK(7, 0) |
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| 61 | #define MT6363_RG_BUCK_VS1_VOSEL_ADDR 0x224 |
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| 62 | #define MT6363_RG_BUCK_VS1_VOSEL_MASK GENMASK(7, 0) |
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| 63 | #define MT6363_RG_BUCK_VS3_VOSEL_ADDR 0x225 |
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| 64 | #define MT6363_RG_BUCK_VS3_VOSEL_MASK GENMASK(7, 0) |
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| 65 | #define MT6363_RG_LDO_VSRAM_DIGRF_VOSEL_ADDR 0x228 |
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| 66 | #define MT6363_RG_LDO_VSRAM_DIGRF_VOSEL_MASK GENMASK(6, 0) |
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| 67 | #define MT6363_RG_LDO_VSRAM_MDFE_VOSEL_ADDR 0x229 |
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| 68 | #define MT6363_RG_LDO_VSRAM_MDFE_VOSEL_MASK GENMASK(6, 0) |
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| 69 | #define MT6363_RG_LDO_VSRAM_MODEM_VOSEL_ADDR 0x22a |
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| 70 | #define MT6363_RG_LDO_VSRAM_MODEM_VOSEL_MASK GENMASK(6, 0) |
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| 71 | #define MT6363_BUCK_TOP_KEY_PROT_LO 0x13fa |
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| 72 | #define MT6363_BUCK_VS2_WDTDBG_VOSEL_ADDR 0x13fc |
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| 73 | #define MT6363_BUCK_VBUCK1_WDTDBG_VOSEL_ADDR 0x13fd |
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| 74 | #define MT6363_BUCK_VBUCK2_WDTDBG_VOSEL_ADDR 0x13fe |
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| 75 | #define MT6363_BUCK_VBUCK3_WDTDBG_VOSEL_ADDR 0x13ff |
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| 76 | #define MT6363_BUCK_VBUCK4_WDTDBG_VOSEL_ADDR 0x1400 |
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| 77 | #define MT6363_BUCK_VBUCK5_WDTDBG_VOSEL_ADDR 0x1401 |
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| 78 | #define MT6363_BUCK_VBUCK6_WDTDBG_VOSEL_ADDR 0x1402 |
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| 79 | #define MT6363_BUCK_VBUCK7_WDTDBG_VOSEL_ADDR 0x1403 |
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| 80 | #define MT6363_BUCK_VS1_WDTDBG_VOSEL_ADDR 0x1404 |
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| 81 | #define MT6363_BUCK_VS3_WDTDBG_VOSEL_ADDR 0x1405 |
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| 82 | #define MT6363_RG_BUCK_EFUSE_RSV1 0x1417 |
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| 83 | #define MT6363_RG_BUCK_EFUSE_RSV1_MASK GENMASK(7, 4) |
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| 84 | #define MT6363_BUCK_VS2_OP_EN_0 0x145d |
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| 85 | #define MT6363_BUCK_VS2_HW_LP_MODE 0x1468 |
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| 86 | #define MT6363_BUCK_VBUCK1_OP_EN_0 0x14dd |
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| 87 | #define MT6363_BUCK_VBUCK1_HW_LP_MODE 0x14e8 |
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| 88 | #define MT6363_RG_BUCK_VBUCK1_SSHUB_EN_ADDR 0x14ea |
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| 89 | #define MT6363_RG_BUCK_VBUCK1_SSHUB_VOSEL_ADDR 0x14eb |
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| 90 | #define MT6363_RG_BUCK_VBUCK1_SSHUB_VOSEL_MASK GENMASK(7, 0) |
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| 91 | #define MT6363_BUCK_VBUCK2_OP_EN_0 0x155d |
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| 92 | #define MT6363_BUCK_VBUCK2_HW_LP_MODE 0x1568 |
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| 93 | #define MT6363_RG_BUCK_VBUCK2_SSHUB_EN_ADDR 0x156a |
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| 94 | #define MT6363_RG_BUCK_VBUCK2_SSHUB_VOSEL_ADDR 0x156b |
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| 95 | #define MT6363_RG_BUCK_VBUCK2_SSHUB_VOSEL_MASK GENMASK(7, 0) |
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| 96 | #define MT6363_BUCK_VBUCK3_OP_EN_0 0x15dd |
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| 97 | #define MT6363_BUCK_VBUCK3_HW_LP_MODE 0x15e8 |
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| 98 | #define MT6363_BUCK_VBUCK4_OP_EN_0 0x165d |
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| 99 | #define MT6363_BUCK_VBUCK4_HW_LP_MODE 0x1668 |
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| 100 | #define MT6363_RG_BUCK_VBUCK4_SSHUB_EN_ADDR 0x166a |
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| 101 | #define MT6363_RG_BUCK_VBUCK4_SSHUB_VOSEL_ADDR 0x166b |
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| 102 | #define MT6363_RG_BUCK_VBUCK4_SSHUB_VOSEL_MASK GENMASK(7, 0) |
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| 103 | #define MT6363_BUCK_VBUCK5_OP_EN_0 0x16dd |
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| 104 | #define MT6363_BUCK_VBUCK5_HW_LP_MODE 0x16e8 |
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| 105 | #define MT6363_BUCK_VBUCK6_OP_EN_0 0x175d |
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| 106 | #define MT6363_BUCK_VBUCK6_HW_LP_MODE 0x1768 |
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| 107 | #define MT6363_BUCK_VBUCK7_OP_EN_0 0x17dd |
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| 108 | #define MT6363_BUCK_VBUCK7_HW_LP_MODE 0x17e8 |
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| 109 | #define MT6363_BUCK_VS1_OP_EN_0 0x185d |
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| 110 | #define MT6363_BUCK_VS1_HW_LP_MODE 0x1868 |
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| 111 | #define MT6363_BUCK_VS3_OP_EN_0 0x18dd |
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| 112 | #define MT6363_BUCK_VS3_HW_LP_MODE 0x18e8 |
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| 113 | #define MT6363_RG_VS1_FCCM_ADDR 0x1964 |
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| 114 | #define MT6363_RG_VS1_FCCM_BIT 0 |
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| 115 | #define MT6363_RG_VS3_FCCM_ADDR 0x1973 |
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| 116 | #define MT6363_RG_VS3_FCCM_BIT 0 |
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| 117 | #define MT6363_RG_BUCK0_FCCM_ADDR 0x1a02 |
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| 118 | #define MT6363_RG_VBUCK1_FCCM_BIT 0 |
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| 119 | #define MT6363_RG_VBUCK2_FCCM_BIT 1 |
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| 120 | #define MT6363_RG_VBUCK3_FCCM_BIT 2 |
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| 121 | #define MT6363_RG_VS2_FCCM_BIT 3 |
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| 122 | #define MT6363_RG_BUCK0_1_FCCM_ADDR 0x1a82 |
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| 123 | #define MT6363_RG_VBUCK4_FCCM_BIT 0 |
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| 124 | #define MT6363_RG_VBUCK5_FCCM_BIT 1 |
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| 125 | #define MT6363_RG_VBUCK6_FCCM_BIT 2 |
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| 126 | #define MT6363_RG_VBUCK7_FCCM_BIT 3 |
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| 127 | #define MT6363_RG_VCN13_VOSEL_ADDR 0x1b0f |
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| 128 | #define MT6363_RG_VCN13_VOSEL_MASK GENMASK(3, 0) |
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| 129 | #define MT6363_RG_VEMC_VOSEL_ADDR 0x1b10 |
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| 130 | #define MT6363_RG_VEMC_VOSEL_MASK GENMASK(3, 0) |
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| 131 | #define MT6363_RG_VEMC_VOSEL_1_MASK GENMASK(7, 4) |
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| 132 | #define MT6363_RG_LDO_VSRAM_CPUB_VOSEL_ADDR 0x1b14 |
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| 133 | #define MT6363_RG_LDO_VSRAM_CPUB_VOSEL_MASK GENMASK(6, 0) |
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| 134 | #define MT6363_RG_LDO_VSRAM_CPUM_VOSEL_ADDR 0x1b15 |
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| 135 | #define MT6363_RG_LDO_VSRAM_CPUM_VOSEL_MASK GENMASK(6, 0) |
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| 136 | #define MT6363_RG_LDO_VSRAM_CPUL_VOSEL_ADDR 0x1b16 |
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| 137 | #define MT6363_RG_LDO_VSRAM_CPUL_VOSEL_MASK GENMASK(6, 0) |
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| 138 | #define MT6363_RG_LDO_VSRAM_APU_VOSEL_ADDR 0x1b17 |
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| 139 | #define MT6363_RG_LDO_VSRAM_APU_VOSEL_MASK GENMASK(6, 0) |
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| 140 | #define MT6363_RG_VEMC_VOCAL_ADDR 0x1b1b |
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| 141 | #define MT6363_RG_VEMC_VOCAL_MASK GENMASK(3, 0) |
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| 142 | #define MT6363_RG_LDO_VCN15_ADDR 0x1b57 |
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| 143 | #define MT6363_RG_LDO_VCN15_EN_BIT 0 |
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| 144 | #define MT6363_RG_LDO_VCN15_LP_BIT 1 |
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| 145 | #define MT6363_LDO_VCN15_HW_LP_MODE 0x1b5b |
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| 146 | #define MT6363_LDO_VCN15_OP_EN0 0x1b5c |
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| 147 | #define MT6363_RG_LDO_VRF09_ADDR 0x1b65 |
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| 148 | #define MT6363_RG_LDO_VRF09_EN_BIT 0 |
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| 149 | #define MT6363_RG_LDO_VRF09_LP_BIT 1 |
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| 150 | #define MT6363_LDO_VRF09_HW_LP_MODE 0x1b69 |
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| 151 | #define MT6363_LDO_VRF09_OP_EN0 0x1b6a |
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| 152 | #define MT6363_RG_LDO_VRF12_ADDR 0x1b73 |
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| 153 | #define MT6363_RG_LDO_VRF12_EN_BIT 0 |
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| 154 | #define MT6363_RG_LDO_VRF12_LP_BIT 1 |
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| 155 | #define MT6363_LDO_VRF12_HW_LP_MODE 0x1b77 |
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| 156 | #define MT6363_LDO_VRF12_OP_EN0 0x1b78 |
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| 157 | #define MT6363_RG_LDO_VRF13_ADDR 0x1b81 |
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| 158 | #define MT6363_RG_LDO_VRF13_EN_BIT 0 |
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| 159 | #define MT6363_RG_LDO_VRF13_LP_BIT 1 |
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| 160 | #define MT6363_LDO_VRF13_HW_LP_MODE 0x1b85 |
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| 161 | #define MT6363_LDO_VRF13_OP_EN0 0x1b86 |
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| 162 | #define MT6363_RG_LDO_VRF18_ADDR 0x1b8f |
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| 163 | #define MT6363_RG_LDO_VRF18_EN_BIT 0 |
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| 164 | #define MT6363_RG_LDO_VRF18_LP_BIT 1 |
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| 165 | #define MT6363_LDO_VRF18_HW_LP_MODE 0x1b93 |
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| 166 | #define MT6363_LDO_VRF18_OP_EN0 0x1b94 |
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| 167 | #define MT6363_RG_LDO_VRFIO18_ADDR 0x1b9d |
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| 168 | #define MT6363_RG_LDO_VRFIO18_EN_BIT 0 |
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| 169 | #define MT6363_RG_LDO_VRFIO18_LP_BIT 1 |
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| 170 | #define MT6363_LDO_VRFIO18_HW_LP_MODE 0x1ba1 |
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| 171 | #define MT6363_LDO_VRFIO18_OP_EN0 0x1ba2 |
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| 172 | #define MT6363_RG_LDO_VTREF18_ADDR 0x1bd7 |
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| 173 | #define MT6363_RG_LDO_VTREF18_EN_BIT 0 |
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| 174 | #define MT6363_RG_LDO_VTREF18_LP_BIT 1 |
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| 175 | #define MT6363_LDO_VTREF18_HW_LP_MODE 0x1bdb |
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| 176 | #define MT6363_LDO_VTREF18_OP_EN0 0x1bdc |
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| 177 | #define MT6363_RG_LDO_VAUX18_ADDR 0x1be5 |
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| 178 | #define MT6363_RG_LDO_VAUX18_EN_BIT 0 |
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| 179 | #define MT6363_RG_LDO_VAUX18_LP_BIT 1 |
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| 180 | #define MT6363_LDO_VAUX18_HW_LP_MODE 0x1be9 |
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| 181 | #define MT6363_LDO_VAUX18_OP_EN0 0x1bea |
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| 182 | #define MT6363_RG_LDO_VEMC_ADDR 0x1bf3 |
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| 183 | #define MT6363_RG_LDO_VEMC_EN_BIT 0 |
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| 184 | #define MT6363_RG_LDO_VEMC_LP_BIT 1 |
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| 185 | #define MT6363_LDO_VEMC_HW_LP_MODE 0x1bf7 |
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| 186 | #define MT6363_LDO_VEMC_OP_EN0 0x1bf8 |
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| 187 | #define MT6363_RG_LDO_VUFS12_ADDR 0x1c01 |
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| 188 | #define MT6363_RG_LDO_VUFS12_EN_BIT 0 |
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| 189 | #define MT6363_RG_LDO_VUFS12_LP_BIT 1 |
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| 190 | #define MT6363_LDO_VUFS12_HW_LP_MODE 0x1c05 |
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| 191 | #define MT6363_LDO_VUFS12_OP_EN0 0x1c06 |
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| 192 | #define MT6363_RG_LDO_VUFS18_ADDR 0x1c0f |
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| 193 | #define MT6363_RG_LDO_VUFS18_EN_BIT 0 |
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| 194 | #define MT6363_RG_LDO_VUFS18_LP_BIT 1 |
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| 195 | #define MT6363_LDO_VUFS18_HW_LP_MODE 0x1c13 |
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| 196 | #define MT6363_LDO_VUFS18_OP_EN0 0x1c14 |
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| 197 | #define MT6363_RG_LDO_VIO18_ADDR 0x1c1d |
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| 198 | #define MT6363_RG_LDO_VIO18_EN_BIT 0 |
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| 199 | #define MT6363_RG_LDO_VIO18_LP_BIT 1 |
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| 200 | #define MT6363_LDO_VIO18_HW_LP_MODE 0x1c21 |
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| 201 | #define MT6363_LDO_VIO18_OP_EN0 0x1c22 |
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| 202 | #define MT6363_RG_LDO_VIO075_ADDR 0x1c57 |
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| 203 | #define MT6363_RG_LDO_VIO075_EN_BIT 0 |
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| 204 | #define MT6363_RG_LDO_VIO075_LP_BIT 1 |
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| 205 | #define MT6363_LDO_VIO075_HW_LP_MODE 0x1c5b |
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| 206 | #define MT6363_LDO_VIO075_OP_EN0 0x1c5c |
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| 207 | #define MT6363_RG_LDO_VA12_1_ADDR 0x1c65 |
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| 208 | #define MT6363_RG_LDO_VA12_1_EN_BIT 0 |
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| 209 | #define MT6363_RG_LDO_VA12_1_LP_BIT 1 |
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| 210 | #define MT6363_LDO_VA12_1_HW_LP_MODE 0x1c69 |
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| 211 | #define MT6363_LDO_VA12_1_OP_EN0 0x1c6a |
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| 212 | #define MT6363_RG_LDO_VA12_2_ADDR 0x1c73 |
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| 213 | #define MT6363_RG_LDO_VA12_2_EN_BIT 0 |
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| 214 | #define MT6363_RG_LDO_VA12_2_LP_BIT 1 |
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| 215 | #define MT6363_LDO_VA12_2_HW_LP_MODE 0x1c77 |
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| 216 | #define MT6363_LDO_VA12_2_OP_EN0 0x1c78 |
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| 217 | #define MT6363_RG_LDO_VA15_ADDR 0x1c81 |
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| 218 | #define MT6363_RG_LDO_VA15_EN_BIT 0 |
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| 219 | #define MT6363_RG_LDO_VA15_LP_BIT 1 |
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| 220 | #define MT6363_LDO_VA15_HW_LP_MODE 0x1c85 |
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| 221 | #define MT6363_LDO_VA15_OP_EN0 0x1c86 |
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| 222 | #define MT6363_RG_LDO_VM18_ADDR 0x1c8f |
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| 223 | #define MT6363_RG_LDO_VM18_EN_BIT 0 |
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| 224 | #define MT6363_RG_LDO_VM18_LP_BIT 1 |
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| 225 | #define MT6363_LDO_VM18_HW_LP_MODE 0x1c93 |
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| 226 | #define MT6363_LDO_VM18_OP_EN0 0x1c94 |
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| 227 | #define MT6363_RG_LDO_VCN13_ADDR 0x1cd7 |
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| 228 | #define MT6363_RG_LDO_VCN13_EN_BIT 0 |
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| 229 | #define MT6363_RG_LDO_VCN13_LP_BIT 1 |
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| 230 | #define MT6363_LDO_VCN13_HW_LP_MODE 0x1cdb |
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| 231 | #define MT6363_LDO_VCN13_OP_EN0 0x1ce4 |
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| 232 | #define MT6363_LDO_VSRAM_DIGRF_HW_LP_MODE 0x1cf1 |
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| 233 | #define MT6363_LDO_VSRAM_DIGRF_OP_EN0 0x1cfa |
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| 234 | #define MT6363_LDO_VSRAM_MDFE_HW_LP_MODE 0x1d5b |
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| 235 | #define MT6363_LDO_VSRAM_MDFE_OP_EN0 0x1d64 |
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| 236 | #define MT6363_LDO_VSRAM_MODEM_HW_LP_MODE 0x1d76 |
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| 237 | #define MT6363_LDO_VSRAM_MODEM_OP_EN0 0x1d7f |
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| 238 | #define MT6363_RG_LDO_VSRAM_CPUB_ADDR 0x1dd7 |
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| 239 | #define MT6363_RG_LDO_VSRAM_CPUB_EN_BIT 0 |
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| 240 | #define MT6363_RG_LDO_VSRAM_CPUB_LP_BIT 1 |
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| 241 | #define MT6363_LDO_VSRAM_CPUB_HW_LP_MODE 0x1ddb |
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| 242 | #define MT6363_LDO_VSRAM_CPUB_OP_EN0 0x1de4 |
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| 243 | #define MT6363_RG_LDO_VSRAM_CPUM_ADDR 0x1ded |
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| 244 | #define MT6363_RG_LDO_VSRAM_CPUM_EN_BIT 0 |
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| 245 | #define MT6363_RG_LDO_VSRAM_CPUM_LP_BIT 1 |
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| 246 | #define MT6363_LDO_VSRAM_CPUM_HW_LP_MODE 0x1df1 |
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| 247 | #define MT6363_LDO_VSRAM_CPUM_OP_EN0 0x1dfa |
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| 248 | #define MT6363_RG_LDO_VSRAM_CPUL_ADDR 0x1e57 |
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| 249 | #define MT6363_RG_LDO_VSRAM_CPUL_EN_BIT 0 |
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| 250 | #define MT6363_RG_LDO_VSRAM_CPUL_LP_BIT 1 |
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| 251 | #define MT6363_LDO_VSRAM_CPUL_HW_LP_MODE 0x1e5b |
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| 252 | #define MT6363_LDO_VSRAM_CPUL_OP_EN0 0x1e64 |
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| 253 | #define MT6363_RG_LDO_VSRAM_APU_ADDR 0x1e6d |
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| 254 | #define MT6363_RG_LDO_VSRAM_APU_EN_BIT 0 |
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| 255 | #define MT6363_RG_LDO_VSRAM_APU_LP_BIT 1 |
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| 256 | #define MT6363_LDO_VSRAM_APU_HW_LP_MODE 0x1e71 |
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| 257 | #define MT6363_LDO_VSRAM_APU_OP_EN0 0x1e7a |
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| 258 | #define MT6363_RG_VTREF18_VOCAL_ADDR 0x1ed8 |
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| 259 | #define MT6363_RG_VTREF18_VOCAL_MASK GENMASK(3, 0) |
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| 260 | #define MT6363_RG_VTREF18_VOSEL_ADDR 0x1ed9 |
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| 261 | #define MT6363_RG_VTREF18_VOSEL_MASK GENMASK(3, 0) |
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| 262 | #define MT6363_RG_VAUX18_VOCAL_ADDR 0x1edc |
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| 263 | #define MT6363_RG_VAUX18_VOCAL_MASK GENMASK(3, 0) |
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| 264 | #define MT6363_RG_VAUX18_VOSEL_ADDR 0x1edd |
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| 265 | #define MT6363_RG_VAUX18_VOSEL_MASK GENMASK(3, 0) |
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| 266 | #define MT6363_RG_VCN15_VOCAL_ADDR 0x1ee3 |
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| 267 | #define MT6363_RG_VCN15_VOCAL_MASK GENMASK(3, 0) |
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| 268 | #define MT6363_RG_VCN15_VOSEL_ADDR 0x1ee4 |
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| 269 | #define MT6363_RG_VCN15_VOSEL_MASK GENMASK(3, 0) |
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| 270 | #define MT6363_RG_VUFS18_VOCAL_ADDR 0x1ee7 |
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| 271 | #define MT6363_RG_VUFS18_VOCAL_MASK GENMASK(3, 0) |
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| 272 | #define MT6363_RG_VUFS18_VOSEL_ADDR 0x1ee8 |
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| 273 | #define MT6363_RG_VUFS18_VOSEL_MASK GENMASK(3, 0) |
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| 274 | #define MT6363_RG_VIO18_VOCAL_ADDR 0x1eeb |
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| 275 | #define MT6363_RG_VIO18_VOCAL_MASK GENMASK(3, 0) |
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| 276 | #define MT6363_RG_VIO18_VOSEL_ADDR 0x1eec |
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| 277 | #define MT6363_RG_VIO18_VOSEL_MASK GENMASK(3, 0) |
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| 278 | #define MT6363_RG_VM18_VOCAL_ADDR 0x1eef |
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| 279 | #define MT6363_RG_VM18_VOCAL_MASK GENMASK(3, 0) |
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| 280 | #define MT6363_RG_VM18_VOSEL_ADDR 0x1ef0 |
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| 281 | #define MT6363_RG_VM18_VOSEL_MASK GENMASK(3, 0) |
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| 282 | #define MT6363_RG_VA15_VOCAL_ADDR 0x1ef3 |
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| 283 | #define MT6363_RG_VA15_VOCAL_MASK GENMASK(3, 0) |
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| 284 | #define MT6363_RG_VA15_VOSEL_ADDR 0x1ef4 |
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| 285 | #define MT6363_RG_VA15_VOSEL_MASK GENMASK(3, 0) |
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| 286 | #define MT6363_RG_VRF18_VOCAL_ADDR 0x1ef7 |
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| 287 | #define MT6363_RG_VRF18_VOCAL_MASK GENMASK(3, 0) |
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| 288 | #define MT6363_RG_VRF18_VOSEL_ADDR 0x1ef8 |
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| 289 | #define MT6363_RG_VRF18_VOSEL_MASK GENMASK(3, 0) |
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| 290 | #define MT6363_RG_VRFIO18_VOCAL_ADDR 0x1efb |
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| 291 | #define MT6363_RG_VRFIO18_VOCAL_MASK GENMASK(3, 0) |
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| 292 | #define MT6363_RG_VRFIO18_VOSEL_ADDR 0x1efc |
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| 293 | #define MT6363_RG_VRFIO18_VOSEL_MASK GENMASK(3, 0) |
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| 294 | #define MT6363_RG_VIO075_VOCFG_ADDR 0x1f01 |
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| 295 | #define MT6363_RG_VIO075_VOCAL_ADDR MT6363_RG_VIO075_VOCFG_ADDR |
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| 296 | #define MT6363_RG_VIO075_VOCAL_MASK GENMASK(3, 0) |
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| 297 | #define MT6363_RG_VIO075_VOSEL_ADDR MT6363_RG_VIO075_VOCFG_ADDR |
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| 298 | #define MT6363_RG_VIO075_VOSEL_MASK GENMASK(6, 4) |
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| 299 | #define MT6363_RG_VCN13_VOCAL_ADDR 0x1f58 |
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| 300 | #define MT6363_RG_VCN13_VOCAL_MASK GENMASK(3, 0) |
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| 301 | #define MT6363_RG_VUFS12_VOCAL_ADDR 0x1f61 |
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| 302 | #define MT6363_RG_VUFS12_VOCAL_MASK GENMASK(3, 0) |
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| 303 | #define MT6363_RG_VUFS12_VOSEL_ADDR 0x1f62 |
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| 304 | #define MT6363_RG_VUFS12_VOSEL_MASK GENMASK(3, 0) |
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| 305 | #define MT6363_RG_VA12_1_VOCAL_ADDR 0x1f65 |
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| 306 | #define MT6363_RG_VA12_1_VOCAL_MASK GENMASK(3, 0) |
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| 307 | #define MT6363_RG_VA12_1_VOSEL_ADDR 0x1f66 |
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| 308 | #define MT6363_RG_VA12_1_VOSEL_MASK GENMASK(3, 0) |
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| 309 | #define MT6363_RG_VA12_2_VOCAL_ADDR 0x1f69 |
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| 310 | #define MT6363_RG_VA12_2_VOCAL_MASK GENMASK(3, 0) |
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| 311 | #define MT6363_RG_VA12_2_VOSEL_ADDR 0x1f6a |
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| 312 | #define MT6363_RG_VA12_2_VOSEL_MASK GENMASK(3, 0) |
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| 313 | #define MT6363_RG_VRF12_VOCAL_ADDR 0x1f6d |
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| 314 | #define MT6363_RG_VRF12_VOCAL_MASK GENMASK(3, 0) |
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| 315 | #define MT6363_RG_VRF12_VOSEL_ADDR 0x1f6e |
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| 316 | #define MT6363_RG_VRF12_VOSEL_MASK GENMASK(3, 0) |
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| 317 | #define MT6363_RG_VRF13_VOCAL_ADDR 0x1f71 |
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| 318 | #define MT6363_RG_VRF13_VOCAL_MASK GENMASK(3, 0) |
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| 319 | #define MT6363_RG_VRF13_VOSEL_ADDR 0x1f72 |
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| 320 | #define MT6363_RG_VRF13_VOSEL_MASK GENMASK(3, 0) |
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| 321 | #define MT6363_RG_VRF09_VOCAL_ADDR 0x1f78 |
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| 322 | #define MT6363_RG_VRF09_VOCAL_MASK GENMASK(3, 0) |
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| 323 | #define MT6363_RG_VRF09_VOSEL_ADDR 0x1f79 |
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| 324 | #define MT6363_RG_VRF09_VOSEL_MASK GENMASK(3, 0) |
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| 325 | #define MT6363_ISINK_EN_CTRL0 0x21db |
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| 326 | #define MT6363_ISINK_CTRL0_MASK GENMASK(7, 0) |
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| 327 | #define MT6363_ISINK_EN_CTRL1 0x21dc |
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| 328 | #define MT6363_ISINK_CTRL1_MASK GENMASK(7, 4) |
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| 329 | |
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| 330 | #endif /* __LINUX_REGULATOR_MT6363_H */ |
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| 331 | |
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